48 #define _W5500_IO_BASE_ 0x00000000
50 #define _W5500_SPI_READ_ (0x00 << 2) //< SPI interface Read operation in Control Phase
51 #define _W5500_SPI_WRITE_ (0x01 << 2) //< SPI interface Write operation in Control Phase
53 #define WIZCHIP_CREG_BLOCK 0x00 //< Common register block
54 #define WIZCHIP_SREG_BLOCK(N) (1+4*N) //< Socket N register block
55 #define WIZCHIP_TXBUF_BLOCK(N) (2+4*N) //< Socket N Tx buffer address block
56 #define WIZCHIP_RXBUF_BLOCK(N) (3+4*N) //< Socket N Rx buffer address block
58 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
64 #define IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR)
65 #define IINCHIP_WRITE(ADDR,VAL) WIZCHIP_WRITE(ADDR,VAL)
66 #define IINCHIP_READ_BUF(ADDR,BUF,LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN)
67 #define IINCHIP_WRITE_BUF(ADDR,BUF,LEN) WIZCHIP_WRITE(ADDR,BUF,LEN)
204 #define MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
211 #define GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
218 #define SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
225 #define SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
232 #define SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
239 #define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
256 #define IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
274 #define IMR (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
282 #define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
291 #define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
301 #define RTR (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
309 #define RCR (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
316 #define PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
323 #define PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
330 #define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
337 #define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
344 #define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
353 #define UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
362 #define UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
369 #define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
387 #define VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
421 #define Sn_MR(N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
440 #define Sn_CR(N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
458 #define Sn_IR(N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
481 #define Sn_SR(N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
489 #define Sn_PORT(N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
497 #define Sn_DHAR(N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
507 #define Sn_DIPR(N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
517 #define Sn_DPORT(N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
524 #define Sn_MSSR(N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
534 #define Sn_TOS(N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
541 #define Sn_TTL(N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
560 #define Sn_RXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
571 #define Sn_TXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
582 #define Sn_TX_FSR(N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
594 #define Sn_TX_RD(N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
608 #define Sn_TX_WR(N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
617 #define Sn_RX_RSR(N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
630 #define Sn_RX_RD(N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
639 #define Sn_RX_WR(N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
649 #define Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
656 #define Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
669 #define Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
708 #define MR_PPPOE 0x08
723 #define IR_CONFLICT 0x80
730 #define IR_UNREACH 0x40
736 #define IR_PPPoE 0x20
746 #define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask.
747 #define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value
748 #define PHYCFGR_OPMDC_ALLA (7<<3)
749 #define PHYCFGR_OPMDC_PDOWN (6<<3)
750 #define PHYCFGR_OPMDC_NA (5<<3)
751 #define PHYCFGR_OPMDC_100FA (4<<3)
752 #define PHYCFGR_OPMDC_100F (3<<3)
753 #define PHYCFGR_OPMDC_100H (2<<3)
754 #define PHYCFGR_OPMDC_10F (1<<3)
755 #define PHYCFGR_OPMDC_10H (0<<3)
756 #define PHYCFGR_DPX_FULL (1<<2)
757 #define PHYCFGR_DPX_HALF (0<<2)
758 #define PHYCFGR_SPD_100 (1<<1)
759 #define PHYCFGR_SPD_10 (0<<1)
760 #define PHYCFGR_LNK_ON (1<<0)
761 #define PHYCFGR_LNK_OFF (0<<0)
801 #define Sn_MR_MULTI 0x80
810 #define Sn_MR_BCASTB 0x40
820 #define Sn_MR_ND 0x20
828 #define Sn_MR_UCASTB 0x10
835 #define Sn_MR_MACRAW 0x04
843 #define Sn_MR_UDP 0x02
849 #define Sn_MR_TCP 0x01
855 #define Sn_MR_CLOSE 0x00
868 #define Sn_MR_MFEN Sn_MR_MULTI
877 #define Sn_MR_MMB Sn_MR_ND
885 #define Sn_MR_MIP6B Sn_MR_UCASTB
894 #define Sn_MR_MC Sn_MR_ND
900 #define SOCK_STREAM Sn_MR_TCP
905 #define SOCK_DGRAM Sn_MR_UDP
921 #define Sn_CR_OPEN 0x01
932 #define Sn_CR_LISTEN 0x02
944 #define Sn_CR_CONNECT 0x04
957 #define Sn_CR_DISCON 0x08
963 #define Sn_CR_CLOSE 0x10
971 #define Sn_CR_SEND 0x20
981 #define Sn_CR_SEND_MAC 0x21
989 #define Sn_CR_SEND_KEEP 0x22
997 #define Sn_CR_RECV 0x40
1004 #define Sn_IR_SENDOK 0x10
1010 #define Sn_IR_TIMEOUT 0x08
1016 #define Sn_IR_RECV 0x04
1022 #define Sn_IR_DISCON 0x02
1028 #define Sn_IR_CON 0x01
1036 #define SOCK_CLOSED 0x00
1044 #define SOCK_INIT 0x13
1052 #define SOCK_LISTEN 0x14
1061 #define SOCK_SYNSENT 0x15
1069 #define SOCK_SYNRECV 0x16
1078 #define SOCK_ESTABLISHED 0x17
1086 #define SOCK_FIN_WAIT 0x18
1094 #define SOCK_CLOSING 0x1A
1102 #define SOCK_TIME_WAIT 0x1B
1110 #define SOCK_CLOSE_WAIT 0x1C
1117 #define SOCK_LAST_ACK 0x1D
1125 #define SOCK_UDP 0x22
1135 #define SOCK_MACRAW 0x42
1140 #define IPPROTO_IP 0 //< Dummy for IP
1141 #define IPPROTO_ICMP 1 //< Control message protocol
1142 #define IPPROTO_IGMP 2 //< Internet group management protocol
1143 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated)
1144 #define IPPROTO_TCP 6 //< TCP
1145 #define IPPROTO_PUP 12 //< PUP
1146 #define IPPROTO_UDP 17 //< UDP
1147 #define IPPROTO_IDP 22 //< XNS idp
1148 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol
1149 #define IPPROTO_RAW 255 //< Raw IP packet
1163 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
1176 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
1229 WIZCHIP_WRITE(MR,mr)
1247 #define setGAR(gar) \
1248 WIZCHIP_WRITE_BUF(GAR,gar,4)
1256 #define getGAR(gar) \
1257 WIZCHIP_READ_BUF(GAR,gar,4)
1265 #define setSUBR(subr) \
1266 WIZCHIP_WRITE_BUF(SUBR, subr,4)
1275 #define getSUBR(subr) \
1276 WIZCHIP_READ_BUF(SUBR, subr, 4)
1284 #define setSHAR(shar) \
1285 WIZCHIP_WRITE_BUF(SHAR, shar, 6)
1293 #define getSHAR(shar) \
1294 WIZCHIP_READ_BUF(SHAR, shar, 6)
1302 #define setSIPR(sipr) \
1303 WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
1311 #define getSIPR(sipr) \
1312 WIZCHIP_READ_BUF(SIPR, sipr, 4)
1320 #define setINTLEVEL(intlevel) {\
1321 WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \
1322 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
1332 #define getINTLEVEL() \
1333 ((WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
1342 WIZCHIP_WRITE(IR, (ir & 0xF0))
1351 (WIZCHIP_READ(IR) & 0xF0)
1358 #define setIMR(imr) \
1359 WIZCHIP_WRITE(IMR, imr)
1377 #define setSIR(sir) \
1378 WIZCHIP_WRITE(SIR, sir)
1394 #define setSIMR(simr) \
1395 WIZCHIP_WRITE(SIMR, simr)
1412 #define setRTR(rtr) {\
1413 WIZCHIP_WRITE(RTR, (uint8_t)(rtr >> 8)); \
1414 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(RTR,1), (uint8_t) rtr); \
1424 ((WIZCHIP_READ(RTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(RTR,1)))
1432 #define setRCR(rcr) \
1433 WIZCHIP_WRITE(RCR, rcr)
1452 #define setPTIMER(ptimer) \
1453 WIZCHIP_WRITE(PTIMER, ptimer)
1461 #define getPTIMER() \
1462 WIZCHIP_READ(PTIMER)
1470 #define setPMAGIC(pmagic) \
1471 WIZCHIP_WRITE(PMAGIC, pmagic)
1479 #define getPMAGIC() \
1480 WIZCHIP_READ(PMAGIC)
1488 #define setPHAR(phar) \
1489 WIZCHIP_WRITE_BUF(PHAR, phar, 6)
1497 #define getPHAR(phar) \
1498 WIZCHIP_READ_BUF(PHAR, phar, 6)
1506 #define setPSID(psid) {\
1507 WIZCHIP_WRITE(PSID, (uint8_t)(psid >> 8)); \
1508 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); \
1519 ((WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
1527 #define setPMRU(pmru) { \
1528 WIZCHIP_WRITE(PMRU, (uint8_t)(pmru>>8)); \
1529 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); \
1539 ((WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
1546 #define getUIPR(uipr) \
1547 WIZCHIP_READ_BUF(UIPR,uipr,6)
1554 #define getUPORTR() \
1555 ((WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
1563 #define setPHYCFGR(phycfgr) \
1564 WIZCHIP_WRITE(PHYCFGR, phycfgr)
1572 #define getPHYCFGR() \
1573 WIZCHIP_READ(PHYCFGR)
1580 #define getVERSIONR() \
1581 WIZCHIP_READ(VERSIONR)
1595 #define setSn_MR(sn, mr) \
1596 WIZCHIP_WRITE(Sn_MR(sn),mr)
1605 #define getSn_MR(sn) \
1606 WIZCHIP_READ(Sn_MR(sn))
1615 #define setSn_CR(sn, cr) \
1616 WIZCHIP_WRITE(Sn_CR(sn), cr)
1625 #define getSn_CR(sn) \
1626 WIZCHIP_READ(Sn_CR(sn))
1635 #define setSn_IR(sn, ir) \
1636 WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F))
1645 #define getSn_IR(sn) \
1646 (WIZCHIP_READ(Sn_IR(sn)) & 0x1F)
1655 #define setSn_IMR(sn, imr) \
1656 WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F))
1665 #define getSn_IMR(sn) \
1666 (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F)
1674 #define getSn_SR(sn) \
1675 WIZCHIP_READ(Sn_SR(sn))
1684 #define setSn_PORT(sn, port) { \
1685 WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
1686 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
1696 #define getSn_PORT(sn) \
1697 ((WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
1706 #define setSn_DHAR(sn, dhar) \
1707 WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
1716 #define getSn_DHAR(sn, dhar) \
1717 WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
1726 #define setSn_DIPR(sn, dipr) \
1727 WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
1736 #define getSn_DIPR(sn, dipr) \
1737 WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
1746 #define setSn_DPORT(sn, dport) { \
1747 WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
1748 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
1758 #define getSn_DPORT(sn) \
1759 ((WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
1768 #define setSn_MSSR(sn, mss) { \
1769 WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
1770 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
1780 #define getSn_MSSR(sn) \
1781 ((WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
1790 #define setSn_TOS(sn, tos) \
1791 WIZCHIP_WRITE(Sn_TOS(sn), tos)
1800 #define getSn_TOS(sn) \
1801 WIZCHIP_READ(Sn_TOS(sn))
1810 #define setSn_TTL(sn, ttl) \
1811 WIZCHIP_WRITE(Sn_TTL(sn), ttl)
1821 #define getSn_TTL(sn) \
1822 WIZCHIP_READ(Sn_TTL(sn))
1832 #define setSn_RXBUF_SIZE(sn, rxbufsize) \
1833 WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize)
1843 #define getSn_RXBUF_SIZE(sn) \
1844 WIZCHIP_READ(Sn_RXBUF_SIZE(sn))
1853 #define setSn_TXBUF_SIZE(sn, txbufsize) \
1854 WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize)
1863 #define getSn_TXBUF_SIZE(sn) \
1864 WIZCHIP_READ(Sn_TXBUF_SIZE(sn))
1880 #define getSn_TX_RD(sn) \
1881 ((WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
1890 #define setSn_TX_WR(sn, txwr) { \
1891 WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
1892 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
1902 #define getSn_TX_WR(sn) \
1903 ((WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
1922 #define setSn_RX_RD(sn, rxrd) { \
1923 WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
1924 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
1934 #define getSn_RX_RD(sn) \
1935 ((WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
1943 #define getSn_RX_WR(sn) \
1944 ((WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
1954 #define setSn_FRAG(sn, frag) { \
1955 WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
1956 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
1966 #define getSn_FRAG(sn) \
1967 ((WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
1976 #define setSn_KPALVTR(sn, kpalvt) \
1977 WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt)
1986 #define getSn_KPALVTR(sn) \
1987 WIZCHIP_READ(Sn_KPALVTR(sn))
1999 #define getSn_RxMAX(sn) \
2000 (getSn_RXBUF_SIZE(sn) << 10)
2008 #define getSn_TxMAX(sn) \
2009 (getSn_TXBUF_SIZE(sn) << 10)
2026 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2043 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);