/* ----------------------------------------------------------------------
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* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
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*
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* $Date: 19. March 2015
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* $Revision: V.1.4.5
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*
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* Project: CMSIS DSP Library
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* Title: arm_cmplx_dot_prod_q31.c
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*
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* Description: Q31 complex dot product
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*
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* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of ARM LIMITED nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* -------------------------------------------------------------------- */
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#include "arm_math.h"
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/**
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* @ingroup groupCmplxMath
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*/
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/**
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* @addtogroup cmplx_dot_prod
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* @{
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*/
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/**
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* @brief Q31 complex dot product
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* @param *pSrcA points to the first input vector
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* @param *pSrcB points to the second input vector
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* @param numSamples number of complex samples in each vector
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* @param *realResult real part of the result returned here
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* @param *imagResult imaginary part of the result returned here
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* @return none.
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*
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* <b>Scaling and Overflow Behavior:</b>
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* \par
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* The function is implemented using an internal 64-bit accumulator.
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* The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.
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* The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.
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* Additions are nonsaturating and no overflow will occur as long as <code>numSamples</code> is less than 32768.
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* The return results <code>realResult</code> and <code>imagResult</code> are in 16.48 format.
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* Input down scaling is not required.
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*/
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void arm_cmplx_dot_prod_q31(
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q31_t * pSrcA,
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q31_t * pSrcB,
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uint32_t numSamples,
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q63_t * realResult,
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q63_t * imagResult)
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{
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q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
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q31_t a0,b0,c0,d0;
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#ifndef ARM_MATH_CM0_FAMILY
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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uint32_t blkCnt; /* loop counter */
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/*loop Unrolling */
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blkCnt = numSamples >> 2u;
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/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
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** a second loop below computes the remaining 1 to 3 samples. */
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while(blkCnt > 0u)
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{
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a0 = *pSrcA++;
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b0 = *pSrcA++;
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c0 = *pSrcB++;
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d0 = *pSrcB++;
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real_sum += ((q63_t)a0 * c0) >> 14;
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imag_sum += ((q63_t)a0 * d0) >> 14;
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real_sum -= ((q63_t)b0 * d0) >> 14;
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imag_sum += ((q63_t)b0 * c0) >> 14;
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a0 = *pSrcA++;
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b0 = *pSrcA++;
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c0 = *pSrcB++;
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d0 = *pSrcB++;
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real_sum += ((q63_t)a0 * c0) >> 14;
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imag_sum += ((q63_t)a0 * d0) >> 14;
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real_sum -= ((q63_t)b0 * d0) >> 14;
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imag_sum += ((q63_t)b0 * c0) >> 14;
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a0 = *pSrcA++;
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b0 = *pSrcA++;
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c0 = *pSrcB++;
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d0 = *pSrcB++;
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real_sum += ((q63_t)a0 * c0) >> 14;
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imag_sum += ((q63_t)a0 * d0) >> 14;
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real_sum -= ((q63_t)b0 * d0) >> 14;
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imag_sum += ((q63_t)b0 * c0) >> 14;
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a0 = *pSrcA++;
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b0 = *pSrcA++;
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c0 = *pSrcB++;
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d0 = *pSrcB++;
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real_sum += ((q63_t)a0 * c0) >> 14;
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imag_sum += ((q63_t)a0 * d0) >> 14;
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real_sum -= ((q63_t)b0 * d0) >> 14;
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imag_sum += ((q63_t)b0 * c0) >> 14;
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/* Decrement the loop counter */
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blkCnt--;
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}
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/* If the numSamples is not a multiple of 4, compute any remaining output samples here.
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** No loop unrolling is used. */
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blkCnt = numSamples % 0x4u;
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while(blkCnt > 0u)
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{
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a0 = *pSrcA++;
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b0 = *pSrcA++;
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c0 = *pSrcB++;
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d0 = *pSrcB++;
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real_sum += ((q63_t)a0 * c0) >> 14;
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imag_sum += ((q63_t)a0 * d0) >> 14;
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real_sum -= ((q63_t)b0 * d0) >> 14;
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imag_sum += ((q63_t)b0 * c0) >> 14;
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/* Decrement the loop counter */
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blkCnt--;
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}
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#else
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/* Run the below code for Cortex-M0 */
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while(numSamples > 0u)
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{
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a0 = *pSrcA++;
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b0 = *pSrcA++;
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c0 = *pSrcB++;
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d0 = *pSrcB++;
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real_sum += ((q63_t)a0 * c0) >> 14;
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imag_sum += ((q63_t)a0 * d0) >> 14;
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real_sum -= ((q63_t)b0 * d0) >> 14;
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imag_sum += ((q63_t)b0 * c0) >> 14;
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/* Decrement the loop counter */
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numSamples--;
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}
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#endif /* #ifndef ARM_MATH_CM0_FAMILY */
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/* Store the real and imaginary results in 16.48 format */
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*realResult = real_sum;
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*imagResult = imag_sum;
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}
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/**
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* @} end of cmplx_dot_prod group
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*/
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