// File: STM32F030_070.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F030x4/x6/x8/xC, STM32F070x6/xB Reference manual (RM0360)
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// refer to STM32F030x4 STM32F030x6, STM32F030x8 STM32F030xC datasheet
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// STM32F070CB STM32F070RB, STM32F070C6 STM32F070F6 datasheet
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o.2> DBG_STANDBY <i> Debug standby mode
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// <o.1> DBG_STOP <i> Debug stop mode
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// </h>
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DbgMCU_CR = 0x00000006;
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// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.21> DBG_I2C1_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
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// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
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// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
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// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
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// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// </h>
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DbgMCU_APB1_Fz = 0x00000000;
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// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.18> DBG_TIM17_STOP <i> TIM17 counter stopped when core is halted
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// <o.17> DBG_TIM16_STOP <i> TIM16 counter stopped when core is halted
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// <o.16> DBG_TIM15_STOP <i> TIM15 counter stopped when core is halted
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// <o.11> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// <h> Flash Download Options
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// <o.0> Option Byte Loading <i> Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset)
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// </h>
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DoOptionByteLoading = 0x00000000;
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// <<< end of configuration section >>>
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