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2022-09-29 e1f35018c4dec304b00f50d9dbe12204fd57a623

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bfc108	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_ll_usart.c
	4	* @author MCD Application Team
	5	* @brief USART LL module driver.
	6	******************************************************************************
	7	* @attention
	8	*
	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	10	*
	11	* Redistribution and use in source and binary forms, with or without modification,
	12	* are permitted provided that the following conditions are met:
	13	* 1. Redistributions of source code must retain the above copyright notice,
	14	* this list of conditions and the following disclaimer.
	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	19	* may be used to endorse or promote products derived from this software
	20	* without specific prior written permission.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	******************************************************************************
	34	*/
	35	#if defined(USE_FULL_LL_DRIVER)
	36
	37	/* Includes ------------------------------------------------------------------*/
	38	#include "stm32f0xx_ll_usart.h"
	39	#include "stm32f0xx_ll_rcc.h"
	40	#include "stm32f0xx_ll_bus.h"
	41	#ifdef USE_FULL_ASSERT
	42	#include "stm32_assert.h"
	43	#else
	44	#define assert_param(expr) ((void)0U)
	45	#endif
	46
	47	/** @addtogroup STM32F0xx_LL_Driver
	48	* @{
	49	*/
	50
	51	#if defined (USART1) \|\| defined (USART2) \|\| defined (USART3) \|\| defined (USART4) \|\| defined (USART5) \|\| defined (USART6) \|\| defined (USART7) \|\| defined (USART8)
	52
	53	/** @addtogroup USART_LL
	54	* @{
	55	*/
	56
	57	/* Private types -------------------------------------------------------------*/
	58	/* Private variables ---------------------------------------------------------*/
	59	/* Private constants ---------------------------------------------------------*/
	60	/** @addtogroup USART_LL_Private_Constants
	61	* @{
	62	*/
	63
	64	/**
	65	* @}
	66	*/
	67
	68
	69	/* Private macros ------------------------------------------------------------*/
	70	/** @addtogroup USART_LL_Private_Macros
	71	* @{
	72	*/
	73
	74	/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
	75	* divided by the smallest oversampling used on the USART (i.e. 8) */
	76	#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 6000000U)
	77
	78	/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
	79	#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
	80
	81	/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
	82	#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
	83
	84	#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
	85	\|\| ((__VALUE__) == LL_USART_DIRECTION_RX) \
	86	\|\| ((__VALUE__) == LL_USART_DIRECTION_TX) \
	87	\|\| ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
	88
	89	#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
	90	\|\| ((__VALUE__) == LL_USART_PARITY_EVEN) \
	91	\|\| ((__VALUE__) == LL_USART_PARITY_ODD))
	92
	93	#if defined(USART_7BITS_SUPPORT)
	94	#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
	95	\|\| ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
	96	\|\| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
	97	#else
	98	#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
	99	\|\| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
	100	#endif
	101
	102	#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
	103	\|\| ((__VALUE__) == LL_USART_OVERSAMPLING_8))
	104
	105	#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
	106	\|\| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
	107
	108	#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
	109	\|\| ((__VALUE__) == LL_USART_PHASE_2EDGE))
	110
	111	#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
	112	\|\| ((__VALUE__) == LL_USART_POLARITY_HIGH))
	113
	114	#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
	115	\|\| ((__VALUE__) == LL_USART_CLOCK_ENABLE))
	116
	117	#if defined(USART_SMARTCARD_SUPPORT)
	118	#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
	119	\|\| ((__VALUE__) == LL_USART_STOPBITS_1) \
	120	\|\| ((__VALUE__) == LL_USART_STOPBITS_1_5) \
	121	\|\| ((__VALUE__) == LL_USART_STOPBITS_2))
	122	#else
	123	#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_1) \
	124	\|\| ((__VALUE__) == LL_USART_STOPBITS_2))
	125	#endif
	126
	127	#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
	128	\|\| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
	129	\|\| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
	130	\|\| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
	131
	132	/**
	133	* @}
	134	*/
	135
	136	/* Private function prototypes -----------------------------------------------*/
	137
	138	/* Exported functions --------------------------------------------------------*/
	139	/** @addtogroup USART_LL_Exported_Functions
	140	* @{
	141	*/
	142
	143	/** @addtogroup USART_LL_EF_Init
	144	* @{
	145	*/
	146
	147	/**
	148	* @brief De-initialize USART registers (Registers restored to their default values).
	149	* @param USARTx USART Instance
	150	* @retval An ErrorStatus enumeration value:
	151	* - SUCCESS: USART registers are de-initialized
	152	* - ERROR: USART registers are not de-initialized
	153	*/
	154	ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
	155	{
	156	ErrorStatus status = SUCCESS;
	157
	158	/* Check the parameters */
	159	assert_param(IS_UART_INSTANCE(USARTx));
	160
	161	if (USARTx == USART1)
	162	{
	163	/* Force reset of USART clock */
	164	LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART1);
	165
	166	/* Release reset of USART clock */
	167	LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART1);
	168	}
	169	#if defined(USART2)
	170	else if (USARTx == USART2)
	171	{
	172	/* Force reset of USART clock */
	173	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
	174
	175	/* Release reset of USART clock */
	176	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
	177	}
	178	#endif /* USART2 */
	179	#if defined(USART3)
	180	else if (USARTx == USART3)
	181	{
	182	/* Force reset of USART clock */
	183	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
	184
	185	/* Release reset of USART clock */
	186	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
	187	}
	188	#endif /* USART3 */
	189	#if defined(USART4)
	190	else if (USARTx == USART4)
	191	{
	192	/* Force reset of USART clock */
	193	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4);
	194
	195	/* Release reset of USART clock */
	196	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4);
	197	}
	198	#endif /* USART4 */
	199	#if defined(USART5)
	200	else if (USARTx == USART5)
	201	{
	202	/* Force reset of USART clock */
	203	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5);
	204
	205	/* Release reset of USART clock */
	206	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5);
	207	}
	208	#endif /* USART5 */
	209	#if defined(USART6)
	210	else if (USARTx == USART6)
	211	{
	212	/* Force reset of USART clock */
	213	LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART6);
	214
	215	/* Release reset of USART clock */
	216	LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART6);
	217	}
	218	#endif /* USART6 */
	219	#if defined(USART7)
	220	else if (USARTx == USART7)
	221	{
	222	/* Force reset of USART clock */
	223	LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART7);
	224
	225	/* Release reset of USART clock */
	226	LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART7);
	227	}
	228	#endif /* USART7 */
	229	#if defined(USART8)
	230	else if (USARTx == USART8)
	231	{
	232	/* Force reset of USART clock */
	233	LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART8);
	234
	235	/* Release reset of USART clock */
	236	LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART8);
	237	}
	238	#endif /* USART8 */
	239	else
	240	{
	241	status = ERROR;
	242	}
	243
	244	return (status);
	245	}
	246
	247	/**
	248	* @brief Initialize USART registers according to the specified
	249	* parameters in USART_InitStruct.
	250	* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
	251	* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
	252	* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
	253	* @param USARTx USART Instance
	254	* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
	255	* that contains the configuration information for the specified USART peripheral.
	256	* @retval An ErrorStatus enumeration value:
	257	* - SUCCESS: USART registers are initialized according to USART_InitStruct content
	258	* - ERROR: Problem occurred during USART Registers initialization
	259	*/
	260	ErrorStatus LL_USART_Init(USART_TypeDef USARTx, LL_USART_InitTypeDef USART_InitStruct)
	261	{
	262	ErrorStatus status = ERROR;
	263	uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
	264	#if defined(STM32F030x8) \|\| defined(STM32F030xC) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070x6) \|\| defined(STM32F070xB) \|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	265	LL_RCC_ClocksTypeDef RCC_Clocks;
	266	#endif
	267
	268	/* Check the parameters */
	269	assert_param(IS_UART_INSTANCE(USARTx));
	270	assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
	271	assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
	272	assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
	273	assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
	274	assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
	275	assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
	276	assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
	277
	278	/* USART needs to be in disabled state, in order to be able to configure some bits in
	279	CRx registers */
	280	if (LL_USART_IsEnabled(USARTx) == 0U)
	281	{
	282	/*---------------------------- USART CR1 Configuration ---------------------
	283	* Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
	284	* - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
	285	* - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
	286	* - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
	287	* - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
	288	*/
	289	MODIFY_REG(USARTx->CR1,
	290	(USART_CR1_M \| USART_CR1_PCE \| USART_CR1_PS \|
	291	USART_CR1_TE \| USART_CR1_RE \| USART_CR1_OVER8),
	292	(USART_InitStruct->DataWidth \| USART_InitStruct->Parity \|
	293	USART_InitStruct->TransferDirection \| USART_InitStruct->OverSampling));
	294
	295	/*---------------------------- USART CR2 Configuration ---------------------
	296	* Configure USARTx CR2 (Stop bits) with parameters:
	297	* - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
	298	* - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
	299	*/
	300	LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
	301
	302	/*---------------------------- USART CR3 Configuration ---------------------
	303	* Configure USARTx CR3 (Hardware Flow Control) with parameters:
	304	* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
	305	*/
	306	LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
	307
	308	/*---------------------------- USART BRR Configuration ---------------------
	309	* Retrieve Clock frequency used for USART Peripheral
	310	*/
	311	if (USARTx == USART1)
	312	{
	313	periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
	314	}
	315	#if defined(USART2)
	316	else if (USARTx == USART2)
	317	{
	318	#if defined (RCC_CFGR3_USART2SW)
	319	periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
	320	#else
	321	/* USART2 clock is PCLK */
	322	LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
	323	periphclk = RCC_Clocks.PCLK1_Frequency;
	324	#endif
	325	}
	326	#endif /* USART2 */
	327	#if defined(USART3)
	328	else if (USARTx == USART3)
	329	{
	330	#if defined (RCC_CFGR3_USART3SW)
	331	periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
	332	#else
	333	/* USART3 clock is PCLK */
	334	LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
	335	periphclk = RCC_Clocks.PCLK1_Frequency;
	336	#endif
	337	}
	338	#endif /* USART3 */
	339	#if defined(USART4)
	340	else if (USARTx == USART4)
	341	{
	342	/* USART4 clock is PCLK */
	343	LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
	344	periphclk = RCC_Clocks.PCLK1_Frequency;
	345	}
	346	#endif /* USART4 */
	347	#if defined(USART5)
	348	else if (USARTx == USART5)
	349	{
	350	/* USART5 clock is PCLK */
	351	LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
	352	periphclk = RCC_Clocks.PCLK1_Frequency;
	353	}
	354	#endif /* USART5 */
	355	#if defined(USART6)
	356	else if (USARTx == USART6)
	357	{
	358	/* USART6 clock is PCLK */
	359	LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
	360	periphclk = RCC_Clocks.PCLK1_Frequency;
	361	}
	362	#endif /* USART6 */
	363	#if defined(USART7)
	364	else if (USARTx == USART7)
	365	{
	366	/* USART7 clock is PCLK */
	367	LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
	368	periphclk = RCC_Clocks.PCLK1_Frequency;
	369	}
	370	#endif /* USART7 */
	371	#if defined(USART8)
	372	else if (USARTx == USART8)
	373	{
	374	/* USART8 clock is PCLK */
	375	LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
	376	periphclk = RCC_Clocks.PCLK1_Frequency;
	377	}
	378	#endif /* USART8 */
	379	else
	380	{
	381	/* Nothing to do, as error code is already assigned to ERROR value */
	382	}
	383
	384	/* Configure the USART Baud Rate :
	385	- valid baud rate value (different from 0) is required
	386	- Peripheral clock as returned by RCC service, should be valid (different from 0).
	387	*/
	388	if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
	389	&& (USART_InitStruct->BaudRate != 0U))
	390	{
	391	status = SUCCESS;
	392	LL_USART_SetBaudRate(USARTx,
	393	periphclk,
	394	USART_InitStruct->OverSampling,
	395	USART_InitStruct->BaudRate);
	396
	397	/* Check BRR is greater than or equal to 16d */
	398	assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
	399
	400	/* Check BRR is greater than or equal to 16d */
	401	assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
	402	}
	403	}
	404	/* Endif (=> USART not in Disabled state => return ERROR) */
	405
	406	return (status);
	407	}
	408
	409	/**
	410	* @brief Set each @ref LL_USART_InitTypeDef field to default value.
	411	* @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
	412	* whose fields will be set to default values.
	413	* @retval None
	414	*/
	415
	416	void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
	417	{
	418	/* Set USART_InitStruct fields to default values */
	419	USART_InitStruct->BaudRate = 9600U;
	420	USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
	421	USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
	422	USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
	423	USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
	424	USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
	425	USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
	426	}
	427
	428	/**
	429	* @brief Initialize USART Clock related settings according to the
	430	* specified parameters in the USART_ClockInitStruct.
	431	* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
	432	* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
	433	* @param USARTx USART Instance
	434	* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
	435	* that contains the Clock configuration information for the specified USART peripheral.
	436	* @retval An ErrorStatus enumeration value:
	437	* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
	438	* - ERROR: Problem occurred during USART Registers initialization
	439	*/
	440	ErrorStatus LL_USART_ClockInit(USART_TypeDef USARTx, LL_USART_ClockInitTypeDef USART_ClockInitStruct)
	441	{
	442	ErrorStatus status = SUCCESS;
	443
	444	/* Check USART Instance and Clock signal output parameters */
	445	assert_param(IS_UART_INSTANCE(USARTx));
	446	assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
	447
	448	/* USART needs to be in disabled state, in order to be able to configure some bits in
	449	CRx registers */
	450	if (LL_USART_IsEnabled(USARTx) == 0U)
	451	{
	452	/---------------------------- USART CR2 Configuration -----------------------/
	453	/* If Clock signal has to be output */
	454	if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
	455	{
	456	/* Deactivate Clock signal delivery :
	457	* - Disable Clock Output: USART_CR2_CLKEN cleared
	458	*/
	459	LL_USART_DisableSCLKOutput(USARTx);
	460	}
	461	else
	462	{
	463	/* Ensure USART instance is USART capable */
	464	assert_param(IS_USART_INSTANCE(USARTx));
	465
	466	/* Check clock related parameters */
	467	assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
	468	assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
	469	assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
	470
	471	/*---------------------------- USART CR2 Configuration -----------------------
	472	* Configure USARTx CR2 (Clock signal related bits) with parameters:
	473	* - Enable Clock Output: USART_CR2_CLKEN set
	474	* - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
	475	* - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
	476	* - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
	477	*/
	478	MODIFY_REG(USARTx->CR2,
	479	USART_CR2_CLKEN \| USART_CR2_CPHA \| USART_CR2_CPOL \| USART_CR2_LBCL,
	480	USART_CR2_CLKEN \| USART_ClockInitStruct->ClockPolarity \|
	481	USART_ClockInitStruct->ClockPhase \| USART_ClockInitStruct->LastBitClockPulse);
	482	}
	483	}
	484	/* Else (USART not in Disabled state => return ERROR */
	485	else
	486	{
	487	status = ERROR;
	488	}
	489
	490	return (status);
	491	}
	492
	493	/**
	494	* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
	495	* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
	496	* whose fields will be set to default values.
	497	* @retval None
	498	*/
	499	void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
	500	{
	501	/* Set LL_USART_ClockInitStruct fields with default values */
	502	USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
	503	USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
	504	USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
	505	USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
	506	}
	507
	508	/**
	509	* @}
	510	*/
	511
	512	/**
	513	* @}
	514	*/
	515
	516	/**
	517	* @}
	518	*/
	519
	520	#endif /* USART1 \|\| USART2\|\| USART3 \|\| USART4 \|\| USART5 \|\| USART6 \|\| USART7 \|\| USART8 */
	521
	522	/**
	523	* @}
	524	*/
	525
	526	#endif /* USE_FULL_LL_DRIVER */
	527
	528	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
	529