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2022-10-17 d69aae90ede578aaebc355dafd3496993ccea126

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bfc108	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_hal_spi.c
	4	* @author MCD Application Team
	5	* @brief SPI HAL module driver.
	6	* This file provides firmware functions to manage the following
	7	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
	8	* + Initialization and de-initialization functions
	9	* + IO operation functions
	10	* + Peripheral Control functions
	11	* + Peripheral State functions
	12	*
	13	@verbatim
	14	==============================================================================
	15	##### How to use this driver #####
	16	==============================================================================
	17	[..]
	18	The SPI HAL driver can be used as follows:
	19
	20	(#) Declare a SPI_HandleTypeDef handle structure, for example:
	21	SPI_HandleTypeDef hspi;
	22
	23	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
	24	(##) Enable the SPIx interface clock
	25	(##) SPI pins configuration
	26	(+++) Enable the clock for the SPI GPIOs
	27	(+++) Configure these SPI pins as alternate function push-pull
	28	(##) NVIC configuration if you need to use interrupt process
	29	(+++) Configure the SPIx interrupt priority
	30	(+++) Enable the NVIC SPI IRQ handle
	31	(##) DMA Configuration if you need to use DMA process
	32	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
	33	(+++) Enable the DMAx clock
	34	(+++) Configure the DMA handle parameters
	35	(+++) Configure the DMA Tx or Rx Stream/Channel
	36	(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
	37	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
	38
	39	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
	40	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
	41
	42	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
	43	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
	44	by calling the customized HAL_SPI_MspInit() API.
	45	[..]
	46	Circular mode restriction:
	47	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
	48	(##) Master 2Lines RxOnly
	49	(##) Master 1Line Rx
	50	(#) The CRC feature is not managed when the DMA circular mode is enabled
	51	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
	52	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
	53	[..]
	54	Master Receive mode restriction:
	55	(#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
	56	bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
	57	does not initiate a new transfer the following procedure has to be respected:
	58	(##) HAL_SPI_DeInit()
	59	(##) HAL_SPI_Init()
	60	[..]
	61	The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI
	62	modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the
	63	maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
	64	the APBx peripheral clock frequency (fPCLK) used by the SPI instance.
	65
	66	[..]
	67	Data buffer address alignment restriction:
	68	(#) In case more than 1 byte is requested to be transferred, the HAL SPI uses 16-bit access for data buffer.
	69	But there is no support for unaligned accesses on the Cortex-M0 processor.
	70	So, if the user wants to transfer more than 1 byte, it shall ensure that 16-bit aligned address is used for:
	71	(##) pData parameter in HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_Receive() and HAL_SPI_Receive_IT()
	72	(##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT()
	73	(#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA()
	74	and HAL_SPI_TransmitReceive_DMA().
	75
	76	@endverbatim
	77
	78	Additional table :
	79
	80	DataSize = SPI_DATASIZE_8BIT:
	81	+----------------------------------------------------------------------------------------------+
	82	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
	83	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
	84	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
	85	\|==============================================================================================\|
	86	\| T \| Polling \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
	87	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	88	\| / \| Interrupt \| Fpclk/4 \| Fpclk/16 \| NA \| NA \| NA \| NA \|
	89	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	90	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
	91	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
	92	\| \| Polling \| Fpclk/4 \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \|
	93	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	94	\| R \| Interrupt \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \| Fpclk/4 \|
	95	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	96	\| \| DMA \| Fpclk/4 \| Fpclk/2 \| Fpclk/2 \| Fpclk/16 \| Fpclk/2 \| Fpclk/16 \|
	97	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
	98	\| \| Polling \| Fpclk/8 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/8 \|
	99	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	100	\| T \| Interrupt \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/16 \| Fpclk/8 \|
	101	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	102	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/16 \|
	103	+----------------------------------------------------------------------------------------------+
	104
	105	DataSize = SPI_DATASIZE_16BIT:
	106	+----------------------------------------------------------------------------------------------+
	107	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
	108	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
	109	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
	110	\|==============================================================================================\|
	111	\| T \| Polling \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
	112	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	113	\| / \| Interrupt \| Fpclk/4 \| Fpclk/16 \| NA \| NA \| NA \| NA \|
	114	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	115	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
	116	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
	117	\| \| Polling \| Fpclk/4 \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \|
	118	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	119	\| R \| Interrupt \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \| Fpclk/4 \|
	120	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	121	\| \| DMA \| Fpclk/4 \| Fpclk/2 \| Fpclk/2 \| Fpclk/16 \| Fpclk/2 \| Fpclk/16 \|
	122	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
	123	\| \| Polling \| Fpclk/8 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/8 \|
	124	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	125	\| T \| Interrupt \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/16 \| Fpclk/8 \|
	126	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
	127	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/16 \|
	128	+----------------------------------------------------------------------------------------------+
	129	@note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
	130	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
	131	@note
	132	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
	133	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
	134	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
	135
	136	******************************************************************************
	137	* @attention
	138	*
	139	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	140	*
	141	* Redistribution and use in source and binary forms, with or without modification,
	142	* are permitted provided that the following conditions are met:
	143	* 1. Redistributions of source code must retain the above copyright notice,
	144	* this list of conditions and the following disclaimer.
	145	* 2. Redistributions in binary form must reproduce the above copyright notice,
	146	* this list of conditions and the following disclaimer in the documentation
	147	* and/or other materials provided with the distribution.
	148	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	149	* may be used to endorse or promote products derived from this software
	150	* without specific prior written permission.
	151	*
	152	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	153	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	154	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	155	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	156	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	157	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	158	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	159	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	160	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	161	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	162	*
	163	******************************************************************************
	164	*/
	165
	166	/* Includes ------------------------------------------------------------------*/
	167	#include "stm32f0xx_hal.h"
	168
	169	/** @addtogroup STM32F0xx_HAL_Driver
	170	* @{
	171	*/
	172
	173	/** @defgroup SPI SPI
	174	* @brief SPI HAL module driver
	175	* @{
	176	*/
	177	#ifdef HAL_SPI_MODULE_ENABLED
	178
	179	/* Private typedef -----------------------------------------------------------*/
	180	/* Private defines -----------------------------------------------------------*/
	181	/** @defgroup SPI_Private_Constants SPI Private Constants
	182	* @{
	183	*/
	184	#define SPI_DEFAULT_TIMEOUT 100U
	185	/**
	186	* @}
	187	*/
	188
	189	/* Private macros ------------------------------------------------------------*/
	190	/* Private variables ---------------------------------------------------------*/
	191	/* Private function prototypes -----------------------------------------------*/
	192	/** @defgroup SPI_Private_Functions SPI Private Functions
	193	* @{
	194	*/
	195	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
	196	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
	197	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
	198	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
	199	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
	200	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
	201	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
	202	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
	203	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
	204	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
	205	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
	206	uint32_t Timeout, uint32_t Tickstart);
	207	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
	208	uint32_t Timeout, uint32_t Tickstart);
	209	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
	210	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
	211	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
	212	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
	213	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
	214	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
	215	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
	216	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
	217	#if (USE_SPI_CRC != 0U)
	218	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
	219	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
	220	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
	221	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
	222	#endif /* USE_SPI_CRC */
	223	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
	224	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
	225	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
	226	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
	227	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
	228	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
	229	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
	230	/**
	231	* @}
	232	*/
	233
	234	/* Exported functions --------------------------------------------------------*/
	235	/** @defgroup SPI_Exported_Functions SPI Exported Functions
	236	* @{
	237	*/
	238
	239	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
	240	* @brief Initialization and Configuration functions
	241	*
	242	@verbatim
	243	===============================================================================
	244	##### Initialization and de-initialization functions #####
	245	===============================================================================
	246	[..] This subsection provides a set of functions allowing to initialize and
	247	de-initialize the SPIx peripheral:
	248
	249	(+) User must implement HAL_SPI_MspInit() function in which he configures
	250	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
	251
	252	(+) Call the function HAL_SPI_Init() to configure the selected device with
	253	the selected configuration:
	254	(++) Mode
	255	(++) Direction
	256	(++) Data Size
	257	(++) Clock Polarity and Phase
	258	(++) NSS Management
	259	(++) BaudRate Prescaler
	260	(++) FirstBit
	261	(++) TIMode
	262	(++) CRC Calculation
	263	(++) CRC Polynomial if CRC enabled
	264	(++) CRC Length, used only with Data8 and Data16
	265	(++) FIFO reception threshold
	266
	267	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
	268	of the selected SPIx peripheral.
	269
	270	@endverbatim
	271	* @{
	272	*/
	273
	274	/**
	275	* @brief Initialize the SPI according to the specified parameters
	276	* in the SPI_InitTypeDef and initialize the associated handle.
	277	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	278	* the configuration information for SPI module.
	279	* @retval HAL status
	280	*/
	281	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
	282	{
	283	uint32_t frxth;
	284
	285	/* Check the SPI handle allocation */
	286	if (hspi == NULL)
	287	{
	288	return HAL_ERROR;
	289	}
	290
	291	/* Check the parameters */
	292	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
	293	assert_param(IS_SPI_MODE(hspi->Init.Mode));
	294	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
	295	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
	296	assert_param(IS_SPI_NSS(hspi->Init.NSS));
	297	assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
	298	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
	299	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
	300	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
	301	if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
	302	{
	303	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
	304	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
	305	}
	306	#if (USE_SPI_CRC != 0U)
	307	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
	308	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	309	{
	310	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
	311	assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
	312	}
	313	#else
	314	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
	315	#endif /* USE_SPI_CRC */
	316
	317	if (hspi->State == HAL_SPI_STATE_RESET)
	318	{
	319	/* Allocate lock resource and initialize it */
	320	hspi->Lock = HAL_UNLOCKED;
	321
	322	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
	323	HAL_SPI_MspInit(hspi);
	324	}
	325
	326	hspi->State = HAL_SPI_STATE_BUSY;
	327
	328	/* Disable the selected SPI peripheral */
	329	__HAL_SPI_DISABLE(hspi);
	330
	331	/* Align by default the rs fifo threshold on the data size */
	332	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	333	{
	334	frxth = SPI_RXFIFO_THRESHOLD_HF;
	335	}
	336	else
	337	{
	338	frxth = SPI_RXFIFO_THRESHOLD_QF;
	339	}
	340
	341	/* CRC calculation is valid only for 16Bit and 8 Bit */
	342	if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
	343	{
	344	/* CRC must be disabled */
	345	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
	346	}
	347
	348	/* Align the CRC Length on the data size */
	349	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
	350	{
	351	/* CRC Length aligned on the data size : value set by default */
	352	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	353	{
	354	hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
	355	}
	356	else
	357	{
	358	hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
	359	}
	360	}
	361
	362	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
	363	/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
	364	Communication speed, First bit and CRC calculation state */
	365	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \|
	366	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
	367	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation));
	368	#if (USE_SPI_CRC != 0U)
	369	/* Configure : CRC Length */
	370	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
	371	{
	372	hspi->Instance->CR1 \|= SPI_CR1_CRCL;
	373	}
	374	#endif /* USE_SPI_CRC */
	375
	376	/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */
	377	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) \| hspi->Init.TIMode \|
	378	hspi->Init.NSSPMode \| hspi->Init.DataSize) \| frxth);
	379
	380	#if (USE_SPI_CRC != 0U)
	381	/---------------------------- SPIx CRCPOLY Configuration ------------------/
	382	/* Configure : CRC Polynomial */
	383	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	384	{
	385	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
	386	}
	387	#endif /* USE_SPI_CRC */
	388
	389	#if defined(SPI_I2SCFGR_I2SMOD)
	390	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
	391	CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
	392	#endif /* SPI_I2SCFGR_I2SMOD */
	393
	394	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	395	hspi->State = HAL_SPI_STATE_READY;
	396
	397	return HAL_OK;
	398	}
	399
	400	/**
	401	* @brief De-Initialize the SPI peripheral.
	402	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	403	* the configuration information for SPI module.
	404	* @retval HAL status
	405	*/
	406	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
	407	{
	408	/* Check the SPI handle allocation */
	409	if (hspi == NULL)
	410	{
	411	return HAL_ERROR;
	412	}
	413
	414	/* Check SPI Instance parameter */
	415	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
	416
	417	hspi->State = HAL_SPI_STATE_BUSY;
	418
	419	/* Disable the SPI Peripheral Clock */
	420	__HAL_SPI_DISABLE(hspi);
	421
	422	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
	423	HAL_SPI_MspDeInit(hspi);
	424
	425	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	426	hspi->State = HAL_SPI_STATE_RESET;
	427
	428	/* Release Lock */
	429	__HAL_UNLOCK(hspi);
	430
	431	return HAL_OK;
	432	}
	433
	434	/**
	435	* @brief Initialize the SPI MSP.
	436	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	437	* the configuration information for SPI module.
	438	* @retval None
	439	*/
	440	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
	441	{
	442	/* Prevent unused argument(s) compilation warning */
	443	UNUSED(hspi);
	444
	445	/* NOTE : This function should not be modified, when the callback is needed,
	446	the HAL_SPI_MspInit should be implemented in the user file
	447	*/
	448	}
	449
	450	/**
	451	* @brief De-Initialize the SPI MSP.
	452	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	453	* the configuration information for SPI module.
	454	* @retval None
	455	*/
	456	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
	457	{
	458	/* Prevent unused argument(s) compilation warning */
	459	UNUSED(hspi);
	460
	461	/* NOTE : This function should not be modified, when the callback is needed,
	462	the HAL_SPI_MspDeInit should be implemented in the user file
	463	*/
	464	}
	465
	466	/**
	467	* @}
	468	*/
	469
	470	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
	471	* @brief Data transfers functions
	472	*
	473	@verbatim
	474	==============================================================================
	475	##### IO operation functions #####
	476	===============================================================================
	477	[..]
	478	This subsection provides a set of functions allowing to manage the SPI
	479	data transfers.
	480
	481	[..] The SPI supports master and slave mode :
	482
	483	(#) There are two modes of transfer:
	484	(++) Blocking mode: The communication is performed in polling mode.
	485	The HAL status of all data processing is returned by the same function
	486	after finishing transfer.
	487	(++) No-Blocking mode: The communication is performed using Interrupts
	488	or DMA, These APIs return the HAL status.
	489	The end of the data processing will be indicated through the
	490	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
	491	using DMA mode.
	492	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
	493	will be executed respectively at the end of the transmit or Receive process
	494	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
	495
	496	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
	497	exist for 1Line (simplex) and 2Lines (full duplex) modes.
	498
	499	@endverbatim
	500	* @{
	501	*/
	502
	503	/**
	504	* @brief Transmit an amount of data in blocking mode.
	505	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	506	* the configuration information for SPI module.
	507	* @param pData pointer to data buffer
	508	* @param Size amount of data to be sent
	509	* @param Timeout Timeout duration
	510	* @retval HAL status
	511	*/
	512	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
	513	{
	514	uint32_t tickstart = 0U;
	515	HAL_StatusTypeDef errorcode = HAL_OK;
	516
	517	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (Size > 1U))
	518	{
	519	/* in this case, 16-bit access is performed on Data
	520	So, check Data is 16-bit aligned address */
	521	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
	522	}
	523
	524	/* Check Direction parameter */
	525	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
	526
	527	/* Process Locked */
	528	__HAL_LOCK(hspi);
	529
	530	/* Init tickstart for timeout management*/
	531	tickstart = HAL_GetTick();
	532
	533	if (hspi->State != HAL_SPI_STATE_READY)
	534	{
	535	errorcode = HAL_BUSY;
	536	goto error;
	537	}
	538
	539	if ((pData == NULL) \|\| (Size == 0U))
	540	{
	541	errorcode = HAL_ERROR;
	542	goto error;
	543	}
	544
	545	/* Set the transaction information */
	546	hspi->State = HAL_SPI_STATE_BUSY_TX;
	547	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	548	hspi->pTxBuffPtr = (uint8_t *)pData;
	549	hspi->TxXferSize = Size;
	550	hspi->TxXferCount = Size;
	551
	552	/Init field not used in handle to zero /
	553	hspi->pRxBuffPtr = (uint8_t *)NULL;
	554	hspi->RxXferSize = 0U;
	555	hspi->RxXferCount = 0U;
	556	hspi->TxISR = NULL;
	557	hspi->RxISR = NULL;
	558
	559	/* Configure communication direction : 1Line */
	560	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
	561	{
	562	SPI_1LINE_TX(hspi);
	563	}
	564
	565	#if (USE_SPI_CRC != 0U)
	566	/* Reset CRC Calculation */
	567	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	568	{
	569	SPI_RESET_CRC(hspi);
	570	}
	571	#endif /* USE_SPI_CRC */
	572
	573	/* Check if the SPI is already enabled */
	574	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
	575	{
	576	/* Enable SPI peripheral */
	577	__HAL_SPI_ENABLE(hspi);
	578	}
	579
	580	/* Transmit data in 16 Bit mode */
	581	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	582	{
	583	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
	584	{
	585	hspi->Instance->DR = ((uint16_t )pData);
	586	pData += sizeof(uint16_t);
	587	hspi->TxXferCount--;
	588	}
	589	/* Transmit data in 16 Bit mode */
	590	while (hspi->TxXferCount > 0U)
	591	{
	592	/* Wait until TXE flag is set to send data */
	593	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
	594	{
	595	hspi->Instance->DR = ((uint16_t )pData);
	596	pData += sizeof(uint16_t);
	597	hspi->TxXferCount--;
	598	}
	599	else
	600	{
	601	/* Timeout management */
	602	if ((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
	603	{
	604	errorcode = HAL_TIMEOUT;
	605	goto error;
	606	}
	607	}
	608	}
	609	}
	610	/* Transmit data in 8 Bit mode */
	611	else
	612	{
	613	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
	614	{
	615	if (hspi->TxXferCount > 1U)
	616	{
	617	/* write on the data register in packing mode */
	618	hspi->Instance->DR = ((uint16_t )pData);
	619	pData += sizeof(uint16_t);
	620	hspi->TxXferCount -= 2U;
	621	}
	622	else
	623	{
	624	((__IO uint8_t )&hspi->Instance->DR) = (*pData++);
	625	hspi->TxXferCount--;
	626	}
	627	}
	628	while (hspi->TxXferCount > 0U)
	629	{
	630	/* Wait until TXE flag is set to send data */
	631	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
	632	{
	633	if (hspi->TxXferCount > 1U)
	634	{
	635	/* write on the data register in packing mode */
	636	hspi->Instance->DR = ((uint16_t )pData);
	637	pData += sizeof(uint16_t);
	638	hspi->TxXferCount -= 2U;
	639	}
	640	else
	641	{
	642	((__IO uint8_t )&hspi->Instance->DR) = (*pData++);
	643	hspi->TxXferCount--;
	644	}
	645	}
	646	else
	647	{
	648	/* Timeout management */
	649	if ((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
	650	{
	651	errorcode = HAL_TIMEOUT;
	652	goto error;
	653	}
	654	}
	655	}
	656	}
	657	#if (USE_SPI_CRC != 0U)
	658	/* Enable CRC Transmission */
	659	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	660	{
	661	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
	662	}
	663	#endif /* USE_SPI_CRC */
	664
	665	/* Check the end of the transaction */
	666	if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
	667	{
	668	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
	669	}
	670
	671	/* Clear overrun flag in 2 Lines communication mode because received is not read */
	672	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
	673	{
	674	__HAL_SPI_CLEAR_OVRFLAG(hspi);
	675	}
	676
	677	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
	678	{
	679	errorcode = HAL_ERROR;
	680	}
	681
	682	error:
	683	hspi->State = HAL_SPI_STATE_READY;
	684	/* Process Unlocked */
	685	__HAL_UNLOCK(hspi);
	686	return errorcode;
	687	}
	688
	689	/**
	690	* @brief Receive an amount of data in blocking mode.
	691	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	692	* the configuration information for SPI module.
	693	* @param pData pointer to data buffer
	694	* @param Size amount of data to be received
	695	* @param Timeout Timeout duration
	696	* @retval HAL status
	697	*/
	698	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
	699	{
	700	#if (USE_SPI_CRC != 0U)
	701	__IO uint16_t tmpreg = 0U;
	702	#endif /* USE_SPI_CRC */
	703	uint32_t tickstart = 0U;
	704	HAL_StatusTypeDef errorcode = HAL_OK;
	705
	706	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (Size > 1U))
	707	{
	708	/* in this case, 16-bit access is performed on Data
	709	So, check Data is 16-bit aligned address */
	710	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
	711	}
	712
	713	if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
	714	{
	715	hspi->State = HAL_SPI_STATE_BUSY_RX;
	716	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
	717	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
	718	}
	719
	720	/* Process Locked */
	721	__HAL_LOCK(hspi);
	722
	723	/* Init tickstart for timeout management*/
	724	tickstart = HAL_GetTick();
	725
	726	if (hspi->State != HAL_SPI_STATE_READY)
	727	{
	728	errorcode = HAL_BUSY;
	729	goto error;
	730	}
	731
	732	if ((pData == NULL) \|\| (Size == 0U))
	733	{
	734	errorcode = HAL_ERROR;
	735	goto error;
	736	}
	737
	738	/* Set the transaction information */
	739	hspi->State = HAL_SPI_STATE_BUSY_RX;
	740	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	741	hspi->pRxBuffPtr = (uint8_t *)pData;
	742	hspi->RxXferSize = Size;
	743	hspi->RxXferCount = Size;
	744
	745	/Init field not used in handle to zero /
	746	hspi->pTxBuffPtr = (uint8_t *)NULL;
	747	hspi->TxXferSize = 0U;
	748	hspi->TxXferCount = 0U;
	749	hspi->RxISR = NULL;
	750	hspi->TxISR = NULL;
	751
	752	#if (USE_SPI_CRC != 0U)
	753	/* Reset CRC Calculation */
	754	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	755	{
	756	SPI_RESET_CRC(hspi);
	757	/* this is done to handle the CRCNEXT before the latest data */
	758	hspi->RxXferCount--;
	759	}
	760	#endif /* USE_SPI_CRC */
	761
	762	/* Set the Rx FiFo threshold */
	763	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	764	{
	765	/* set fiforxthresold according the reception data length: 16bit */
	766	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	767	}
	768	else
	769	{
	770	/* set fiforxthresold according the reception data length: 8bit */
	771	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	772	}
	773
	774	/* Configure communication direction: 1Line */
	775	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
	776	{
	777	SPI_1LINE_RX(hspi);
	778	}
	779
	780	/* Check if the SPI is already enabled */
	781	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
	782	{
	783	/* Enable SPI peripheral */
	784	__HAL_SPI_ENABLE(hspi);
	785	}
	786
	787	/* Receive data in 8 Bit mode */
	788	if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
	789	{
	790	/* Transfer loop */
	791	while (hspi->RxXferCount > 0U)
	792	{
	793	/* Check the RXNE flag */
	794	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
	795	{
	796	/* read the received data */
	797	(* (uint8_t )pData) = (__IO uint8_t *)&hspi->Instance->DR;
	798	pData += sizeof(uint8_t);
	799	hspi->RxXferCount--;
	800	}
	801	else
	802	{
	803	/* Timeout management */
	804	if ((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
	805	{
	806	errorcode = HAL_TIMEOUT;
	807	goto error;
	808	}
	809	}
	810	}
	811	}
	812	else
	813	{
	814	/* Transfer loop */
	815	while (hspi->RxXferCount > 0U)
	816	{
	817	/* Check the RXNE flag */
	818	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
	819	{
	820	((uint16_t )pData) = hspi->Instance->DR;
	821	pData += sizeof(uint16_t);
	822	hspi->RxXferCount--;
	823	}
	824	else
	825	{
	826	/* Timeout management */
	827	if ((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
	828	{
	829	errorcode = HAL_TIMEOUT;
	830	goto error;
	831	}
	832	}
	833	}
	834	}
	835
	836	#if (USE_SPI_CRC != 0U)
	837	/* Handle the CRC Transmission */
	838	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	839	{
	840	/* freeze the CRC before the latest data */
	841	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
	842
	843	/* Read the latest data */
	844	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
	845	{
	846	/* the latest data has not been received */
	847	errorcode = HAL_TIMEOUT;
	848	goto error;
	849	}
	850
	851	/* Receive last data in 16 Bit mode */
	852	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	853	{
	854	((uint16_t )pData) = hspi->Instance->DR;
	855	}
	856	/* Receive last data in 8 Bit mode */
	857	else
	858	{
	859	((uint8_t )pData) = (__IO uint8_t )&hspi->Instance->DR;
	860	}
	861
	862	/* Wait the CRC data */
	863	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
	864	{
	865	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	866	errorcode = HAL_TIMEOUT;
	867	goto error;
	868	}
	869
	870	/* Read CRC to Flush DR and RXNE flag */
	871	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
	872	{
	873	tmpreg = hspi->Instance->DR;
	874	/* To avoid GCC warning */
	875	UNUSED(tmpreg);
	876	}
	877	else
	878	{
	879	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
	880	/* To avoid GCC warning */
	881	UNUSED(tmpreg);
	882
	883	if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
	884	{
	885	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
	886	{
	887	/* Error on the CRC reception */
	888	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	889	errorcode = HAL_TIMEOUT;
	890	goto error;
	891	}
	892	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
	893	/* To avoid GCC warning */
	894	UNUSED(tmpreg);
	895	}
	896	}
	897	}
	898	#endif /* USE_SPI_CRC */
	899
	900	/* Check the end of the transaction */
	901	if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
	902	{
	903	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
	904	}
	905
	906	#if (USE_SPI_CRC != 0U)
	907	/* Check if CRC error occurred */
	908	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
	909	{
	910	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	911	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
	912	}
	913	#endif /* USE_SPI_CRC */
	914
	915	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
	916	{
	917	errorcode = HAL_ERROR;
	918	}
	919
	920	error :
	921	hspi->State = HAL_SPI_STATE_READY;
	922	__HAL_UNLOCK(hspi);
	923	return errorcode;
	924	}
	925
	926	/**
	927	* @brief Transmit and Receive an amount of data in blocking mode.
	928	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	929	* the configuration information for SPI module.
	930	* @param pTxData pointer to transmission data buffer
	931	* @param pRxData pointer to reception data buffer
	932	* @param Size amount of data to be sent and received
	933	* @param Timeout Timeout duration
	934	* @retval HAL status
	935	*/
	936	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size,
	937	uint32_t Timeout)
	938	{
	939	uint32_t tmp = 0U, tmp1 = 0U;
	940	#if (USE_SPI_CRC != 0U)
	941	__IO uint16_t tmpreg = 0U;
	942	#endif /* USE_SPI_CRC */
	943	uint32_t tickstart = 0U;
	944	/* Variable used to alternate Rx and Tx during transfer */
	945	uint32_t txallowed = 1U;
	946	HAL_StatusTypeDef errorcode = HAL_OK;
	947
	948	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (Size > 1U))
	949	{
	950	/* in this case, 16-bit access is performed on Data
	951	So, check Data is 16-bit aligned address */
	952	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
	953	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
	954	}
	955
	956	/* Check Direction parameter */
	957	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
	958
	959	/* Process Locked */
	960	__HAL_LOCK(hspi);
	961
	962	/* Init tickstart for timeout management*/
	963	tickstart = HAL_GetTick();
	964
	965	tmp = hspi->State;
	966	tmp1 = hspi->Init.Mode;
	967
	968	if (!((tmp == HAL_SPI_STATE_READY) \|\| \
	969	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
	970	{
	971	errorcode = HAL_BUSY;
	972	goto error;
	973	}
	974
	975	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
	976	{
	977	errorcode = HAL_ERROR;
	978	goto error;
	979	}
	980
	981	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
	982	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
	983	{
	984	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
	985	}
	986
	987	/* Set the transaction information */
	988	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	989	hspi->pRxBuffPtr = (uint8_t *)pRxData;
	990	hspi->RxXferCount = Size;
	991	hspi->RxXferSize = Size;
	992	hspi->pTxBuffPtr = (uint8_t *)pTxData;
	993	hspi->TxXferCount = Size;
	994	hspi->TxXferSize = Size;
	995
	996	/Init field not used in handle to zero /
	997	hspi->RxISR = NULL;
	998	hspi->TxISR = NULL;
	999
	1000	#if (USE_SPI_CRC != 0U)
	1001	/* Reset CRC Calculation */
	1002	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	1003	{
	1004	SPI_RESET_CRC(hspi);
	1005	}
	1006	#endif /* USE_SPI_CRC */
	1007
	1008	/* Set the Rx Fifo threshold */
	1009	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount > 1U))
	1010	{
	1011	/* set fiforxthreshold according the reception data length: 16bit */
	1012	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1013	}
	1014	else
	1015	{
	1016	/* set fiforxthreshold according the reception data length: 8bit */
	1017	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1018	}
	1019
	1020	/* Check if the SPI is already enabled */
	1021	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
	1022	{
	1023	/* Enable SPI peripheral */
	1024	__HAL_SPI_ENABLE(hspi);
	1025	}
	1026
	1027	/* Transmit and Receive data in 16 Bit mode */
	1028	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	1029	{
	1030	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
	1031	{
	1032	hspi->Instance->DR = ((uint16_t )pTxData);
	1033	pTxData += sizeof(uint16_t);
	1034	hspi->TxXferCount--;
	1035	}
	1036	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
	1037	{
	1038	/* Check TXE flag */
	1039	if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
	1040	{
	1041	hspi->Instance->DR = ((uint16_t )pTxData);
	1042	pTxData += sizeof(uint16_t);
	1043	hspi->TxXferCount--;
	1044	/* Next Data is a reception (Rx). Tx not allowed */
	1045	txallowed = 0U;
	1046
	1047	#if (USE_SPI_CRC != 0U)
	1048	/* Enable CRC Transmission */
	1049	if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
	1050	{
	1051	/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
	1052	if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
	1053	{
	1054	SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
	1055	}
	1056	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
	1057	}
	1058	#endif /* USE_SPI_CRC */
	1059	}
	1060
	1061	/* Check RXNE flag */
	1062	if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
	1063	{
	1064	((uint16_t )pRxData) = hspi->Instance->DR;
	1065	pRxData += sizeof(uint16_t);
	1066	hspi->RxXferCount--;
	1067	/* Next Data is a Transmission (Tx). Tx is allowed */
	1068	txallowed = 1U;
	1069	}
	1070	if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
	1071	{
	1072	errorcode = HAL_TIMEOUT;
	1073	goto error;
	1074	}
	1075	}
	1076	}
	1077	/* Transmit and Receive data in 8 Bit mode */
	1078	else
	1079	{
	1080	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
	1081	{
	1082	if (hspi->TxXferCount > 1U)
	1083	{
	1084	hspi->Instance->DR = ((uint16_t )pTxData);
	1085	pTxData += sizeof(uint16_t);
	1086	hspi->TxXferCount -= 2U;
	1087	}
	1088	else
	1089	{
	1090	(__IO uint8_t )&hspi->Instance->DR = (*pTxData++);
	1091	hspi->TxXferCount--;
	1092	}
	1093	}
	1094	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
	1095	{
	1096	/* check TXE flag */
	1097	if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
	1098	{
	1099	if (hspi->TxXferCount > 1U)
	1100	{
	1101	hspi->Instance->DR = ((uint16_t )pTxData);
	1102	pTxData += sizeof(uint16_t);
	1103	hspi->TxXferCount -= 2U;
	1104	}
	1105	else
	1106	{
	1107	(__IO uint8_t )&hspi->Instance->DR = (*pTxData++);
	1108	hspi->TxXferCount--;
	1109	}
	1110	/* Next Data is a reception (Rx). Tx not allowed */
	1111	txallowed = 0U;
	1112
	1113	#if (USE_SPI_CRC != 0U)
	1114	/* Enable CRC Transmission */
	1115	if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
	1116	{
	1117	/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
	1118	if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
	1119	{
	1120	SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
	1121	}
	1122	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
	1123	}
	1124	#endif /* USE_SPI_CRC */
	1125	}
	1126
	1127	/* Wait until RXNE flag is reset */
	1128	if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
	1129	{
	1130	if (hspi->RxXferCount > 1U)
	1131	{
	1132	((uint16_t )pRxData) = hspi->Instance->DR;
	1133	pRxData += sizeof(uint16_t);
	1134	hspi->RxXferCount -= 2U;
	1135	if (hspi->RxXferCount <= 1U)
	1136	{
	1137	/* set fiforxthresold before to switch on 8 bit data size */
	1138	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1139	}
	1140	}
	1141	else
	1142	{
	1143	((uint8_t )pRxData++) = (__IO uint8_t )&hspi->Instance->DR;
	1144	hspi->RxXferCount--;
	1145	}
	1146	/* Next Data is a Transmission (Tx). Tx is allowed */
	1147	txallowed = 1U;
	1148	}
	1149	if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
	1150	{
	1151	errorcode = HAL_TIMEOUT;
	1152	goto error;
	1153	}
	1154	}
	1155	}
	1156
	1157	#if (USE_SPI_CRC != 0U)
	1158	/* Read CRC from DR to close CRC calculation process */
	1159	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	1160	{
	1161	/* Wait until TXE flag */
	1162	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
	1163	{
	1164	/* Error on the CRC reception */
	1165	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	1166	errorcode = HAL_TIMEOUT;
	1167	goto error;
	1168	}
	1169	/* Read CRC */
	1170	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
	1171	{
	1172	tmpreg = hspi->Instance->DR;
	1173	/* To avoid GCC warning */
	1174	UNUSED(tmpreg);
	1175	}
	1176	else
	1177	{
	1178	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
	1179	/* To avoid GCC warning */
	1180	UNUSED(tmpreg);
	1181
	1182	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
	1183	{
	1184	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
	1185	{
	1186	/* Error on the CRC reception */
	1187	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	1188	errorcode = HAL_TIMEOUT;
	1189	goto error;
	1190	}
	1191	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
	1192	/* To avoid GCC warning */
	1193	UNUSED(tmpreg);
	1194	}
	1195	}
	1196	}
	1197
	1198	/* Check if CRC error occurred */
	1199	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
	1200	{
	1201	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	1202	/* Clear CRC Flag */
	1203	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
	1204
	1205	errorcode = HAL_ERROR;
	1206	}
	1207	#endif /* USE_SPI_CRC */
	1208
	1209	/* Check the end of the transaction */
	1210	if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
	1211	{
	1212	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
	1213	}
	1214
	1215	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
	1216	{
	1217	errorcode = HAL_ERROR;
	1218	}
	1219
	1220	error :
	1221	hspi->State = HAL_SPI_STATE_READY;
	1222	__HAL_UNLOCK(hspi);
	1223	return errorcode;
	1224	}
	1225
	1226	/**
	1227	* @brief Transmit an amount of data in non-blocking mode with Interrupt.
	1228	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	1229	* the configuration information for SPI module.
	1230	* @param pData pointer to data buffer
	1231	* @param Size amount of data to be sent
	1232	* @retval HAL status
	1233	*/
	1234	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
	1235	{
	1236	HAL_StatusTypeDef errorcode = HAL_OK;
	1237
	1238	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (Size > 1U))
	1239	{
	1240	/* in this case, 16-bit access is performed on Data
	1241	So, check Data is 16-bit aligned address */
	1242	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
	1243	}
	1244
	1245	/* Check Direction parameter */
	1246	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
	1247
	1248	/* Process Locked */
	1249	__HAL_LOCK(hspi);
	1250
	1251	if ((pData == NULL) \|\| (Size == 0U))
	1252	{
	1253	errorcode = HAL_ERROR;
	1254	goto error;
	1255	}
	1256
	1257	if (hspi->State != HAL_SPI_STATE_READY)
	1258	{
	1259	errorcode = HAL_BUSY;
	1260	goto error;
	1261	}
	1262
	1263	/* Set the transaction information */
	1264	hspi->State = HAL_SPI_STATE_BUSY_TX;
	1265	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	1266	hspi->pTxBuffPtr = (uint8_t *)pData;
	1267	hspi->TxXferSize = Size;
	1268	hspi->TxXferCount = Size;
	1269
	1270	/* Init field not used in handle to zero */
	1271	hspi->pRxBuffPtr = (uint8_t *)NULL;
	1272	hspi->RxXferSize = 0U;
	1273	hspi->RxXferCount = 0U;
	1274	hspi->RxISR = NULL;
	1275
	1276	/* Set the function for IT treatment */
	1277	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	1278	{
	1279	hspi->TxISR = SPI_TxISR_16BIT;
	1280	}
	1281	else
	1282	{
	1283	hspi->TxISR = SPI_TxISR_8BIT;
	1284	}
	1285
	1286	/* Configure communication direction : 1Line */
	1287	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
	1288	{
	1289	SPI_1LINE_TX(hspi);
	1290	}
	1291
	1292	#if (USE_SPI_CRC != 0U)
	1293	/* Reset CRC Calculation */
	1294	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	1295	{
	1296	SPI_RESET_CRC(hspi);
	1297	}
	1298	#endif /* USE_SPI_CRC */
	1299
	1300	/* Enable TXE and ERR interrupt */
	1301	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
	1302
	1303
	1304	/* Check if the SPI is already enabled */
	1305	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
	1306	{
	1307	/* Enable SPI peripheral */
	1308	__HAL_SPI_ENABLE(hspi);
	1309	}
	1310
	1311	error :
	1312	__HAL_UNLOCK(hspi);
	1313	return errorcode;
	1314	}
	1315
	1316	/**
	1317	* @brief Receive an amount of data in non-blocking mode with Interrupt.
	1318	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	1319	* the configuration information for SPI module.
	1320	* @param pData pointer to data buffer
	1321	* @param Size amount of data to be sent
	1322	* @retval HAL status
	1323	*/
	1324	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
	1325	{
	1326	HAL_StatusTypeDef errorcode = HAL_OK;
	1327
	1328	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (Size > 1U))
	1329	{
	1330	/* in this case, 16-bit access is performed on Data
	1331	So, check Data is 16-bit aligned address */
	1332	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
	1333	}
	1334
	1335	if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
	1336	{
	1337	hspi->State = HAL_SPI_STATE_BUSY_RX;
	1338	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
	1339	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
	1340	}
	1341
	1342	/* Process Locked */
	1343	__HAL_LOCK(hspi);
	1344
	1345	if (hspi->State != HAL_SPI_STATE_READY)
	1346	{
	1347	errorcode = HAL_BUSY;
	1348	goto error;
	1349	}
	1350
	1351	if ((pData == NULL) \|\| (Size == 0U))
	1352	{
	1353	errorcode = HAL_ERROR;
	1354	goto error;
	1355	}
	1356
	1357	/* Set the transaction information */
	1358	hspi->State = HAL_SPI_STATE_BUSY_RX;
	1359	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	1360	hspi->pRxBuffPtr = (uint8_t *)pData;
	1361	hspi->RxXferSize = Size;
	1362	hspi->RxXferCount = Size;
	1363
	1364	/* Init field not used in handle to zero */
	1365	hspi->pTxBuffPtr = (uint8_t *)NULL;
	1366	hspi->TxXferSize = 0U;
	1367	hspi->TxXferCount = 0U;
	1368	hspi->TxISR = NULL;
	1369
	1370	/* Check the data size to adapt Rx threshold and the set the function for IT treatment */
	1371	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	1372	{
	1373	/* Set fiforxthresold according the reception data length: 16 bit */
	1374	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1375	hspi->RxISR = SPI_RxISR_16BIT;
	1376	}
	1377	else
	1378	{
	1379	/* Set fiforxthresold according the reception data length: 8 bit */
	1380	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1381	hspi->RxISR = SPI_RxISR_8BIT;
	1382	}
	1383
	1384	/* Configure communication direction : 1Line */
	1385	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
	1386	{
	1387	SPI_1LINE_RX(hspi);
	1388	}
	1389
	1390	#if (USE_SPI_CRC != 0U)
	1391	/* Reset CRC Calculation */
	1392	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	1393	{
	1394	hspi->CRCSize = 1U;
	1395	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
	1396	{
	1397	hspi->CRCSize = 2U;
	1398	}
	1399	SPI_RESET_CRC(hspi);
	1400	}
	1401	else
	1402	{
	1403	hspi->CRCSize = 0U;
	1404	}
	1405	#endif /* USE_SPI_CRC */
	1406
	1407	/* Enable TXE and ERR interrupt */
	1408	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
	1409
	1410	/* Note : The SPI must be enabled after unlocking current process
	1411	to avoid the risk of SPI interrupt handle execution before current
	1412	process unlock */
	1413
	1414	/* Check if the SPI is already enabled */
	1415	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
	1416	{
	1417	/* Enable SPI peripheral */
	1418	__HAL_SPI_ENABLE(hspi);
	1419	}
	1420
	1421	error :
	1422	/* Process Unlocked */
	1423	__HAL_UNLOCK(hspi);
	1424	return errorcode;
	1425	}
	1426
	1427	/**
	1428	* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
	1429	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	1430	* the configuration information for SPI module.
	1431	* @param pTxData pointer to transmission data buffer
	1432	* @param pRxData pointer to reception data buffer
	1433	* @param Size amount of data to be sent and received
	1434	* @retval HAL status
	1435	*/
	1436	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
	1437	{
	1438	uint32_t tmp = 0U, tmp1 = 0U;
	1439	HAL_StatusTypeDef errorcode = HAL_OK;
	1440
	1441	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (Size > 1U))
	1442	{
	1443	/* in this case, 16-bit access is performed on Data
	1444	So, check Data is 16-bit aligned address */
	1445	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
	1446	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
	1447	}
	1448
	1449	/* Check Direction parameter */
	1450	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
	1451
	1452	/* Process locked */
	1453	__HAL_LOCK(hspi);
	1454
	1455	tmp = hspi->State;
	1456	tmp1 = hspi->Init.Mode;
	1457
	1458	if (!((tmp == HAL_SPI_STATE_READY) \|\| \
	1459	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
	1460	{
	1461	errorcode = HAL_BUSY;
	1462	goto error;
	1463	}
	1464
	1465	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
	1466	{
	1467	errorcode = HAL_ERROR;
	1468	goto error;
	1469	}
	1470
	1471	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
	1472	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
	1473	{
	1474	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
	1475	}
	1476
	1477	/* Set the transaction information */
	1478	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	1479	hspi->pTxBuffPtr = (uint8_t *)pTxData;
	1480	hspi->TxXferSize = Size;
	1481	hspi->TxXferCount = Size;
	1482	hspi->pRxBuffPtr = (uint8_t *)pRxData;
	1483	hspi->RxXferSize = Size;
	1484	hspi->RxXferCount = Size;
	1485
	1486	/* Set the function for IT treatment */
	1487	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	1488	{
	1489	hspi->RxISR = SPI_2linesRxISR_16BIT;
	1490	hspi->TxISR = SPI_2linesTxISR_16BIT;
	1491	}
	1492	else
	1493	{
	1494	hspi->RxISR = SPI_2linesRxISR_8BIT;
	1495	hspi->TxISR = SPI_2linesTxISR_8BIT;
	1496	}
	1497
	1498	#if (USE_SPI_CRC != 0U)
	1499	/* Reset CRC Calculation */
	1500	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	1501	{
	1502	hspi->CRCSize = 1U;
	1503	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
	1504	{
	1505	hspi->CRCSize = 2U;
	1506	}
	1507	SPI_RESET_CRC(hspi);
	1508	}
	1509	else
	1510	{
	1511	hspi->CRCSize = 0U;
	1512	}
	1513	#endif /* USE_SPI_CRC */
	1514
	1515	/* Check if packing mode is enabled and if there is more than 2 data to receive */
	1516	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount >= 2U))
	1517	{
	1518	/* Set fiforxthresold according the reception data length: 16 bit */
	1519	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1520	}
	1521	else
	1522	{
	1523	/* Set fiforxthresold according the reception data length: 8 bit */
	1524	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1525	}
	1526
	1527	/* Enable TXE, RXNE and ERR interrupt */
	1528	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
	1529
	1530	/* Check if the SPI is already enabled */
	1531	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
	1532	{
	1533	/* Enable SPI peripheral */
	1534	__HAL_SPI_ENABLE(hspi);
	1535	}
	1536
	1537	error :
	1538	/* Process Unlocked */
	1539	__HAL_UNLOCK(hspi);
	1540	return errorcode;
	1541	}
	1542
	1543	/**
	1544	* @brief Transmit an amount of data in non-blocking mode with DMA.
	1545	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	1546	* the configuration information for SPI module.
	1547	* @param pData pointer to data buffer
	1548	* @param Size amount of data to be sent
	1549	* @retval HAL status
	1550	*/
	1551	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
	1552	{
	1553	HAL_StatusTypeDef errorcode = HAL_OK;
	1554
	1555	/* check tx dma handle */
	1556	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
	1557
	1558	/* Check Direction parameter */
	1559	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
	1560
	1561	/* Process Locked */
	1562	__HAL_LOCK(hspi);
	1563
	1564	if (hspi->State != HAL_SPI_STATE_READY)
	1565	{
	1566	errorcode = HAL_BUSY;
	1567	goto error;
	1568	}
	1569
	1570	if ((pData == NULL) \|\| (Size == 0U))
	1571	{
	1572	errorcode = HAL_ERROR;
	1573	goto error;
	1574	}
	1575
	1576	/* Set the transaction information */
	1577	hspi->State = HAL_SPI_STATE_BUSY_TX;
	1578	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	1579	hspi->pTxBuffPtr = (uint8_t *)pData;
	1580	hspi->TxXferSize = Size;
	1581	hspi->TxXferCount = Size;
	1582
	1583	/* Init field not used in handle to zero */
	1584	hspi->pRxBuffPtr = (uint8_t *)NULL;
	1585	hspi->TxISR = NULL;
	1586	hspi->RxISR = NULL;
	1587	hspi->RxXferSize = 0U;
	1588	hspi->RxXferCount = 0U;
	1589
	1590	/* Configure communication direction : 1Line */
	1591	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
	1592	{
	1593	SPI_1LINE_TX(hspi);
	1594	}
	1595
	1596	#if (USE_SPI_CRC != 0U)
	1597	/* Reset CRC Calculation */
	1598	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	1599	{
	1600	SPI_RESET_CRC(hspi);
	1601	}
	1602	#endif /* USE_SPI_CRC */
	1603
	1604	/* Set the SPI TxDMA Half transfer complete callback */
	1605	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
	1606
	1607	/* Set the SPI TxDMA transfer complete callback */
	1608	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
	1609
	1610	/* Set the DMA error callback */
	1611	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
	1612
	1613	/* Set the DMA AbortCpltCallback */
	1614	hspi->hdmatx->XferAbortCallback = NULL;
	1615
	1616	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
	1617	/* Packing mode is enabled only if the DMA setting is HALWORD */
	1618	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
	1619	{
	1620	/* Check the even/odd of the data size + crc if enabled */
	1621	if ((hspi->TxXferCount & 0x1U) == 0U)
	1622	{
	1623	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
	1624	hspi->TxXferCount = (hspi->TxXferCount >> 1U);
	1625	}
	1626	else
	1627	{
	1628	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
	1629	hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
	1630	}
	1631	}
	1632
	1633	/* Enable the Tx DMA Stream/Channel */
	1634	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
	1635
	1636	/* Check if the SPI is already enabled */
	1637	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
	1638	{
	1639	/* Enable SPI peripheral */
	1640	__HAL_SPI_ENABLE(hspi);
	1641	}
	1642
	1643	/* Enable the SPI Error Interrupt Bit */
	1644	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
	1645
	1646	/* Enable Tx DMA Request */
	1647	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
	1648
	1649	error :
	1650	/* Process Unlocked */
	1651	__HAL_UNLOCK(hspi);
	1652	return errorcode;
	1653	}
	1654
	1655	/**
	1656	* @brief Receive an amount of data in non-blocking mode with DMA.
	1657	* @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
	1658	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	1659	* the configuration information for SPI module.
	1660	* @param pData pointer to data buffer
	1661	* @note When the CRC feature is enabled the pData Length must be Size + 1.
	1662	* @param Size amount of data to be sent
	1663	* @retval HAL status
	1664	*/
	1665	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
	1666	{
	1667	HAL_StatusTypeDef errorcode = HAL_OK;
	1668
	1669	/* check rx dma handle */
	1670	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
	1671
	1672	if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
	1673	{
	1674	hspi->State = HAL_SPI_STATE_BUSY_RX;
	1675
	1676	/* check tx dma handle */
	1677	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
	1678
	1679	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
	1680	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
	1681	}
	1682
	1683	/* Process Locked */
	1684	__HAL_LOCK(hspi);
	1685
	1686	if (hspi->State != HAL_SPI_STATE_READY)
	1687	{
	1688	errorcode = HAL_BUSY;
	1689	goto error;
	1690	}
	1691
	1692	if ((pData == NULL) \|\| (Size == 0U))
	1693	{
	1694	errorcode = HAL_ERROR;
	1695	goto error;
	1696	}
	1697
	1698	/* Set the transaction information */
	1699	hspi->State = HAL_SPI_STATE_BUSY_RX;
	1700	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	1701	hspi->pRxBuffPtr = (uint8_t *)pData;
	1702	hspi->RxXferSize = Size;
	1703	hspi->RxXferCount = Size;
	1704
	1705	/Init field not used in handle to zero /
	1706	hspi->RxISR = NULL;
	1707	hspi->TxISR = NULL;
	1708	hspi->TxXferSize = 0U;
	1709	hspi->TxXferCount = 0U;
	1710
	1711	/* Configure communication direction : 1Line */
	1712	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
	1713	{
	1714	SPI_1LINE_RX(hspi);
	1715	}
	1716
	1717	#if (USE_SPI_CRC != 0U)
	1718	/* Reset CRC Calculation */
	1719	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	1720	{
	1721	SPI_RESET_CRC(hspi);
	1722	}
	1723	#endif /* USE_SPI_CRC */
	1724
	1725	#if defined (STM32F030x6) \|\| defined (STM32F030x8) \|\| defined (STM32F031x6)\|\| defined (STM32F038xx) \|\| defined (STM32F051x8) \|\| defined (STM32F058xx)
	1726	/* Packing mode management is enabled by the DMA settings */
	1727	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
	1728	{
	1729	/* Restriction the DMA data received is not allowed in this mode */
	1730	errorcode = HAL_ERROR;
	1731	goto error;
	1732	}
	1733	#endif
	1734
	1735	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
	1736	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	1737	{
	1738	/* Set fiforxthresold according the reception data length: 16bit */
	1739	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1740	}
	1741	else
	1742	{
	1743	/* Set fiforxthresold according the reception data length: 8bit */
	1744	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1745
	1746	if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
	1747	{
	1748	/* set fiforxthresold according the reception data length: 16bit */
	1749	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1750
	1751	if ((hspi->RxXferCount & 0x1U) == 0x0U)
	1752	{
	1753	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
	1754	hspi->RxXferCount = hspi->RxXferCount >> 1U;
	1755	}
	1756	else
	1757	{
	1758	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
	1759	hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
	1760	}
	1761	}
	1762	}
	1763
	1764	/* Set the SPI RxDMA Half transfer complete callback */
	1765	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
	1766
	1767	/* Set the SPI Rx DMA transfer complete callback */
	1768	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
	1769
	1770	/* Set the DMA error callback */
	1771	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
	1772
	1773	/* Set the DMA AbortCpltCallback */
	1774	hspi->hdmarx->XferAbortCallback = NULL;
	1775
	1776	/* Enable the Rx DMA Stream/Channel */
	1777	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
	1778
	1779	/* Check if the SPI is already enabled */
	1780	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
	1781	{
	1782	/* Enable SPI peripheral */
	1783	__HAL_SPI_ENABLE(hspi);
	1784	}
	1785
	1786	/* Enable the SPI Error Interrupt Bit */
	1787	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
	1788
	1789	/* Enable Rx DMA Request */
	1790	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
	1791
	1792	error:
	1793	/* Process Unlocked */
	1794	__HAL_UNLOCK(hspi);
	1795	return errorcode;
	1796	}
	1797
	1798	/**
	1799	* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
	1800	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	1801	* the configuration information for SPI module.
	1802	* @param pTxData pointer to transmission data buffer
	1803	* @param pRxData pointer to reception data buffer
	1804	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
	1805	* @param Size amount of data to be sent
	1806	* @retval HAL status
	1807	*/
	1808	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData,
	1809	uint16_t Size)
	1810	{
	1811	uint32_t tmp = 0U, tmp1 = 0U;
	1812	HAL_StatusTypeDef errorcode = HAL_OK;
	1813
	1814	/* check rx & tx dma handles */
	1815	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
	1816	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
	1817
	1818	/* Check Direction parameter */
	1819	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
	1820
	1821	/* Process locked */
	1822	__HAL_LOCK(hspi);
	1823
	1824	tmp = hspi->State;
	1825	tmp1 = hspi->Init.Mode;
	1826	if (!((tmp == HAL_SPI_STATE_READY) \|\|
	1827	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
	1828	{
	1829	errorcode = HAL_BUSY;
	1830	goto error;
	1831	}
	1832
	1833	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
	1834	{
	1835	errorcode = HAL_ERROR;
	1836	goto error;
	1837	}
	1838
	1839	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
	1840	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
	1841	{
	1842	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
	1843	}
	1844
	1845	/* Set the transaction information */
	1846	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	1847	hspi->pTxBuffPtr = (uint8_t *)pTxData;
	1848	hspi->TxXferSize = Size;
	1849	hspi->TxXferCount = Size;
	1850	hspi->pRxBuffPtr = (uint8_t *)pRxData;
	1851	hspi->RxXferSize = Size;
	1852	hspi->RxXferCount = Size;
	1853
	1854	/* Init field not used in handle to zero */
	1855	hspi->RxISR = NULL;
	1856	hspi->TxISR = NULL;
	1857
	1858	#if (USE_SPI_CRC != 0U)
	1859	/* Reset CRC Calculation */
	1860	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	1861	{
	1862	SPI_RESET_CRC(hspi);
	1863	}
	1864	#endif /* USE_SPI_CRC */
	1865
	1866	#if defined (STM32F030x6) \|\| defined (STM32F030x8) \|\| defined (STM32F031x6) \|\| defined (STM32F038xx) \|\| defined (STM32F051x8) \|\| defined (STM32F058xx)
	1867	/* packing mode management is enabled by the DMA settings */
	1868	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
	1869	{
	1870	/* Restriction the DMA data received is not allowed in this mode */
	1871	errorcode = HAL_ERROR;
	1872	goto error;
	1873	}
	1874	#endif
	1875
	1876
	1877	/* Reset the threshold bit */
	1878	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX \| SPI_CR2_LDMARX);
	1879
	1880	/* The packing mode management is enabled by the DMA settings according the spi data size */
	1881	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	1882	{
	1883	/* Set fiforxthreshold according the reception data length: 16bit */
	1884	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1885	}
	1886	else
	1887	{
	1888	/* Set fiforxthresold according the reception data length: 8bit */
	1889	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1890
	1891	if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
	1892	{
	1893	if ((hspi->TxXferSize & 0x1U) == 0x0U)
	1894	{
	1895	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
	1896	hspi->TxXferCount = hspi->TxXferCount >> 1U;
	1897	}
	1898	else
	1899	{
	1900	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
	1901	hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
	1902	}
	1903	}
	1904
	1905	if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
	1906	{
	1907	/* Set fiforxthresold according the reception data length: 16bit */
	1908	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	1909
	1910	if ((hspi->RxXferCount & 0x1U) == 0x0U)
	1911	{
	1912	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
	1913	hspi->RxXferCount = hspi->RxXferCount >> 1U;
	1914	}
	1915	else
	1916	{
	1917	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
	1918	hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
	1919	}
	1920	}
	1921	}
	1922
	1923	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
	1924	if (hspi->State == HAL_SPI_STATE_BUSY_RX)
	1925	{
	1926	/* Set the SPI Rx DMA Half transfer complete callback */
	1927	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
	1928	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
	1929	}
	1930	else
	1931	{
	1932	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
	1933	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
	1934	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
	1935	}
	1936
	1937	/* Set the DMA error callback */
	1938	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
	1939
	1940	/* Set the DMA AbortCpltCallback */
	1941	hspi->hdmarx->XferAbortCallback = NULL;
	1942
	1943	/* Enable the Rx DMA Stream/Channel */
	1944	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
	1945
	1946	/* Enable Rx DMA Request */
	1947	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
	1948
	1949	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
	1950	is performed in DMA reception complete callback */
	1951	hspi->hdmatx->XferHalfCpltCallback = NULL;
	1952	hspi->hdmatx->XferCpltCallback = NULL;
	1953	hspi->hdmatx->XferErrorCallback = NULL;
	1954	hspi->hdmatx->XferAbortCallback = NULL;
	1955
	1956	/* Enable the Tx DMA Stream/Channel */
	1957	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
	1958
	1959	/* Check if the SPI is already enabled */
	1960	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
	1961	{
	1962	/* Enable SPI peripheral */
	1963	__HAL_SPI_ENABLE(hspi);
	1964	}
	1965	/* Enable the SPI Error Interrupt Bit */
	1966	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
	1967
	1968	/* Enable Tx DMA Request */
	1969	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
	1970
	1971	error :
	1972	/* Process Unlocked */
	1973	__HAL_UNLOCK(hspi);
	1974	return errorcode;
	1975	}
	1976
	1977	/**
	1978	* @brief Abort ongoing transfer (blocking mode).
	1979	* @param hspi SPI handle.
	1980	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
	1981	* started in Interrupt or DMA mode.
	1982	* This procedure performs following operations :
	1983	* - Disable SPI Interrupts (depending of transfer direction)
	1984	* - Disable the DMA transfer in the peripheral register (if enabled)
	1985	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
	1986	* - Set handle State to READY
	1987	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
	1988	* @retval HAL status
	1989	*/
	1990	HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
	1991	{
	1992	HAL_StatusTypeDef errorcode;
	1993	__IO uint32_t count, resetcount;
	1994
	1995	/* Initialized local variable */
	1996	errorcode = HAL_OK;
	1997	resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
	1998	count = resetcount;
	1999
	2000	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
	2001	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
	2002	{
	2003	hspi->TxISR = SPI_AbortTx_ISR;
	2004	/* Wait HAL_SPI_STATE_ABORT state */
	2005	do
	2006	{
	2007	if (count-- == 0U)
	2008	{
	2009	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
	2010	break;
	2011	}
	2012	}
	2013	while (hspi->State != HAL_SPI_STATE_ABORT);
	2014	/* Reset Timeout Counter */
	2015	count = resetcount;
	2016	}
	2017
	2018	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
	2019	{
	2020	hspi->RxISR = SPI_AbortRx_ISR;
	2021	/* Wait HAL_SPI_STATE_ABORT state */
	2022	do
	2023	{
	2024	if (count-- == 0U)
	2025	{
	2026	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
	2027	break;
	2028	}
	2029	}
	2030	while (hspi->State != HAL_SPI_STATE_ABORT);
	2031	/* Reset Timeout Counter */
	2032	count = resetcount;
	2033	}
	2034
	2035	/* Clear ERRIE interrupts in case of DMA Mode */
	2036	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
	2037
	2038	/* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
	2039	if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) \|\| (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
	2040	{
	2041	/* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
	2042	if (hspi->hdmatx != NULL)
	2043	{
	2044	/* Set the SPI DMA Abort callback :
	2045	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
	2046	hspi->hdmatx->XferAbortCallback = NULL;
	2047
	2048	/* Abort DMA Tx Handle linked to SPI Peripheral */
	2049	if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
	2050	{
	2051	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	2052	}
	2053
	2054	/* Disable Tx DMA Request */
	2055	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
	2056
	2057	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	2058	{
	2059	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	2060	}
	2061
	2062	/* Disable SPI Peripheral */
	2063	__HAL_SPI_DISABLE(hspi);
	2064
	2065	/* Empty the FRLVL fifo */
	2066	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	2067	{
	2068	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	2069	}
	2070	}
	2071	/* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
	2072	if (hspi->hdmarx != NULL)
	2073	{
	2074	/* Set the SPI DMA Abort callback :
	2075	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
	2076	hspi->hdmarx->XferAbortCallback = NULL;
	2077
	2078	/* Abort DMA Rx Handle linked to SPI Peripheral */
	2079	if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
	2080	{
	2081	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	2082	}
	2083
	2084	/* Disable peripheral */
	2085	__HAL_SPI_DISABLE(hspi);
	2086
	2087	/* Control the BSY flag */
	2088	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	2089	{
	2090	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	2091	}
	2092
	2093	/* Empty the FRLVL fifo */
	2094	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	2095	{
	2096	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	2097	}
	2098
	2099	/* Disable Rx DMA Request */
	2100	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
	2101	}
	2102	}
	2103	/* Reset Tx and Rx transfer counters */
	2104	hspi->RxXferCount = 0U;
	2105	hspi->TxXferCount = 0U;
	2106
	2107	/* Check error during Abort procedure */
	2108	if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
	2109	{
	2110	/* return HAL_Error in case of error during Abort procedure */
	2111	errorcode = HAL_ERROR;
	2112	}
	2113	else
	2114	{
	2115	/* Reset errorCode */
	2116	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	2117	}
	2118
	2119	/* Clear the Error flags in the SR register */
	2120	__HAL_SPI_CLEAR_OVRFLAG(hspi);
	2121	__HAL_SPI_CLEAR_FREFLAG(hspi);
	2122
	2123	/* Restore hspi->state to ready */
	2124	hspi->State = HAL_SPI_STATE_READY;
	2125
	2126	return errorcode;
	2127	}
	2128
	2129	/**
	2130	* @brief Abort ongoing transfer (Interrupt mode).
	2131	* @param hspi SPI handle.
	2132	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
	2133	* started in Interrupt or DMA mode.
	2134	* This procedure performs following operations :
	2135	* - Disable SPI Interrupts (depending of transfer direction)
	2136	* - Disable the DMA transfer in the peripheral register (if enabled)
	2137	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
	2138	* - Set handle State to READY
	2139	* - At abort completion, call user abort complete callback
	2140	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
	2141	* considered as completed only when user abort complete callback is executed (not when exiting function).
	2142	* @retval HAL status
	2143	*/
	2144	HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
	2145	{
	2146	HAL_StatusTypeDef errorcode;
	2147	uint32_t abortcplt ;
	2148	__IO uint32_t count, resetcount;
	2149
	2150	/* Initialized local variable */
	2151	errorcode = HAL_OK;
	2152	abortcplt = 1U;
	2153	resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
	2154	count = resetcount;
	2155
	2156	/* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
	2157	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
	2158	{
	2159	hspi->TxISR = SPI_AbortTx_ISR;
	2160	/* Wait HAL_SPI_STATE_ABORT state */
	2161	do
	2162	{
	2163	if (count-- == 0U)
	2164	{
	2165	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
	2166	break;
	2167	}
	2168	}
	2169	while (hspi->State != HAL_SPI_STATE_ABORT);
	2170	/* Reset Timeout Counter */
	2171	count = resetcount;
	2172	}
	2173
	2174	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
	2175	{
	2176	hspi->RxISR = SPI_AbortRx_ISR;
	2177	/* Wait HAL_SPI_STATE_ABORT state */
	2178	do
	2179	{
	2180	if (count-- == 0U)
	2181	{
	2182	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
	2183	break;
	2184	}
	2185	}
	2186	while (hspi->State != HAL_SPI_STATE_ABORT);
	2187	/* Reset Timeout Counter */
	2188	count = resetcount;
	2189	}
	2190
	2191	/* Clear ERRIE interrupts in case of DMA Mode */
	2192	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
	2193
	2194	/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
	2195	before any call to DMA Abort functions */
	2196	/* DMA Tx Handle is valid */
	2197	if (hspi->hdmatx != NULL)
	2198	{
	2199	/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
	2200	Otherwise, set it to NULL */
	2201	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
	2202	{
	2203	hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
	2204	}
	2205	else
	2206	{
	2207	hspi->hdmatx->XferAbortCallback = NULL;
	2208	}
	2209	}
	2210	/* DMA Rx Handle is valid */
	2211	if (hspi->hdmarx != NULL)
	2212	{
	2213	/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
	2214	Otherwise, set it to NULL */
	2215	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
	2216	{
	2217	hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
	2218	}
	2219	else
	2220	{
	2221	hspi->hdmarx->XferAbortCallback = NULL;
	2222	}
	2223	}
	2224
	2225	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
	2226	if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
	2227	{
	2228	/* Abort the SPI DMA Tx Stream/Channel */
	2229	if (hspi->hdmatx != NULL)
	2230	{
	2231	/* Abort DMA Tx Handle linked to SPI Peripheral */
	2232	if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
	2233	{
	2234	hspi->hdmatx->XferAbortCallback = NULL;
	2235	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	2236	}
	2237	else
	2238	{
	2239	abortcplt = 0U;
	2240	}
	2241	}
	2242	/* Abort the SPI DMA Rx Stream/Channel */
	2243	if (hspi->hdmarx != NULL)
	2244	{
	2245	/* Abort DMA Rx Handle linked to SPI Peripheral */
	2246	if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
	2247	{
	2248	hspi->hdmarx->XferAbortCallback = NULL;
	2249	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	2250	abortcplt = 1U;
	2251	}
	2252	else
	2253	{
	2254	abortcplt = 0U;
	2255	}
	2256	}
	2257	}
	2258
	2259	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
	2260	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
	2261	{
	2262	/* Abort the SPI DMA Tx Stream/Channel */
	2263	if (hspi->hdmatx != NULL)
	2264	{
	2265	/* Abort DMA Tx Handle linked to SPI Peripheral */
	2266	if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
	2267	{
	2268	hspi->hdmatx->XferAbortCallback = NULL;
	2269	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	2270	}
	2271	else
	2272	{
	2273	abortcplt = 0U;
	2274	}
	2275	}
	2276	}
	2277	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
	2278	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
	2279	{
	2280	/* Abort the SPI DMA Rx Stream/Channel */
	2281	if (hspi->hdmarx != NULL)
	2282	{
	2283	/* Abort DMA Rx Handle linked to SPI Peripheral */
	2284	if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
	2285	{
	2286	hspi->hdmarx->XferAbortCallback = NULL;
	2287	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	2288	}
	2289	else
	2290	{
	2291	abortcplt = 0U;
	2292	}
	2293	}
	2294	}
	2295
	2296	if (abortcplt == 1U)
	2297	{
	2298	/* Reset Tx and Rx transfer counters */
	2299	hspi->RxXferCount = 0U;
	2300	hspi->TxXferCount = 0U;
	2301
	2302	/* Check error during Abort procedure */
	2303	if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
	2304	{
	2305	/* return HAL_Error in case of error during Abort procedure */
	2306	errorcode = HAL_ERROR;
	2307	}
	2308	else
	2309	{
	2310	/* Reset errorCode */
	2311	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	2312	}
	2313
	2314	/* Clear the Error flags in the SR register */
	2315	__HAL_SPI_CLEAR_OVRFLAG(hspi);
	2316	__HAL_SPI_CLEAR_FREFLAG(hspi);
	2317
	2318	/* Restore hspi->State to Ready */
	2319	hspi->State = HAL_SPI_STATE_READY;
	2320
	2321	/* As no DMA to be aborted, call directly user Abort complete callback */
	2322	HAL_SPI_AbortCpltCallback(hspi);
	2323	}
	2324
	2325	return errorcode;
	2326	}
	2327
	2328	/**
	2329	* @brief Pause the DMA Transfer.
	2330	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2331	* the configuration information for the specified SPI module.
	2332	* @retval HAL status
	2333	*/
	2334	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
	2335	{
	2336	/* Process Locked */
	2337	__HAL_LOCK(hspi);
	2338
	2339	/* Disable the SPI DMA Tx & Rx requests */
	2340	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
	2341
	2342	/* Process Unlocked */
	2343	__HAL_UNLOCK(hspi);
	2344
	2345	return HAL_OK;
	2346	}
	2347
	2348	/**
	2349	* @brief Resume the DMA Transfer.
	2350	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2351	* the configuration information for the specified SPI module.
	2352	* @retval HAL status
	2353	*/
	2354	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
	2355	{
	2356	/* Process Locked */
	2357	__HAL_LOCK(hspi);
	2358
	2359	/* Enable the SPI DMA Tx & Rx requests */
	2360	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
	2361
	2362	/* Process Unlocked */
	2363	__HAL_UNLOCK(hspi);
	2364
	2365	return HAL_OK;
	2366	}
	2367
	2368	/**
	2369	* @brief Stop the DMA Transfer.
	2370	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2371	* the configuration information for the specified SPI module.
	2372	* @retval HAL status
	2373	*/
	2374	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
	2375	{
	2376	/* The Lock is not implemented on this API to allow the user application
	2377	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
	2378	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
	2379	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
	2380	*/
	2381
	2382	/* Abort the SPI DMA tx Stream/Channel */
	2383	if (hspi->hdmatx != NULL)
	2384	{
	2385	HAL_DMA_Abort(hspi->hdmatx);
	2386	}
	2387	/* Abort the SPI DMA rx Stream/Channel */
	2388	if (hspi->hdmarx != NULL)
	2389	{
	2390	HAL_DMA_Abort(hspi->hdmarx);
	2391	}
	2392
	2393	/* Disable the SPI DMA Tx & Rx requests */
	2394	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
	2395	hspi->State = HAL_SPI_STATE_READY;
	2396	return HAL_OK;
	2397	}
	2398
	2399	/**
	2400	* @brief Handle SPI interrupt request.
	2401	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2402	* the configuration information for the specified SPI module.
	2403	* @retval None
	2404	*/
	2405	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
	2406	{
	2407	uint32_t itsource = hspi->Instance->CR2;
	2408	uint32_t itflag = hspi->Instance->SR;
	2409
	2410	/* SPI in mode Receiver ----------------------------------------------------*/
	2411	if (((itflag & SPI_FLAG_OVR) == RESET) &&
	2412	((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
	2413	{
	2414	hspi->RxISR(hspi);
	2415	return;
	2416	}
	2417
	2418	/* SPI in mode Transmitter -------------------------------------------------*/
	2419	if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
	2420	{
	2421	hspi->TxISR(hspi);
	2422	return;
	2423	}
	2424
	2425	/* SPI in Error Treatment --------------------------------------------------*/
	2426	if (((itflag & (SPI_FLAG_MODF \| SPI_FLAG_OVR \| SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
	2427	{
	2428	/* SPI Overrun error interrupt occurred ----------------------------------*/
	2429	if ((itflag & SPI_FLAG_OVR) != RESET)
	2430	{
	2431	if (hspi->State != HAL_SPI_STATE_BUSY_TX)
	2432	{
	2433	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
	2434	__HAL_SPI_CLEAR_OVRFLAG(hspi);
	2435	}
	2436	else
	2437	{
	2438	__HAL_SPI_CLEAR_OVRFLAG(hspi);
	2439	return;
	2440	}
	2441	}
	2442
	2443	/* SPI Mode Fault error interrupt occurred -------------------------------*/
	2444	if ((itflag & SPI_FLAG_MODF) != RESET)
	2445	{
	2446	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
	2447	__HAL_SPI_CLEAR_MODFFLAG(hspi);
	2448	}
	2449
	2450	/* SPI Frame error interrupt occurred ------------------------------------*/
	2451	if ((itflag & SPI_FLAG_FRE) != RESET)
	2452	{
	2453	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
	2454	__HAL_SPI_CLEAR_FREFLAG(hspi);
	2455	}
	2456
	2457	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
	2458	{
	2459	/* Disable all interrupts */
	2460	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
	2461
	2462	hspi->State = HAL_SPI_STATE_READY;
	2463	/* Disable the SPI DMA requests if enabled */
	2464	if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) \|\| (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
	2465	{
	2466	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN));
	2467
	2468	/* Abort the SPI DMA Rx channel */
	2469	if (hspi->hdmarx != NULL)
	2470	{
	2471	/* Set the SPI DMA Abort callback :
	2472	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
	2473	hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
	2474	HAL_DMA_Abort_IT(hspi->hdmarx);
	2475	}
	2476	/* Abort the SPI DMA Tx channel */
	2477	if (hspi->hdmatx != NULL)
	2478	{
	2479	/* Set the SPI DMA Abort callback :
	2480	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
	2481	hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
	2482	HAL_DMA_Abort_IT(hspi->hdmatx);
	2483	}
	2484	}
	2485	else
	2486	{
	2487	/* Call user error callback */
	2488	HAL_SPI_ErrorCallback(hspi);
	2489	}
	2490	}
	2491	return;
	2492	}
	2493	}
	2494
	2495	/**
	2496	* @brief Tx Transfer completed callback.
	2497	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2498	* the configuration information for SPI module.
	2499	* @retval None
	2500	*/
	2501	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
	2502	{
	2503	/* Prevent unused argument(s) compilation warning */
	2504	UNUSED(hspi);
	2505
	2506	/* NOTE : This function should not be modified, when the callback is needed,
	2507	the HAL_SPI_TxCpltCallback should be implemented in the user file
	2508	*/
	2509	}
	2510
	2511	/**
	2512	* @brief Rx Transfer completed callback.
	2513	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2514	* the configuration information for SPI module.
	2515	* @retval None
	2516	*/
	2517	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
	2518	{
	2519	/* Prevent unused argument(s) compilation warning */
	2520	UNUSED(hspi);
	2521
	2522	/* NOTE : This function should not be modified, when the callback is needed,
	2523	the HAL_SPI_RxCpltCallback should be implemented in the user file
	2524	*/
	2525	}
	2526
	2527	/**
	2528	* @brief Tx and Rx Transfer completed callback.
	2529	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2530	* the configuration information for SPI module.
	2531	* @retval None
	2532	*/
	2533	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
	2534	{
	2535	/* Prevent unused argument(s) compilation warning */
	2536	UNUSED(hspi);
	2537
	2538	/* NOTE : This function should not be modified, when the callback is needed,
	2539	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
	2540	*/
	2541	}
	2542
	2543	/**
	2544	* @brief Tx Half Transfer completed callback.
	2545	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2546	* the configuration information for SPI module.
	2547	* @retval None
	2548	*/
	2549	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
	2550	{
	2551	/* Prevent unused argument(s) compilation warning */
	2552	UNUSED(hspi);
	2553
	2554	/* NOTE : This function should not be modified, when the callback is needed,
	2555	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
	2556	*/
	2557	}
	2558
	2559	/**
	2560	* @brief Rx Half Transfer completed callback.
	2561	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2562	* the configuration information for SPI module.
	2563	* @retval None
	2564	*/
	2565	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
	2566	{
	2567	/* Prevent unused argument(s) compilation warning */
	2568	UNUSED(hspi);
	2569
	2570	/* NOTE : This function should not be modified, when the callback is needed,
	2571	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
	2572	*/
	2573	}
	2574
	2575	/**
	2576	* @brief Tx and Rx Half Transfer callback.
	2577	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2578	* the configuration information for SPI module.
	2579	* @retval None
	2580	*/
	2581	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
	2582	{
	2583	/* Prevent unused argument(s) compilation warning */
	2584	UNUSED(hspi);
	2585
	2586	/* NOTE : This function should not be modified, when the callback is needed,
	2587	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
	2588	*/
	2589	}
	2590
	2591	/**
	2592	* @brief SPI error callback.
	2593	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2594	* the configuration information for SPI module.
	2595	* @retval None
	2596	*/
	2597	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
	2598	{
	2599	/* Prevent unused argument(s) compilation warning */
	2600	UNUSED(hspi);
	2601
	2602	/* NOTE : This function should not be modified, when the callback is needed,
	2603	the HAL_SPI_ErrorCallback should be implemented in the user file
	2604	*/
	2605	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
	2606	and user can use HAL_SPI_GetError() API to check the latest error occurred
	2607	*/
	2608	}
	2609
	2610	/**
	2611	* @brief SPI Abort Complete callback.
	2612	* @param hspi SPI handle.
	2613	* @retval None
	2614	*/
	2615	__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
	2616	{
	2617	/* Prevent unused argument(s) compilation warning */
	2618	UNUSED(hspi);
	2619
	2620	/* NOTE : This function should not be modified, when the callback is needed,
	2621	the HAL_SPI_AbortCpltCallback can be implemented in the user file.
	2622	*/
	2623	}
	2624
	2625	/**
	2626	* @}
	2627	*/
	2628
	2629	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
	2630	* @brief SPI control functions
	2631	*
	2632	@verbatim
	2633	===============================================================================
	2634	##### Peripheral State and Errors functions #####
	2635	===============================================================================
	2636	[..]
	2637	This subsection provides a set of functions allowing to control the SPI.
	2638	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
	2639	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
	2640	@endverbatim
	2641	* @{
	2642	*/
	2643
	2644	/**
	2645	* @brief Return the SPI handle state.
	2646	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2647	* the configuration information for SPI module.
	2648	* @retval SPI state
	2649	*/
	2650	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
	2651	{
	2652	/* Return SPI handle state */
	2653	return hspi->State;
	2654	}
	2655
	2656	/**
	2657	* @brief Return the SPI error code.
	2658	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	2659	* the configuration information for SPI module.
	2660	* @retval SPI error code in bitmap format
	2661	*/
	2662	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
	2663	{
	2664	/* Return SPI ErrorCode */
	2665	return hspi->ErrorCode;
	2666	}
	2667
	2668	/**
	2669	* @}
	2670	*/
	2671
	2672	/**
	2673	* @}
	2674	*/
	2675
	2676	/** @addtogroup SPI_Private_Functions
	2677	* @brief Private functions
	2678	* @{
	2679	*/
	2680
	2681	/**
	2682	* @brief DMA SPI transmit process complete callback.
	2683	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	2684	* the configuration information for the specified DMA module.
	2685	* @retval None
	2686	*/
	2687	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
	2688	{
	2689	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
	2690	uint32_t tickstart = 0U;
	2691
	2692	/* Init tickstart for timeout managment*/
	2693	tickstart = HAL_GetTick();
	2694
	2695	/* DMA Normal Mode */
	2696	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
	2697	{
	2698	/* Disable ERR interrupt */
	2699	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
	2700
	2701	/* Disable Tx DMA Request */
	2702	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
	2703
	2704	/* Check the end of the transaction */
	2705	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
	2706	{
	2707	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
	2708	}
	2709
	2710	/* Clear overrun flag in 2 Lines communication mode because received data is not read */
	2711	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
	2712	{
	2713	__HAL_SPI_CLEAR_OVRFLAG(hspi);
	2714	}
	2715
	2716	hspi->TxXferCount = 0U;
	2717	hspi->State = HAL_SPI_STATE_READY;
	2718
	2719	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
	2720	{
	2721	HAL_SPI_ErrorCallback(hspi);
	2722	return;
	2723	}
	2724	}
	2725	HAL_SPI_TxCpltCallback(hspi);
	2726	}
	2727
	2728	/**
	2729	* @brief DMA SPI receive process complete callback.
	2730	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	2731	* the configuration information for the specified DMA module.
	2732	* @retval None
	2733	*/
	2734	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
	2735	{
	2736	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
	2737	uint32_t tickstart = 0U;
	2738	#if (USE_SPI_CRC != 0U)
	2739	__IO uint16_t tmpreg = 0U;
	2740	#endif /* USE_SPI_CRC */
	2741
	2742	/* Init tickstart for timeout management*/
	2743	tickstart = HAL_GetTick();
	2744
	2745	/* DMA Normal Mode */
	2746	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
	2747	{
	2748	/* Disable ERR interrupt */
	2749	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
	2750
	2751	#if (USE_SPI_CRC != 0U)
	2752	/* CRC handling */
	2753	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	2754	{
	2755	/* Wait until RXNE flag */
	2756	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
	2757	{
	2758	/* Error on the CRC reception */
	2759	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	2760	}
	2761	/* Read CRC */
	2762	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
	2763	{
	2764	tmpreg = hspi->Instance->DR;
	2765	/* To avoid GCC warning */
	2766	UNUSED(tmpreg);
	2767	}
	2768	else
	2769	{
	2770	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
	2771	/* To avoid GCC warning */
	2772	UNUSED(tmpreg);
	2773
	2774	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
	2775	{
	2776	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
	2777	{
	2778	/* Error on the CRC reception */
	2779	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	2780	}
	2781	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
	2782	/* To avoid GCC warning */
	2783	UNUSED(tmpreg);
	2784	}
	2785	}
	2786	}
	2787	#endif /* USE_SPI_CRC */
	2788
	2789	/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
	2790	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
	2791
	2792	/* Check the end of the transaction */
	2793	if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
	2794	{
	2795	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
	2796	}
	2797
	2798	hspi->RxXferCount = 0U;
	2799	hspi->State = HAL_SPI_STATE_READY;
	2800
	2801	#if (USE_SPI_CRC != 0U)
	2802	/* Check if CRC error occurred */
	2803	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
	2804	{
	2805	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	2806	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
	2807	}
	2808	#endif /* USE_SPI_CRC */
	2809
	2810	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
	2811	{
	2812	HAL_SPI_ErrorCallback(hspi);
	2813	return;
	2814	}
	2815	}
	2816	HAL_SPI_RxCpltCallback(hspi);
	2817	}
	2818
	2819	/**
	2820	* @brief DMA SPI transmit receive process complete callback.
	2821	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	2822	* the configuration information for the specified DMA module.
	2823	* @retval None
	2824	*/
	2825	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
	2826	{
	2827	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
	2828	uint32_t tickstart = 0U;
	2829	#if (USE_SPI_CRC != 0U)
	2830	__IO int16_t tmpreg = 0U;
	2831	#endif /* USE_SPI_CRC */
	2832	/* Init tickstart for timeout management*/
	2833	tickstart = HAL_GetTick();
	2834
	2835	/* DMA Normal Mode */
	2836	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
	2837	{
	2838	/* Disable ERR interrupt */
	2839	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
	2840
	2841	#if (USE_SPI_CRC != 0U)
	2842	/* CRC handling */
	2843	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	2844	{
	2845	if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
	2846	{
	2847	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
	2848	tickstart) != HAL_OK)
	2849	{
	2850	/* Error on the CRC reception */
	2851	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	2852	}
	2853	/* Read CRC to Flush DR and RXNE flag */
	2854	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
	2855	/* To avoid GCC warning */
	2856	UNUSED(tmpreg);
	2857	}
	2858	else
	2859	{
	2860	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
	2861	{
	2862	/* Error on the CRC reception */
	2863	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	2864	}
	2865	/* Read CRC to Flush DR and RXNE flag */
	2866	tmpreg = hspi->Instance->DR;
	2867	/* To avoid GCC warning */
	2868	UNUSED(tmpreg);
	2869	}
	2870	}
	2871	#endif /* USE_SPI_CRC */
	2872
	2873	/* Check the end of the transaction */
	2874	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
	2875	{
	2876	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
	2877	}
	2878
	2879	/* Disable Rx/Tx DMA Request */
	2880	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
	2881
	2882	hspi->TxXferCount = 0U;
	2883	hspi->RxXferCount = 0U;
	2884	hspi->State = HAL_SPI_STATE_READY;
	2885
	2886	#if (USE_SPI_CRC != 0U)
	2887	/* Check if CRC error occurred */
	2888	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
	2889	{
	2890	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	2891	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
	2892	}
	2893	#endif /* USE_SPI_CRC */
	2894
	2895	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
	2896	{
	2897	HAL_SPI_ErrorCallback(hspi);
	2898	return;
	2899	}
	2900	}
	2901	HAL_SPI_TxRxCpltCallback(hspi);
	2902	}
	2903
	2904	/**
	2905	* @brief DMA SPI half transmit process complete callback.
	2906	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	2907	* the configuration information for the specified DMA module.
	2908	* @retval None
	2909	*/
	2910	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
	2911	{
	2912	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
	2913
	2914	HAL_SPI_TxHalfCpltCallback(hspi);
	2915	}
	2916
	2917	/**
	2918	* @brief DMA SPI half receive process complete callback
	2919	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	2920	* the configuration information for the specified DMA module.
	2921	* @retval None
	2922	*/
	2923	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
	2924	{
	2925	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
	2926
	2927	HAL_SPI_RxHalfCpltCallback(hspi);
	2928	}
	2929
	2930	/**
	2931	* @brief DMA SPI half transmit receive process complete callback.
	2932	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	2933	* the configuration information for the specified DMA module.
	2934	* @retval None
	2935	*/
	2936	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
	2937	{
	2938	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
	2939
	2940	HAL_SPI_TxRxHalfCpltCallback(hspi);
	2941	}
	2942
	2943	/**
	2944	* @brief DMA SPI communication error callback.
	2945	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	2946	* the configuration information for the specified DMA module.
	2947	* @retval None
	2948	*/
	2949	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
	2950	{
	2951	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
	2952
	2953	/* Stop the disable DMA transfer on SPI side */
	2954	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
	2955
	2956	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
	2957	hspi->State = HAL_SPI_STATE_READY;
	2958	HAL_SPI_ErrorCallback(hspi);
	2959	}
	2960
	2961	/**
	2962	* @brief DMA SPI communication abort callback, when initiated by HAL services on Error
	2963	* (To be called at end of DMA Abort procedure following error occurrence).
	2964	* @param hdma DMA handle.
	2965	* @retval None
	2966	*/
	2967	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
	2968	{
	2969	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
	2970	hspi->RxXferCount = 0U;
	2971	hspi->TxXferCount = 0U;
	2972
	2973	HAL_SPI_ErrorCallback(hspi);
	2974	}
	2975
	2976	/**
	2977	* @brief DMA SPI Tx communication abort callback, when initiated by user
	2978	* (To be called at end of DMA Tx Abort procedure following user abort request).
	2979	* @note When this callback is executed, User Abort complete call back is called only if no
	2980	* Abort still ongoing for Rx DMA Handle.
	2981	* @param hdma DMA handle.
	2982	* @retval None
	2983	*/
	2984	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
	2985	{
	2986	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
	2987
	2988	hspi->hdmatx->XferAbortCallback = NULL;
	2989
	2990	/* Disable Tx DMA Request */
	2991	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
	2992
	2993	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	2994	{
	2995	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	2996	}
	2997
	2998	/* Disable SPI Peripheral */
	2999	__HAL_SPI_DISABLE(hspi);
	3000
	3001	/* Empty the FRLVL fifo */
	3002	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	3003	{
	3004	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	3005	}
	3006
	3007	/* Check if an Abort process is still ongoing */
	3008	if (hspi->hdmarx != NULL)
	3009	{
	3010	if (hspi->hdmarx->XferAbortCallback != NULL)
	3011	{
	3012	return;
	3013	}
	3014	}
	3015
	3016	/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
	3017	hspi->RxXferCount = 0U;
	3018	hspi->TxXferCount = 0U;
	3019
	3020	/* Check no error during Abort procedure */
	3021	if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
	3022	{
	3023	/* Reset errorCode */
	3024	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	3025	}
	3026
	3027	/* Clear the Error flags in the SR register */
	3028	__HAL_SPI_CLEAR_OVRFLAG(hspi);
	3029	__HAL_SPI_CLEAR_FREFLAG(hspi);
	3030
	3031	/* Restore hspi->State to Ready */
	3032	hspi->State = HAL_SPI_STATE_READY;
	3033
	3034	/* Call user Abort complete callback */
	3035	HAL_SPI_AbortCpltCallback(hspi);
	3036	}
	3037
	3038	/**
	3039	* @brief DMA SPI Rx communication abort callback, when initiated by user
	3040	* (To be called at end of DMA Rx Abort procedure following user abort request).
	3041	* @note When this callback is executed, User Abort complete call back is called only if no
	3042	* Abort still ongoing for Tx DMA Handle.
	3043	* @param hdma DMA handle.
	3044	* @retval None
	3045	*/
	3046	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
	3047	{
	3048	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
	3049
	3050	/* Disable SPI Peripheral */
	3051	__HAL_SPI_DISABLE(hspi);
	3052
	3053	hspi->hdmarx->XferAbortCallback = NULL;
	3054
	3055	/* Disable Rx DMA Request */
	3056	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
	3057
	3058	/* Control the BSY flag */
	3059	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	3060	{
	3061	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	3062	}
	3063
	3064	/* Empty the FRLVL fifo */
	3065	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	3066	{
	3067	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	3068	}
	3069
	3070	/* Check if an Abort process is still ongoing */
	3071	if (hspi->hdmatx != NULL)
	3072	{
	3073	if (hspi->hdmatx->XferAbortCallback != NULL)
	3074	{
	3075	return;
	3076	}
	3077	}
	3078
	3079	/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
	3080	hspi->RxXferCount = 0U;
	3081	hspi->TxXferCount = 0U;
	3082
	3083	/* Check no error during Abort procedure */
	3084	if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
	3085	{
	3086	/* Reset errorCode */
	3087	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
	3088	}
	3089
	3090	/* Clear the Error flags in the SR register */
	3091	__HAL_SPI_CLEAR_OVRFLAG(hspi);
	3092	__HAL_SPI_CLEAR_FREFLAG(hspi);
	3093
	3094	/* Restore hspi->State to Ready */
	3095	hspi->State = HAL_SPI_STATE_READY;
	3096
	3097	/* Call user Abort complete callback */
	3098	HAL_SPI_AbortCpltCallback(hspi);
	3099	}
	3100
	3101	/**
	3102	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
	3103	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3104	* the configuration information for SPI module.
	3105	* @retval None
	3106	*/
	3107	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
	3108	{
	3109	/* Receive data in packing mode */
	3110	if (hspi->RxXferCount > 1U)
	3111	{
	3112	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
	3113	hspi->pRxBuffPtr += sizeof(uint16_t);
	3114	hspi->RxXferCount -= 2U;
	3115	if (hspi->RxXferCount == 1U)
	3116	{
	3117	/* set fiforxthresold according the reception data length: 8bit */
	3118	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	3119	}
	3120	}
	3121	/* Receive data in 8 Bit mode */
	3122	else
	3123	{
	3124	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
	3125	hspi->RxXferCount--;
	3126	}
	3127
	3128	/* check end of the reception */
	3129	if (hspi->RxXferCount == 0U)
	3130	{
	3131	#if (USE_SPI_CRC != 0U)
	3132	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	3133	{
	3134	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
	3135	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
	3136	return;
	3137	}
	3138	#endif /* USE_SPI_CRC */
	3139
	3140	/* Disable RXNE and ERR interrupt */
	3141	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
	3142
	3143	if (hspi->TxXferCount == 0U)
	3144	{
	3145	SPI_CloseRxTx_ISR(hspi);
	3146	}
	3147	}
	3148	}
	3149
	3150	#if (USE_SPI_CRC != 0U)
	3151	/**
	3152	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
	3153	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3154	* the configuration information for SPI module.
	3155	* @retval None
	3156	*/
	3157	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
	3158	{
	3159	__IO uint8_t tmpreg = 0U;
	3160
	3161	/* Read data register to flush CRC */
	3162	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
	3163
	3164	/* To avoid GCC warning */
	3165	UNUSED(tmpreg);
	3166
	3167	hspi->CRCSize--;
	3168
	3169	/* check end of the reception */
	3170	if (hspi->CRCSize == 0U)
	3171	{
	3172	/* Disable RXNE and ERR interrupt */
	3173	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
	3174
	3175	if (hspi->TxXferCount == 0U)
	3176	{
	3177	SPI_CloseRxTx_ISR(hspi);
	3178	}
	3179	}
	3180	}
	3181	#endif /* USE_SPI_CRC */
	3182
	3183	/**
	3184	* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
	3185	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3186	* the configuration information for SPI module.
	3187	* @retval None
	3188	*/
	3189	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
	3190	{
	3191	/* Transmit data in packing Bit mode */
	3192	if (hspi->TxXferCount >= 2U)
	3193	{
	3194	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
	3195	hspi->pTxBuffPtr += sizeof(uint16_t);
	3196	hspi->TxXferCount -= 2U;
	3197	}
	3198	/* Transmit data in 8 Bit mode */
	3199	else
	3200	{
	3201	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
	3202	hspi->TxXferCount--;
	3203	}
	3204
	3205	/* check the end of the transmission */
	3206	if (hspi->TxXferCount == 0U)
	3207	{
	3208	#if (USE_SPI_CRC != 0U)
	3209	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	3210	{
	3211	/* Set CRC Next Bit to send CRC */
	3212	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
	3213	/* Disable TXE interrupt */
	3214	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
	3215	return;
	3216	}
	3217	#endif /* USE_SPI_CRC */
	3218
	3219	/* Disable TXE interrupt */
	3220	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
	3221
	3222	if (hspi->RxXferCount == 0U)
	3223	{
	3224	SPI_CloseRxTx_ISR(hspi);
	3225	}
	3226	}
	3227	}
	3228
	3229	/**
	3230	* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
	3231	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3232	* the configuration information for SPI module.
	3233	* @retval None
	3234	*/
	3235	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
	3236	{
	3237	/* Receive data in 16 Bit mode */
	3238	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
	3239	hspi->pRxBuffPtr += sizeof(uint16_t);
	3240	hspi->RxXferCount--;
	3241
	3242	if (hspi->RxXferCount == 0U)
	3243	{
	3244	#if (USE_SPI_CRC != 0U)
	3245	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	3246	{
	3247	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
	3248	return;
	3249	}
	3250	#endif /* USE_SPI_CRC */
	3251
	3252	/* Disable RXNE interrupt */
	3253	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
	3254
	3255	if (hspi->TxXferCount == 0U)
	3256	{
	3257	SPI_CloseRxTx_ISR(hspi);
	3258	}
	3259	}
	3260	}
	3261
	3262	#if (USE_SPI_CRC != 0U)
	3263	/**
	3264	* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
	3265	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3266	* the configuration information for SPI module.
	3267	* @retval None
	3268	*/
	3269	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
	3270	{
	3271	/* Receive data in 16 Bit mode */
	3272	__IO uint16_t tmpreg = 0U;
	3273
	3274	/* Read data register to flush CRC */
	3275	tmpreg = hspi->Instance->DR;
	3276
	3277	/* To avoid GCC warning */
	3278	UNUSED(tmpreg);
	3279
	3280	/* Disable RXNE interrupt */
	3281	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
	3282
	3283	SPI_CloseRxTx_ISR(hspi);
	3284	}
	3285	#endif /* USE_SPI_CRC */
	3286
	3287	/**
	3288	* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
	3289	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3290	* the configuration information for SPI module.
	3291	* @retval None
	3292	*/
	3293	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
	3294	{
	3295	/* Transmit data in 16 Bit mode */
	3296	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
	3297	hspi->pTxBuffPtr += sizeof(uint16_t);
	3298	hspi->TxXferCount--;
	3299
	3300	/* Enable CRC Transmission */
	3301	if (hspi->TxXferCount == 0U)
	3302	{
	3303	#if (USE_SPI_CRC != 0U)
	3304	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	3305	{
	3306	/* Set CRC Next Bit to send CRC */
	3307	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
	3308	/* Disable TXE interrupt */
	3309	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
	3310	return;
	3311	}
	3312	#endif /* USE_SPI_CRC */
	3313
	3314	/* Disable TXE interrupt */
	3315	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
	3316
	3317	if (hspi->RxXferCount == 0U)
	3318	{
	3319	SPI_CloseRxTx_ISR(hspi);
	3320	}
	3321	}
	3322	}
	3323
	3324	#if (USE_SPI_CRC != 0U)
	3325	/**
	3326	* @brief Manage the CRC 8-bit receive in Interrupt context.
	3327	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3328	* the configuration information for SPI module.
	3329	* @retval None
	3330	*/
	3331	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
	3332	{
	3333	__IO uint8_t tmpreg = 0U;
	3334
	3335	/* Read data register to flush CRC */
	3336	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
	3337
	3338	/* To avoid GCC warning */
	3339	UNUSED(tmpreg);
	3340
	3341	hspi->CRCSize--;
	3342
	3343	if (hspi->CRCSize == 0U)
	3344	{
	3345	SPI_CloseRx_ISR(hspi);
	3346	}
	3347	}
	3348	#endif /* USE_SPI_CRC */
	3349
	3350	/**
	3351	* @brief Manage the receive 8-bit in Interrupt context.
	3352	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3353	* the configuration information for SPI module.
	3354	* @retval None
	3355	*/
	3356	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
	3357	{
	3358	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
	3359	hspi->RxXferCount--;
	3360
	3361	#if (USE_SPI_CRC != 0U)
	3362	/* Enable CRC Transmission */
	3363	if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
	3364	{
	3365	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
	3366	}
	3367	#endif /* USE_SPI_CRC */
	3368
	3369	if (hspi->RxXferCount == 0U)
	3370	{
	3371	#if (USE_SPI_CRC != 0U)
	3372	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	3373	{
	3374	hspi->RxISR = SPI_RxISR_8BITCRC;
	3375	return;
	3376	}
	3377	#endif /* USE_SPI_CRC */
	3378	SPI_CloseRx_ISR(hspi);
	3379	}
	3380	}
	3381
	3382	#if (USE_SPI_CRC != 0U)
	3383	/**
	3384	* @brief Manage the CRC 16-bit receive in Interrupt context.
	3385	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3386	* the configuration information for SPI module.
	3387	* @retval None
	3388	*/
	3389	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
	3390	{
	3391	__IO uint16_t tmpreg = 0U;
	3392
	3393	/* Read data register to flush CRC */
	3394	tmpreg = hspi->Instance->DR;
	3395
	3396	/* To avoid GCC warning */
	3397	UNUSED(tmpreg);
	3398
	3399	/* Disable RXNE and ERR interrupt */
	3400	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
	3401
	3402	SPI_CloseRx_ISR(hspi);
	3403	}
	3404	#endif /* USE_SPI_CRC */
	3405
	3406	/**
	3407	* @brief Manage the 16-bit receive in Interrupt context.
	3408	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3409	* the configuration information for SPI module.
	3410	* @retval None
	3411	*/
	3412	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
	3413	{
	3414	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
	3415	hspi->pRxBuffPtr += sizeof(uint16_t);
	3416	hspi->RxXferCount--;
	3417
	3418	#if (USE_SPI_CRC != 0U)
	3419	/* Enable CRC Transmission */
	3420	if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
	3421	{
	3422	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
	3423	}
	3424	#endif /* USE_SPI_CRC */
	3425
	3426	if (hspi->RxXferCount == 0U)
	3427	{
	3428	#if (USE_SPI_CRC != 0U)
	3429	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	3430	{
	3431	hspi->RxISR = SPI_RxISR_16BITCRC;
	3432	return;
	3433	}
	3434	#endif /* USE_SPI_CRC */
	3435	SPI_CloseRx_ISR(hspi);
	3436	}
	3437	}
	3438
	3439	/**
	3440	* @brief Handle the data 8-bit transmit in Interrupt mode.
	3441	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3442	* the configuration information for SPI module.
	3443	* @retval None
	3444	*/
	3445	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
	3446	{
	3447	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
	3448	hspi->TxXferCount--;
	3449
	3450	if (hspi->TxXferCount == 0U)
	3451	{
	3452	#if (USE_SPI_CRC != 0U)
	3453	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	3454	{
	3455	/* Enable CRC Transmission */
	3456	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
	3457	}
	3458	#endif /* USE_SPI_CRC */
	3459	SPI_CloseTx_ISR(hspi);
	3460	}
	3461	}
	3462
	3463	/**
	3464	* @brief Handle the data 16-bit transmit in Interrupt mode.
	3465	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3466	* the configuration information for SPI module.
	3467	* @retval None
	3468	*/
	3469	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
	3470	{
	3471	/* Transmit data in 16 Bit mode */
	3472	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
	3473	hspi->pTxBuffPtr += sizeof(uint16_t);
	3474	hspi->TxXferCount--;
	3475
	3476	if (hspi->TxXferCount == 0U)
	3477	{
	3478	#if (USE_SPI_CRC != 0U)
	3479	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	3480	{
	3481	/* Enable CRC Transmission */
	3482	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
	3483	}
	3484	#endif /* USE_SPI_CRC */
	3485	SPI_CloseTx_ISR(hspi);
	3486	}
	3487	}
	3488
	3489	/**
	3490	* @brief Handle SPI Communication Timeout.
	3491	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3492	* the configuration information for SPI module.
	3493	* @param Flag SPI flag to check
	3494	* @param State flag state to check
	3495	* @param Timeout Timeout duration
	3496	* @param Tickstart tick start value
	3497	* @retval HAL status
	3498	*/
	3499	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
	3500	uint32_t Timeout, uint32_t Tickstart)
	3501	{
	3502	while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
	3503	{
	3504	if (Timeout != HAL_MAX_DELAY)
	3505	{
	3506	if ((Timeout == 0U) \|\| ((HAL_GetTick() - Tickstart) >= Timeout))
	3507	{
	3508	/* Disable the SPI and reset the CRC: the CRC value should be cleared
	3509	on both master and slave sides in order to resynchronize the master
	3510	and slave for their respective CRC calculation */
	3511
	3512	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
	3513	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
	3514
	3515	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
	3516	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
	3517	{
	3518	/* Disable SPI peripheral */
	3519	__HAL_SPI_DISABLE(hspi);
	3520	}
	3521
	3522	/* Reset CRC Calculation */
	3523	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	3524	{
	3525	SPI_RESET_CRC(hspi);
	3526	}
	3527
	3528	hspi->State = HAL_SPI_STATE_READY;
	3529
	3530	/* Process Unlocked */
	3531	__HAL_UNLOCK(hspi);
	3532
	3533	return HAL_TIMEOUT;
	3534	}
	3535	}
	3536	}
	3537
	3538	return HAL_OK;
	3539	}
	3540
	3541	/**
	3542	* @brief Handle SPI FIFO Communication Timeout.
	3543	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3544	* the configuration information for SPI module.
	3545	* @param Fifo Fifo to check
	3546	* @param State Fifo state to check
	3547	* @param Timeout Timeout duration
	3548	* @param Tickstart tick start value
	3549	* @retval HAL status
	3550	*/
	3551	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
	3552	uint32_t Timeout, uint32_t Tickstart)
	3553	{
	3554	__IO uint8_t tmpreg;
	3555
	3556	while ((hspi->Instance->SR & Fifo) != State)
	3557	{
	3558	if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
	3559	{
	3560	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
	3561	/* To avoid GCC warning */
	3562	UNUSED(tmpreg);
	3563	}
	3564
	3565	if (Timeout != HAL_MAX_DELAY)
	3566	{
	3567	if ((Timeout == 0U) \|\| ((HAL_GetTick() - Tickstart) >= Timeout))
	3568	{
	3569	/* Disable the SPI and reset the CRC: the CRC value should be cleared
	3570	on both master and slave sides in order to resynchronize the master
	3571	and slave for their respective CRC calculation */
	3572
	3573	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
	3574	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
	3575
	3576	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
	3577	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
	3578	{
	3579	/* Disable SPI peripheral */
	3580	__HAL_SPI_DISABLE(hspi);
	3581	}
	3582
	3583	/* Reset CRC Calculation */
	3584	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
	3585	{
	3586	SPI_RESET_CRC(hspi);
	3587	}
	3588
	3589	hspi->State = HAL_SPI_STATE_READY;
	3590
	3591	/* Process Unlocked */
	3592	__HAL_UNLOCK(hspi);
	3593
	3594	return HAL_TIMEOUT;
	3595	}
	3596	}
	3597	}
	3598
	3599	return HAL_OK;
	3600	}
	3601
	3602	/**
	3603	* @brief Handle the check of the RX transaction complete.
	3604	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3605	* the configuration information for SPI module.
	3606	* @param Timeout Timeout duration
	3607	* @param Tickstart tick start value
	3608	* @retval HAL status
	3609	*/
	3610	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
	3611	{
	3612	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
	3613	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
	3614	{
	3615	/* Disable SPI peripheral */
	3616	__HAL_SPI_DISABLE(hspi);
	3617	}
	3618
	3619	/* Control the BSY flag */
	3620	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
	3621	{
	3622	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
	3623	return HAL_TIMEOUT;
	3624	}
	3625
	3626	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
	3627	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
	3628	{
	3629	/* Empty the FRLVL fifo */
	3630	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
	3631	{
	3632	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
	3633	return HAL_TIMEOUT;
	3634	}
	3635	}
	3636	return HAL_OK;
	3637	}
	3638
	3639	/**
	3640	* @brief Handle the check of the RXTX or TX transaction complete.
	3641	* @param hspi SPI handle
	3642	* @param Timeout Timeout duration
	3643	* @param Tickstart tick start value
	3644	* @retval HAL status
	3645	*/
	3646	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
	3647	{
	3648	/* Control if the TX fifo is empty */
	3649	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
	3650	{
	3651	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
	3652	return HAL_TIMEOUT;
	3653	}
	3654
	3655	/* Control the BSY flag */
	3656	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
	3657	{
	3658	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
	3659	return HAL_TIMEOUT;
	3660	}
	3661
	3662	/* Control if the RX fifo is empty */
	3663	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
	3664	{
	3665	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
	3666	return HAL_TIMEOUT;
	3667	}
	3668	return HAL_OK;
	3669	}
	3670
	3671	/**
	3672	* @brief Handle the end of the RXTX transaction.
	3673	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3674	* the configuration information for SPI module.
	3675	* @retval None
	3676	*/
	3677	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
	3678	{
	3679	uint32_t tickstart = 0U;
	3680
	3681	/* Init tickstart for timeout managment*/
	3682	tickstart = HAL_GetTick();
	3683
	3684	/* Disable ERR interrupt */
	3685	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
	3686
	3687	/* Check the end of the transaction */
	3688	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
	3689	{
	3690	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
	3691	}
	3692
	3693	#if (USE_SPI_CRC != 0U)
	3694	/* Check if CRC error occurred */
	3695	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
	3696	{
	3697	hspi->State = HAL_SPI_STATE_READY;
	3698	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	3699	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
	3700	HAL_SPI_ErrorCallback(hspi);
	3701	}
	3702	else
	3703	{
	3704	#endif /* USE_SPI_CRC */
	3705	if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
	3706	{
	3707	if (hspi->State == HAL_SPI_STATE_BUSY_RX)
	3708	{
	3709	hspi->State = HAL_SPI_STATE_READY;
	3710	HAL_SPI_RxCpltCallback(hspi);
	3711	}
	3712	else
	3713	{
	3714	hspi->State = HAL_SPI_STATE_READY;
	3715	HAL_SPI_TxRxCpltCallback(hspi);
	3716	}
	3717	}
	3718	else
	3719	{
	3720	hspi->State = HAL_SPI_STATE_READY;
	3721	HAL_SPI_ErrorCallback(hspi);
	3722	}
	3723	#if (USE_SPI_CRC != 0U)
	3724	}
	3725	#endif /* USE_SPI_CRC */
	3726	}
	3727
	3728	/**
	3729	* @brief Handle the end of the RX transaction.
	3730	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3731	* the configuration information for SPI module.
	3732	* @retval None
	3733	*/
	3734	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
	3735	{
	3736	/* Disable RXNE and ERR interrupt */
	3737	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
	3738
	3739	/* Check the end of the transaction */
	3740	if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	3741	{
	3742	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
	3743	}
	3744	hspi->State = HAL_SPI_STATE_READY;
	3745
	3746	#if (USE_SPI_CRC != 0U)
	3747	/* Check if CRC error occurred */
	3748	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
	3749	{
	3750	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
	3751	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
	3752	HAL_SPI_ErrorCallback(hspi);
	3753	}
	3754	else
	3755	{
	3756	#endif /* USE_SPI_CRC */
	3757	if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
	3758	{
	3759	HAL_SPI_RxCpltCallback(hspi);
	3760	}
	3761	else
	3762	{
	3763	HAL_SPI_ErrorCallback(hspi);
	3764	}
	3765	#if (USE_SPI_CRC != 0U)
	3766	}
	3767	#endif /* USE_SPI_CRC */
	3768	}
	3769
	3770	/**
	3771	* @brief Handle the end of the TX transaction.
	3772	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3773	* the configuration information for SPI module.
	3774	* @retval None
	3775	*/
	3776	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
	3777	{
	3778	uint32_t tickstart = 0U;
	3779
	3780	/* Init tickstart for timeout management*/
	3781	tickstart = HAL_GetTick();
	3782
	3783	/* Disable TXE and ERR interrupt */
	3784	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
	3785
	3786	/* Check the end of the transaction */
	3787	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
	3788	{
	3789	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
	3790	}
	3791
	3792	/* Clear overrun flag in 2 Lines communication mode because received is not read */
	3793	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
	3794	{
	3795	__HAL_SPI_CLEAR_OVRFLAG(hspi);
	3796	}
	3797
	3798	hspi->State = HAL_SPI_STATE_READY;
	3799	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
	3800	{
	3801	HAL_SPI_ErrorCallback(hspi);
	3802	}
	3803	else
	3804	{
	3805	HAL_SPI_TxCpltCallback(hspi);
	3806	}
	3807	}
	3808
	3809	/**
	3810	* @brief Handle abort a Rx transaction.
	3811	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3812	* the configuration information for SPI module.
	3813	* @retval None
	3814	*/
	3815	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
	3816	{
	3817	__IO uint32_t count;
	3818
	3819	/* Disable SPI Peripheral */
	3820	__HAL_SPI_DISABLE(hspi);
	3821
	3822	count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
	3823
	3824	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
	3825	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE \| SPI_CR2_RXNEIE \| SPI_CR2_ERRIE));
	3826
	3827	/* Check RXNEIE is disabled */
	3828	do
	3829	{
	3830	if (count-- == 0U)
	3831	{
	3832	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
	3833	break;
	3834	}
	3835	}
	3836	while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
	3837
	3838	/* Control the BSY flag */
	3839	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	3840	{
	3841	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	3842	}
	3843
	3844	/* Empty the FRLVL fifo */
	3845	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	3846	{
	3847	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	3848	}
	3849
	3850	hspi->State = HAL_SPI_STATE_ABORT;
	3851	}
	3852
	3853	/**
	3854	* @brief Handle abort a Tx or Rx/Tx transaction.
	3855	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
	3856	* the configuration information for SPI module.
	3857	* @retval None
	3858	*/
	3859	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
	3860	{
	3861	__IO uint32_t count;
	3862
	3863	count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
	3864
	3865	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
	3866	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE \| SPI_CR2_RXNEIE \| SPI_CR2_ERRIE));
	3867
	3868	/* Check TXEIE is disabled */
	3869	do
	3870	{
	3871	if (count-- == 0U)
	3872	{
	3873	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
	3874	break;
	3875	}
	3876	}
	3877	while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
	3878
	3879	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	3880	{
	3881	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	3882	}
	3883
	3884	/* Disable SPI Peripheral */
	3885	__HAL_SPI_DISABLE(hspi);
	3886
	3887	/* Empty the FRLVL fifo */
	3888	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
	3889	{
	3890	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
	3891	}
	3892
	3893	hspi->State = HAL_SPI_STATE_ABORT;
	3894	}
	3895
	3896	/**
	3897	* @}
	3898	*/
	3899
	3900	#endif /* HAL_SPI_MODULE_ENABLED */
	3901
	3902	/**
	3903	* @}
	3904	*/
	3905
	3906	/**
	3907	* @}
	3908	*/
	3909
	3910	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/