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2022-10-17 d69aae90ede578aaebc355dafd3496993ccea126

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bfc108	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_hal_rcc.c
	4	* @author MCD Application Team
	5	* @brief RCC HAL module driver.
	6	* This file provides firmware functions to manage the following
	7	* functionalities of the Reset and Clock Control (RCC) peripheral:
	8	* + Initialization and de-initialization functions
	9	* + Peripheral Control functions
	10	*
	11	@verbatim
	12	==============================================================================
	13	##### RCC specific features #####
	14	==============================================================================
	15	[..]
	16	After reset the device is running from Internal High Speed oscillator
	17	(HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
	18	and all peripherals are off except internal SRAM, Flash and JTAG.
	19	(+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
	20	all peripherals mapped on these buses are running at HSI speed.
	21	(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
	22	(+) All GPIOs are in input floating state, except the JTAG pins which
	23	are assigned to be used for debug purpose.
	24	[..] Once the device started from reset, the user application has to:
	25	(+) Configure the clock source to be used to drive the System clock
	26	(if the application needs higher frequency/performance)
	27	(+) Configure the System clock frequency and Flash settings
	28	(+) Configure the AHB and APB buses prescalers
	29	(+) Enable the clock for the peripheral(s) to be used
	30	(+) Configure the clock source(s) for peripherals whose clocks are not
	31	derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..)
	32
	33	##### RCC Limitations #####
	34	==============================================================================
	35	[..]
	36	A delay between an RCC peripheral clock enable and the effective peripheral
	37	enabling should be taken into account in order to manage the peripheral read/write
	38	from/to registers.
	39	(+) This delay depends on the peripheral mapping.
	40	(++) AHB & APB peripherals, 1 dummy read is necessary
	41
	42	[..]
	43	Workarounds:
	44	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
	45	inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
	46
	47	@endverbatim
	48	******************************************************************************
	49	* @attention
	50	*
	51	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	52	*
	53	* Redistribution and use in source and binary forms, with or without modification,
	54	* are permitted provided that the following conditions are met:
	55	* 1. Redistributions of source code must retain the above copyright notice,
	56	* this list of conditions and the following disclaimer.
	57	* 2. Redistributions in binary form must reproduce the above copyright notice,
	58	* this list of conditions and the following disclaimer in the documentation
	59	* and/or other materials provided with the distribution.
	60	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	61	* may be used to endorse or promote products derived from this software
	62	* without specific prior written permission.
	63	*
	64	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	65	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	66	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	67	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	68	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	69	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	70	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	71	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	72	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	73	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	74	*
	75	******************************************************************************
	76	*/
	77
	78	/* Includes ------------------------------------------------------------------*/
	79	#include "stm32f0xx_hal.h"
	80
	81	/** @addtogroup STM32F0xx_HAL_Driver
	82	* @{
	83	*/
	84
	85	/** @defgroup RCC RCC
	86	* @brief RCC HAL module driver
	87	* @{
	88	*/
	89
	90	#ifdef HAL_RCC_MODULE_ENABLED
	91
	92	/* Private typedef -----------------------------------------------------------*/
	93	/* Private define ------------------------------------------------------------*/
	94	/** @defgroup RCC_Private_Constants RCC Private Constants
	95	* @{
	96	*/
	97	/**
	98	* @}
	99	*/
	100	/* Private macro -------------------------------------------------------------*/
	101	/** @defgroup RCC_Private_Macros RCC Private Macros
	102	* @{
	103	*/
	104
	105	#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
	106	#define MCO1_GPIO_PORT GPIOA
	107	#define MCO1_PIN GPIO_PIN_8
	108
	109	/**
	110	* @}
	111	*/
	112
	113	/* Private variables ---------------------------------------------------------*/
	114	/** @defgroup RCC_Private_Variables RCC Private Variables
	115	* @{
	116	*/
	117	/**
	118	* @}
	119	*/
	120
	121	/* Private function prototypes -----------------------------------------------*/
	122	/* Exported functions ---------------------------------------------------------*/
	123
	124	/** @defgroup RCC_Exported_Functions RCC Exported Functions
	125	* @{
	126	*/
	127
	128	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
	129	* @brief Initialization and Configuration functions
	130	*
	131	@verbatim
	132	===============================================================================
	133	##### Initialization and de-initialization functions #####
	134	===============================================================================
	135	[..]
	136	This section provides functions allowing to configure the internal/external oscillators
	137	(HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK,
	138	AHB and APB1).
	139
	140	[..] Internal/external clock and PLL configuration
	141	(#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
	142	the PLL as System clock source.
	143	The HSI clock can be used also to clock the USART and I2C peripherals.
	144
	145	(#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock
	146	the ADC peripheral.
	147
	148	(#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
	149	clock source.
	150
	151	(#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
	152	through the PLL as System clock source. Can be used also as RTC clock source.
	153
	154	(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
	155
	156	(#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks:
	157	(++) The first output is used to generate the high speed system clock (up to 48 MHz)
	158	(++) The second output is used to generate the clock for the USB FS (48 MHz)
	159	(++) The third output may be used to generate the clock for the TIM, I2C and USART
	160	peripherals (up to 48 MHz)
	161
	162	(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
	163	and if a HSE clock failure occurs(HSE used directly or through PLL as System
	164	clock source), the System clocks automatically switched to HSI and an interrupt
	165	is generated if enabled. The interrupt is linked to the Cortex-M0 NMI
	166	(Non-Maskable Interrupt) exception vector.
	167
	168	(#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
	169	clock (divided by 2) output on pin (such as PA8 pin).
	170
	171	[..] System, AHB and APB buses clocks configuration
	172	(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
	173	HSE and PLL.
	174	The AHB clock (HCLK) is derived from System clock through configurable
	175	prescaler and used to clock the CPU, memory and peripherals mapped
	176	on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived
	177	from AHB clock through configurable prescalers and used to clock
	178	the peripherals mapped on these buses. You can use
	179	"@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
	180
	181	(#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
	182	(++) The FLASH program/erase clock which is always HSI 8MHz clock.
	183	(++) The USB 48 MHz clock which is derived from the PLL VCO clock.
	184	(++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
	185	(++) The I2C clock which can be derived as well from HSI 8MHz clock.
	186	(++) The ADC clock which is derived from PLL output.
	187	(++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
	188	(HSE divided by a programmable prescaler). The System clock (SYSCLK)
	189	frequency must be higher or equal to the RTC clock frequency.
	190	(++) IWDG clock which is always the LSI clock.
	191
	192	(#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz,
	193	Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
	194
	195	(#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
	196	prefetch is disabled.
	197	@endverbatim
	198	* @{
	199	*/
	200
	201	/*
	202	Additional consideration on the SYSCLK based on Latency settings:
	203	+-----------------------------------------------+
	204	\| Latency \| SYSCLK clock frequency (MHz) \|
	205	\|---------------\|-------------------------------\|
	206	\|0WS(1CPU cycle)\| 0 < SYSCLK <= 24 \|
	207	\|---------------\|-------------------------------\|
	208	\|1WS(2CPU cycle)\| 24 < SYSCLK <= 48 \|
	209	+-----------------------------------------------+
	210	*/
	211
	212	/**
	213	* @brief Resets the RCC clock configuration to the default reset state.
	214	* @note The default reset state of the clock configuration is given below:
	215	* - HSI ON and used as system clock source
	216	* - HSE and PLL OFF
	217	* - AHB, APB1 prescaler set to 1.
	218	* - CSS and MCO1 OFF
	219	* - All interrupts disabled
	220	* @note This function does not modify the configuration of the
	221	* - Peripheral clocks
	222	* - LSI, LSE and RTC clocks
	223	* @retval None
	224	*/
	225	void HAL_RCC_DeInit(void)
	226	{
	227	/* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
	228	SET_BIT(RCC->CR, RCC_CR_HSION \| RCC_CR_HSITRIM_4);
	229
	230	/* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
	231	CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW \| RCC_CFGR_HPRE \| RCC_CFGR_PPRE \| RCC_CFGR_MCO);
	232
	233	/* Reset HSEON, CSSON, PLLON bits */
	234	CLEAR_BIT(RCC->CR, RCC_CR_PLLON \| RCC_CR_CSSON \| RCC_CR_HSEON);
	235
	236	/* Reset HSEBYP bit */
	237	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
	238
	239	/* Reset CFGR register */
	240	CLEAR_REG(RCC->CFGR);
	241
	242	/* Reset CFGR2 register */
	243	CLEAR_REG(RCC->CFGR2);
	244
	245	/* Reset CFGR3 register */
	246	CLEAR_REG(RCC->CFGR3);
	247
	248	/* Disable all interrupts */
	249	CLEAR_REG(RCC->CIR);
	250
	251	/* Update the SystemCoreClock global variable */
	252	SystemCoreClock = HSI_VALUE;
	253	}
	254
	255	/**
	256	* @brief Initializes the RCC Oscillators according to the specified parameters in the
	257	* RCC_OscInitTypeDef.
	258	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
	259	* contains the configuration information for the RCC Oscillators.
	260	* @note The PLL is not disabled when used as system clock.
	261	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
	262	* supported by this macro. User should request a transition to LSE Off
	263	* first and then LSE On or LSE Bypass.
	264	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
	265	* supported by this macro. User should request a transition to HSE Off
	266	* first and then HSE On or HSE Bypass.
	267	* @retval HAL status
	268	*/
	269	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
	270	{
	271	uint32_t tickstart = 0U;
	272
	273	/* Check the parameters */
	274	assert_param(RCC_OscInitStruct != NULL);
	275	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
	276
	277	/------------------------------- HSE Configuration ------------------------/
	278	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
	279	{
	280	/* Check the parameters */
	281	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
	282
	283	/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
	284	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
	285	\|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
	286	{
	287	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
	288	{
	289	return HAL_ERROR;
	290	}
	291	}
	292	else
	293	{
	294	/* Set the new HSE configuration ---------------------------------------*/
	295	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
	296
	297
	298	/* Check the HSE State */
	299	if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
	300	{
	301	/* Get Start Tick */
	302	tickstart = HAL_GetTick();
	303
	304	/* Wait till HSE is ready */
	305	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
	306	{
	307	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
	308	{
	309	return HAL_TIMEOUT;
	310	}
	311	}
	312	}
	313	else
	314	{
	315	/* Get Start Tick */
	316	tickstart = HAL_GetTick();
	317
	318	/* Wait till HSE is disabled */
	319	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
	320	{
	321	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
	322	{
	323	return HAL_TIMEOUT;
	324	}
	325	}
	326	}
	327	}
	328	}
	329	/----------------------------- HSI Configuration --------------------------/
	330	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
	331	{
	332	/* Check the parameters */
	333	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
	334	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
	335
	336	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
	337	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
	338	\|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
	339	{
	340	/* When HSI is used as system clock it will not disabled */
	341	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
	342	{
	343	return HAL_ERROR;
	344	}
	345	/* Otherwise, just the calibration is allowed */
	346	else
	347	{
	348	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
	349	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
	350	}
	351	}
	352	else
	353	{
	354	/* Check the HSI State */
	355	if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
	356	{
	357	/* Enable the Internal High Speed oscillator (HSI). */
	358	__HAL_RCC_HSI_ENABLE();
	359
	360	/* Get Start Tick */
	361	tickstart = HAL_GetTick();
	362
	363	/* Wait till HSI is ready */
	364	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
	365	{
	366	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
	367	{
	368	return HAL_TIMEOUT;
	369	}
	370	}
	371
	372	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
	373	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
	374	}
	375	else
	376	{
	377	/* Disable the Internal High Speed oscillator (HSI). */
	378	__HAL_RCC_HSI_DISABLE();
	379
	380	/* Get Start Tick */
	381	tickstart = HAL_GetTick();
	382
	383	/* Wait till HSI is disabled */
	384	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
	385	{
	386	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
	387	{
	388	return HAL_TIMEOUT;
	389	}
	390	}
	391	}
	392	}
	393	}
	394	/------------------------------ LSI Configuration -------------------------/
	395	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
	396	{
	397	/* Check the parameters */
	398	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
	399
	400	/* Check the LSI State */
	401	if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
	402	{
	403	/* Enable the Internal Low Speed oscillator (LSI). */
	404	__HAL_RCC_LSI_ENABLE();
	405
	406	/* Get Start Tick */
	407	tickstart = HAL_GetTick();
	408
	409	/* Wait till LSI is ready */
	410	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
	411	{
	412	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
	413	{
	414	return HAL_TIMEOUT;
	415	}
	416	}
	417	}
	418	else
	419	{
	420	/* Disable the Internal Low Speed oscillator (LSI). */
	421	__HAL_RCC_LSI_DISABLE();
	422
	423	/* Get Start Tick */
	424	tickstart = HAL_GetTick();
	425
	426	/* Wait till LSI is disabled */
	427	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
	428	{
	429	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
	430	{
	431	return HAL_TIMEOUT;
	432	}
	433	}
	434	}
	435	}
	436	/------------------------------ LSE Configuration -------------------------/
	437	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
	438	{
	439	FlagStatus pwrclkchanged = RESET;
	440
	441	/* Check the parameters */
	442	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
	443
	444	/* Update LSE configuration in Backup Domain control register */
	445	/* Requires to enable write access to Backup Domain of necessary */
	446	if(__HAL_RCC_PWR_IS_CLK_DISABLED())
	447	{
	448	__HAL_RCC_PWR_CLK_ENABLE();
	449	pwrclkchanged = SET;
	450	}
	451
	452	if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
	453	{
	454	/* Enable write access to Backup domain */
	455	SET_BIT(PWR->CR, PWR_CR_DBP);
	456
	457	/* Wait for Backup domain Write protection disable */
	458	tickstart = HAL_GetTick();
	459
	460	while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
	461	{
	462	if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
	463	{
	464	return HAL_TIMEOUT;
	465	}
	466	}
	467	}
	468
	469	/* Set the new LSE configuration -----------------------------------------*/
	470	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
	471	/* Check the LSE State */
	472	if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
	473	{
	474	/* Get Start Tick */
	475	tickstart = HAL_GetTick();
	476
	477	/* Wait till LSE is ready */
	478	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
	479	{
	480	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
	481	{
	482	return HAL_TIMEOUT;
	483	}
	484	}
	485	}
	486	else
	487	{
	488	/* Get Start Tick */
	489	tickstart = HAL_GetTick();
	490
	491	/* Wait till LSE is disabled */
	492	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
	493	{
	494	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
	495	{
	496	return HAL_TIMEOUT;
	497	}
	498	}
	499	}
	500
	501	/* Require to disable power clock if necessary */
	502	if(pwrclkchanged == SET)
	503	{
	504	__HAL_RCC_PWR_CLK_DISABLE();
	505	}
	506	}
	507
	508	/----------------------------- HSI14 Configuration --------------------------/
	509	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
	510	{
	511	/* Check the parameters */
	512	assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
	513	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
	514
	515	/* Check the HSI14 State */
	516	if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
	517	{
	518	/* Disable ADC control of the Internal High Speed oscillator HSI14 */
	519	__HAL_RCC_HSI14ADC_DISABLE();
	520
	521	/* Enable the Internal High Speed oscillator (HSI). */
	522	__HAL_RCC_HSI14_ENABLE();
	523
	524	/* Get Start Tick */
	525	tickstart = HAL_GetTick();
	526
	527	/* Wait till HSI is ready */
	528	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
	529	{
	530	if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
	531	{
	532	return HAL_TIMEOUT;
	533	}
	534	}
	535
	536	/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
	537	__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
	538	}
	539	else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
	540	{
	541	/* Enable ADC control of the Internal High Speed oscillator HSI14 */
	542	__HAL_RCC_HSI14ADC_ENABLE();
	543
	544	/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
	545	__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
	546	}
	547	else
	548	{
	549	/* Disable ADC control of the Internal High Speed oscillator HSI14 */
	550	__HAL_RCC_HSI14ADC_DISABLE();
	551
	552	/* Disable the Internal High Speed oscillator (HSI). */
	553	__HAL_RCC_HSI14_DISABLE();
	554
	555	/* Get Start Tick */
	556	tickstart = HAL_GetTick();
	557
	558	/* Wait till HSI is ready */
	559	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
	560	{
	561	if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
	562	{
	563	return HAL_TIMEOUT;
	564	}
	565	}
	566	}
	567	}
	568
	569	#if defined(RCC_HSI48_SUPPORT)
	570	/----------------------------- HSI48 Configuration --------------------------/
	571	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
	572	{
	573	/* Check the parameters */
	574	assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
	575
	576	/* When the HSI48 is used as system clock it is not allowed to be disabled */
	577	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) \|\|
	578	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
	579	{
	580	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
	581	{
	582	return HAL_ERROR;
	583	}
	584	}
	585	else
	586	{
	587	/* Check the HSI48 State */
	588	if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
	589	{
	590	/* Enable the Internal High Speed oscillator (HSI48). */
	591	__HAL_RCC_HSI48_ENABLE();
	592
	593	/* Get Start Tick */
	594	tickstart = HAL_GetTick();
	595
	596	/* Wait till HSI48 is ready */
	597	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
	598	{
	599	if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
	600	{
	601	return HAL_TIMEOUT;
	602	}
	603	}
	604	}
	605	else
	606	{
	607	/* Disable the Internal High Speed oscillator (HSI48). */
	608	__HAL_RCC_HSI48_DISABLE();
	609
	610	/* Get Start Tick */
	611	tickstart = HAL_GetTick();
	612
	613	/* Wait till HSI48 is ready */
	614	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
	615	{
	616	if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
	617	{
	618	return HAL_TIMEOUT;
	619	}
	620	}
	621	}
	622	}
	623	}
	624	#endif /* RCC_HSI48_SUPPORT */
	625
	626	/-------------------------------- PLL Configuration -----------------------/
	627	/* Check the parameters */
	628	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
	629	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
	630	{
	631	/* Check if the PLL is used as system clock or not */
	632	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
	633	{
	634	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
	635	{
	636	/* Check the parameters */
	637	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
	638	assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
	639	assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
	640
	641	/* Disable the main PLL. */
	642	__HAL_RCC_PLL_DISABLE();
	643
	644	/* Get Start Tick */
	645	tickstart = HAL_GetTick();
	646
	647	/* Wait till PLL is disabled */
	648	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
	649	{
	650	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
	651	{
	652	return HAL_TIMEOUT;
	653	}
	654	}
	655
	656	/* Configure the main PLL clock source, predivider and multiplication factor. */
	657	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
	658	RCC_OscInitStruct->PLL.PREDIV,
	659	RCC_OscInitStruct->PLL.PLLMUL);
	660	/* Enable the main PLL. */
	661	__HAL_RCC_PLL_ENABLE();
	662
	663	/* Get Start Tick */
	664	tickstart = HAL_GetTick();
	665
	666	/* Wait till PLL is ready */
	667	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
	668	{
	669	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
	670	{
	671	return HAL_TIMEOUT;
	672	}
	673	}
	674	}
	675	else
	676	{
	677	/* Disable the main PLL. */
	678	__HAL_RCC_PLL_DISABLE();
	679
	680	/* Get Start Tick */
	681	tickstart = HAL_GetTick();
	682
	683	/* Wait till PLL is disabled */
	684	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
	685	{
	686	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
	687	{
	688	return HAL_TIMEOUT;
	689	}
	690	}
	691	}
	692	}
	693	else
	694	{
	695	return HAL_ERROR;
	696	}
	697	}
	698
	699	return HAL_OK;
	700	}
	701
	702	/**
	703	* @brief Initializes the CPU, AHB and APB buses clocks according to the specified
	704	* parameters in the RCC_ClkInitStruct.
	705	* @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
	706	* contains the configuration information for the RCC peripheral.
	707	* @param FLatency FLASH Latency
	708	* The value of this parameter depend on device used within the same series
	709	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
	710	* and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
	711	*
	712	* @note The HSI is used (enabled by hardware) as system clock source after
	713	* start-up from Reset, wake-up from STOP and STANDBY mode, or in case
	714	* of failure of the HSE used directly or indirectly as system clock
	715	* (if the Clock Security System CSS is enabled).
	716	*
	717	* @note A switch from one clock source to another occurs only if the target
	718	* clock source is ready (clock stable after start-up delay or PLL locked).
	719	* If a clock source which is not yet ready is selected, the switch will
	720	* occur when the clock source will be ready.
	721	* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
	722	* currently used as system clock source.
	723	* @retval HAL status
	724	*/
	725	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
	726	{
	727	uint32_t tickstart = 0U;
	728
	729	/* Check the parameters */
	730	assert_param(RCC_ClkInitStruct != NULL);
	731	assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
	732	assert_param(IS_FLASH_LATENCY(FLatency));
	733
	734	/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
	735	must be correctly programmed according to the frequency of the CPU clock
	736	(HCLK) of the device. */
	737
	738	/* Increasing the number of wait states because of higher CPU frequency */
	739	if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
	740	{
	741	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
	742	__HAL_FLASH_SET_LATENCY(FLatency);
	743
	744	/* Check that the new number of wait states is taken into account to access the Flash
	745	memory by reading the FLASH_ACR register */
	746	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
	747	{
	748	return HAL_ERROR;
	749	}
	750	}
	751
	752	/-------------------------- HCLK Configuration --------------------------/
	753	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
	754	{
	755	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
	756	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
	757	}
	758
	759	/------------------------- SYSCLK Configuration ---------------------------/
	760	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
	761	{
	762	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
	763
	764	/* HSE is selected as System Clock Source */
	765	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
	766	{
	767	/* Check the HSE ready flag */
	768	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
	769	{
	770	return HAL_ERROR;
	771	}
	772	}
	773	/* PLL is selected as System Clock Source */
	774	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
	775	{
	776	/* Check the PLL ready flag */
	777	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
	778	{
	779	return HAL_ERROR;
	780	}
	781	}
	782	#if defined(RCC_CFGR_SWS_HSI48)
	783	/* HSI48 is selected as System Clock Source */
	784	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
	785	{
	786	/* Check the HSI48 ready flag */
	787	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
	788	{
	789	return HAL_ERROR;
	790	}
	791	}
	792	#endif /* RCC_CFGR_SWS_HSI48 */
	793	/* HSI is selected as System Clock Source */
	794	else
	795	{
	796	/* Check the HSI ready flag */
	797	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
	798	{
	799	return HAL_ERROR;
	800	}
	801	}
	802	__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
	803
	804	/* Get Start Tick */
	805	tickstart = HAL_GetTick();
	806
	807	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
	808	{
	809	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
	810	{
	811	if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
	812	{
	813	return HAL_TIMEOUT;
	814	}
	815	}
	816	}
	817	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
	818	{
	819	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
	820	{
	821	if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
	822	{
	823	return HAL_TIMEOUT;
	824	}
	825	}
	826	}
	827	#if defined(RCC_CFGR_SWS_HSI48)
	828	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
	829	{
	830	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
	831	{
	832	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
	833	{
	834	return HAL_TIMEOUT;
	835	}
	836	}
	837	}
	838	#endif /* RCC_CFGR_SWS_HSI48 */
	839	else
	840	{
	841	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
	842	{
	843	if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
	844	{
	845	return HAL_TIMEOUT;
	846	}
	847	}
	848	}
	849	}
	850	/* Decreasing the number of wait states because of lower CPU frequency */
	851	if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
	852	{
	853	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
	854	__HAL_FLASH_SET_LATENCY(FLatency);
	855
	856	/* Check that the new number of wait states is taken into account to access the Flash
	857	memory by reading the FLASH_ACR register */
	858	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
	859	{
	860	return HAL_ERROR;
	861	}
	862	}
	863
	864	/-------------------------- PCLK1 Configuration ---------------------------/
	865	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
	866	{
	867	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
	868	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
	869	}
	870
	871	/* Update the SystemCoreClock global variable */
	872	SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
	873
	874	/* Configure the source of time base considering new system clocks settings*/
	875	HAL_InitTick (TICK_INT_PRIORITY);
	876
	877	return HAL_OK;
	878	}
	879
	880	/**
	881	* @}
	882	*/
	883
	884	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
	885	* @brief RCC clocks control functions
	886	*
	887	@verbatim
	888	===============================================================================
	889	##### Peripheral Control functions #####
	890	===============================================================================
	891	[..]
	892	This subsection provides a set of functions allowing to control the RCC Clocks
	893	frequencies.
	894
	895	@endverbatim
	896	* @{
	897	*/
	898
	899	#if defined(RCC_CFGR_MCOPRE)
	900	/**
	901	* @brief Selects the clock source to output on MCO pin.
	902	* @note MCO pin should be configured in alternate function mode.
	903	* @param RCC_MCOx specifies the output direction for the clock source.
	904	* This parameter can be one of the following values:
	905	* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
	906	* @param RCC_MCOSource specifies the clock source to output.
	907	* This parameter can be one of the following values:
	908	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected
	909	* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
	910	* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
	911	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
	912	* @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
	913	* @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
	914	* @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
	915	@if STM32F042x6
	916	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
	917	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	918	@elseif STM32F048xx
	919	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
	920	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	921	@elseif STM32F071xB
	922	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
	923	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	924	@elseif STM32F072xB
	925	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
	926	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	927	@elseif STM32F078xx
	928	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
	929	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	930	@elseif STM32F091xC
	931	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
	932	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	933	@elseif STM32F098xx
	934	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
	935	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	936	@elif STM32F030x6
	937	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	938	@elif STM32F030xC
	939	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	940	@elif STM32F031x6
	941	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	942	@elif STM32F038xx
	943	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	944	@elif STM32F070x6
	945	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	946	@elif STM32F070xB
	947	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
	948	@endif
	949	* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
	950	* @param RCC_MCODiv specifies the MCO DIV.
	951	* This parameter can be one of the following values:
	952	* @arg @ref RCC_MCODIV_1 no division applied to MCO clock
	953	* @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
	954	* @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
	955	* @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
	956	* @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
	957	* @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock
	958	* @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock
	959	* @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock
	960	* @retval None
	961	*/
	962	#else
	963	/**
	964	* @brief Selects the clock source to output on MCO pin.
	965	* @note MCO pin should be configured in alternate function mode.
	966	* @param RCC_MCOx specifies the output direction for the clock source.
	967	* This parameter can be one of the following values:
	968	* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
	969	* @param RCC_MCOSource specifies the clock source to output.
	970	* This parameter can be one of the following values:
	971	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
	972	* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
	973	* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
	974	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
	975	* @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
	976	* @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
	977	* @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
	978	* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
	979	* @param RCC_MCODiv specifies the MCO DIV.
	980	* This parameter can be one of the following values:
	981	* @arg @ref RCC_MCODIV_1 no division applied to MCO clock
	982	* @retval None
	983	*/
	984	#endif
	985	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
	986	{
	987	GPIO_InitTypeDef gpio;
	988
	989	/* Check the parameters */
	990	assert_param(IS_RCC_MCO(RCC_MCOx));
	991	assert_param(IS_RCC_MCODIV(RCC_MCODiv));
	992	assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
	993
	994	/* Configure the MCO1 pin in alternate function mode */
	995	gpio.Mode = GPIO_MODE_AF_PP;
	996	gpio.Speed = GPIO_SPEED_FREQ_HIGH;
	997	gpio.Pull = GPIO_NOPULL;
	998	gpio.Pin = MCO1_PIN;
	999	gpio.Alternate = GPIO_AF0_MCO;
	1000
	1001	/* MCO1 Clock Enable */
	1002	MCO1_CLK_ENABLE();
	1003
	1004	HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
	1005
	1006	/* Configure the MCO clock source */
	1007	__HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
	1008	}
	1009
	1010	/**
	1011	* @brief Enables the Clock Security System.
	1012	* @note If a failure is detected on the HSE oscillator clock, this oscillator
	1013	* is automatically disabled and an interrupt is generated to inform the
	1014	* software about the failure (Clock Security System Interrupt, CSSI),
	1015	* allowing the MCU to perform rescue operations. The CSSI is linked to
	1016	* the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
	1017	* @retval None
	1018	*/
	1019	void HAL_RCC_EnableCSS(void)
	1020	{
	1021	SET_BIT(RCC->CR, RCC_CR_CSSON) ;
	1022	}
	1023
	1024	/**
	1025	* @brief Disables the Clock Security System.
	1026	* @retval None
	1027	*/
	1028	void HAL_RCC_DisableCSS(void)
	1029	{
	1030	CLEAR_BIT(RCC->CR, RCC_CR_CSSON) ;
	1031	}
	1032
	1033	/**
	1034	* @brief Returns the SYSCLK frequency
	1035	* @note The system frequency computed by this function is not the real
	1036	* frequency in the chip. It is calculated based on the predefined
	1037	* constant and the selected clock source:
	1038	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
	1039	* @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
	1040	* divided by PREDIV factor(**)
	1041	* @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
	1042	* divided by PREDIV factor(**) or depending on STM32F0xxxx devices either a value based
	1043	* on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the
	1044	* PLL factor.
	1045	* @note (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
	1046	* 8 MHz) but the real value may vary depending on the variations
	1047	* in voltage and temperature.
	1048	* @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
	1049	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
	1050	* frequency of the crystal used. Otherwise, this function may
	1051	* have wrong result.
	1052	*
	1053	* @note The result of this function could be not correct when using fractional
	1054	* value for HSE crystal.
	1055	*
	1056	* @note This function can be used by the user application to compute the
	1057	* baud-rate for the communication peripherals or configure other parameters.
	1058	*
	1059	* @note Each time SYSCLK changes, this function must be called to update the
	1060	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
	1061	*
	1062	* @retval SYSCLK frequency
	1063	*/
	1064	uint32_t HAL_RCC_GetSysClockFreq(void)
	1065	{
	1066	const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
	1067	10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
	1068	const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
	1069	9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
	1070
	1071	uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
	1072	uint32_t sysclockfreq = 0U;
	1073
	1074	tmpreg = RCC->CFGR;
	1075
	1076	/* Get SYSCLK source -------------------------------------------------------*/
	1077	switch (tmpreg & RCC_CFGR_SWS)
	1078	{
	1079	case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
	1080	{
	1081	sysclockfreq = HSE_VALUE;
	1082	break;
	1083	}
	1084	case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
	1085	{
	1086	pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
	1087	prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
	1088	if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
	1089	{
	1090	/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
	1091	pllclk = (HSE_VALUE / prediv) * pllmul;
	1092	}
	1093	#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV)
	1094	else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
	1095	{
	1096	/* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */
	1097	pllclk = (HSI48_VALUE / prediv) * pllmul;
	1098	}
	1099	#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */
	1100	else
	1101	{
	1102	#if (defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC))
	1103	/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
	1104	pllclk = (HSI_VALUE / prediv) * pllmul;
	1105	#else
	1106	/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
	1107	pllclk = (uint32_t)((HSI_VALUE >> 1U) * pllmul);
	1108	#endif
	1109	}
	1110	sysclockfreq = pllclk;
	1111	break;
	1112	}
	1113	#if defined(RCC_CFGR_SWS_HSI48)
	1114	case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */
	1115	{
	1116	sysclockfreq = HSI48_VALUE;
	1117	break;
	1118	}
	1119	#endif /* RCC_CFGR_SWS_HSI48 */
	1120	case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
	1121	default: /* HSI used as system clock */
	1122	{
	1123	sysclockfreq = HSI_VALUE;
	1124	break;
	1125	}
	1126	}
	1127	return sysclockfreq;
	1128	}
	1129
	1130	/**
	1131	* @brief Returns the HCLK frequency
	1132	* @note Each time HCLK changes, this function must be called to update the
	1133	* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
	1134	*
	1135	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
	1136	* and updated within this function
	1137	* @retval HCLK frequency
	1138	*/
	1139	uint32_t HAL_RCC_GetHCLKFreq(void)
	1140	{
	1141	return SystemCoreClock;
	1142	}
	1143
	1144	/**
	1145	* @brief Returns the PCLK1 frequency
	1146	* @note Each time PCLK1 changes, this function must be called to update the
	1147	* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
	1148	* @retval PCLK1 frequency
	1149	*/
	1150	uint32_t HAL_RCC_GetPCLK1Freq(void)
	1151	{
	1152	/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
	1153	return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]);
	1154	}
	1155
	1156	/**
	1157	* @brief Configures the RCC_OscInitStruct according to the internal
	1158	* RCC configuration registers.
	1159	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
	1160	* will be configured.
	1161	* @retval None
	1162	*/
	1163	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
	1164	{
	1165	/* Check the parameters */
	1166	assert_param(RCC_OscInitStruct != NULL);
	1167
	1168	/* Set all possible values for the Oscillator type parameter ---------------*/
	1169	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \
	1170	\| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI \| RCC_OSCILLATORTYPE_HSI14;
	1171	#if defined(RCC_HSI48_SUPPORT)
	1172	RCC_OscInitStruct->OscillatorType \|= RCC_OSCILLATORTYPE_HSI48;
	1173	#endif /* RCC_HSI48_SUPPORT */
	1174
	1175
	1176	/* Get the HSE configuration -----------------------------------------------*/
	1177	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
	1178	{
	1179	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
	1180	}
	1181	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
	1182	{
	1183	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
	1184	}
	1185	else
	1186	{
	1187	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
	1188	}
	1189
	1190	/* Get the HSI configuration -----------------------------------------------*/
	1191	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
	1192	{
	1193	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
	1194	}
	1195	else
	1196	{
	1197	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
	1198	}
	1199
	1200	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber);
	1201
	1202	/* Get the LSE configuration -----------------------------------------------*/
	1203	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
	1204	{
	1205	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
	1206	}
	1207	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
	1208	{
	1209	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
	1210	}
	1211	else
	1212	{
	1213	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
	1214	}
	1215
	1216	/* Get the LSI configuration -----------------------------------------------*/
	1217	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
	1218	{
	1219	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
	1220	}
	1221	else
	1222	{
	1223	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
	1224	}
	1225
	1226	/* Get the HSI14 configuration -----------------------------------------------*/
	1227	if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON)
	1228	{
	1229	RCC_OscInitStruct->HSI14State = RCC_HSI_ON;
	1230	}
	1231	else
	1232	{
	1233	RCC_OscInitStruct->HSI14State = RCC_HSI_OFF;
	1234	}
	1235
	1236	RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_HSI14TRIM_BIT_NUMBER);
	1237
	1238	#if defined(RCC_HSI48_SUPPORT)
	1239	/* Get the HSI48 configuration if any-----------------------------------------*/
	1240	RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE();
	1241	#endif /* RCC_HSI48_SUPPORT */
	1242
	1243	/* Get the PLL configuration -----------------------------------------------*/
	1244	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
	1245	{
	1246	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
	1247	}
	1248	else
	1249	{
	1250	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
	1251	}
	1252	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
	1253	RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
	1254	RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
	1255	}
	1256
	1257	/**
	1258	* @brief Get the RCC_ClkInitStruct according to the internal
	1259	* RCC configuration registers.
	1260	* @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
	1261	* contains the current clock configuration.
	1262	* @param pFLatency Pointer on the Flash Latency.
	1263	* @retval None
	1264	*/
	1265	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)
	1266	{
	1267	/* Check the parameters */
	1268	assert_param(RCC_ClkInitStruct != NULL);
	1269	assert_param(pFLatency != NULL);
	1270
	1271	/* Set all possible values for the Clock type parameter --------------------*/
	1272	RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1;
	1273
	1274	/* Get the SYSCLK configuration --------------------------------------------*/
	1275	RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
	1276
	1277	/* Get the HCLK configuration ----------------------------------------------*/
	1278	RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
	1279
	1280	/* Get the APB1 configuration ----------------------------------------------*/
	1281	RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
	1282	/* Get the Flash Wait State (Latency) configuration ------------------------*/
	1283	*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
	1284	}
	1285
	1286	/**
	1287	* @brief This function handles the RCC CSS interrupt request.
	1288	* @note This API should be called under the NMI_Handler().
	1289	* @retval None
	1290	*/
	1291	void HAL_RCC_NMI_IRQHandler(void)
	1292	{
	1293	/* Check RCC CSSF flag */
	1294	if(__HAL_RCC_GET_IT(RCC_IT_CSS))
	1295	{
	1296	/* RCC Clock Security System interrupt user callback */
	1297	HAL_RCC_CSSCallback();
	1298
	1299	/* Clear RCC CSS pending bit */
	1300	__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
	1301	}
	1302	}
	1303
	1304	/**
	1305	* @brief RCC Clock Security System interrupt callback
	1306	* @retval none
	1307	*/
	1308	__weak void HAL_RCC_CSSCallback(void)
	1309	{
	1310	/* NOTE : This function Should not be modified, when the callback is needed,
	1311	the HAL_RCC_CSSCallback could be implemented in the user file
	1312	*/
	1313	}
	1314
	1315	/**
	1316	* @}
	1317	*/
	1318
	1319	/**
	1320	* @}
	1321	*/
	1322
	1323	#endif /* HAL_RCC_MODULE_ENABLED */
	1324	/**
	1325	* @}
	1326	*/
	1327
	1328	/**
	1329	* @}
	1330	*/
	1331
	1332	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/