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| bfc108 | 1 | /** |
| Q | 2 | ****************************************************************************** |
| 3 | * @file stm32f070xb.h | |
| 4 | * @author MCD Application Team | |
| 5 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. | |
| 6 | * This file contains all the peripheral register's definitions, bits | |
| 7 | * definitions and memory mapping for STM32F0xx devices. | |
| 8 | * | |
| 9 | * This file contains: | |
| 10 | * - Data structures and the address mapping for all peripherals | |
| 11 | * - Peripheral's registers declarations and bits definition | |
| 12 | * - Macros to access peripheral抯 registers hardware | |
| 13 | * | |
| 14 | ****************************************************************************** | |
| 15 | * @attention | |
| 16 | * | |
| 17 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> | |
| 18 | * | |
| 19 | * Redistribution and use in source and binary forms, with or without modification, | |
| 20 | * are permitted provided that the following conditions are met: | |
| 21 | * 1. Redistributions of source code must retain the above copyright notice, | |
| 22 | * this list of conditions and the following disclaimer. | |
| 23 | * 2. Redistributions in binary form must reproduce the above copyright notice, | |
| 24 | * this list of conditions and the following disclaimer in the documentation | |
| 25 | * and/or other materials provided with the distribution. | |
| 26 | * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
| 27 | * may be used to endorse or promote products derived from this software | |
| 28 | * without specific prior written permission. | |
| 29 | * | |
| 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
| 31 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 32 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
| 33 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
| 34 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
| 36 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
| 37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
| 38 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 39 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 40 | * | |
| 41 | ****************************************************************************** | |
| 42 | */ | |
| 43 | ||
| 44 | /** @addtogroup CMSIS | |
| 45 | * @{ | |
| 46 | */ | |
| 47 | ||
| 48 | /** @addtogroup stm32f070xb | |
| 49 | * @{ | |
| 50 | */ | |
| 51 | ||
| 52 | #ifndef __STM32F070xB_H | |
| 53 | #define __STM32F070xB_H | |
| 54 | ||
| 55 | #ifdef __cplusplus | |
| 56 | extern "C" { | |
| 57 | #endif /* __cplusplus */ | |
| 58 | ||
| 59 | /** @addtogroup Configuration_section_for_CMSIS | |
| 60 | * @{ | |
| 61 | */ | |
| 62 | /** | |
| 63 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals | |
| 64 | */ | |
| 65 | #define __CM0_REV 0 /*!< Core Revision r0p0 */ | |
| 66 | #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ | |
| 67 | #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ | |
| 68 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ | |
| 69 | ||
| 70 | /** | |
| 71 | * @} | |
| 72 | */ | |
| 73 | ||
| 74 | /** @addtogroup Peripheral_interrupt_number_definition | |
| 75 | * @{ | |
| 76 | */ | |
| 77 | ||
| 78 | /** | |
| 79 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device | |
| 80 | * in @ref Library_configuration_section | |
| 81 | */ | |
| 82 | ||
| 83 | /*!< Interrupt Number Definition */ | |
| 84 | typedef enum | |
| 85 | { | |
| 86 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ | |
| 87 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ | |
| 88 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ | |
| 89 | SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ | |
| 90 | PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ | |
| 91 | SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ | |
| 92 | ||
| 93 | /****** STM32F0 specific Interrupt Numbers ******************************************************************/ | |
| 94 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ | |
| 95 | RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ | |
| 96 | FLASH_IRQn = 3, /*!< FLASH global Interrupt */ | |
| 97 | RCC_IRQn = 4, /*!< RCC global Interrupt */ | |
| 98 | EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ | |
| 99 | EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ | |
| 100 | EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ | |
| 101 | DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ | |
| 102 | DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ | |
| 103 | DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ | |
| 104 | ADC1_IRQn = 12, /*!< ADC1 Interrupt */ | |
| 105 | TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ | |
| 106 | TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ | |
| 107 | TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ | |
| 108 | TIM6_IRQn = 17, /*!< TIM6 global Interrupt */ | |
| 109 | TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ | |
| 110 | TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ | |
| 111 | TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ | |
| 112 | TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ | |
| 113 | TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ | |
| 114 | I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ | |
| 115 | I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ | |
| 116 | SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ | |
| 117 | SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ | |
| 118 | USART1_IRQn = 27, /*!< USART1 global Interrupt */ | |
| 119 | USART2_IRQn = 28, /*!< USART2 global Interrupt */ | |
| 120 | USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupt */ | |
| 121 | USB_IRQn = 31 /*!< USB global Interrupt & EXTI Line18 Interrupt */ | |
| 122 | } IRQn_Type; | |
| 123 | ||
| 124 | /** | |
| 125 | * @} | |
| 126 | */ | |
| 127 | ||
| 128 | #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ | |
| 129 | #include "system_stm32f0xx.h" /* STM32F0xx System Header */ | |
| 130 | #include <stdint.h> | |
| 131 | ||
| 132 | /** @addtogroup Peripheral_registers_structures | |
| 133 | * @{ | |
| 134 | */ | |
| 135 | ||
| 136 | /** | |
| 137 | * @brief Analog to Digital Converter | |
| 138 | */ | |
| 139 | ||
| 140 | typedef struct | |
| 141 | { | |
| 142 | __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ | |
| 143 | __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ | |
| 144 | __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ | |
| 145 | __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ | |
| 146 | __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ | |
| 147 | __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ | |
| 148 | uint32_t RESERVED1; /*!< Reserved, 0x18 */ | |
| 149 | uint32_t RESERVED2; /*!< Reserved, 0x1C */ | |
| 150 | __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ | |
| 151 | uint32_t RESERVED3; /*!< Reserved, 0x24 */ | |
| 152 | __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ | |
| 153 | uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ | |
| 154 | __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ | |
| 155 | } ADC_TypeDef; | |
| 156 | ||
| 157 | typedef struct | |
| 158 | { | |
| 159 | __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ | |
| 160 | } ADC_Common_TypeDef; | |
| 161 | ||
| 162 | /** | |
| 163 | * @brief CRC calculation unit | |
| 164 | */ | |
| 165 | ||
| 166 | typedef struct | |
| 167 | { | |
| 168 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ | |
| 169 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ | |
| 170 | uint8_t RESERVED0; /*!< Reserved, 0x05 */ | |
| 171 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ | |
| 172 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ | |
| 173 | uint32_t RESERVED2; /*!< Reserved, 0x0C */ | |
| 174 | __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ | |
| 175 | __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ | |
| 176 | } CRC_TypeDef; | |
| 177 | ||
| 178 | /** | |
| 179 | * @brief Debug MCU | |
| 180 | */ | |
| 181 | ||
| 182 | typedef struct | |
| 183 | { | |
| 184 | __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ | |
| 185 | __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ | |
| 186 | __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ | |
| 187 | __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ | |
| 188 | }DBGMCU_TypeDef; | |
| 189 | ||
| 190 | /** | |
| 191 | * @brief DMA Controller | |
| 192 | */ | |
| 193 | ||
| 194 | typedef struct | |
| 195 | { | |
| 196 | __IO uint32_t CCR; /*!< DMA channel x configuration register */ | |
| 197 | __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ | |
| 198 | __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ | |
| 199 | __IO uint32_t CMAR; /*!< DMA channel x memory address register */ | |
| 200 | } DMA_Channel_TypeDef; | |
| 201 | ||
| 202 | typedef struct | |
| 203 | { | |
| 204 | __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ | |
| 205 | __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ | |
| 206 | } DMA_TypeDef; | |
| 207 | ||
| 208 | /** | |
| 209 | * @brief External Interrupt/Event Controller | |
| 210 | */ | |
| 211 | ||
| 212 | typedef struct | |
| 213 | { | |
| 214 | __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ | |
| 215 | __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ | |
| 216 | __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ | |
| 217 | __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ | |
| 218 | __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ | |
| 219 | __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ | |
| 220 | } EXTI_TypeDef; | |
| 221 | ||
| 222 | /** | |
| 223 | * @brief FLASH Registers | |
| 224 | */ | |
| 225 | typedef struct | |
| 226 | { | |
| 227 | __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */ | |
| 228 | __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */ | |
| 229 | __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */ | |
| 230 | __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */ | |
| 231 | __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */ | |
| 232 | __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */ | |
| 233 | __IO uint32_t RESERVED; /*!< Reserved, 0x18 */ | |
| 234 | __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */ | |
| 235 | __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */ | |
| 236 | } FLASH_TypeDef; | |
| 237 | ||
| 238 | /** | |
| 239 | * @brief Option Bytes Registers | |
| 240 | */ | |
| 241 | typedef struct | |
| 242 | { | |
| 243 | __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ | |
| 244 | __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ | |
| 245 | __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ | |
| 246 | __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ | |
| 247 | __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ | |
| 248 | __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ | |
| 249 | __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */ | |
| 250 | __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */ | |
| 251 | } OB_TypeDef; | |
| 252 | ||
| 253 | /** | |
| 254 | * @brief General Purpose I/O | |
| 255 | */ | |
| 256 | ||
| 257 | typedef struct | |
| 258 | { | |
| 259 | __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ | |
| 260 | __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ | |
| 261 | __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ | |
| 262 | __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ | |
| 263 | __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ | |
| 264 | __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ | |
| 265 | __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ | |
| 266 | __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ | |
| 267 | __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ | |
| 268 | __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ | |
| 269 | } GPIO_TypeDef; | |
| 270 | ||
| 271 | /** | |
| 272 | * @brief SysTem Configuration | |
| 273 | */ | |
| 274 | ||
| 275 | typedef struct | |
| 276 | { | |
| 277 | __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ | |
| 278 | uint32_t RESERVED; /*!< Reserved, 0x04 */ | |
| 279 | __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ | |
| 280 | __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ | |
| 281 | } SYSCFG_TypeDef; | |
| 282 | ||
| 283 | /** | |
| 284 | * @brief Inter-integrated Circuit Interface | |
| 285 | */ | |
| 286 | ||
| 287 | typedef struct | |
| 288 | { | |
| 289 | __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ | |
| 290 | __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ | |
| 291 | __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ | |
| 292 | __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ | |
| 293 | __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ | |
| 294 | __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ | |
| 295 | __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ | |
| 296 | __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ | |
| 297 | __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ | |
| 298 | __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ | |
| 299 | __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ | |
| 300 | } I2C_TypeDef; | |
| 301 | ||
| 302 | /** | |
| 303 | * @brief Independent WATCHDOG | |
| 304 | */ | |
| 305 | ||
| 306 | typedef struct | |
| 307 | { | |
| 308 | __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ | |
| 309 | __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ | |
| 310 | __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ | |
| 311 | __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ | |
| 312 | __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ | |
| 313 | } IWDG_TypeDef; | |
| 314 | ||
| 315 | /** | |
| 316 | * @brief Power Control | |
| 317 | */ | |
| 318 | ||
| 319 | typedef struct | |
| 320 | { | |
| 321 | __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ | |
| 322 | __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ | |
| 323 | } PWR_TypeDef; | |
| 324 | ||
| 325 | /** | |
| 326 | * @brief Reset and Clock Control | |
| 327 | */ | |
| 328 | ||
| 329 | typedef struct | |
| 330 | { | |
| 331 | __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ | |
| 332 | __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ | |
| 333 | __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ | |
| 334 | __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ | |
| 335 | __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ | |
| 336 | __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ | |
| 337 | __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ | |
| 338 | __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ | |
| 339 | __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ | |
| 340 | __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ | |
| 341 | __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ | |
| 342 | __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ | |
| 343 | __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ | |
| 344 | __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */ | |
| 345 | } RCC_TypeDef; | |
| 346 | ||
| 347 | /** | |
| 348 | * @brief Real-Time Clock | |
| 349 | */ | |
| 350 | typedef struct | |
| 351 | { | |
| 352 | __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ | |
| 353 | __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ | |
| 354 | __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ | |
| 355 | __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ | |
| 356 | __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ | |
| 357 | __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ | |
| 358 | uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ | |
| 359 | __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ | |
| 360 | uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ | |
| 361 | __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ | |
| 362 | __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ | |
| 363 | __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ | |
| 364 | __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ | |
| 365 | __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ | |
| 366 | __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ | |
| 367 | __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ | |
| 368 | __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ | |
| 369 | __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ | |
| 370 | } RTC_TypeDef; | |
| 371 | ||
| 372 | /** | |
| 373 | * @brief Serial Peripheral Interface | |
| 374 | */ | |
| 375 | ||
| 376 | typedef struct | |
| 377 | { | |
| 378 | __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ | |
| 379 | __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ | |
| 380 | __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ | |
| 381 | __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ | |
| 382 | __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ | |
| 383 | __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ | |
| 384 | __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ | |
| 385 | __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ | |
| 386 | } SPI_TypeDef; | |
| 387 | ||
| 388 | /** | |
| 389 | * @brief TIM | |
| 390 | */ | |
| 391 | typedef struct | |
| 392 | { | |
| 393 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ | |
| 394 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ | |
| 395 | __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ | |
| 396 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ | |
| 397 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ | |
| 398 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ | |
| 399 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ | |
| 400 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ | |
| 401 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ | |
| 402 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ | |
| 403 | __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ | |
| 404 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ | |
| 405 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ | |
| 406 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ | |
| 407 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ | |
| 408 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ | |
| 409 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ | |
| 410 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ | |
| 411 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ | |
| 412 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ | |
| 413 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ | |
| 414 | } TIM_TypeDef; | |
| 415 | ||
| 416 | /** | |
| 417 | * @brief Universal Synchronous Asynchronous Receiver Transmitter | |
| 418 | */ | |
| 419 | ||
| 420 | typedef struct | |
| 421 | { | |
| 422 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ | |
| 423 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ | |
| 424 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ | |
| 425 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ | |
| 426 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ | |
| 427 | __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ | |
| 428 | __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ | |
| 429 | __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ | |
| 430 | __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ | |
| 431 | __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ | |
| 432 | uint16_t RESERVED1; /*!< Reserved, 0x26 */ | |
| 433 | __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ | |
| 434 | uint16_t RESERVED2; /*!< Reserved, 0x2A */ | |
| 435 | } USART_TypeDef; | |
| 436 | ||
| 437 | /** | |
| 438 | * @brief Universal Serial Bus Full Speed Device | |
| 439 | */ | |
| 440 | ||
| 441 | typedef struct | |
| 442 | { | |
| 443 | __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ | |
| 444 | __IO uint16_t RESERVED0; /*!< Reserved */ | |
| 445 | __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ | |
| 446 | __IO uint16_t RESERVED1; /*!< Reserved */ | |
| 447 | __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ | |
| 448 | __IO uint16_t RESERVED2; /*!< Reserved */ | |
| 449 | __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ | |
| 450 | __IO uint16_t RESERVED3; /*!< Reserved */ | |
| 451 | __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ | |
| 452 | __IO uint16_t RESERVED4; /*!< Reserved */ | |
| 453 | __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ | |
| 454 | __IO uint16_t RESERVED5; /*!< Reserved */ | |
| 455 | __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ | |
| 456 | __IO uint16_t RESERVED6; /*!< Reserved */ | |
| 457 | __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ | |
| 458 | __IO uint16_t RESERVED7[17]; /*!< Reserved */ | |
| 459 | __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ | |
| 460 | __IO uint16_t RESERVED8; /*!< Reserved */ | |
| 461 | __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ | |
| 462 | __IO uint16_t RESERVED9; /*!< Reserved */ | |
| 463 | __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ | |
| 464 | __IO uint16_t RESERVEDA; /*!< Reserved */ | |
| 465 | __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ | |
| 466 | __IO uint16_t RESERVEDB; /*!< Reserved */ | |
| 467 | __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ | |
| 468 | __IO uint16_t RESERVEDC; /*!< Reserved */ | |
| 469 | __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ | |
| 470 | __IO uint16_t RESERVEDD; /*!< Reserved */ | |
| 471 | __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ | |
| 472 | __IO uint16_t RESERVEDE; /*!< Reserved */ | |
| 473 | } USB_TypeDef; | |
| 474 | ||
| 475 | /** | |
| 476 | * @brief Window WATCHDOG | |
| 477 | */ | |
| 478 | typedef struct | |
| 479 | { | |
| 480 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ | |
| 481 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ | |
| 482 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ | |
| 483 | } WWDG_TypeDef; | |
| 484 | ||
| 485 | /** | |
| 486 | * @} | |
| 487 | */ | |
| 488 | ||
| 489 | /** @addtogroup Peripheral_memory_map | |
| 490 | * @{ | |
| 491 | */ | |
| 492 | ||
| 493 | #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */ | |
| 494 | #define FLASH_BANK1_END ((uint32_t)0x0801FFFFU) /*!< FLASH END address of bank1 */ | |
| 495 | #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ | |
| 496 | #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ | |
| 497 | ||
| 498 | /*!< Peripheral memory map */ | |
| 499 | #define APBPERIPH_BASE PERIPH_BASE | |
| 500 | #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) | |
| 501 | #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) | |
| 502 | ||
| 503 | /*!< APB peripherals */ | |
| 504 | #define TIM3_BASE (APBPERIPH_BASE + 0x00000400) | |
| 505 | #define TIM6_BASE (APBPERIPH_BASE + 0x00001000) | |
| 506 | #define TIM7_BASE (APBPERIPH_BASE + 0x00001400) | |
| 507 | #define TIM14_BASE (APBPERIPH_BASE + 0x00002000) | |
| 508 | #define RTC_BASE (APBPERIPH_BASE + 0x00002800) | |
| 509 | #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00) | |
| 510 | #define IWDG_BASE (APBPERIPH_BASE + 0x00003000) | |
| 511 | #define SPI2_BASE (APBPERIPH_BASE + 0x00003800) | |
| 512 | #define USART2_BASE (APBPERIPH_BASE + 0x00004400) | |
| 513 | #define USART3_BASE (APBPERIPH_BASE + 0x00004800) | |
| 514 | #define USART4_BASE (APBPERIPH_BASE + 0x00004C00) | |
| 515 | #define I2C1_BASE (APBPERIPH_BASE + 0x00005400) | |
| 516 | #define I2C2_BASE (APBPERIPH_BASE + 0x00005800) | |
| 517 | #define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ | |
| 518 | #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ | |
| 519 | #define PWR_BASE (APBPERIPH_BASE + 0x00007000) | |
| 520 | #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) | |
| 521 | #define EXTI_BASE (APBPERIPH_BASE + 0x00010400) | |
| 522 | #define ADC1_BASE (APBPERIPH_BASE + 0x00012400) | |
| 523 | #define ADC_BASE (APBPERIPH_BASE + 0x00012708) | |
| 524 | #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00) | |
| 525 | #define SPI1_BASE (APBPERIPH_BASE + 0x00013000) | |
| 526 | #define USART1_BASE (APBPERIPH_BASE + 0x00013800) | |
| 527 | #define TIM15_BASE (APBPERIPH_BASE + 0x00014000) | |
| 528 | #define TIM16_BASE (APBPERIPH_BASE + 0x00014400) | |
| 529 | #define TIM17_BASE (APBPERIPH_BASE + 0x00014800) | |
| 530 | #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800) | |
| 531 | ||
| 532 | /*!< AHB peripherals */ | |
| 533 | #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) | |
| 534 | #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) | |
| 535 | #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) | |
| 536 | #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) | |
| 537 | #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) | |
| 538 | #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) | |
| 539 | ||
| 540 | #define RCC_BASE (AHBPERIPH_BASE + 0x00001000) | |
| 541 | #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */ | |
| 542 | #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< FLASH Option Bytes base address */ | |
| 543 | #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */ | |
| 544 | #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */ | |
| 545 | #define CRC_BASE (AHBPERIPH_BASE + 0x00003000) | |
| 546 | ||
| 547 | /*!< AHB2 peripherals */ | |
| 548 | #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000) | |
| 549 | #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400) | |
| 550 | #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800) | |
| 551 | #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00) | |
| 552 | #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400) | |
| 553 | ||
| 554 | /** | |
| 555 | * @} | |
| 556 | */ | |
| 557 | ||
| 558 | /** @addtogroup Peripheral_declaration | |
| 559 | * @{ | |
| 560 | */ | |
| 561 | ||
| 562 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) | |
| 563 | #define TIM6 ((TIM_TypeDef *) TIM6_BASE) | |
| 564 | #define TIM7 ((TIM_TypeDef *) TIM7_BASE) | |
| 565 | #define TIM14 ((TIM_TypeDef *) TIM14_BASE) | |
| 566 | #define RTC ((RTC_TypeDef *) RTC_BASE) | |
| 567 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) | |
| 568 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) | |
| 569 | #define USART2 ((USART_TypeDef *) USART2_BASE) | |
| 570 | #define USART3 ((USART_TypeDef *) USART3_BASE) | |
| 571 | #define USART4 ((USART_TypeDef *) USART4_BASE) | |
| 572 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) | |
| 573 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) | |
| 574 | #define PWR ((PWR_TypeDef *) PWR_BASE) | |
| 575 | #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) | |
| 576 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) | |
| 577 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) | |
| 578 | #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) | |
| 579 | #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */ | |
| 580 | #define TIM1 ((TIM_TypeDef *) TIM1_BASE) | |
| 581 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) | |
| 582 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) | |
| 583 | #define USART1 ((USART_TypeDef *) USART1_BASE) | |
| 584 | #define TIM15 ((TIM_TypeDef *) TIM15_BASE) | |
| 585 | #define TIM16 ((TIM_TypeDef *) TIM16_BASE) | |
| 586 | #define TIM17 ((TIM_TypeDef *) TIM17_BASE) | |
| 587 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) | |
| 588 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) | |
| 589 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) | |
| 590 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) | |
| 591 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) | |
| 592 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) | |
| 593 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) | |
| 594 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) | |
| 595 | #define OB ((OB_TypeDef *) OB_BASE) | |
| 596 | #define RCC ((RCC_TypeDef *) RCC_BASE) | |
| 597 | #define CRC ((CRC_TypeDef *) CRC_BASE) | |
| 598 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) | |
| 599 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) | |
| 600 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) | |
| 601 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) | |
| 602 | #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) | |
| 603 | #define USB ((USB_TypeDef *) USB_BASE) | |
| 604 | /** | |
| 605 | * @} | |
| 606 | */ | |
| 607 | ||
| 608 | /** @addtogroup Exported_constants | |
| 609 | * @{ | |
| 610 | */ | |
| 611 | ||
| 612 | /** @addtogroup Peripheral_Registers_Bits_Definition | |
| 613 | * @{ | |
| 614 | */ | |
| 615 | ||
| 616 | /******************************************************************************/ | |
| 617 | /* Peripheral Registers Bits Definition */ | |
| 618 | /******************************************************************************/ | |
| 619 | ||
| 620 | /******************************************************************************/ | |
| 621 | /* */ | |
| 622 | /* Analog to Digital Converter (ADC) */ | |
| 623 | /* */ | |
| 624 | /******************************************************************************/ | |
| 625 | ||
| 626 | /* | |
| 627 | * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) | |
| 628 | */ | |
| 629 | /* Note: No specific macro feature on this device */ | |
| 630 | ||
| 631 | /******************** Bits definition for ADC_ISR register ******************/ | |
| 632 | #define ADC_ISR_ADRDY_Pos (0U) | |
| 633 | #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ | |
| 634 | #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ | |
| 635 | #define ADC_ISR_EOSMP_Pos (1U) | |
| 636 | #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ | |
| 637 | #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ | |
| 638 | #define ADC_ISR_EOC_Pos (2U) | |
| 639 | #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ | |
| 640 | #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ | |
| 641 | #define ADC_ISR_EOS_Pos (3U) | |
| 642 | #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ | |
| 643 | #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ | |
| 644 | #define ADC_ISR_OVR_Pos (4U) | |
| 645 | #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ | |
| 646 | #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ | |
| 647 | #define ADC_ISR_AWD1_Pos (7U) | |
| 648 | #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ | |
| 649 | #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ | |
| 650 | ||
| 651 | /* Legacy defines */ | |
| 652 | #define ADC_ISR_AWD (ADC_ISR_AWD1) | |
| 653 | #define ADC_ISR_EOSEQ (ADC_ISR_EOS) | |
| 654 | ||
| 655 | /******************** Bits definition for ADC_IER register ******************/ | |
| 656 | #define ADC_IER_ADRDYIE_Pos (0U) | |
| 657 | #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ | |
| 658 | #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ | |
| 659 | #define ADC_IER_EOSMPIE_Pos (1U) | |
| 660 | #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ | |
| 661 | #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ | |
| 662 | #define ADC_IER_EOCIE_Pos (2U) | |
| 663 | #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ | |
| 664 | #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ | |
| 665 | #define ADC_IER_EOSIE_Pos (3U) | |
| 666 | #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ | |
| 667 | #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ | |
| 668 | #define ADC_IER_OVRIE_Pos (4U) | |
| 669 | #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ | |
| 670 | #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ | |
| 671 | #define ADC_IER_AWD1IE_Pos (7U) | |
| 672 | #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ | |
| 673 | #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ | |
| 674 | ||
| 675 | /* Legacy defines */ | |
| 676 | #define ADC_IER_AWDIE (ADC_IER_AWD1IE) | |
| 677 | #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) | |
| 678 | ||
| 679 | /******************** Bits definition for ADC_CR register *******************/ | |
| 680 | #define ADC_CR_ADEN_Pos (0U) | |
| 681 | #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ | |
| 682 | #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ | |
| 683 | #define ADC_CR_ADDIS_Pos (1U) | |
| 684 | #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ | |
| 685 | #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ | |
| 686 | #define ADC_CR_ADSTART_Pos (2U) | |
| 687 | #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ | |
| 688 | #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ | |
| 689 | #define ADC_CR_ADSTP_Pos (4U) | |
| 690 | #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ | |
| 691 | #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ | |
| 692 | #define ADC_CR_ADCAL_Pos (31U) | |
| 693 | #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ | |
| 694 | #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ | |
| 695 | ||
| 696 | /******************* Bits definition for ADC_CFGR1 register *****************/ | |
| 697 | #define ADC_CFGR1_DMAEN_Pos (0U) | |
| 698 | #define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ | |
| 699 | #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ | |
| 700 | #define ADC_CFGR1_DMACFG_Pos (1U) | |
| 701 | #define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ | |
| 702 | #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ | |
| 703 | #define ADC_CFGR1_SCANDIR_Pos (2U) | |
| 704 | #define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ | |
| 705 | #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ | |
| 706 | ||
| 707 | #define ADC_CFGR1_RES_Pos (3U) | |
| 708 | #define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ | |
| 709 | #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ | |
| 710 | #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ | |
| 711 | #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ | |
| 712 | ||
| 713 | #define ADC_CFGR1_ALIGN_Pos (5U) | |
| 714 | #define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ | |
| 715 | #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ | |
| 716 | ||
| 717 | #define ADC_CFGR1_EXTSEL_Pos (6U) | |
| 718 | #define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ | |
| 719 | #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ | |
| 720 | #define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ | |
| 721 | #define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ | |
| 722 | #define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ | |
| 723 | ||
| 724 | #define ADC_CFGR1_EXTEN_Pos (10U) | |
| 725 | #define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ | |
| 726 | #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ | |
| 727 | #define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ | |
| 728 | #define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ | |
| 729 | ||
| 730 | #define ADC_CFGR1_OVRMOD_Pos (12U) | |
| 731 | #define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ | |
| 732 | #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ | |
| 733 | #define ADC_CFGR1_CONT_Pos (13U) | |
| 734 | #define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ | |
| 735 | #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ | |
| 736 | #define ADC_CFGR1_WAIT_Pos (14U) | |
| 737 | #define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ | |
| 738 | #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ | |
| 739 | #define ADC_CFGR1_AUTOFF_Pos (15U) | |
| 740 | #define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ | |
| 741 | #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ | |
| 742 | #define ADC_CFGR1_DISCEN_Pos (16U) | |
| 743 | #define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ | |
| 744 | #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ | |
| 745 | ||
| 746 | #define ADC_CFGR1_AWD1SGL_Pos (22U) | |
| 747 | #define ADC_CFGR1_AWD1SGL_Msk (0x1U << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ | |
| 748 | #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ | |
| 749 | #define ADC_CFGR1_AWD1EN_Pos (23U) | |
| 750 | #define ADC_CFGR1_AWD1EN_Msk (0x1U << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ | |
| 751 | #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ | |
| 752 | ||
| 753 | #define ADC_CFGR1_AWD1CH_Pos (26U) | |
| 754 | #define ADC_CFGR1_AWD1CH_Msk (0x1FU << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ | |
| 755 | #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ | |
| 756 | #define ADC_CFGR1_AWD1CH_0 (0x01U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ | |
| 757 | #define ADC_CFGR1_AWD1CH_1 (0x02U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ | |
| 758 | #define ADC_CFGR1_AWD1CH_2 (0x04U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ | |
| 759 | #define ADC_CFGR1_AWD1CH_3 (0x08U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ | |
| 760 | #define ADC_CFGR1_AWD1CH_4 (0x10U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ | |
| 761 | ||
| 762 | /* Legacy defines */ | |
| 763 | #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) | |
| 764 | #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL) | |
| 765 | #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN) | |
| 766 | #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH) | |
| 767 | #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0) | |
| 768 | #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1) | |
| 769 | #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2) | |
| 770 | #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) | |
| 771 | #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) | |
| 772 | ||
| 773 | /******************* Bits definition for ADC_CFGR2 register *****************/ | |
| 774 | #define ADC_CFGR2_CKMODE_Pos (30U) | |
| 775 | #define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ | |
| 776 | #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ | |
| 777 | #define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ | |
| 778 | #define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ | |
| 779 | ||
| 780 | /* Legacy defines */ | |
| 781 | #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */ | |
| 782 | #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */ | |
| 783 | ||
| 784 | /****************** Bit definition for ADC_SMPR register ********************/ | |
| 785 | #define ADC_SMPR_SMP_Pos (0U) | |
| 786 | #define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ | |
| 787 | #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */ | |
| 788 | #define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ | |
| 789 | #define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ | |
| 790 | #define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ | |
| 791 | ||
| 792 | /* Legacy defines */ | |
| 793 | #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */ | |
| 794 | #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */ | |
| 795 | #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */ | |
| 796 | #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */ | |
| 797 | ||
| 798 | /******************* Bit definition for ADC_TR register ********************/ | |
| 799 | #define ADC_TR1_LT1_Pos (0U) | |
| 800 | #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ | |
| 801 | #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ | |
| 802 | #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ | |
| 803 | #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ | |
| 804 | #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ | |
| 805 | #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ | |
| 806 | #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ | |
| 807 | #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ | |
| 808 | #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ | |
| 809 | #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ | |
| 810 | #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ | |
| 811 | #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ | |
| 812 | #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ | |
| 813 | #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ | |
| 814 | ||
| 815 | #define ADC_TR1_HT1_Pos (16U) | |
| 816 | #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ | |
| 817 | #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ | |
| 818 | #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ | |
| 819 | #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ | |
| 820 | #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ | |
| 821 | #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ | |
| 822 | #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ | |
| 823 | #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ | |
| 824 | #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ | |
| 825 | #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ | |
| 826 | #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ | |
| 827 | #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ | |
| 828 | #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ | |
| 829 | #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ | |
| 830 | ||
| 831 | /* Legacy defines */ | |
| 832 | #define ADC_TR_HT (ADC_TR1_HT1) | |
| 833 | #define ADC_TR_LT (ADC_TR1_LT1) | |
| 834 | #define ADC_HTR_HT (ADC_TR1_HT1) | |
| 835 | #define ADC_LTR_LT (ADC_TR1_LT1) | |
| 836 | ||
| 837 | /****************** Bit definition for ADC_CHSELR register ******************/ | |
| 838 | #define ADC_CHSELR_CHSEL_Pos (0U) | |
| 839 | #define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ | |
| 840 | #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 841 | #define ADC_CHSELR_CHSEL18_Pos (18U) | |
| 842 | #define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ | |
| 843 | #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 844 | #define ADC_CHSELR_CHSEL17_Pos (17U) | |
| 845 | #define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ | |
| 846 | #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 847 | #define ADC_CHSELR_CHSEL16_Pos (16U) | |
| 848 | #define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ | |
| 849 | #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 850 | #define ADC_CHSELR_CHSEL15_Pos (15U) | |
| 851 | #define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ | |
| 852 | #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 853 | #define ADC_CHSELR_CHSEL14_Pos (14U) | |
| 854 | #define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ | |
| 855 | #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 856 | #define ADC_CHSELR_CHSEL13_Pos (13U) | |
| 857 | #define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ | |
| 858 | #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 859 | #define ADC_CHSELR_CHSEL12_Pos (12U) | |
| 860 | #define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ | |
| 861 | #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 862 | #define ADC_CHSELR_CHSEL11_Pos (11U) | |
| 863 | #define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ | |
| 864 | #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 865 | #define ADC_CHSELR_CHSEL10_Pos (10U) | |
| 866 | #define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ | |
| 867 | #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 868 | #define ADC_CHSELR_CHSEL9_Pos (9U) | |
| 869 | #define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ | |
| 870 | #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 871 | #define ADC_CHSELR_CHSEL8_Pos (8U) | |
| 872 | #define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ | |
| 873 | #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 874 | #define ADC_CHSELR_CHSEL7_Pos (7U) | |
| 875 | #define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ | |
| 876 | #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 877 | #define ADC_CHSELR_CHSEL6_Pos (6U) | |
| 878 | #define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ | |
| 879 | #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 880 | #define ADC_CHSELR_CHSEL5_Pos (5U) | |
| 881 | #define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ | |
| 882 | #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 883 | #define ADC_CHSELR_CHSEL4_Pos (4U) | |
| 884 | #define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ | |
| 885 | #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 886 | #define ADC_CHSELR_CHSEL3_Pos (3U) | |
| 887 | #define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ | |
| 888 | #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 889 | #define ADC_CHSELR_CHSEL2_Pos (2U) | |
| 890 | #define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ | |
| 891 | #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 892 | #define ADC_CHSELR_CHSEL1_Pos (1U) | |
| 893 | #define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ | |
| 894 | #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 895 | #define ADC_CHSELR_CHSEL0_Pos (0U) | |
| 896 | #define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ | |
| 897 | #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ | |
| 898 | ||
| 899 | /******************** Bit definition for ADC_DR register ********************/ | |
| 900 | #define ADC_DR_DATA_Pos (0U) | |
| 901 | #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ | |
| 902 | #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ | |
| 903 | #define ADC_DR_DATA_0 (0x0001U << ADC_DR_DATA_Pos) /*!< 0x00000001 */ | |
| 904 | #define ADC_DR_DATA_1 (0x0002U << ADC_DR_DATA_Pos) /*!< 0x00000002 */ | |
| 905 | #define ADC_DR_DATA_2 (0x0004U << ADC_DR_DATA_Pos) /*!< 0x00000004 */ | |
| 906 | #define ADC_DR_DATA_3 (0x0008U << ADC_DR_DATA_Pos) /*!< 0x00000008 */ | |
| 907 | #define ADC_DR_DATA_4 (0x0010U << ADC_DR_DATA_Pos) /*!< 0x00000010 */ | |
| 908 | #define ADC_DR_DATA_5 (0x0020U << ADC_DR_DATA_Pos) /*!< 0x00000020 */ | |
| 909 | #define ADC_DR_DATA_6 (0x0040U << ADC_DR_DATA_Pos) /*!< 0x00000040 */ | |
| 910 | #define ADC_DR_DATA_7 (0x0080U << ADC_DR_DATA_Pos) /*!< 0x00000080 */ | |
| 911 | #define ADC_DR_DATA_8 (0x0100U << ADC_DR_DATA_Pos) /*!< 0x00000100 */ | |
| 912 | #define ADC_DR_DATA_9 (0x0200U << ADC_DR_DATA_Pos) /*!< 0x00000200 */ | |
| 913 | #define ADC_DR_DATA_10 (0x0400U << ADC_DR_DATA_Pos) /*!< 0x00000400 */ | |
| 914 | #define ADC_DR_DATA_11 (0x0800U << ADC_DR_DATA_Pos) /*!< 0x00000800 */ | |
| 915 | #define ADC_DR_DATA_12 (0x1000U << ADC_DR_DATA_Pos) /*!< 0x00001000 */ | |
| 916 | #define ADC_DR_DATA_13 (0x2000U << ADC_DR_DATA_Pos) /*!< 0x00002000 */ | |
| 917 | #define ADC_DR_DATA_14 (0x4000U << ADC_DR_DATA_Pos) /*!< 0x00004000 */ | |
| 918 | #define ADC_DR_DATA_15 (0x8000U << ADC_DR_DATA_Pos) /*!< 0x00008000 */ | |
| 919 | ||
| 920 | /************************* ADC Common registers *****************************/ | |
| 921 | /******************* Bit definition for ADC_CCR register ********************/ | |
| 922 | #define ADC_CCR_VREFEN_Pos (22U) | |
| 923 | #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ | |
| 924 | #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ | |
| 925 | #define ADC_CCR_TSEN_Pos (23U) | |
| 926 | #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ | |
| 927 | #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ | |
| 928 | ||
| 929 | ||
| 930 | /******************************************************************************/ | |
| 931 | /* */ | |
| 932 | /* CRC calculation unit (CRC) */ | |
| 933 | /* */ | |
| 934 | /******************************************************************************/ | |
| 935 | /******************* Bit definition for CRC_DR register *********************/ | |
| 936 | #define CRC_DR_DR_Pos (0U) | |
| 937 | #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ | |
| 938 | #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ | |
| 939 | ||
| 940 | /******************* Bit definition for CRC_IDR register ********************/ | |
| 941 | #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ | |
| 942 | ||
| 943 | /******************** Bit definition for CRC_CR register ********************/ | |
| 944 | #define CRC_CR_RESET_Pos (0U) | |
| 945 | #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ | |
| 946 | #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ | |
| 947 | #define CRC_CR_REV_IN_Pos (5U) | |
| 948 | #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ | |
| 949 | #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ | |
| 950 | #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ | |
| 951 | #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ | |
| 952 | #define CRC_CR_REV_OUT_Pos (7U) | |
| 953 | #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ | |
| 954 | #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ | |
| 955 | ||
| 956 | /******************* Bit definition for CRC_INIT register *******************/ | |
| 957 | #define CRC_INIT_INIT_Pos (0U) | |
| 958 | #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ | |
| 959 | #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ | |
| 960 | ||
| 961 | /******************************************************************************/ | |
| 962 | /* */ | |
| 963 | /* Debug MCU (DBGMCU) */ | |
| 964 | /* */ | |
| 965 | /******************************************************************************/ | |
| 966 | ||
| 967 | /**************** Bit definition for DBGMCU_IDCODE register *****************/ | |
| 968 | #define DBGMCU_IDCODE_DEV_ID_Pos (0U) | |
| 969 | #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ | |
| 970 | #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ | |
| 971 | ||
| 972 | #define DBGMCU_IDCODE_REV_ID_Pos (16U) | |
| 973 | #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ | |
| 974 | #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ | |
| 975 | #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ | |
| 976 | #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ | |
| 977 | #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ | |
| 978 | #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ | |
| 979 | #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ | |
| 980 | #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ | |
| 981 | #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ | |
| 982 | #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ | |
| 983 | #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ | |
| 984 | #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ | |
| 985 | #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ | |
| 986 | #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ | |
| 987 | #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ | |
| 988 | #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ | |
| 989 | #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ | |
| 990 | #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ | |
| 991 | ||
| 992 | /****************** Bit definition for DBGMCU_CR register *******************/ | |
| 993 | #define DBGMCU_CR_DBG_STOP_Pos (1U) | |
| 994 | #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ | |
| 995 | #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ | |
| 996 | #define DBGMCU_CR_DBG_STANDBY_Pos (2U) | |
| 997 | #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ | |
| 998 | #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ | |
| 999 | ||
| 1000 | /****************** Bit definition for DBGMCU_APB1_FZ register **************/ | |
| 1001 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) | |
| 1002 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ | |
| 1003 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ | |
| 1004 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) | |
| 1005 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ | |
| 1006 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ | |
| 1007 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) | |
| 1008 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ | |
| 1009 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */ | |
| 1010 | #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) | |
| 1011 | #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ | |
| 1012 | #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */ | |
| 1013 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) | |
| 1014 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ | |
| 1015 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ | |
| 1016 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) | |
| 1017 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ | |
| 1018 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ | |
| 1019 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) | |
| 1020 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ | |
| 1021 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ | |
| 1022 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) | |
| 1023 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ | |
| 1024 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ | |
| 1025 | ||
| 1026 | /****************** Bit definition for DBGMCU_APB2_FZ register **************/ | |
| 1027 | #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U) | |
| 1028 | #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ | |
| 1029 | #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ | |
| 1030 | #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U) | |
| 1031 | #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ | |
| 1032 | #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted */ | |
| 1033 | #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U) | |
| 1034 | #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ | |
| 1035 | #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */ | |
| 1036 | #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U) | |
| 1037 | #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ | |
| 1038 | #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */ | |
| 1039 | ||
| 1040 | /******************************************************************************/ | |
| 1041 | /* */ | |
| 1042 | /* DMA Controller (DMA) */ | |
| 1043 | /* */ | |
| 1044 | /******************************************************************************/ | |
| 1045 | /******************* Bit definition for DMA_ISR register ********************/ | |
| 1046 | #define DMA_ISR_GIF1_Pos (0U) | |
| 1047 | #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ | |
| 1048 | #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ | |
| 1049 | #define DMA_ISR_TCIF1_Pos (1U) | |
| 1050 | #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ | |
| 1051 | #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ | |
| 1052 | #define DMA_ISR_HTIF1_Pos (2U) | |
| 1053 | #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ | |
| 1054 | #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ | |
| 1055 | #define DMA_ISR_TEIF1_Pos (3U) | |
| 1056 | #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ | |
| 1057 | #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ | |
| 1058 | #define DMA_ISR_GIF2_Pos (4U) | |
| 1059 | #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ | |
| 1060 | #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ | |
| 1061 | #define DMA_ISR_TCIF2_Pos (5U) | |
| 1062 | #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ | |
| 1063 | #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ | |
| 1064 | #define DMA_ISR_HTIF2_Pos (6U) | |
| 1065 | #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ | |
| 1066 | #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ | |
| 1067 | #define DMA_ISR_TEIF2_Pos (7U) | |
| 1068 | #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ | |
| 1069 | #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ | |
| 1070 | #define DMA_ISR_GIF3_Pos (8U) | |
| 1071 | #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ | |
| 1072 | #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ | |
| 1073 | #define DMA_ISR_TCIF3_Pos (9U) | |
| 1074 | #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ | |
| 1075 | #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ | |
| 1076 | #define DMA_ISR_HTIF3_Pos (10U) | |
| 1077 | #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ | |
| 1078 | #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ | |
| 1079 | #define DMA_ISR_TEIF3_Pos (11U) | |
| 1080 | #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ | |
| 1081 | #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ | |
| 1082 | #define DMA_ISR_GIF4_Pos (12U) | |
| 1083 | #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ | |
| 1084 | #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ | |
| 1085 | #define DMA_ISR_TCIF4_Pos (13U) | |
| 1086 | #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ | |
| 1087 | #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ | |
| 1088 | #define DMA_ISR_HTIF4_Pos (14U) | |
| 1089 | #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ | |
| 1090 | #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ | |
| 1091 | #define DMA_ISR_TEIF4_Pos (15U) | |
| 1092 | #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ | |
| 1093 | #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ | |
| 1094 | #define DMA_ISR_GIF5_Pos (16U) | |
| 1095 | #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ | |
| 1096 | #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ | |
| 1097 | #define DMA_ISR_TCIF5_Pos (17U) | |
| 1098 | #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ | |
| 1099 | #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ | |
| 1100 | #define DMA_ISR_HTIF5_Pos (18U) | |
| 1101 | #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ | |
| 1102 | #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ | |
| 1103 | #define DMA_ISR_TEIF5_Pos (19U) | |
| 1104 | #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ | |
| 1105 | #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ | |
| 1106 | ||
| 1107 | /******************* Bit definition for DMA_IFCR register *******************/ | |
| 1108 | #define DMA_IFCR_CGIF1_Pos (0U) | |
| 1109 | #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ | |
| 1110 | #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ | |
| 1111 | #define DMA_IFCR_CTCIF1_Pos (1U) | |
| 1112 | #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ | |
| 1113 | #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ | |
| 1114 | #define DMA_IFCR_CHTIF1_Pos (2U) | |
| 1115 | #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ | |
| 1116 | #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ | |
| 1117 | #define DMA_IFCR_CTEIF1_Pos (3U) | |
| 1118 | #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ | |
| 1119 | #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ | |
| 1120 | #define DMA_IFCR_CGIF2_Pos (4U) | |
| 1121 | #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ | |
| 1122 | #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ | |
| 1123 | #define DMA_IFCR_CTCIF2_Pos (5U) | |
| 1124 | #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ | |
| 1125 | #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ | |
| 1126 | #define DMA_IFCR_CHTIF2_Pos (6U) | |
| 1127 | #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ | |
| 1128 | #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ | |
| 1129 | #define DMA_IFCR_CTEIF2_Pos (7U) | |
| 1130 | #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ | |
| 1131 | #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ | |
| 1132 | #define DMA_IFCR_CGIF3_Pos (8U) | |
| 1133 | #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ | |
| 1134 | #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ | |
| 1135 | #define DMA_IFCR_CTCIF3_Pos (9U) | |
| 1136 | #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ | |
| 1137 | #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ | |
| 1138 | #define DMA_IFCR_CHTIF3_Pos (10U) | |
| 1139 | #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ | |
| 1140 | #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ | |
| 1141 | #define DMA_IFCR_CTEIF3_Pos (11U) | |
| 1142 | #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ | |
| 1143 | #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ | |
| 1144 | #define DMA_IFCR_CGIF4_Pos (12U) | |
| 1145 | #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ | |
| 1146 | #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ | |
| 1147 | #define DMA_IFCR_CTCIF4_Pos (13U) | |
| 1148 | #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ | |
| 1149 | #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ | |
| 1150 | #define DMA_IFCR_CHTIF4_Pos (14U) | |
| 1151 | #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ | |
| 1152 | #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ | |
| 1153 | #define DMA_IFCR_CTEIF4_Pos (15U) | |
| 1154 | #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ | |
| 1155 | #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ | |
| 1156 | #define DMA_IFCR_CGIF5_Pos (16U) | |
| 1157 | #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ | |
| 1158 | #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ | |
| 1159 | #define DMA_IFCR_CTCIF5_Pos (17U) | |
| 1160 | #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ | |
| 1161 | #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ | |
| 1162 | #define DMA_IFCR_CHTIF5_Pos (18U) | |
| 1163 | #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ | |
| 1164 | #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ | |
| 1165 | #define DMA_IFCR_CTEIF5_Pos (19U) | |
| 1166 | #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ | |
| 1167 | #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ | |
| 1168 | ||
| 1169 | /******************* Bit definition for DMA_CCR register ********************/ | |
| 1170 | #define DMA_CCR_EN_Pos (0U) | |
| 1171 | #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ | |
| 1172 | #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ | |
| 1173 | #define DMA_CCR_TCIE_Pos (1U) | |
| 1174 | #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ | |
| 1175 | #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ | |
| 1176 | #define DMA_CCR_HTIE_Pos (2U) | |
| 1177 | #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ | |
| 1178 | #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ | |
| 1179 | #define DMA_CCR_TEIE_Pos (3U) | |
| 1180 | #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ | |
| 1181 | #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ | |
| 1182 | #define DMA_CCR_DIR_Pos (4U) | |
| 1183 | #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ | |
| 1184 | #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ | |
| 1185 | #define DMA_CCR_CIRC_Pos (5U) | |
| 1186 | #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ | |
| 1187 | #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ | |
| 1188 | #define DMA_CCR_PINC_Pos (6U) | |
| 1189 | #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ | |
| 1190 | #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ | |
| 1191 | #define DMA_CCR_MINC_Pos (7U) | |
| 1192 | #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ | |
| 1193 | #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ | |
| 1194 | ||
| 1195 | #define DMA_CCR_PSIZE_Pos (8U) | |
| 1196 | #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ | |
| 1197 | #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ | |
| 1198 | #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ | |
| 1199 | #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ | |
| 1200 | ||
| 1201 | #define DMA_CCR_MSIZE_Pos (10U) | |
| 1202 | #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ | |
| 1203 | #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ | |
| 1204 | #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ | |
| 1205 | #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ | |
| 1206 | ||
| 1207 | #define DMA_CCR_PL_Pos (12U) | |
| 1208 | #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ | |
| 1209 | #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ | |
| 1210 | #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ | |
| 1211 | #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ | |
| 1212 | ||
| 1213 | #define DMA_CCR_MEM2MEM_Pos (14U) | |
| 1214 | #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ | |
| 1215 | #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ | |
| 1216 | ||
| 1217 | /****************** Bit definition for DMA_CNDTR register *******************/ | |
| 1218 | #define DMA_CNDTR_NDT_Pos (0U) | |
| 1219 | #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ | |
| 1220 | #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ | |
| 1221 | ||
| 1222 | /****************** Bit definition for DMA_CPAR register ********************/ | |
| 1223 | #define DMA_CPAR_PA_Pos (0U) | |
| 1224 | #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ | |
| 1225 | #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ | |
| 1226 | ||
| 1227 | /****************** Bit definition for DMA_CMAR register ********************/ | |
| 1228 | #define DMA_CMAR_MA_Pos (0U) | |
| 1229 | #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ | |
| 1230 | #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ | |
| 1231 | ||
| 1232 | /******************************************************************************/ | |
| 1233 | /* */ | |
| 1234 | /* External Interrupt/Event Controller (EXTI) */ | |
| 1235 | /* */ | |
| 1236 | /******************************************************************************/ | |
| 1237 | /******************* Bit definition for EXTI_IMR register *******************/ | |
| 1238 | #define EXTI_IMR_MR0_Pos (0U) | |
| 1239 | #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ | |
| 1240 | #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ | |
| 1241 | #define EXTI_IMR_MR1_Pos (1U) | |
| 1242 | #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ | |
| 1243 | #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ | |
| 1244 | #define EXTI_IMR_MR2_Pos (2U) | |
| 1245 | #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ | |
| 1246 | #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ | |
| 1247 | #define EXTI_IMR_MR3_Pos (3U) | |
| 1248 | #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ | |
| 1249 | #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ | |
| 1250 | #define EXTI_IMR_MR4_Pos (4U) | |
| 1251 | #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ | |
| 1252 | #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ | |
| 1253 | #define EXTI_IMR_MR5_Pos (5U) | |
| 1254 | #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ | |
| 1255 | #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ | |
| 1256 | #define EXTI_IMR_MR6_Pos (6U) | |
| 1257 | #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ | |
| 1258 | #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ | |
| 1259 | #define EXTI_IMR_MR7_Pos (7U) | |
| 1260 | #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ | |
| 1261 | #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ | |
| 1262 | #define EXTI_IMR_MR8_Pos (8U) | |
| 1263 | #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ | |
| 1264 | #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ | |
| 1265 | #define EXTI_IMR_MR9_Pos (9U) | |
| 1266 | #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ | |
| 1267 | #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ | |
| 1268 | #define EXTI_IMR_MR10_Pos (10U) | |
| 1269 | #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ | |
| 1270 | #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ | |
| 1271 | #define EXTI_IMR_MR11_Pos (11U) | |
| 1272 | #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ | |
| 1273 | #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ | |
| 1274 | #define EXTI_IMR_MR12_Pos (12U) | |
| 1275 | #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ | |
| 1276 | #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ | |
| 1277 | #define EXTI_IMR_MR13_Pos (13U) | |
| 1278 | #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ | |
| 1279 | #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ | |
| 1280 | #define EXTI_IMR_MR14_Pos (14U) | |
| 1281 | #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ | |
| 1282 | #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ | |
| 1283 | #define EXTI_IMR_MR15_Pos (15U) | |
| 1284 | #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ | |
| 1285 | #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ | |
| 1286 | #define EXTI_IMR_MR17_Pos (17U) | |
| 1287 | #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ | |
| 1288 | #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ | |
| 1289 | #define EXTI_IMR_MR18_Pos (18U) | |
| 1290 | #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ | |
| 1291 | #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ | |
| 1292 | #define EXTI_IMR_MR19_Pos (19U) | |
| 1293 | #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ | |
| 1294 | #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ | |
| 1295 | #define EXTI_IMR_MR20_Pos (20U) | |
| 1296 | #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ | |
| 1297 | #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ | |
| 1298 | #define EXTI_IMR_MR23_Pos (23U) | |
| 1299 | #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ | |
| 1300 | #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ | |
| 1301 | ||
| 1302 | /* References Defines */ | |
| 1303 | #define EXTI_IMR_IM0 EXTI_IMR_MR0 | |
| 1304 | #define EXTI_IMR_IM1 EXTI_IMR_MR1 | |
| 1305 | #define EXTI_IMR_IM2 EXTI_IMR_MR2 | |
| 1306 | #define EXTI_IMR_IM3 EXTI_IMR_MR3 | |
| 1307 | #define EXTI_IMR_IM4 EXTI_IMR_MR4 | |
| 1308 | #define EXTI_IMR_IM5 EXTI_IMR_MR5 | |
| 1309 | #define EXTI_IMR_IM6 EXTI_IMR_MR6 | |
| 1310 | #define EXTI_IMR_IM7 EXTI_IMR_MR7 | |
| 1311 | #define EXTI_IMR_IM8 EXTI_IMR_MR8 | |
| 1312 | #define EXTI_IMR_IM9 EXTI_IMR_MR9 | |
| 1313 | #define EXTI_IMR_IM10 EXTI_IMR_MR10 | |
| 1314 | #define EXTI_IMR_IM11 EXTI_IMR_MR11 | |
| 1315 | #define EXTI_IMR_IM12 EXTI_IMR_MR12 | |
| 1316 | #define EXTI_IMR_IM13 EXTI_IMR_MR13 | |
| 1317 | #define EXTI_IMR_IM14 EXTI_IMR_MR14 | |
| 1318 | #define EXTI_IMR_IM15 EXTI_IMR_MR15 | |
| 1319 | #define EXTI_IMR_IM17 EXTI_IMR_MR17 | |
| 1320 | #define EXTI_IMR_IM18 EXTI_IMR_MR18 | |
| 1321 | #define EXTI_IMR_IM19 EXTI_IMR_MR19 | |
| 1322 | #define EXTI_IMR_IM20 EXTI_IMR_MR20 | |
| 1323 | #define EXTI_IMR_IM23 EXTI_IMR_MR23 | |
| 1324 | ||
| 1325 | #define EXTI_IMR_IM_Pos (0U) | |
| 1326 | #define EXTI_IMR_IM_Msk (0x9EFFFFU << EXTI_IMR_IM_Pos) /*!< 0x009EFFFF */ | |
| 1327 | #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ | |
| 1328 | ||
| 1329 | ||
| 1330 | /****************** Bit definition for EXTI_EMR register ********************/ | |
| 1331 | #define EXTI_EMR_MR0_Pos (0U) | |
| 1332 | #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ | |
| 1333 | #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ | |
| 1334 | #define EXTI_EMR_MR1_Pos (1U) | |
| 1335 | #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ | |
| 1336 | #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ | |
| 1337 | #define EXTI_EMR_MR2_Pos (2U) | |
| 1338 | #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ | |
| 1339 | #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ | |
| 1340 | #define EXTI_EMR_MR3_Pos (3U) | |
| 1341 | #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ | |
| 1342 | #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ | |
| 1343 | #define EXTI_EMR_MR4_Pos (4U) | |
| 1344 | #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ | |
| 1345 | #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ | |
| 1346 | #define EXTI_EMR_MR5_Pos (5U) | |
| 1347 | #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ | |
| 1348 | #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ | |
| 1349 | #define EXTI_EMR_MR6_Pos (6U) | |
| 1350 | #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ | |
| 1351 | #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ | |
| 1352 | #define EXTI_EMR_MR7_Pos (7U) | |
| 1353 | #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ | |
| 1354 | #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ | |
| 1355 | #define EXTI_EMR_MR8_Pos (8U) | |
| 1356 | #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ | |
| 1357 | #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ | |
| 1358 | #define EXTI_EMR_MR9_Pos (9U) | |
| 1359 | #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ | |
| 1360 | #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ | |
| 1361 | #define EXTI_EMR_MR10_Pos (10U) | |
| 1362 | #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ | |
| 1363 | #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ | |
| 1364 | #define EXTI_EMR_MR11_Pos (11U) | |
| 1365 | #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ | |
| 1366 | #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ | |
| 1367 | #define EXTI_EMR_MR12_Pos (12U) | |
| 1368 | #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ | |
| 1369 | #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ | |
| 1370 | #define EXTI_EMR_MR13_Pos (13U) | |
| 1371 | #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ | |
| 1372 | #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ | |
| 1373 | #define EXTI_EMR_MR14_Pos (14U) | |
| 1374 | #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ | |
| 1375 | #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ | |
| 1376 | #define EXTI_EMR_MR15_Pos (15U) | |
| 1377 | #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ | |
| 1378 | #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ | |
| 1379 | #define EXTI_EMR_MR17_Pos (17U) | |
| 1380 | #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ | |
| 1381 | #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ | |
| 1382 | #define EXTI_EMR_MR18_Pos (18U) | |
| 1383 | #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ | |
| 1384 | #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ | |
| 1385 | #define EXTI_EMR_MR19_Pos (19U) | |
| 1386 | #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ | |
| 1387 | #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ | |
| 1388 | #define EXTI_EMR_MR20_Pos (20U) | |
| 1389 | #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ | |
| 1390 | #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ | |
| 1391 | #define EXTI_EMR_MR23_Pos (23U) | |
| 1392 | #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ | |
| 1393 | #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ | |
| 1394 | ||
| 1395 | /* References Defines */ | |
| 1396 | #define EXTI_EMR_EM0 EXTI_EMR_MR0 | |
| 1397 | #define EXTI_EMR_EM1 EXTI_EMR_MR1 | |
| 1398 | #define EXTI_EMR_EM2 EXTI_EMR_MR2 | |
| 1399 | #define EXTI_EMR_EM3 EXTI_EMR_MR3 | |
| 1400 | #define EXTI_EMR_EM4 EXTI_EMR_MR4 | |
| 1401 | #define EXTI_EMR_EM5 EXTI_EMR_MR5 | |
| 1402 | #define EXTI_EMR_EM6 EXTI_EMR_MR6 | |
| 1403 | #define EXTI_EMR_EM7 EXTI_EMR_MR7 | |
| 1404 | #define EXTI_EMR_EM8 EXTI_EMR_MR8 | |
| 1405 | #define EXTI_EMR_EM9 EXTI_EMR_MR9 | |
| 1406 | #define EXTI_EMR_EM10 EXTI_EMR_MR10 | |
| 1407 | #define EXTI_EMR_EM11 EXTI_EMR_MR11 | |
| 1408 | #define EXTI_EMR_EM12 EXTI_EMR_MR12 | |
| 1409 | #define EXTI_EMR_EM13 EXTI_EMR_MR13 | |
| 1410 | #define EXTI_EMR_EM14 EXTI_EMR_MR14 | |
| 1411 | #define EXTI_EMR_EM15 EXTI_EMR_MR15 | |
| 1412 | #define EXTI_EMR_EM17 EXTI_EMR_MR17 | |
| 1413 | #define EXTI_EMR_EM18 EXTI_EMR_MR18 | |
| 1414 | #define EXTI_EMR_EM19 EXTI_EMR_MR19 | |
| 1415 | #define EXTI_EMR_EM20 EXTI_EMR_MR20 | |
| 1416 | #define EXTI_EMR_EM23 EXTI_EMR_MR23 | |
| 1417 | ||
| 1418 | /******************* Bit definition for EXTI_RTSR register ******************/ | |
| 1419 | #define EXTI_RTSR_TR0_Pos (0U) | |
| 1420 | #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ | |
| 1421 | #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ | |
| 1422 | #define EXTI_RTSR_TR1_Pos (1U) | |
| 1423 | #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ | |
| 1424 | #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ | |
| 1425 | #define EXTI_RTSR_TR2_Pos (2U) | |
| 1426 | #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ | |
| 1427 | #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ | |
| 1428 | #define EXTI_RTSR_TR3_Pos (3U) | |
| 1429 | #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ | |
| 1430 | #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ | |
| 1431 | #define EXTI_RTSR_TR4_Pos (4U) | |
| 1432 | #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ | |
| 1433 | #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ | |
| 1434 | #define EXTI_RTSR_TR5_Pos (5U) | |
| 1435 | #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ | |
| 1436 | #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ | |
| 1437 | #define EXTI_RTSR_TR6_Pos (6U) | |
| 1438 | #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ | |
| 1439 | #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ | |
| 1440 | #define EXTI_RTSR_TR7_Pos (7U) | |
| 1441 | #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ | |
| 1442 | #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ | |
| 1443 | #define EXTI_RTSR_TR8_Pos (8U) | |
| 1444 | #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ | |
| 1445 | #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ | |
| 1446 | #define EXTI_RTSR_TR9_Pos (9U) | |
| 1447 | #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ | |
| 1448 | #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ | |
| 1449 | #define EXTI_RTSR_TR10_Pos (10U) | |
| 1450 | #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ | |
| 1451 | #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ | |
| 1452 | #define EXTI_RTSR_TR11_Pos (11U) | |
| 1453 | #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ | |
| 1454 | #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ | |
| 1455 | #define EXTI_RTSR_TR12_Pos (12U) | |
| 1456 | #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ | |
| 1457 | #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ | |
| 1458 | #define EXTI_RTSR_TR13_Pos (13U) | |
| 1459 | #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ | |
| 1460 | #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ | |
| 1461 | #define EXTI_RTSR_TR14_Pos (14U) | |
| 1462 | #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ | |
| 1463 | #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ | |
| 1464 | #define EXTI_RTSR_TR15_Pos (15U) | |
| 1465 | #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ | |
| 1466 | #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ | |
| 1467 | #define EXTI_RTSR_TR16_Pos (16U) | |
| 1468 | #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ | |
| 1469 | #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ | |
| 1470 | #define EXTI_RTSR_TR17_Pos (17U) | |
| 1471 | #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ | |
| 1472 | #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ | |
| 1473 | #define EXTI_RTSR_TR19_Pos (19U) | |
| 1474 | #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ | |
| 1475 | #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ | |
| 1476 | #define EXTI_RTSR_TR20_Pos (20U) | |
| 1477 | #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ | |
| 1478 | #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ | |
| 1479 | ||
| 1480 | /* References Defines */ | |
| 1481 | #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 | |
| 1482 | #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 | |
| 1483 | #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 | |
| 1484 | #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 | |
| 1485 | #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 | |
| 1486 | #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 | |
| 1487 | #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 | |
| 1488 | #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 | |
| 1489 | #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 | |
| 1490 | #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 | |
| 1491 | #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 | |
| 1492 | #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 | |
| 1493 | #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 | |
| 1494 | #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 | |
| 1495 | #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 | |
| 1496 | #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 | |
| 1497 | #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 | |
| 1498 | #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 | |
| 1499 | #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 | |
| 1500 | #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 | |
| 1501 | ||
| 1502 | /******************* Bit definition for EXTI_FTSR register *******************/ | |
| 1503 | #define EXTI_FTSR_TR0_Pos (0U) | |
| 1504 | #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ | |
| 1505 | #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ | |
| 1506 | #define EXTI_FTSR_TR1_Pos (1U) | |
| 1507 | #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ | |
| 1508 | #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ | |
| 1509 | #define EXTI_FTSR_TR2_Pos (2U) | |
| 1510 | #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ | |
| 1511 | #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ | |
| 1512 | #define EXTI_FTSR_TR3_Pos (3U) | |
| 1513 | #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ | |
| 1514 | #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ | |
| 1515 | #define EXTI_FTSR_TR4_Pos (4U) | |
| 1516 | #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ | |
| 1517 | #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ | |
| 1518 | #define EXTI_FTSR_TR5_Pos (5U) | |
| 1519 | #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ | |
| 1520 | #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ | |
| 1521 | #define EXTI_FTSR_TR6_Pos (6U) | |
| 1522 | #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ | |
| 1523 | #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ | |
| 1524 | #define EXTI_FTSR_TR7_Pos (7U) | |
| 1525 | #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ | |
| 1526 | #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ | |
| 1527 | #define EXTI_FTSR_TR8_Pos (8U) | |
| 1528 | #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ | |
| 1529 | #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ | |
| 1530 | #define EXTI_FTSR_TR9_Pos (9U) | |
| 1531 | #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ | |
| 1532 | #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ | |
| 1533 | #define EXTI_FTSR_TR10_Pos (10U) | |
| 1534 | #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ | |
| 1535 | #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ | |
| 1536 | #define EXTI_FTSR_TR11_Pos (11U) | |
| 1537 | #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ | |
| 1538 | #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ | |
| 1539 | #define EXTI_FTSR_TR12_Pos (12U) | |
| 1540 | #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ | |
| 1541 | #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ | |
| 1542 | #define EXTI_FTSR_TR13_Pos (13U) | |
| 1543 | #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ | |
| 1544 | #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ | |
| 1545 | #define EXTI_FTSR_TR14_Pos (14U) | |
| 1546 | #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ | |
| 1547 | #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ | |
| 1548 | #define EXTI_FTSR_TR15_Pos (15U) | |
| 1549 | #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ | |
| 1550 | #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ | |
| 1551 | #define EXTI_FTSR_TR16_Pos (16U) | |
| 1552 | #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ | |
| 1553 | #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ | |
| 1554 | #define EXTI_FTSR_TR17_Pos (17U) | |
| 1555 | #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ | |
| 1556 | #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ | |
| 1557 | #define EXTI_FTSR_TR19_Pos (19U) | |
| 1558 | #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ | |
| 1559 | #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ | |
| 1560 | #define EXTI_FTSR_TR20_Pos (20U) | |
| 1561 | #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ | |
| 1562 | #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ | |
| 1563 | ||
| 1564 | /* References Defines */ | |
| 1565 | #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 | |
| 1566 | #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 | |
| 1567 | #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 | |
| 1568 | #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 | |
| 1569 | #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 | |
| 1570 | #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 | |
| 1571 | #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 | |
| 1572 | #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 | |
| 1573 | #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 | |
| 1574 | #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 | |
| 1575 | #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 | |
| 1576 | #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 | |
| 1577 | #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 | |
| 1578 | #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 | |
| 1579 | #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 | |
| 1580 | #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 | |
| 1581 | #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 | |
| 1582 | #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 | |
| 1583 | #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 | |
| 1584 | #define EXTI_FTSR_FT20 EXTI_FTSR_TR20 | |
| 1585 | ||
| 1586 | /******************* Bit definition for EXTI_SWIER register *******************/ | |
| 1587 | #define EXTI_SWIER_SWIER0_Pos (0U) | |
| 1588 | #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ | |
| 1589 | #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ | |
| 1590 | #define EXTI_SWIER_SWIER1_Pos (1U) | |
| 1591 | #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ | |
| 1592 | #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ | |
| 1593 | #define EXTI_SWIER_SWIER2_Pos (2U) | |
| 1594 | #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ | |
| 1595 | #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ | |
| 1596 | #define EXTI_SWIER_SWIER3_Pos (3U) | |
| 1597 | #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ | |
| 1598 | #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ | |
| 1599 | #define EXTI_SWIER_SWIER4_Pos (4U) | |
| 1600 | #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ | |
| 1601 | #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ | |
| 1602 | #define EXTI_SWIER_SWIER5_Pos (5U) | |
| 1603 | #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ | |
| 1604 | #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ | |
| 1605 | #define EXTI_SWIER_SWIER6_Pos (6U) | |
| 1606 | #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ | |
| 1607 | #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ | |
| 1608 | #define EXTI_SWIER_SWIER7_Pos (7U) | |
| 1609 | #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ | |
| 1610 | #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ | |
| 1611 | #define EXTI_SWIER_SWIER8_Pos (8U) | |
| 1612 | #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ | |
| 1613 | #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ | |
| 1614 | #define EXTI_SWIER_SWIER9_Pos (9U) | |
| 1615 | #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ | |
| 1616 | #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ | |
| 1617 | #define EXTI_SWIER_SWIER10_Pos (10U) | |
| 1618 | #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ | |
| 1619 | #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ | |
| 1620 | #define EXTI_SWIER_SWIER11_Pos (11U) | |
| 1621 | #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ | |
| 1622 | #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ | |
| 1623 | #define EXTI_SWIER_SWIER12_Pos (12U) | |
| 1624 | #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ | |
| 1625 | #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ | |
| 1626 | #define EXTI_SWIER_SWIER13_Pos (13U) | |
| 1627 | #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ | |
| 1628 | #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ | |
| 1629 | #define EXTI_SWIER_SWIER14_Pos (14U) | |
| 1630 | #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ | |
| 1631 | #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ | |
| 1632 | #define EXTI_SWIER_SWIER15_Pos (15U) | |
| 1633 | #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ | |
| 1634 | #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ | |
| 1635 | #define EXTI_SWIER_SWIER16_Pos (16U) | |
| 1636 | #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ | |
| 1637 | #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ | |
| 1638 | #define EXTI_SWIER_SWIER17_Pos (17U) | |
| 1639 | #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ | |
| 1640 | #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ | |
| 1641 | #define EXTI_SWIER_SWIER19_Pos (19U) | |
| 1642 | #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ | |
| 1643 | #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ | |
| 1644 | #define EXTI_SWIER_SWIER20_Pos (20U) | |
| 1645 | #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ | |
| 1646 | #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ | |
| 1647 | ||
| 1648 | /* References Defines */ | |
| 1649 | #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 | |
| 1650 | #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 | |
| 1651 | #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 | |
| 1652 | #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 | |
| 1653 | #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 | |
| 1654 | #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 | |
| 1655 | #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 | |
| 1656 | #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 | |
| 1657 | #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 | |
| 1658 | #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 | |
| 1659 | #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 | |
| 1660 | #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 | |
| 1661 | #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 | |
| 1662 | #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 | |
| 1663 | #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 | |
| 1664 | #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 | |
| 1665 | #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 | |
| 1666 | #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 | |
| 1667 | #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 | |
| 1668 | #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 | |
| 1669 | ||
| 1670 | /****************** Bit definition for EXTI_PR register *********************/ | |
| 1671 | #define EXTI_PR_PR0_Pos (0U) | |
| 1672 | #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ | |
| 1673 | #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */ | |
| 1674 | #define EXTI_PR_PR1_Pos (1U) | |
| 1675 | #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ | |
| 1676 | #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */ | |
| 1677 | #define EXTI_PR_PR2_Pos (2U) | |
| 1678 | #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ | |
| 1679 | #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */ | |
| 1680 | #define EXTI_PR_PR3_Pos (3U) | |
| 1681 | #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ | |
| 1682 | #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */ | |
| 1683 | #define EXTI_PR_PR4_Pos (4U) | |
| 1684 | #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ | |
| 1685 | #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */ | |
| 1686 | #define EXTI_PR_PR5_Pos (5U) | |
| 1687 | #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ | |
| 1688 | #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */ | |
| 1689 | #define EXTI_PR_PR6_Pos (6U) | |
| 1690 | #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ | |
| 1691 | #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */ | |
| 1692 | #define EXTI_PR_PR7_Pos (7U) | |
| 1693 | #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ | |
| 1694 | #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */ | |
| 1695 | #define EXTI_PR_PR8_Pos (8U) | |
| 1696 | #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ | |
| 1697 | #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */ | |
| 1698 | #define EXTI_PR_PR9_Pos (9U) | |
| 1699 | #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ | |
| 1700 | #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */ | |
| 1701 | #define EXTI_PR_PR10_Pos (10U) | |
| 1702 | #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ | |
| 1703 | #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */ | |
| 1704 | #define EXTI_PR_PR11_Pos (11U) | |
| 1705 | #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ | |
| 1706 | #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */ | |
| 1707 | #define EXTI_PR_PR12_Pos (12U) | |
| 1708 | #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ | |
| 1709 | #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */ | |
| 1710 | #define EXTI_PR_PR13_Pos (13U) | |
| 1711 | #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ | |
| 1712 | #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */ | |
| 1713 | #define EXTI_PR_PR14_Pos (14U) | |
| 1714 | #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ | |
| 1715 | #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */ | |
| 1716 | #define EXTI_PR_PR15_Pos (15U) | |
| 1717 | #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ | |
| 1718 | #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */ | |
| 1719 | #define EXTI_PR_PR16_Pos (16U) | |
| 1720 | #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ | |
| 1721 | #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */ | |
| 1722 | #define EXTI_PR_PR17_Pos (17U) | |
| 1723 | #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ | |
| 1724 | #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */ | |
| 1725 | #define EXTI_PR_PR19_Pos (19U) | |
| 1726 | #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ | |
| 1727 | #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */ | |
| 1728 | #define EXTI_PR_PR20_Pos (20U) | |
| 1729 | #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ | |
| 1730 | #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit 20 */ | |
| 1731 | ||
| 1732 | /* References Defines */ | |
| 1733 | #define EXTI_PR_PIF0 EXTI_PR_PR0 | |
| 1734 | #define EXTI_PR_PIF1 EXTI_PR_PR1 | |
| 1735 | #define EXTI_PR_PIF2 EXTI_PR_PR2 | |
| 1736 | #define EXTI_PR_PIF3 EXTI_PR_PR3 | |
| 1737 | #define EXTI_PR_PIF4 EXTI_PR_PR4 | |
| 1738 | #define EXTI_PR_PIF5 EXTI_PR_PR5 | |
| 1739 | #define EXTI_PR_PIF6 EXTI_PR_PR6 | |
| 1740 | #define EXTI_PR_PIF7 EXTI_PR_PR7 | |
| 1741 | #define EXTI_PR_PIF8 EXTI_PR_PR8 | |
| 1742 | #define EXTI_PR_PIF9 EXTI_PR_PR9 | |
| 1743 | #define EXTI_PR_PIF10 EXTI_PR_PR10 | |
| 1744 | #define EXTI_PR_PIF11 EXTI_PR_PR11 | |
| 1745 | #define EXTI_PR_PIF12 EXTI_PR_PR12 | |
| 1746 | #define EXTI_PR_PIF13 EXTI_PR_PR13 | |
| 1747 | #define EXTI_PR_PIF14 EXTI_PR_PR14 | |
| 1748 | #define EXTI_PR_PIF15 EXTI_PR_PR15 | |
| 1749 | #define EXTI_PR_PIF16 EXTI_PR_PR16 | |
| 1750 | #define EXTI_PR_PIF17 EXTI_PR_PR17 | |
| 1751 | #define EXTI_PR_PIF19 EXTI_PR_PR19 | |
| 1752 | #define EXTI_PR_PIF20 EXTI_PR_PR20 | |
| 1753 | ||
| 1754 | /******************************************************************************/ | |
| 1755 | /* */ | |
| 1756 | /* FLASH and Option Bytes Registers */ | |
| 1757 | /* */ | |
| 1758 | /******************************************************************************/ | |
| 1759 | ||
| 1760 | /******************* Bit definition for FLASH_ACR register ******************/ | |
| 1761 | #define FLASH_ACR_LATENCY_Pos (0U) | |
| 1762 | #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ | |
| 1763 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ | |
| 1764 | ||
| 1765 | #define FLASH_ACR_PRFTBE_Pos (4U) | |
| 1766 | #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ | |
| 1767 | #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ | |
| 1768 | #define FLASH_ACR_PRFTBS_Pos (5U) | |
| 1769 | #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ | |
| 1770 | #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ | |
| 1771 | ||
| 1772 | /****************** Bit definition for FLASH_KEYR register ******************/ | |
| 1773 | #define FLASH_KEYR_FKEYR_Pos (0U) | |
| 1774 | #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ | |
| 1775 | #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ | |
| 1776 | ||
| 1777 | /***************** Bit definition for FLASH_OPTKEYR register ****************/ | |
| 1778 | #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) | |
| 1779 | #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ | |
| 1780 | #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ | |
| 1781 | ||
| 1782 | /****************** FLASH Keys **********************************************/ | |
| 1783 | #define FLASH_KEY1_Pos (0U) | |
| 1784 | #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ | |
| 1785 | #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */ | |
| 1786 | #define FLASH_KEY2_Pos (0U) | |
| 1787 | #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ | |
| 1788 | #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1 | |
| 1789 | to unlock the write access to the FPEC. */ | |
| 1790 | ||
| 1791 | #define FLASH_OPTKEY1_Pos (0U) | |
| 1792 | #define FLASH_OPTKEY1_Msk (0x45670123U << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */ | |
| 1793 | #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */ | |
| 1794 | #define FLASH_OPTKEY2_Pos (0U) | |
| 1795 | #define FLASH_OPTKEY2_Msk (0xCDEF89ABU << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */ | |
| 1796 | #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to | |
| 1797 | unlock the write access to the option byte block */ | |
| 1798 | ||
| 1799 | /****************** Bit definition for FLASH_SR register *******************/ | |
| 1800 | #define FLASH_SR_BSY_Pos (0U) | |
| 1801 | #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ | |
| 1802 | #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ | |
| 1803 | #define FLASH_SR_PGERR_Pos (2U) | |
| 1804 | #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ | |
| 1805 | #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ | |
| 1806 | #define FLASH_SR_WRPRTERR_Pos (4U) | |
| 1807 | #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ | |
| 1808 | #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ | |
| 1809 | #define FLASH_SR_EOP_Pos (5U) | |
| 1810 | #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ | |
| 1811 | #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ | |
| 1812 | #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */ | |
| 1813 | ||
| 1814 | /******************* Bit definition for FLASH_CR register *******************/ | |
| 1815 | #define FLASH_CR_PG_Pos (0U) | |
| 1816 | #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ | |
| 1817 | #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ | |
| 1818 | #define FLASH_CR_PER_Pos (1U) | |
| 1819 | #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */ | |
| 1820 | #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ | |
| 1821 | #define FLASH_CR_MER_Pos (2U) | |
| 1822 | #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */ | |
| 1823 | #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ | |
| 1824 | #define FLASH_CR_OPTPG_Pos (4U) | |
| 1825 | #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ | |
| 1826 | #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ | |
| 1827 | #define FLASH_CR_OPTER_Pos (5U) | |
| 1828 | #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ | |
| 1829 | #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ | |
| 1830 | #define FLASH_CR_STRT_Pos (6U) | |
| 1831 | #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ | |
| 1832 | #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ | |
| 1833 | #define FLASH_CR_LOCK_Pos (7U) | |
| 1834 | #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ | |
| 1835 | #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ | |
| 1836 | #define FLASH_CR_OPTWRE_Pos (9U) | |
| 1837 | #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ | |
| 1838 | #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ | |
| 1839 | #define FLASH_CR_ERRIE_Pos (10U) | |
| 1840 | #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ | |
| 1841 | #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ | |
| 1842 | #define FLASH_CR_EOPIE_Pos (12U) | |
| 1843 | #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ | |
| 1844 | #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ | |
| 1845 | #define FLASH_CR_OBL_LAUNCH_Pos (13U) | |
| 1846 | #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */ | |
| 1847 | #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */ | |
| 1848 | ||
| 1849 | /******************* Bit definition for FLASH_AR register *******************/ | |
| 1850 | #define FLASH_AR_FAR_Pos (0U) | |
| 1851 | #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ | |
| 1852 | #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ | |
| 1853 | ||
| 1854 | /****************** Bit definition for FLASH_OBR register *******************/ | |
| 1855 | #define FLASH_OBR_OPTERR_Pos (0U) | |
| 1856 | #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ | |
| 1857 | #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ | |
| 1858 | #define FLASH_OBR_RDPRT1_Pos (1U) | |
| 1859 | #define FLASH_OBR_RDPRT1_Msk (0x1U << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */ | |
| 1860 | #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */ | |
| 1861 | #define FLASH_OBR_RDPRT2_Pos (2U) | |
| 1862 | #define FLASH_OBR_RDPRT2_Msk (0x1U << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */ | |
| 1863 | #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */ | |
| 1864 | ||
| 1865 | #define FLASH_OBR_USER_Pos (8U) | |
| 1866 | #define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */ | |
| 1867 | #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ | |
| 1868 | #define FLASH_OBR_IWDG_SW_Pos (8U) | |
| 1869 | #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */ | |
| 1870 | #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ | |
| 1871 | #define FLASH_OBR_nRST_STOP_Pos (9U) | |
| 1872 | #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */ | |
| 1873 | #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ | |
| 1874 | #define FLASH_OBR_nRST_STDBY_Pos (10U) | |
| 1875 | #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */ | |
| 1876 | #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ | |
| 1877 | #define FLASH_OBR_nBOOT1_Pos (12U) | |
| 1878 | #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */ | |
| 1879 | #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */ | |
| 1880 | #define FLASH_OBR_VDDA_MONITOR_Pos (13U) | |
| 1881 | #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */ | |
| 1882 | #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */ | |
| 1883 | #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U) | |
| 1884 | #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */ | |
| 1885 | #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */ | |
| 1886 | #define FLASH_OBR_DATA0_Pos (16U) | |
| 1887 | #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */ | |
| 1888 | #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ | |
| 1889 | #define FLASH_OBR_DATA1_Pos (24U) | |
| 1890 | #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */ | |
| 1891 | #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ | |
| 1892 | ||
| 1893 | /* Old BOOT1 bit definition, maintained for legacy purpose */ | |
| 1894 | #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 | |
| 1895 | ||
| 1896 | /* Old OBR_VDDA bit definition, maintained for legacy purpose */ | |
| 1897 | #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR | |
| 1898 | ||
| 1899 | /****************** Bit definition for FLASH_WRPR register ******************/ | |
| 1900 | #define FLASH_WRPR_WRP_Pos (0U) | |
| 1901 | #define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ | |
| 1902 | #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ | |
| 1903 | ||
| 1904 | /*----------------------------------------------------------------------------*/ | |
| 1905 | ||
| 1906 | /****************** Bit definition for OB_RDP register **********************/ | |
| 1907 | #define OB_RDP_RDP_Pos (0U) | |
| 1908 | #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */ | |
| 1909 | #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */ | |
| 1910 | #define OB_RDP_nRDP_Pos (8U) | |
| 1911 | #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */ | |
| 1912 | #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */ | |
| 1913 | ||
| 1914 | /****************** Bit definition for OB_USER register *********************/ | |
| 1915 | #define OB_USER_USER_Pos (16U) | |
| 1916 | #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */ | |
| 1917 | #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */ | |
| 1918 | #define OB_USER_nUSER_Pos (24U) | |
| 1919 | #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */ | |
| 1920 | #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */ | |
| 1921 | ||
| 1922 | /****************** Bit definition for OB_WRP0 register *********************/ | |
| 1923 | #define OB_WRP0_WRP0_Pos (0U) | |
| 1924 | #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */ | |
| 1925 | #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ | |
| 1926 | #define OB_WRP0_nWRP0_Pos (8U) | |
| 1927 | #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ | |
| 1928 | #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ | |
| 1929 | ||
| 1930 | /****************** Bit definition for OB_WRP1 register *********************/ | |
| 1931 | #define OB_WRP1_WRP1_Pos (16U) | |
| 1932 | #define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ | |
| 1933 | #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ | |
| 1934 | #define OB_WRP1_nWRP1_Pos (24U) | |
| 1935 | #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ | |
| 1936 | #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ | |
| 1937 | ||
| 1938 | /****************** Bit definition for OB_WRP2 register *********************/ | |
| 1939 | #define OB_WRP2_WRP2_Pos (0U) | |
| 1940 | #define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */ | |
| 1941 | #define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ | |
| 1942 | #define OB_WRP2_nWRP2_Pos (8U) | |
| 1943 | #define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ | |
| 1944 | #define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ | |
| 1945 | ||
| 1946 | /****************** Bit definition for OB_WRP3 register *********************/ | |
| 1947 | #define OB_WRP3_WRP3_Pos (16U) | |
| 1948 | #define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ | |
| 1949 | #define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ | |
| 1950 | #define OB_WRP3_nWRP3_Pos (24U) | |
| 1951 | #define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ | |
| 1952 | #define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ | |
| 1953 | ||
| 1954 | /******************************************************************************/ | |
| 1955 | /* */ | |
| 1956 | /* General Purpose IOs (GPIO) */ | |
| 1957 | /* */ | |
| 1958 | /******************************************************************************/ | |
| 1959 | /******************* Bit definition for GPIO_MODER register *****************/ | |
| 1960 | #define GPIO_MODER_MODER0_Pos (0U) | |
| 1961 | #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ | |
| 1962 | #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk | |
| 1963 | #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ | |
| 1964 | #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ | |
| 1965 | #define GPIO_MODER_MODER1_Pos (2U) | |
| 1966 | #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ | |
| 1967 | #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk | |
| 1968 | #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ | |
| 1969 | #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ | |
| 1970 | #define GPIO_MODER_MODER2_Pos (4U) | |
| 1971 | #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ | |
| 1972 | #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk | |
| 1973 | #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ | |
| 1974 | #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ | |
| 1975 | #define GPIO_MODER_MODER3_Pos (6U) | |
| 1976 | #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ | |
| 1977 | #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk | |
| 1978 | #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ | |
| 1979 | #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ | |
| 1980 | #define GPIO_MODER_MODER4_Pos (8U) | |
| 1981 | #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ | |
| 1982 | #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk | |
| 1983 | #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ | |
| 1984 | #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ | |
| 1985 | #define GPIO_MODER_MODER5_Pos (10U) | |
| 1986 | #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ | |
| 1987 | #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk | |
| 1988 | #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ | |
| 1989 | #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ | |
| 1990 | #define GPIO_MODER_MODER6_Pos (12U) | |
| 1991 | #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ | |
| 1992 | #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk | |
| 1993 | #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ | |
| 1994 | #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ | |
| 1995 | #define GPIO_MODER_MODER7_Pos (14U) | |
| 1996 | #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ | |
| 1997 | #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk | |
| 1998 | #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ | |
| 1999 | #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ | |
| 2000 | #define GPIO_MODER_MODER8_Pos (16U) | |
| 2001 | #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ | |
| 2002 | #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk | |
| 2003 | #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ | |
| 2004 | #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ | |
| 2005 | #define GPIO_MODER_MODER9_Pos (18U) | |
| 2006 | #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ | |
| 2007 | #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk | |
| 2008 | #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ | |
| 2009 | #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ | |
| 2010 | #define GPIO_MODER_MODER10_Pos (20U) | |
| 2011 | #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ | |
| 2012 | #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk | |
| 2013 | #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ | |
| 2014 | #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ | |
| 2015 | #define GPIO_MODER_MODER11_Pos (22U) | |
| 2016 | #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ | |
| 2017 | #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk | |
| 2018 | #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ | |
| 2019 | #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ | |
| 2020 | #define GPIO_MODER_MODER12_Pos (24U) | |
| 2021 | #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ | |
| 2022 | #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk | |
| 2023 | #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ | |
| 2024 | #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ | |
| 2025 | #define GPIO_MODER_MODER13_Pos (26U) | |
| 2026 | #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ | |
| 2027 | #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk | |
| 2028 | #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ | |
| 2029 | #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ | |
| 2030 | #define GPIO_MODER_MODER14_Pos (28U) | |
| 2031 | #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ | |
| 2032 | #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk | |
| 2033 | #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ | |
| 2034 | #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ | |
| 2035 | #define GPIO_MODER_MODER15_Pos (30U) | |
| 2036 | #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ | |
| 2037 | #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk | |
| 2038 | #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ | |
| 2039 | #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ | |
| 2040 | ||
| 2041 | /****************** Bit definition for GPIO_OTYPER register *****************/ | |
| 2042 | #define GPIO_OTYPER_OT_0 (0x00000001U) | |
| 2043 | #define GPIO_OTYPER_OT_1 (0x00000002U) | |
| 2044 | #define GPIO_OTYPER_OT_2 (0x00000004U) | |
| 2045 | #define GPIO_OTYPER_OT_3 (0x00000008U) | |
| 2046 | #define GPIO_OTYPER_OT_4 (0x00000010U) | |
| 2047 | #define GPIO_OTYPER_OT_5 (0x00000020U) | |
| 2048 | #define GPIO_OTYPER_OT_6 (0x00000040U) | |
| 2049 | #define GPIO_OTYPER_OT_7 (0x00000080U) | |
| 2050 | #define GPIO_OTYPER_OT_8 (0x00000100U) | |
| 2051 | #define GPIO_OTYPER_OT_9 (0x00000200U) | |
| 2052 | #define GPIO_OTYPER_OT_10 (0x00000400U) | |
| 2053 | #define GPIO_OTYPER_OT_11 (0x00000800U) | |
| 2054 | #define GPIO_OTYPER_OT_12 (0x00001000U) | |
| 2055 | #define GPIO_OTYPER_OT_13 (0x00002000U) | |
| 2056 | #define GPIO_OTYPER_OT_14 (0x00004000U) | |
| 2057 | #define GPIO_OTYPER_OT_15 (0x00008000U) | |
| 2058 | ||
| 2059 | /**************** Bit definition for GPIO_OSPEEDR register ******************/ | |
| 2060 | #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U) | |
| 2061 | #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */ | |
| 2062 | #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk | |
| 2063 | #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */ | |
| 2064 | #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */ | |
| 2065 | #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U) | |
| 2066 | #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */ | |
| 2067 | #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk | |
| 2068 | #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */ | |
| 2069 | #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */ | |
| 2070 | #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U) | |
| 2071 | #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */ | |
| 2072 | #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk | |
| 2073 | #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */ | |
| 2074 | #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */ | |
| 2075 | #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U) | |
| 2076 | #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */ | |
| 2077 | #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk | |
| 2078 | #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */ | |
| 2079 | #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */ | |
| 2080 | #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U) | |
| 2081 | #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */ | |
| 2082 | #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk | |
| 2083 | #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */ | |
| 2084 | #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */ | |
| 2085 | #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U) | |
| 2086 | #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */ | |
| 2087 | #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk | |
| 2088 | #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */ | |
| 2089 | #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */ | |
| 2090 | #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U) | |
| 2091 | #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */ | |
| 2092 | #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk | |
| 2093 | #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */ | |
| 2094 | #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */ | |
| 2095 | #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U) | |
| 2096 | #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */ | |
| 2097 | #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk | |
| 2098 | #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */ | |
| 2099 | #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */ | |
| 2100 | #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U) | |
| 2101 | #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */ | |
| 2102 | #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk | |
| 2103 | #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */ | |
| 2104 | #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */ | |
| 2105 | #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U) | |
| 2106 | #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */ | |
| 2107 | #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk | |
| 2108 | #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */ | |
| 2109 | #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */ | |
| 2110 | #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U) | |
| 2111 | #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */ | |
| 2112 | #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk | |
| 2113 | #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */ | |
| 2114 | #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */ | |
| 2115 | #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U) | |
| 2116 | #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */ | |
| 2117 | #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk | |
| 2118 | #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */ | |
| 2119 | #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */ | |
| 2120 | #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U) | |
| 2121 | #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */ | |
| 2122 | #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk | |
| 2123 | #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */ | |
| 2124 | #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */ | |
| 2125 | #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U) | |
| 2126 | #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */ | |
| 2127 | #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk | |
| 2128 | #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */ | |
| 2129 | #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */ | |
| 2130 | #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U) | |
| 2131 | #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */ | |
| 2132 | #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk | |
| 2133 | #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */ | |
| 2134 | #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */ | |
| 2135 | #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U) | |
| 2136 | #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */ | |
| 2137 | #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk | |
| 2138 | #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */ | |
| 2139 | #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */ | |
| 2140 | ||
| 2141 | /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */ | |
| 2142 | #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 | |
| 2143 | #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0 | |
| 2144 | #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1 | |
| 2145 | #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1 | |
| 2146 | #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0 | |
| 2147 | #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1 | |
| 2148 | #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2 | |
| 2149 | #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0 | |
| 2150 | #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1 | |
| 2151 | #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3 | |
| 2152 | #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0 | |
| 2153 | #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1 | |
| 2154 | #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4 | |
| 2155 | #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0 | |
| 2156 | #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1 | |
| 2157 | #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5 | |
| 2158 | #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0 | |
| 2159 | #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1 | |
| 2160 | #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6 | |
| 2161 | #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0 | |
| 2162 | #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1 | |
| 2163 | #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7 | |
| 2164 | #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0 | |
| 2165 | #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1 | |
| 2166 | #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8 | |
| 2167 | #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0 | |
| 2168 | #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1 | |
| 2169 | #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9 | |
| 2170 | #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0 | |
| 2171 | #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1 | |
| 2172 | #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10 | |
| 2173 | #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0 | |
| 2174 | #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1 | |
| 2175 | #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11 | |
| 2176 | #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0 | |
| 2177 | #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1 | |
| 2178 | #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12 | |
| 2179 | #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0 | |
| 2180 | #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1 | |
| 2181 | #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13 | |
| 2182 | #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0 | |
| 2183 | #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1 | |
| 2184 | #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14 | |
| 2185 | #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0 | |
| 2186 | #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1 | |
| 2187 | #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15 | |
| 2188 | #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0 | |
| 2189 | #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 | |
| 2190 | ||
| 2191 | /******************* Bit definition for GPIO_PUPDR register ******************/ | |
| 2192 | #define GPIO_PUPDR_PUPDR0_Pos (0U) | |
| 2193 | #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ | |
| 2194 | #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk | |
| 2195 | #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ | |
| 2196 | #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ | |
| 2197 | #define GPIO_PUPDR_PUPDR1_Pos (2U) | |
| 2198 | #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ | |
| 2199 | #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk | |
| 2200 | #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ | |
| 2201 | #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ | |
| 2202 | #define GPIO_PUPDR_PUPDR2_Pos (4U) | |
| 2203 | #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ | |
| 2204 | #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk | |
| 2205 | #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ | |
| 2206 | #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ | |
| 2207 | #define GPIO_PUPDR_PUPDR3_Pos (6U) | |
| 2208 | #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ | |
| 2209 | #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk | |
| 2210 | #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ | |
| 2211 | #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ | |
| 2212 | #define GPIO_PUPDR_PUPDR4_Pos (8U) | |
| 2213 | #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ | |
| 2214 | #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk | |
| 2215 | #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ | |
| 2216 | #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ | |
| 2217 | #define GPIO_PUPDR_PUPDR5_Pos (10U) | |
| 2218 | #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ | |
| 2219 | #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk | |
| 2220 | #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ | |
| 2221 | #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ | |
| 2222 | #define GPIO_PUPDR_PUPDR6_Pos (12U) | |
| 2223 | #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ | |
| 2224 | #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk | |
| 2225 | #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ | |
| 2226 | #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ | |
| 2227 | #define GPIO_PUPDR_PUPDR7_Pos (14U) | |
| 2228 | #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ | |
| 2229 | #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk | |
| 2230 | #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ | |
| 2231 | #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ | |
| 2232 | #define GPIO_PUPDR_PUPDR8_Pos (16U) | |
| 2233 | #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ | |
| 2234 | #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk | |
| 2235 | #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ | |
| 2236 | #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ | |
| 2237 | #define GPIO_PUPDR_PUPDR9_Pos (18U) | |
| 2238 | #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ | |
| 2239 | #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk | |
| 2240 | #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ | |
| 2241 | #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ | |
| 2242 | #define GPIO_PUPDR_PUPDR10_Pos (20U) | |
| 2243 | #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ | |
| 2244 | #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk | |
| 2245 | #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ | |
| 2246 | #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ | |
| 2247 | #define GPIO_PUPDR_PUPDR11_Pos (22U) | |
| 2248 | #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ | |
| 2249 | #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk | |
| 2250 | #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ | |
| 2251 | #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ | |
| 2252 | #define GPIO_PUPDR_PUPDR12_Pos (24U) | |
| 2253 | #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ | |
| 2254 | #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk | |
| 2255 | #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ | |
| 2256 | #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ | |
| 2257 | #define GPIO_PUPDR_PUPDR13_Pos (26U) | |
| 2258 | #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ | |
| 2259 | #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk | |
| 2260 | #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ | |
| 2261 | #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ | |
| 2262 | #define GPIO_PUPDR_PUPDR14_Pos (28U) | |
| 2263 | #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ | |
| 2264 | #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk | |
| 2265 | #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ | |
| 2266 | #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ | |
| 2267 | #define GPIO_PUPDR_PUPDR15_Pos (30U) | |
| 2268 | #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ | |
| 2269 | #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk | |
| 2270 | #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ | |
| 2271 | #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ | |
| 2272 | ||
| 2273 | /******************* Bit definition for GPIO_IDR register *******************/ | |
| 2274 | #define GPIO_IDR_0 (0x00000001U) | |
| 2275 | #define GPIO_IDR_1 (0x00000002U) | |
| 2276 | #define GPIO_IDR_2 (0x00000004U) | |
| 2277 | #define GPIO_IDR_3 (0x00000008U) | |
| 2278 | #define GPIO_IDR_4 (0x00000010U) | |
| 2279 | #define GPIO_IDR_5 (0x00000020U) | |
| 2280 | #define GPIO_IDR_6 (0x00000040U) | |
| 2281 | #define GPIO_IDR_7 (0x00000080U) | |
| 2282 | #define GPIO_IDR_8 (0x00000100U) | |
| 2283 | #define GPIO_IDR_9 (0x00000200U) | |
| 2284 | #define GPIO_IDR_10 (0x00000400U) | |
| 2285 | #define GPIO_IDR_11 (0x00000800U) | |
| 2286 | #define GPIO_IDR_12 (0x00001000U) | |
| 2287 | #define GPIO_IDR_13 (0x00002000U) | |
| 2288 | #define GPIO_IDR_14 (0x00004000U) | |
| 2289 | #define GPIO_IDR_15 (0x00008000U) | |
| 2290 | ||
| 2291 | /****************** Bit definition for GPIO_ODR register ********************/ | |
| 2292 | #define GPIO_ODR_0 (0x00000001U) | |
| 2293 | #define GPIO_ODR_1 (0x00000002U) | |
| 2294 | #define GPIO_ODR_2 (0x00000004U) | |
| 2295 | #define GPIO_ODR_3 (0x00000008U) | |
| 2296 | #define GPIO_ODR_4 (0x00000010U) | |
| 2297 | #define GPIO_ODR_5 (0x00000020U) | |
| 2298 | #define GPIO_ODR_6 (0x00000040U) | |
| 2299 | #define GPIO_ODR_7 (0x00000080U) | |
| 2300 | #define GPIO_ODR_8 (0x00000100U) | |
| 2301 | #define GPIO_ODR_9 (0x00000200U) | |
| 2302 | #define GPIO_ODR_10 (0x00000400U) | |
| 2303 | #define GPIO_ODR_11 (0x00000800U) | |
| 2304 | #define GPIO_ODR_12 (0x00001000U) | |
| 2305 | #define GPIO_ODR_13 (0x00002000U) | |
| 2306 | #define GPIO_ODR_14 (0x00004000U) | |
| 2307 | #define GPIO_ODR_15 (0x00008000U) | |
| 2308 | ||
| 2309 | /****************** Bit definition for GPIO_BSRR register ********************/ | |
| 2310 | #define GPIO_BSRR_BS_0 (0x00000001U) | |
| 2311 | #define GPIO_BSRR_BS_1 (0x00000002U) | |
| 2312 | #define GPIO_BSRR_BS_2 (0x00000004U) | |
| 2313 | #define GPIO_BSRR_BS_3 (0x00000008U) | |
| 2314 | #define GPIO_BSRR_BS_4 (0x00000010U) | |
| 2315 | #define GPIO_BSRR_BS_5 (0x00000020U) | |
| 2316 | #define GPIO_BSRR_BS_6 (0x00000040U) | |
| 2317 | #define GPIO_BSRR_BS_7 (0x00000080U) | |
| 2318 | #define GPIO_BSRR_BS_8 (0x00000100U) | |
| 2319 | #define GPIO_BSRR_BS_9 (0x00000200U) | |
| 2320 | #define GPIO_BSRR_BS_10 (0x00000400U) | |
| 2321 | #define GPIO_BSRR_BS_11 (0x00000800U) | |
| 2322 | #define GPIO_BSRR_BS_12 (0x00001000U) | |
| 2323 | #define GPIO_BSRR_BS_13 (0x00002000U) | |
| 2324 | #define GPIO_BSRR_BS_14 (0x00004000U) | |
| 2325 | #define GPIO_BSRR_BS_15 (0x00008000U) | |
| 2326 | #define GPIO_BSRR_BR_0 (0x00010000U) | |
| 2327 | #define GPIO_BSRR_BR_1 (0x00020000U) | |
| 2328 | #define GPIO_BSRR_BR_2 (0x00040000U) | |
| 2329 | #define GPIO_BSRR_BR_3 (0x00080000U) | |
| 2330 | #define GPIO_BSRR_BR_4 (0x00100000U) | |
| 2331 | #define GPIO_BSRR_BR_5 (0x00200000U) | |
| 2332 | #define GPIO_BSRR_BR_6 (0x00400000U) | |
| 2333 | #define GPIO_BSRR_BR_7 (0x00800000U) | |
| 2334 | #define GPIO_BSRR_BR_8 (0x01000000U) | |
| 2335 | #define GPIO_BSRR_BR_9 (0x02000000U) | |
| 2336 | #define GPIO_BSRR_BR_10 (0x04000000U) | |
| 2337 | #define GPIO_BSRR_BR_11 (0x08000000U) | |
| 2338 | #define GPIO_BSRR_BR_12 (0x10000000U) | |
| 2339 | #define GPIO_BSRR_BR_13 (0x20000000U) | |
| 2340 | #define GPIO_BSRR_BR_14 (0x40000000U) | |
| 2341 | #define GPIO_BSRR_BR_15 (0x80000000U) | |
| 2342 | ||
| 2343 | /****************** Bit definition for GPIO_LCKR register ********************/ | |
| 2344 | #define GPIO_LCKR_LCK0_Pos (0U) | |
| 2345 | #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ | |
| 2346 | #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk | |
| 2347 | #define GPIO_LCKR_LCK1_Pos (1U) | |
| 2348 | #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ | |
| 2349 | #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk | |
| 2350 | #define GPIO_LCKR_LCK2_Pos (2U) | |
| 2351 | #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ | |
| 2352 | #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk | |
| 2353 | #define GPIO_LCKR_LCK3_Pos (3U) | |
| 2354 | #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ | |
| 2355 | #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk | |
| 2356 | #define GPIO_LCKR_LCK4_Pos (4U) | |
| 2357 | #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ | |
| 2358 | #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk | |
| 2359 | #define GPIO_LCKR_LCK5_Pos (5U) | |
| 2360 | #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ | |
| 2361 | #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk | |
| 2362 | #define GPIO_LCKR_LCK6_Pos (6U) | |
| 2363 | #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ | |
| 2364 | #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk | |
| 2365 | #define GPIO_LCKR_LCK7_Pos (7U) | |
| 2366 | #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ | |
| 2367 | #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk | |
| 2368 | #define GPIO_LCKR_LCK8_Pos (8U) | |
| 2369 | #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ | |
| 2370 | #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk | |
| 2371 | #define GPIO_LCKR_LCK9_Pos (9U) | |
| 2372 | #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ | |
| 2373 | #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk | |
| 2374 | #define GPIO_LCKR_LCK10_Pos (10U) | |
| 2375 | #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ | |
| 2376 | #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk | |
| 2377 | #define GPIO_LCKR_LCK11_Pos (11U) | |
| 2378 | #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ | |
| 2379 | #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk | |
| 2380 | #define GPIO_LCKR_LCK12_Pos (12U) | |
| 2381 | #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ | |
| 2382 | #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk | |
| 2383 | #define GPIO_LCKR_LCK13_Pos (13U) | |
| 2384 | #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ | |
| 2385 | #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk | |
| 2386 | #define GPIO_LCKR_LCK14_Pos (14U) | |
| 2387 | #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ | |
| 2388 | #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk | |
| 2389 | #define GPIO_LCKR_LCK15_Pos (15U) | |
| 2390 | #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ | |
| 2391 | #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk | |
| 2392 | #define GPIO_LCKR_LCKK_Pos (16U) | |
| 2393 | #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ | |
| 2394 | #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk | |
| 2395 | ||
| 2396 | /****************** Bit definition for GPIO_AFRL register ********************/ | |
| 2397 | #define GPIO_AFRL_AFSEL0_Pos (0U) | |
| 2398 | #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ | |
| 2399 | #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk | |
| 2400 | #define GPIO_AFRL_AFSEL1_Pos (4U) | |
| 2401 | #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ | |
| 2402 | #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk | |
| 2403 | #define GPIO_AFRL_AFSEL2_Pos (8U) | |
| 2404 | #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ | |
| 2405 | #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk | |
| 2406 | #define GPIO_AFRL_AFSEL3_Pos (12U) | |
| 2407 | #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ | |
| 2408 | #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk | |
| 2409 | #define GPIO_AFRL_AFSEL4_Pos (16U) | |
| 2410 | #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ | |
| 2411 | #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk | |
| 2412 | #define GPIO_AFRL_AFSEL5_Pos (20U) | |
| 2413 | #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ | |
| 2414 | #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk | |
| 2415 | #define GPIO_AFRL_AFSEL6_Pos (24U) | |
| 2416 | #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ | |
| 2417 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk | |
| 2418 | #define GPIO_AFRL_AFSEL7_Pos (28U) | |
| 2419 | #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ | |
| 2420 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk | |
| 2421 | ||
| 2422 | /* Legacy aliases */ | |
| 2423 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos | |
| 2424 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk | |
| 2425 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 | |
| 2426 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos | |
| 2427 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk | |
| 2428 | #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 | |
| 2429 | #define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos | |
| 2430 | #define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk | |
| 2431 | #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 | |
| 2432 | #define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos | |
| 2433 | #define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk | |
| 2434 | #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 | |
| 2435 | #define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos | |
| 2436 | #define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk | |
| 2437 | #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 | |
| 2438 | #define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos | |
| 2439 | #define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk | |
| 2440 | #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 | |
| 2441 | #define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos | |
| 2442 | #define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk | |
| 2443 | #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 | |
| 2444 | #define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos | |
| 2445 | #define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk | |
| 2446 | #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 | |
| 2447 | ||
| 2448 | /****************** Bit definition for GPIO_AFRH register ********************/ | |
| 2449 | #define GPIO_AFRH_AFSEL8_Pos (0U) | |
| 2450 | #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ | |
| 2451 | #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk | |
| 2452 | #define GPIO_AFRH_AFSEL9_Pos (4U) | |
| 2453 | #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ | |
| 2454 | #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk | |
| 2455 | #define GPIO_AFRH_AFSEL10_Pos (8U) | |
| 2456 | #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ | |
| 2457 | #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk | |
| 2458 | #define GPIO_AFRH_AFSEL11_Pos (12U) | |
| 2459 | #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ | |
| 2460 | #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk | |
| 2461 | #define GPIO_AFRH_AFSEL12_Pos (16U) | |
| 2462 | #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ | |
| 2463 | #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk | |
| 2464 | #define GPIO_AFRH_AFSEL13_Pos (20U) | |
| 2465 | #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ | |
| 2466 | #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk | |
| 2467 | #define GPIO_AFRH_AFSEL14_Pos (24U) | |
| 2468 | #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ | |
| 2469 | #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk | |
| 2470 | #define GPIO_AFRH_AFSEL15_Pos (28U) | |
| 2471 | #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ | |
| 2472 | #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk | |
| 2473 | ||
| 2474 | /* Legacy aliases */ | |
| 2475 | #define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos | |
| 2476 | #define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk | |
| 2477 | #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 | |
| 2478 | #define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos | |
| 2479 | #define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk | |
| 2480 | #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 | |
| 2481 | #define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos | |
| 2482 | #define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk | |
| 2483 | #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 | |
| 2484 | #define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos | |
| 2485 | #define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk | |
| 2486 | #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 | |
| 2487 | #define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos | |
| 2488 | #define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk | |
| 2489 | #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 | |
| 2490 | #define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos | |
| 2491 | #define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk | |
| 2492 | #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 | |
| 2493 | #define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos | |
| 2494 | #define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk | |
| 2495 | #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 | |
| 2496 | #define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos | |
| 2497 | #define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk | |
| 2498 | #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 | |
| 2499 | ||
| 2500 | /****************** Bit definition for GPIO_BRR register *********************/ | |
| 2501 | #define GPIO_BRR_BR_0 (0x00000001U) | |
| 2502 | #define GPIO_BRR_BR_1 (0x00000002U) | |
| 2503 | #define GPIO_BRR_BR_2 (0x00000004U) | |
| 2504 | #define GPIO_BRR_BR_3 (0x00000008U) | |
| 2505 | #define GPIO_BRR_BR_4 (0x00000010U) | |
| 2506 | #define GPIO_BRR_BR_5 (0x00000020U) | |
| 2507 | #define GPIO_BRR_BR_6 (0x00000040U) | |
| 2508 | #define GPIO_BRR_BR_7 (0x00000080U) | |
| 2509 | #define GPIO_BRR_BR_8 (0x00000100U) | |
| 2510 | #define GPIO_BRR_BR_9 (0x00000200U) | |
| 2511 | #define GPIO_BRR_BR_10 (0x00000400U) | |
| 2512 | #define GPIO_BRR_BR_11 (0x00000800U) | |
| 2513 | #define GPIO_BRR_BR_12 (0x00001000U) | |
| 2514 | #define GPIO_BRR_BR_13 (0x00002000U) | |
| 2515 | #define GPIO_BRR_BR_14 (0x00004000U) | |
| 2516 | #define GPIO_BRR_BR_15 (0x00008000U) | |
| 2517 | ||
| 2518 | /******************************************************************************/ | |
| 2519 | /* */ | |
| 2520 | /* Inter-integrated Circuit Interface (I2C) */ | |
| 2521 | /* */ | |
| 2522 | /******************************************************************************/ | |
| 2523 | ||
| 2524 | /******************* Bit definition for I2C_CR1 register *******************/ | |
| 2525 | #define I2C_CR1_PE_Pos (0U) | |
| 2526 | #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ | |
| 2527 | #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ | |
| 2528 | #define I2C_CR1_TXIE_Pos (1U) | |
| 2529 | #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ | |
| 2530 | #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ | |
| 2531 | #define I2C_CR1_RXIE_Pos (2U) | |
| 2532 | #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ | |
| 2533 | #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ | |
| 2534 | #define I2C_CR1_ADDRIE_Pos (3U) | |
| 2535 | #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ | |
| 2536 | #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ | |
| 2537 | #define I2C_CR1_NACKIE_Pos (4U) | |
| 2538 | #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ | |
| 2539 | #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ | |
| 2540 | #define I2C_CR1_STOPIE_Pos (5U) | |
| 2541 | #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ | |
| 2542 | #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ | |
| 2543 | #define I2C_CR1_TCIE_Pos (6U) | |
| 2544 | #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ | |
| 2545 | #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ | |
| 2546 | #define I2C_CR1_ERRIE_Pos (7U) | |
| 2547 | #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ | |
| 2548 | #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ | |
| 2549 | #define I2C_CR1_DNF_Pos (8U) | |
| 2550 | #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ | |
| 2551 | #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ | |
| 2552 | #define I2C_CR1_ANFOFF_Pos (12U) | |
| 2553 | #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ | |
| 2554 | #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ | |
| 2555 | #define I2C_CR1_SWRST_Pos (13U) | |
| 2556 | #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ | |
| 2557 | #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ | |
| 2558 | #define I2C_CR1_TXDMAEN_Pos (14U) | |
| 2559 | #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ | |
| 2560 | #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ | |
| 2561 | #define I2C_CR1_RXDMAEN_Pos (15U) | |
| 2562 | #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ | |
| 2563 | #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ | |
| 2564 | #define I2C_CR1_SBC_Pos (16U) | |
| 2565 | #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ | |
| 2566 | #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ | |
| 2567 | #define I2C_CR1_NOSTRETCH_Pos (17U) | |
| 2568 | #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ | |
| 2569 | #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ | |
| 2570 | #define I2C_CR1_GCEN_Pos (19U) | |
| 2571 | #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ | |
| 2572 | #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ | |
| 2573 | #define I2C_CR1_SMBHEN_Pos (20U) | |
| 2574 | #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ | |
| 2575 | #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ | |
| 2576 | #define I2C_CR1_SMBDEN_Pos (21U) | |
| 2577 | #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ | |
| 2578 | #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ | |
| 2579 | #define I2C_CR1_ALERTEN_Pos (22U) | |
| 2580 | #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ | |
| 2581 | #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ | |
| 2582 | #define I2C_CR1_PECEN_Pos (23U) | |
| 2583 | #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ | |
| 2584 | #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ | |
| 2585 | ||
| 2586 | /****************** Bit definition for I2C_CR2 register ********************/ | |
| 2587 | #define I2C_CR2_SADD_Pos (0U) | |
| 2588 | #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ | |
| 2589 | #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ | |
| 2590 | #define I2C_CR2_RD_WRN_Pos (10U) | |
| 2591 | #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ | |
| 2592 | #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ | |
| 2593 | #define I2C_CR2_ADD10_Pos (11U) | |
| 2594 | #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ | |
| 2595 | #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ | |
| 2596 | #define I2C_CR2_HEAD10R_Pos (12U) | |
| 2597 | #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ | |
| 2598 | #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ | |
| 2599 | #define I2C_CR2_START_Pos (13U) | |
| 2600 | #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */ | |
| 2601 | #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ | |
| 2602 | #define I2C_CR2_STOP_Pos (14U) | |
| 2603 | #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ | |
| 2604 | #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ | |
| 2605 | #define I2C_CR2_NACK_Pos (15U) | |
| 2606 | #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ | |
| 2607 | #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ | |
| 2608 | #define I2C_CR2_NBYTES_Pos (16U) | |
| 2609 | #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ | |
| 2610 | #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ | |
| 2611 | #define I2C_CR2_RELOAD_Pos (24U) | |
| 2612 | #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ | |
| 2613 | #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ | |
| 2614 | #define I2C_CR2_AUTOEND_Pos (25U) | |
| 2615 | #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ | |
| 2616 | #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ | |
| 2617 | #define I2C_CR2_PECBYTE_Pos (26U) | |
| 2618 | #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ | |
| 2619 | #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ | |
| 2620 | ||
| 2621 | /******************* Bit definition for I2C_OAR1 register ******************/ | |
| 2622 | #define I2C_OAR1_OA1_Pos (0U) | |
| 2623 | #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ | |
| 2624 | #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ | |
| 2625 | #define I2C_OAR1_OA1MODE_Pos (10U) | |
| 2626 | #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ | |
| 2627 | #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ | |
| 2628 | #define I2C_OAR1_OA1EN_Pos (15U) | |
| 2629 | #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ | |
| 2630 | #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ | |
| 2631 | ||
| 2632 | /******************* Bit definition for I2C_OAR2 register ******************/ | |
| 2633 | #define I2C_OAR2_OA2_Pos (1U) | |
| 2634 | #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ | |
| 2635 | #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ | |
| 2636 | #define I2C_OAR2_OA2MSK_Pos (8U) | |
| 2637 | #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ | |
| 2638 | #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ | |
| 2639 | #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ | |
| 2640 | #define I2C_OAR2_OA2MASK01_Pos (8U) | |
| 2641 | #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ | |
| 2642 | #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ | |
| 2643 | #define I2C_OAR2_OA2MASK02_Pos (9U) | |
| 2644 | #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ | |
| 2645 | #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ | |
| 2646 | #define I2C_OAR2_OA2MASK03_Pos (8U) | |
| 2647 | #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ | |
| 2648 | #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ | |
| 2649 | #define I2C_OAR2_OA2MASK04_Pos (10U) | |
| 2650 | #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ | |
| 2651 | #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ | |
| 2652 | #define I2C_OAR2_OA2MASK05_Pos (8U) | |
| 2653 | #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ | |
| 2654 | #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ | |
| 2655 | #define I2C_OAR2_OA2MASK06_Pos (9U) | |
| 2656 | #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ | |
| 2657 | #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ | |
| 2658 | #define I2C_OAR2_OA2MASK07_Pos (8U) | |
| 2659 | #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ | |
| 2660 | #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ | |
| 2661 | #define I2C_OAR2_OA2EN_Pos (15U) | |
| 2662 | #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ | |
| 2663 | #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ | |
| 2664 | ||
| 2665 | /******************* Bit definition for I2C_TIMINGR register ****************/ | |
| 2666 | #define I2C_TIMINGR_SCLL_Pos (0U) | |
| 2667 | #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ | |
| 2668 | #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ | |
| 2669 | #define I2C_TIMINGR_SCLH_Pos (8U) | |
| 2670 | #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ | |
| 2671 | #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ | |
| 2672 | #define I2C_TIMINGR_SDADEL_Pos (16U) | |
| 2673 | #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ | |
| 2674 | #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ | |
| 2675 | #define I2C_TIMINGR_SCLDEL_Pos (20U) | |
| 2676 | #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ | |
| 2677 | #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ | |
| 2678 | #define I2C_TIMINGR_PRESC_Pos (28U) | |
| 2679 | #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ | |
| 2680 | #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ | |
| 2681 | ||
| 2682 | /******************* Bit definition for I2C_TIMEOUTR register ****************/ | |
| 2683 | #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) | |
| 2684 | #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ | |
| 2685 | #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ | |
| 2686 | #define I2C_TIMEOUTR_TIDLE_Pos (12U) | |
| 2687 | #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ | |
| 2688 | #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ | |
| 2689 | #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) | |
| 2690 | #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ | |
| 2691 | #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ | |
| 2692 | #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) | |
| 2693 | #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ | |
| 2694 | #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ | |
| 2695 | #define I2C_TIMEOUTR_TEXTEN_Pos (31U) | |
| 2696 | #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ | |
| 2697 | #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ | |
| 2698 | ||
| 2699 | /****************** Bit definition for I2C_ISR register ********************/ | |
| 2700 | #define I2C_ISR_TXE_Pos (0U) | |
| 2701 | #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ | |
| 2702 | #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ | |
| 2703 | #define I2C_ISR_TXIS_Pos (1U) | |
| 2704 | #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ | |
| 2705 | #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ | |
| 2706 | #define I2C_ISR_RXNE_Pos (2U) | |
| 2707 | #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ | |
| 2708 | #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ | |
| 2709 | #define I2C_ISR_ADDR_Pos (3U) | |
| 2710 | #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ | |
| 2711 | #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ | |
| 2712 | #define I2C_ISR_NACKF_Pos (4U) | |
| 2713 | #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ | |
| 2714 | #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ | |
| 2715 | #define I2C_ISR_STOPF_Pos (5U) | |
| 2716 | #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ | |
| 2717 | #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ | |
| 2718 | #define I2C_ISR_TC_Pos (6U) | |
| 2719 | #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */ | |
| 2720 | #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ | |
| 2721 | #define I2C_ISR_TCR_Pos (7U) | |
| 2722 | #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ | |
| 2723 | #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ | |
| 2724 | #define I2C_ISR_BERR_Pos (8U) | |
| 2725 | #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ | |
| 2726 | #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ | |
| 2727 | #define I2C_ISR_ARLO_Pos (9U) | |
| 2728 | #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ | |
| 2729 | #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ | |
| 2730 | #define I2C_ISR_OVR_Pos (10U) | |
| 2731 | #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ | |
| 2732 | #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ | |
| 2733 | #define I2C_ISR_PECERR_Pos (11U) | |
| 2734 | #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ | |
| 2735 | #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ | |
| 2736 | #define I2C_ISR_TIMEOUT_Pos (12U) | |
| 2737 | #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ | |
| 2738 | #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ | |
| 2739 | #define I2C_ISR_ALERT_Pos (13U) | |
| 2740 | #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ | |
| 2741 | #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ | |
| 2742 | #define I2C_ISR_BUSY_Pos (15U) | |
| 2743 | #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ | |
| 2744 | #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ | |
| 2745 | #define I2C_ISR_DIR_Pos (16U) | |
| 2746 | #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ | |
| 2747 | #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ | |
| 2748 | #define I2C_ISR_ADDCODE_Pos (17U) | |
| 2749 | #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ | |
| 2750 | #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ | |
| 2751 | ||
| 2752 | /****************** Bit definition for I2C_ICR register ********************/ | |
| 2753 | #define I2C_ICR_ADDRCF_Pos (3U) | |
| 2754 | #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ | |
| 2755 | #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ | |
| 2756 | #define I2C_ICR_NACKCF_Pos (4U) | |
| 2757 | #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ | |
| 2758 | #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ | |
| 2759 | #define I2C_ICR_STOPCF_Pos (5U) | |
| 2760 | #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ | |
| 2761 | #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ | |
| 2762 | #define I2C_ICR_BERRCF_Pos (8U) | |
| 2763 | #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ | |
| 2764 | #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ | |
| 2765 | #define I2C_ICR_ARLOCF_Pos (9U) | |
| 2766 | #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ | |
| 2767 | #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ | |
| 2768 | #define I2C_ICR_OVRCF_Pos (10U) | |
| 2769 | #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ | |
| 2770 | #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ | |
| 2771 | #define I2C_ICR_PECCF_Pos (11U) | |
| 2772 | #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ | |
| 2773 | #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ | |
| 2774 | #define I2C_ICR_TIMOUTCF_Pos (12U) | |
| 2775 | #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ | |
| 2776 | #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ | |
| 2777 | #define I2C_ICR_ALERTCF_Pos (13U) | |
| 2778 | #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ | |
| 2779 | #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ | |
| 2780 | ||
| 2781 | /****************** Bit definition for I2C_PECR register *******************/ | |
| 2782 | #define I2C_PECR_PEC_Pos (0U) | |
| 2783 | #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ | |
| 2784 | #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ | |
| 2785 | ||
| 2786 | /****************** Bit definition for I2C_RXDR register *********************/ | |
| 2787 | #define I2C_RXDR_RXDATA_Pos (0U) | |
| 2788 | #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ | |
| 2789 | #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ | |
| 2790 | ||
| 2791 | /****************** Bit definition for I2C_TXDR register *******************/ | |
| 2792 | #define I2C_TXDR_TXDATA_Pos (0U) | |
| 2793 | #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ | |
| 2794 | #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ | |
| 2795 | ||
| 2796 | /*****************************************************************************/ | |
| 2797 | /* */ | |
| 2798 | /* Independent WATCHDOG (IWDG) */ | |
| 2799 | /* */ | |
| 2800 | /*****************************************************************************/ | |
| 2801 | /******************* Bit definition for IWDG_KR register *******************/ | |
| 2802 | #define IWDG_KR_KEY_Pos (0U) | |
| 2803 | #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ | |
| 2804 | #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ | |
| 2805 | ||
| 2806 | /******************* Bit definition for IWDG_PR register *******************/ | |
| 2807 | #define IWDG_PR_PR_Pos (0U) | |
| 2808 | #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ | |
| 2809 | #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ | |
| 2810 | #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */ | |
| 2811 | #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */ | |
| 2812 | #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */ | |
| 2813 | ||
| 2814 | /******************* Bit definition for IWDG_RLR register ******************/ | |
| 2815 | #define IWDG_RLR_RL_Pos (0U) | |
| 2816 | #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ | |
| 2817 | #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ | |
| 2818 | ||
| 2819 | /******************* Bit definition for IWDG_SR register *******************/ | |
| 2820 | #define IWDG_SR_PVU_Pos (0U) | |
| 2821 | #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ | |
| 2822 | #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ | |
| 2823 | #define IWDG_SR_RVU_Pos (1U) | |
| 2824 | #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ | |
| 2825 | #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ | |
| 2826 | #define IWDG_SR_WVU_Pos (2U) | |
| 2827 | #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ | |
| 2828 | #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ | |
| 2829 | ||
| 2830 | /******************* Bit definition for IWDG_KR register *******************/ | |
| 2831 | #define IWDG_WINR_WIN_Pos (0U) | |
| 2832 | #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ | |
| 2833 | #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ | |
| 2834 | ||
| 2835 | /*****************************************************************************/ | |
| 2836 | /* */ | |
| 2837 | /* Power Control (PWR) */ | |
| 2838 | /* */ | |
| 2839 | /*****************************************************************************/ | |
| 2840 | ||
| 2841 | /* Note: No specific macro feature on this device */ | |
| 2842 | ||
| 2843 | ||
| 2844 | /******************** Bit definition for PWR_CR register *******************/ | |
| 2845 | #define PWR_CR_LPDS_Pos (0U) | |
| 2846 | #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ | |
| 2847 | #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */ | |
| 2848 | #define PWR_CR_PDDS_Pos (1U) | |
| 2849 | #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ | |
| 2850 | #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ | |
| 2851 | #define PWR_CR_CWUF_Pos (2U) | |
| 2852 | #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ | |
| 2853 | #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ | |
| 2854 | #define PWR_CR_CSBF_Pos (3U) | |
| 2855 | #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ | |
| 2856 | #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ | |
| 2857 | #define PWR_CR_DBP_Pos (8U) | |
| 2858 | #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ | |
| 2859 | #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ | |
| 2860 | ||
| 2861 | /******************* Bit definition for PWR_CSR register *******************/ | |
| 2862 | #define PWR_CSR_WUF_Pos (0U) | |
| 2863 | #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ | |
| 2864 | #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ | |
| 2865 | #define PWR_CSR_SBF_Pos (1U) | |
| 2866 | #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ | |
| 2867 | #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ | |
| 2868 | ||
| 2869 | #define PWR_CSR_EWUP1_Pos (8U) | |
| 2870 | #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ | |
| 2871 | #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ | |
| 2872 | #define PWR_CSR_EWUP2_Pos (9U) | |
| 2873 | #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ | |
| 2874 | #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ | |
| 2875 | #define PWR_CSR_EWUP4_Pos (11U) | |
| 2876 | #define PWR_CSR_EWUP4_Msk (0x1U << PWR_CSR_EWUP4_Pos) /*!< 0x00000800 */ | |
| 2877 | #define PWR_CSR_EWUP4 PWR_CSR_EWUP4_Msk /*!< Enable WKUP pin 4 */ | |
| 2878 | #define PWR_CSR_EWUP5_Pos (12U) | |
| 2879 | #define PWR_CSR_EWUP5_Msk (0x1U << PWR_CSR_EWUP5_Pos) /*!< 0x00001000 */ | |
| 2880 | #define PWR_CSR_EWUP5 PWR_CSR_EWUP5_Msk /*!< Enable WKUP pin 5 */ | |
| 2881 | #define PWR_CSR_EWUP6_Pos (13U) | |
| 2882 | #define PWR_CSR_EWUP6_Msk (0x1U << PWR_CSR_EWUP6_Pos) /*!< 0x00002000 */ | |
| 2883 | #define PWR_CSR_EWUP6 PWR_CSR_EWUP6_Msk /*!< Enable WKUP pin 6 */ | |
| 2884 | #define PWR_CSR_EWUP7_Pos (14U) | |
| 2885 | #define PWR_CSR_EWUP7_Msk (0x1U << PWR_CSR_EWUP7_Pos) /*!< 0x00004000 */ | |
| 2886 | #define PWR_CSR_EWUP7 PWR_CSR_EWUP7_Msk /*!< Enable WKUP pin 7 */ | |
| 2887 | ||
| 2888 | /*****************************************************************************/ | |
| 2889 | /* */ | |
| 2890 | /* Reset and Clock Control */ | |
| 2891 | /* */ | |
| 2892 | /*****************************************************************************/ | |
| 2893 | /* | |
| 2894 | * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) | |
| 2895 | */ | |
| 2896 | #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ | |
| 2897 | ||
| 2898 | /******************** Bit definition for RCC_CR register *******************/ | |
| 2899 | #define RCC_CR_HSION_Pos (0U) | |
| 2900 | #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ | |
| 2901 | #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ | |
| 2902 | #define RCC_CR_HSIRDY_Pos (1U) | |
| 2903 | #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ | |
| 2904 | #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ | |
| 2905 | ||
| 2906 | #define RCC_CR_HSITRIM_Pos (3U) | |
| 2907 | #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ | |
| 2908 | #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ | |
| 2909 | #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ | |
| 2910 | #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ | |
| 2911 | #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ | |
| 2912 | #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ | |
| 2913 | #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ | |
| 2914 | ||
| 2915 | #define RCC_CR_HSICAL_Pos (8U) | |
| 2916 | #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ | |
| 2917 | #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ | |
| 2918 | #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ | |
| 2919 | #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ | |
| 2920 | #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ | |
| 2921 | #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ | |
| 2922 | #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ | |
| 2923 | #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ | |
| 2924 | #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ | |
| 2925 | #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ | |
| 2926 | ||
| 2927 | #define RCC_CR_HSEON_Pos (16U) | |
| 2928 | #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ | |
| 2929 | #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ | |
| 2930 | #define RCC_CR_HSERDY_Pos (17U) | |
| 2931 | #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ | |
| 2932 | #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ | |
| 2933 | #define RCC_CR_HSEBYP_Pos (18U) | |
| 2934 | #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ | |
| 2935 | #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ | |
| 2936 | #define RCC_CR_CSSON_Pos (19U) | |
| 2937 | #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ | |
| 2938 | #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ | |
| 2939 | #define RCC_CR_PLLON_Pos (24U) | |
| 2940 | #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ | |
| 2941 | #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ | |
| 2942 | #define RCC_CR_PLLRDY_Pos (25U) | |
| 2943 | #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ | |
| 2944 | #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ | |
| 2945 | ||
| 2946 | /******************** Bit definition for RCC_CFGR register *****************/ | |
| 2947 | /*!< SW configuration */ | |
| 2948 | #define RCC_CFGR_SW_Pos (0U) | |
| 2949 | #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ | |
| 2950 | #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ | |
| 2951 | #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ | |
| 2952 | #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ | |
| 2953 | ||
| 2954 | #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */ | |
| 2955 | #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */ | |
| 2956 | #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */ | |
| 2957 | ||
| 2958 | /*!< SWS configuration */ | |
| 2959 | #define RCC_CFGR_SWS_Pos (2U) | |
| 2960 | #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ | |
| 2961 | #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ | |
| 2962 | #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ | |
| 2963 | #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ | |
| 2964 | ||
| 2965 | #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */ | |
| 2966 | #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */ | |
| 2967 | #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */ | |
| 2968 | ||
| 2969 | /*!< HPRE configuration */ | |
| 2970 | #define RCC_CFGR_HPRE_Pos (4U) | |
| 2971 | #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ | |
| 2972 | #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ | |
| 2973 | #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ | |
| 2974 | #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ | |
| 2975 | #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ | |
| 2976 | #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ | |
| 2977 | ||
| 2978 | #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ | |
| 2979 | #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ | |
| 2980 | #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ | |
| 2981 | #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ | |
| 2982 | #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ | |
| 2983 | #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ | |
| 2984 | #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ | |
| 2985 | #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ | |
| 2986 | #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ | |
| 2987 | ||
| 2988 | /*!< PPRE configuration */ | |
| 2989 | #define RCC_CFGR_PPRE_Pos (8U) | |
| 2990 | #define RCC_CFGR_PPRE_Msk (0x7U << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */ | |
| 2991 | #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */ | |
| 2992 | #define RCC_CFGR_PPRE_0 (0x1U << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */ | |
| 2993 | #define RCC_CFGR_PPRE_1 (0x2U << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */ | |
| 2994 | #define RCC_CFGR_PPRE_2 (0x4U << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */ | |
| 2995 | ||
| 2996 | #define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */ | |
| 2997 | #define RCC_CFGR_PPRE_DIV2_Pos (10U) | |
| 2998 | #define RCC_CFGR_PPRE_DIV2_Msk (0x1U << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */ | |
| 2999 | #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */ | |
| 3000 | #define RCC_CFGR_PPRE_DIV4_Pos (8U) | |
| 3001 | #define RCC_CFGR_PPRE_DIV4_Msk (0x5U << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */ | |
| 3002 | #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */ | |
| 3003 | #define RCC_CFGR_PPRE_DIV8_Pos (9U) | |
| 3004 | #define RCC_CFGR_PPRE_DIV8_Msk (0x3U << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */ | |
| 3005 | #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */ | |
| 3006 | #define RCC_CFGR_PPRE_DIV16_Pos (8U) | |
| 3007 | #define RCC_CFGR_PPRE_DIV16_Msk (0x7U << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */ | |
| 3008 | #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */ | |
| 3009 | ||
| 3010 | /*!< ADCPPRE configuration */ | |
| 3011 | #define RCC_CFGR_ADCPRE_Pos (14U) | |
| 3012 | #define RCC_CFGR_ADCPRE_Msk (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ | |
| 3013 | #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE bit (ADC prescaler) */ | |
| 3014 | ||
| 3015 | #define RCC_CFGR_ADCPRE_DIV2 (0x00000000U) /*!< PCLK divided by 2 */ | |
| 3016 | #define RCC_CFGR_ADCPRE_DIV4 (0x00004000U) /*!< PCLK divided by 4 */ | |
| 3017 | ||
| 3018 | #define RCC_CFGR_PLLSRC_Pos (15U) | |
| 3019 | #define RCC_CFGR_PLLSRC_Msk (0x3U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */ | |
| 3020 | #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ | |
| 3021 | #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ | |
| 3022 | #define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock selected as PLL entry clock source */ | |
| 3023 | #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */ | |
| 3024 | ||
| 3025 | #define RCC_CFGR_PLLXTPRE_Pos (17U) | |
| 3026 | #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ | |
| 3027 | #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ | |
| 3028 | #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */ | |
| 3029 | #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */ | |
| 3030 | ||
| 3031 | /*!< PLLMUL configuration */ | |
| 3032 | #define RCC_CFGR_PLLMUL_Pos (18U) | |
| 3033 | #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ | |
| 3034 | #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ | |
| 3035 | #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ | |
| 3036 | #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ | |
| 3037 | #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ | |
| 3038 | #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ | |
| 3039 | ||
| 3040 | #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */ | |
| 3041 | #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */ | |
| 3042 | #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */ | |
| 3043 | #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */ | |
| 3044 | #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */ | |
| 3045 | #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */ | |
| 3046 | #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */ | |
| 3047 | #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */ | |
| 3048 | #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */ | |
| 3049 | #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */ | |
| 3050 | #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */ | |
| 3051 | #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */ | |
| 3052 | #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */ | |
| 3053 | #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */ | |
| 3054 | #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */ | |
| 3055 | ||
| 3056 | /*!< USB configuration */ | |
| 3057 | #define RCC_CFGR_USBPRE_Pos (22U) | |
| 3058 | #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ | |
| 3059 | #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB prescaler */ | |
| 3060 | ||
| 3061 | /*!< MCO configuration */ | |
| 3062 | #define RCC_CFGR_MCO_Pos (24U) | |
| 3063 | #define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */ | |
| 3064 | #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ | |
| 3065 | #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ | |
| 3066 | #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ | |
| 3067 | #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ | |
| 3068 | ||
| 3069 | #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */ | |
| 3070 | #define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */ | |
| 3071 | #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */ | |
| 3072 | #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */ | |
| 3073 | #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */ | |
| 3074 | #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */ | |
| 3075 | #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */ | |
| 3076 | #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */ | |
| 3077 | ||
| 3078 | #define RCC_CFGR_MCOPRE_Pos (28U) | |
| 3079 | #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ | |
| 3080 | #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ | |
| 3081 | #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ | |
| 3082 | #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ | |
| 3083 | #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ | |
| 3084 | #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ | |
| 3085 | #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ | |
| 3086 | #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */ | |
| 3087 | #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */ | |
| 3088 | #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */ | |
| 3089 | ||
| 3090 | #define RCC_CFGR_PLLNODIV_Pos (31U) | |
| 3091 | #define RCC_CFGR_PLLNODIV_Msk (0x1U << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */ | |
| 3092 | #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< PLL is not divided to MCO */ | |
| 3093 | ||
| 3094 | /* Reference defines */ | |
| 3095 | #define RCC_CFGR_MCOSEL RCC_CFGR_MCO | |
| 3096 | #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 | |
| 3097 | #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 | |
| 3098 | #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 | |
| 3099 | #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK | |
| 3100 | #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14 | |
| 3101 | #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI | |
| 3102 | #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE | |
| 3103 | #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK | |
| 3104 | #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI | |
| 3105 | #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE | |
| 3106 | #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL | |
| 3107 | ||
| 3108 | /*!<****************** Bit definition for RCC_CIR register *****************/ | |
| 3109 | #define RCC_CIR_LSIRDYF_Pos (0U) | |
| 3110 | #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ | |
| 3111 | #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ | |
| 3112 | #define RCC_CIR_LSERDYF_Pos (1U) | |
| 3113 | #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ | |
| 3114 | #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ | |
| 3115 | #define RCC_CIR_HSIRDYF_Pos (2U) | |
| 3116 | #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ | |
| 3117 | #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ | |
| 3118 | #define RCC_CIR_HSERDYF_Pos (3U) | |
| 3119 | #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ | |
| 3120 | #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ | |
| 3121 | #define RCC_CIR_PLLRDYF_Pos (4U) | |
| 3122 | #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ | |
| 3123 | #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ | |
| 3124 | #define RCC_CIR_HSI14RDYF_Pos (5U) | |
| 3125 | #define RCC_CIR_HSI14RDYF_Msk (0x1U << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */ | |
| 3126 | #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */ | |
| 3127 | #define RCC_CIR_CSSF_Pos (7U) | |
| 3128 | #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ | |
| 3129 | #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ | |
| 3130 | #define RCC_CIR_LSIRDYIE_Pos (8U) | |
| 3131 | #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ | |
| 3132 | #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ | |
| 3133 | #define RCC_CIR_LSERDYIE_Pos (9U) | |
| 3134 | #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ | |
| 3135 | #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ | |
| 3136 | #define RCC_CIR_HSIRDYIE_Pos (10U) | |
| 3137 | #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ | |
| 3138 | #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ | |
| 3139 | #define RCC_CIR_HSERDYIE_Pos (11U) | |
| 3140 | #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ | |
| 3141 | #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ | |
| 3142 | #define RCC_CIR_PLLRDYIE_Pos (12U) | |
| 3143 | #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ | |
| 3144 | #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ | |
| 3145 | #define RCC_CIR_HSI14RDYIE_Pos (13U) | |
| 3146 | #define RCC_CIR_HSI14RDYIE_Msk (0x1U << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */ | |
| 3147 | #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */ | |
| 3148 | #define RCC_CIR_LSIRDYC_Pos (16U) | |
| 3149 | #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ | |
| 3150 | #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ | |
| 3151 | #define RCC_CIR_LSERDYC_Pos (17U) | |
| 3152 | #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ | |
| 3153 | #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ | |
| 3154 | #define RCC_CIR_HSIRDYC_Pos (18U) | |
| 3155 | #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ | |
| 3156 | #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ | |
| 3157 | #define RCC_CIR_HSERDYC_Pos (19U) | |
| 3158 | #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ | |
| 3159 | #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ | |
| 3160 | #define RCC_CIR_PLLRDYC_Pos (20U) | |
| 3161 | #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ | |
| 3162 | #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ | |
| 3163 | #define RCC_CIR_HSI14RDYC_Pos (21U) | |
| 3164 | #define RCC_CIR_HSI14RDYC_Msk (0x1U << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */ | |
| 3165 | #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */ | |
| 3166 | #define RCC_CIR_CSSC_Pos (23U) | |
| 3167 | #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ | |
| 3168 | #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ | |
| 3169 | ||
| 3170 | /***************** Bit definition for RCC_APB2RSTR register ****************/ | |
| 3171 | #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) | |
| 3172 | #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ | |
| 3173 | #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ | |
| 3174 | #define RCC_APB2RSTR_ADCRST_Pos (9U) | |
| 3175 | #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ | |
| 3176 | #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ | |
| 3177 | #define RCC_APB2RSTR_TIM1RST_Pos (11U) | |
| 3178 | #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ | |
| 3179 | #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ | |
| 3180 | #define RCC_APB2RSTR_SPI1RST_Pos (12U) | |
| 3181 | #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ | |
| 3182 | #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ | |
| 3183 | #define RCC_APB2RSTR_USART1RST_Pos (14U) | |
| 3184 | #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ | |
| 3185 | #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ | |
| 3186 | #define RCC_APB2RSTR_TIM15RST_Pos (16U) | |
| 3187 | #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ | |
| 3188 | #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ | |
| 3189 | #define RCC_APB2RSTR_TIM16RST_Pos (17U) | |
| 3190 | #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ | |
| 3191 | #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ | |
| 3192 | #define RCC_APB2RSTR_TIM17RST_Pos (18U) | |
| 3193 | #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ | |
| 3194 | #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ | |
| 3195 | #define RCC_APB2RSTR_DBGMCURST_Pos (22U) | |
| 3196 | #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ | |
| 3197 | #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ | |
| 3198 | ||
| 3199 | /*!< Old ADC1 reset bit definition maintained for legacy purpose */ | |
| 3200 | #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST | |
| 3201 | ||
| 3202 | /***************** Bit definition for RCC_APB1RSTR register ****************/ | |
| 3203 | #define RCC_APB1RSTR_TIM3RST_Pos (1U) | |
| 3204 | #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ | |
| 3205 | #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ | |
| 3206 | #define RCC_APB1RSTR_TIM6RST_Pos (4U) | |
| 3207 | #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ | |
| 3208 | #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ | |
| 3209 | #define RCC_APB1RSTR_TIM7RST_Pos (5U) | |
| 3210 | #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ | |
| 3211 | #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ | |
| 3212 | #define RCC_APB1RSTR_TIM14RST_Pos (8U) | |
| 3213 | #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ | |
| 3214 | #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ | |
| 3215 | #define RCC_APB1RSTR_WWDGRST_Pos (11U) | |
| 3216 | #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ | |
| 3217 | #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ | |
| 3218 | #define RCC_APB1RSTR_SPI2RST_Pos (14U) | |
| 3219 | #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ | |
| 3220 | #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ | |
| 3221 | #define RCC_APB1RSTR_USART2RST_Pos (17U) | |
| 3222 | #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ | |
| 3223 | #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ | |
| 3224 | #define RCC_APB1RSTR_USART3RST_Pos (18U) | |
| 3225 | #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ | |
| 3226 | #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ | |
| 3227 | #define RCC_APB1RSTR_USART4RST_Pos (19U) | |
| 3228 | #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ | |
| 3229 | #define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 reset */ | |
| 3230 | #define RCC_APB1RSTR_I2C1RST_Pos (21U) | |
| 3231 | #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ | |
| 3232 | #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ | |
| 3233 | #define RCC_APB1RSTR_I2C2RST_Pos (22U) | |
| 3234 | #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ | |
| 3235 | #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ | |
| 3236 | #define RCC_APB1RSTR_USBRST_Pos (23U) | |
| 3237 | #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ | |
| 3238 | #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ | |
| 3239 | #define RCC_APB1RSTR_PWRRST_Pos (28U) | |
| 3240 | #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ | |
| 3241 | #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ | |
| 3242 | ||
| 3243 | /****************** Bit definition for RCC_AHBENR register *****************/ | |
| 3244 | #define RCC_AHBENR_DMAEN_Pos (0U) | |
| 3245 | #define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ | |
| 3246 | #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ | |
| 3247 | #define RCC_AHBENR_SRAMEN_Pos (2U) | |
| 3248 | #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ | |
| 3249 | #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ | |
| 3250 | #define RCC_AHBENR_FLITFEN_Pos (4U) | |
| 3251 | #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ | |
| 3252 | #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ | |
| 3253 | #define RCC_AHBENR_CRCEN_Pos (6U) | |
| 3254 | #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ | |
| 3255 | #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ | |
| 3256 | #define RCC_AHBENR_GPIOAEN_Pos (17U) | |
| 3257 | #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */ | |
| 3258 | #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */ | |
| 3259 | #define RCC_AHBENR_GPIOBEN_Pos (18U) | |
| 3260 | #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */ | |
| 3261 | #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */ | |
| 3262 | #define RCC_AHBENR_GPIOCEN_Pos (19U) | |
| 3263 | #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */ | |
| 3264 | #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */ | |
| 3265 | #define RCC_AHBENR_GPIODEN_Pos (20U) | |
| 3266 | #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */ | |
| 3267 | #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */ | |
| 3268 | #define RCC_AHBENR_GPIOFEN_Pos (22U) | |
| 3269 | #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */ | |
| 3270 | #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */ | |
| 3271 | ||
| 3272 | /* Old Bit definition maintained for legacy purpose */ | |
| 3273 | #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ | |
| 3274 | ||
| 3275 | /***************** Bit definition for RCC_APB2ENR register *****************/ | |
| 3276 | #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U) | |
| 3277 | #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1U << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */ | |
| 3278 | #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */ | |
| 3279 | #define RCC_APB2ENR_ADCEN_Pos (9U) | |
| 3280 | #define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ | |
| 3281 | #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ | |
| 3282 | #define RCC_APB2ENR_TIM1EN_Pos (11U) | |
| 3283 | #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ | |
| 3284 | #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ | |
| 3285 | #define RCC_APB2ENR_SPI1EN_Pos (12U) | |
| 3286 | #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ | |
| 3287 | #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ | |
| 3288 | #define RCC_APB2ENR_USART1EN_Pos (14U) | |
| 3289 | #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ | |
| 3290 | #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ | |
| 3291 | #define RCC_APB2ENR_TIM15EN_Pos (16U) | |
| 3292 | #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ | |
| 3293 | #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ | |
| 3294 | #define RCC_APB2ENR_TIM16EN_Pos (17U) | |
| 3295 | #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ | |
| 3296 | #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ | |
| 3297 | #define RCC_APB2ENR_TIM17EN_Pos (18U) | |
| 3298 | #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ | |
| 3299 | #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ | |
| 3300 | #define RCC_APB2ENR_DBGMCUEN_Pos (22U) | |
| 3301 | #define RCC_APB2ENR_DBGMCUEN_Msk (0x1U << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */ | |
| 3302 | #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */ | |
| 3303 | ||
| 3304 | /* Old Bit definition maintained for legacy purpose */ | |
| 3305 | #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */ | |
| 3306 | #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ | |
| 3307 | ||
| 3308 | /***************** Bit definition for RCC_APB1ENR register *****************/ | |
| 3309 | #define RCC_APB1ENR_TIM3EN_Pos (1U) | |
| 3310 | #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ | |
| 3311 | #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ | |
| 3312 | #define RCC_APB1ENR_TIM6EN_Pos (4U) | |
| 3313 | #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ | |
| 3314 | #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ | |
| 3315 | #define RCC_APB1ENR_TIM7EN_Pos (5U) | |
| 3316 | #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ | |
| 3317 | #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ | |
| 3318 | #define RCC_APB1ENR_TIM14EN_Pos (8U) | |
| 3319 | #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */ | |
| 3320 | #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */ | |
| 3321 | #define RCC_APB1ENR_WWDGEN_Pos (11U) | |
| 3322 | #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ | |
| 3323 | #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ | |
| 3324 | #define RCC_APB1ENR_SPI2EN_Pos (14U) | |
| 3325 | #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ | |
| 3326 | #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ | |
| 3327 | #define RCC_APB1ENR_USART2EN_Pos (17U) | |
| 3328 | #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ | |
| 3329 | #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ | |
| 3330 | #define RCC_APB1ENR_USART3EN_Pos (18U) | |
| 3331 | #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ | |
| 3332 | #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART3 clock enable */ | |
| 3333 | #define RCC_APB1ENR_USART4EN_Pos (19U) | |
| 3334 | #define RCC_APB1ENR_USART4EN_Msk (0x1U << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */ | |
| 3335 | #define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */ | |
| 3336 | #define RCC_APB1ENR_I2C1EN_Pos (21U) | |
| 3337 | #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ | |
| 3338 | #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ | |
| 3339 | #define RCC_APB1ENR_I2C2EN_Pos (22U) | |
| 3340 | #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ | |
| 3341 | #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */ | |
| 3342 | #define RCC_APB1ENR_USBEN_Pos (23U) | |
| 3343 | #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ | |
| 3344 | #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ | |
| 3345 | #define RCC_APB1ENR_PWREN_Pos (28U) | |
| 3346 | #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ | |
| 3347 | #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ | |
| 3348 | ||
| 3349 | /******************* Bit definition for RCC_BDCR register ******************/ | |
| 3350 | #define RCC_BDCR_LSEON_Pos (0U) | |
| 3351 | #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ | |
| 3352 | #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ | |
| 3353 | #define RCC_BDCR_LSERDY_Pos (1U) | |
| 3354 | #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ | |
| 3355 | #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ | |
| 3356 | #define RCC_BDCR_LSEBYP_Pos (2U) | |
| 3357 | #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ | |
| 3358 | #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ | |
| 3359 | ||
| 3360 | #define RCC_BDCR_LSEDRV_Pos (3U) | |
| 3361 | #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ | |
| 3362 | #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ | |
| 3363 | #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ | |
| 3364 | #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ | |
| 3365 | ||
| 3366 | #define RCC_BDCR_RTCSEL_Pos (8U) | |
| 3367 | #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ | |
| 3368 | #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ | |
| 3369 | #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ | |
| 3370 | #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ | |
| 3371 | ||
| 3372 | /*!< RTC configuration */ | |
| 3373 | #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ | |
| 3374 | #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */ | |
| 3375 | #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */ | |
| 3376 | #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */ | |
| 3377 | ||
| 3378 | #define RCC_BDCR_RTCEN_Pos (15U) | |
| 3379 | #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ | |
| 3380 | #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ | |
| 3381 | #define RCC_BDCR_BDRST_Pos (16U) | |
| 3382 | #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ | |
| 3383 | #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ | |
| 3384 | ||
| 3385 | /******************* Bit definition for RCC_CSR register *******************/ | |
| 3386 | #define RCC_CSR_LSION_Pos (0U) | |
| 3387 | #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ | |
| 3388 | #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ | |
| 3389 | #define RCC_CSR_LSIRDY_Pos (1U) | |
| 3390 | #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ | |
| 3391 | #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ | |
| 3392 | #define RCC_CSR_V18PWRRSTF_Pos (23U) | |
| 3393 | #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */ | |
| 3394 | #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */ | |
| 3395 | #define RCC_CSR_RMVF_Pos (24U) | |
| 3396 | #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ | |
| 3397 | #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ | |
| 3398 | #define RCC_CSR_OBLRSTF_Pos (25U) | |
| 3399 | #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ | |
| 3400 | #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ | |
| 3401 | #define RCC_CSR_PINRSTF_Pos (26U) | |
| 3402 | #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ | |
| 3403 | #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ | |
| 3404 | #define RCC_CSR_PORRSTF_Pos (27U) | |
| 3405 | #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ | |
| 3406 | #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ | |
| 3407 | #define RCC_CSR_SFTRSTF_Pos (28U) | |
| 3408 | #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ | |
| 3409 | #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ | |
| 3410 | #define RCC_CSR_IWDGRSTF_Pos (29U) | |
| 3411 | #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ | |
| 3412 | #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ | |
| 3413 | #define RCC_CSR_WWDGRSTF_Pos (30U) | |
| 3414 | #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ | |
| 3415 | #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ | |
| 3416 | #define RCC_CSR_LPWRRSTF_Pos (31U) | |
| 3417 | #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ | |
| 3418 | #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ | |
| 3419 | ||
| 3420 | /* Old Bit definition maintained for legacy purpose */ | |
| 3421 | #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ | |
| 3422 | ||
| 3423 | /******************* Bit definition for RCC_AHBRSTR register ***************/ | |
| 3424 | #define RCC_AHBRSTR_GPIOARST_Pos (17U) | |
| 3425 | #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ | |
| 3426 | #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ | |
| 3427 | #define RCC_AHBRSTR_GPIOBRST_Pos (18U) | |
| 3428 | #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ | |
| 3429 | #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ | |
| 3430 | #define RCC_AHBRSTR_GPIOCRST_Pos (19U) | |
| 3431 | #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ | |
| 3432 | #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ | |
| 3433 | #define RCC_AHBRSTR_GPIODRST_Pos (20U) | |
| 3434 | #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ | |
| 3435 | #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ | |
| 3436 | #define RCC_AHBRSTR_GPIOFRST_Pos (22U) | |
| 3437 | #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ | |
| 3438 | #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ | |
| 3439 | ||
| 3440 | /******************* Bit definition for RCC_CFGR2 register *****************/ | |
| 3441 | /*!< PREDIV configuration */ | |
| 3442 | #define RCC_CFGR2_PREDIV_Pos (0U) | |
| 3443 | #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */ | |
| 3444 | #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */ | |
| 3445 | #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */ | |
| 3446 | #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */ | |
| 3447 | #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */ | |
| 3448 | #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */ | |
| 3449 | ||
| 3450 | #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */ | |
| 3451 | #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */ | |
| 3452 | #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */ | |
| 3453 | #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */ | |
| 3454 | #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */ | |
| 3455 | #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */ | |
| 3456 | #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */ | |
| 3457 | #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */ | |
| 3458 | #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */ | |
| 3459 | #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */ | |
| 3460 | #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */ | |
| 3461 | #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */ | |
| 3462 | #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */ | |
| 3463 | #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */ | |
| 3464 | #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */ | |
| 3465 | #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */ | |
| 3466 | ||
| 3467 | /******************* Bit definition for RCC_CFGR3 register *****************/ | |
| 3468 | /*!< USART1 Clock source selection */ | |
| 3469 | #define RCC_CFGR3_USART1SW_Pos (0U) | |
| 3470 | #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */ | |
| 3471 | #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */ | |
| 3472 | #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */ | |
| 3473 | #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */ | |
| 3474 | ||
| 3475 | #define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */ | |
| 3476 | #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */ | |
| 3477 | #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */ | |
| 3478 | #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */ | |
| 3479 | ||
| 3480 | /*!< I2C1 Clock source selection */ | |
| 3481 | #define RCC_CFGR3_I2C1SW_Pos (4U) | |
| 3482 | #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */ | |
| 3483 | #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */ | |
| 3484 | ||
| 3485 | #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */ | |
| 3486 | #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U) | |
| 3487 | #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */ | |
| 3488 | #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */ | |
| 3489 | ||
| 3490 | /*!< USB Clock source selection */ | |
| 3491 | #define RCC_CFGR3_USBSW_Pos (7U) | |
| 3492 | #define RCC_CFGR3_USBSW_Msk (0x1U << RCC_CFGR3_USBSW_Pos) /*!< 0x00000080 */ | |
| 3493 | #define RCC_CFGR3_USBSW RCC_CFGR3_USBSW_Msk /*!< USBSW bits */ | |
| 3494 | ||
| 3495 | #define RCC_CFGR3_USBSW_PLLCLK_Pos (7U) | |
| 3496 | #define RCC_CFGR3_USBSW_PLLCLK_Msk (0x1U << RCC_CFGR3_USBSW_PLLCLK_Pos) /*!< 0x00000080 */ | |
| 3497 | #define RCC_CFGR3_USBSW_PLLCLK RCC_CFGR3_USBSW_PLLCLK_Msk /*!< PLLCLK selected as USB clock source */ | |
| 3498 | ||
| 3499 | /******************* Bit definition for RCC_CR2 register *******************/ | |
| 3500 | #define RCC_CR2_HSI14ON_Pos (0U) | |
| 3501 | #define RCC_CR2_HSI14ON_Msk (0x1U << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */ | |
| 3502 | #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */ | |
| 3503 | #define RCC_CR2_HSI14RDY_Pos (1U) | |
| 3504 | #define RCC_CR2_HSI14RDY_Msk (0x1U << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */ | |
| 3505 | #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */ | |
| 3506 | #define RCC_CR2_HSI14DIS_Pos (2U) | |
| 3507 | #define RCC_CR2_HSI14DIS_Msk (0x1U << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */ | |
| 3508 | #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */ | |
| 3509 | #define RCC_CR2_HSI14TRIM_Pos (3U) | |
| 3510 | #define RCC_CR2_HSI14TRIM_Msk (0x1FU << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */ | |
| 3511 | #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */ | |
| 3512 | #define RCC_CR2_HSI14CAL_Pos (8U) | |
| 3513 | #define RCC_CR2_HSI14CAL_Msk (0xFFU << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */ | |
| 3514 | #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */ | |
| 3515 | ||
| 3516 | /*****************************************************************************/ | |
| 3517 | /* */ | |
| 3518 | /* Real-Time Clock (RTC) */ | |
| 3519 | /* */ | |
| 3520 | /*****************************************************************************/ | |
| 3521 | /* | |
| 3522 | * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) | |
| 3523 | */ | |
| 3524 | #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ | |
| 3525 | #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ | |
| 3526 | #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */ | |
| 3527 | ||
| 3528 | /******************** Bits definition for RTC_TR register ******************/ | |
| 3529 | #define RTC_TR_PM_Pos (22U) | |
| 3530 | #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ | |
| 3531 | #define RTC_TR_PM RTC_TR_PM_Msk | |
| 3532 | #define RTC_TR_HT_Pos (20U) | |
| 3533 | #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ | |
| 3534 | #define RTC_TR_HT RTC_TR_HT_Msk | |
| 3535 | #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ | |
| 3536 | #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ | |
| 3537 | #define RTC_TR_HU_Pos (16U) | |
| 3538 | #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ | |
| 3539 | #define RTC_TR_HU RTC_TR_HU_Msk | |
| 3540 | #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ | |
| 3541 | #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ | |
| 3542 | #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ | |
| 3543 | #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ | |
| 3544 | #define RTC_TR_MNT_Pos (12U) | |
| 3545 | #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ | |
| 3546 | #define RTC_TR_MNT RTC_TR_MNT_Msk | |
| 3547 | #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ | |
| 3548 | #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ | |
| 3549 | #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ | |
| 3550 | #define RTC_TR_MNU_Pos (8U) | |
| 3551 | #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ | |
| 3552 | #define RTC_TR_MNU RTC_TR_MNU_Msk | |
| 3553 | #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ | |
| 3554 | #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ | |
| 3555 | #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ | |
| 3556 | #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ | |
| 3557 | #define RTC_TR_ST_Pos (4U) | |
| 3558 | #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ | |
| 3559 | #define RTC_TR_ST RTC_TR_ST_Msk | |
| 3560 | #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ | |
| 3561 | #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ | |
| 3562 | #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ | |
| 3563 | #define RTC_TR_SU_Pos (0U) | |
| 3564 | #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ | |
| 3565 | #define RTC_TR_SU RTC_TR_SU_Msk | |
| 3566 | #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ | |
| 3567 | #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ | |
| 3568 | #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ | |
| 3569 | #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ | |
| 3570 | ||
| 3571 | /******************** Bits definition for RTC_DR register ******************/ | |
| 3572 | #define RTC_DR_YT_Pos (20U) | |
| 3573 | #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ | |
| 3574 | #define RTC_DR_YT RTC_DR_YT_Msk | |
| 3575 | #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ | |
| 3576 | #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ | |
| 3577 | #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ | |
| 3578 | #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ | |
| 3579 | #define RTC_DR_YU_Pos (16U) | |
| 3580 | #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ | |
| 3581 | #define RTC_DR_YU RTC_DR_YU_Msk | |
| 3582 | #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ | |
| 3583 | #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ | |
| 3584 | #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ | |
| 3585 | #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ | |
| 3586 | #define RTC_DR_WDU_Pos (13U) | |
| 3587 | #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ | |
| 3588 | #define RTC_DR_WDU RTC_DR_WDU_Msk | |
| 3589 | #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ | |
| 3590 | #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ | |
| 3591 | #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ | |
| 3592 | #define RTC_DR_MT_Pos (12U) | |
| 3593 | #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ | |
| 3594 | #define RTC_DR_MT RTC_DR_MT_Msk | |
| 3595 | #define RTC_DR_MU_Pos (8U) | |
| 3596 | #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ | |
| 3597 | #define RTC_DR_MU RTC_DR_MU_Msk | |
| 3598 | #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ | |
| 3599 | #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ | |
| 3600 | #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ | |
| 3601 | #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ | |
| 3602 | #define RTC_DR_DT_Pos (4U) | |
| 3603 | #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ | |
| 3604 | #define RTC_DR_DT RTC_DR_DT_Msk | |
| 3605 | #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ | |
| 3606 | #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ | |
| 3607 | #define RTC_DR_DU_Pos (0U) | |
| 3608 | #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ | |
| 3609 | #define RTC_DR_DU RTC_DR_DU_Msk | |
| 3610 | #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ | |
| 3611 | #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ | |
| 3612 | #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ | |
| 3613 | #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ | |
| 3614 | ||
| 3615 | /******************** Bits definition for RTC_CR register ******************/ | |
| 3616 | #define RTC_CR_COE_Pos (23U) | |
| 3617 | #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ | |
| 3618 | #define RTC_CR_COE RTC_CR_COE_Msk | |
| 3619 | #define RTC_CR_OSEL_Pos (21U) | |
| 3620 | #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ | |
| 3621 | #define RTC_CR_OSEL RTC_CR_OSEL_Msk | |
| 3622 | #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ | |
| 3623 | #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ | |
| 3624 | #define RTC_CR_POL_Pos (20U) | |
| 3625 | #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ | |
| 3626 | #define RTC_CR_POL RTC_CR_POL_Msk | |
| 3627 | #define RTC_CR_COSEL_Pos (19U) | |
| 3628 | #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ | |
| 3629 | #define RTC_CR_COSEL RTC_CR_COSEL_Msk | |
| 3630 | #define RTC_CR_BKP_Pos (18U) | |
| 3631 | #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ | |
| 3632 | #define RTC_CR_BKP RTC_CR_BKP_Msk | |
| 3633 | #define RTC_CR_SUB1H_Pos (17U) | |
| 3634 | #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ | |
| 3635 | #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk | |
| 3636 | #define RTC_CR_ADD1H_Pos (16U) | |
| 3637 | #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ | |
| 3638 | #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk | |
| 3639 | #define RTC_CR_TSIE_Pos (15U) | |
| 3640 | #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ | |
| 3641 | #define RTC_CR_TSIE RTC_CR_TSIE_Msk | |
| 3642 | #define RTC_CR_WUTIE_Pos (14U) | |
| 3643 | #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ | |
| 3644 | #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk | |
| 3645 | #define RTC_CR_ALRAIE_Pos (12U) | |
| 3646 | #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ | |
| 3647 | #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk | |
| 3648 | #define RTC_CR_TSE_Pos (11U) | |
| 3649 | #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ | |
| 3650 | #define RTC_CR_TSE RTC_CR_TSE_Msk | |
| 3651 | #define RTC_CR_WUTE_Pos (10U) | |
| 3652 | #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ | |
| 3653 | #define RTC_CR_WUTE RTC_CR_WUTE_Msk | |
| 3654 | #define RTC_CR_ALRAE_Pos (8U) | |
| 3655 | #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ | |
| 3656 | #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk | |
| 3657 | #define RTC_CR_FMT_Pos (6U) | |
| 3658 | #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ | |
| 3659 | #define RTC_CR_FMT RTC_CR_FMT_Msk | |
| 3660 | #define RTC_CR_BYPSHAD_Pos (5U) | |
| 3661 | #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ | |
| 3662 | #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk | |
| 3663 | #define RTC_CR_REFCKON_Pos (4U) | |
| 3664 | #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ | |
| 3665 | #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk | |
| 3666 | #define RTC_CR_TSEDGE_Pos (3U) | |
| 3667 | #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ | |
| 3668 | #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk | |
| 3669 | #define RTC_CR_WUCKSEL_Pos (0U) | |
| 3670 | #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ | |
| 3671 | #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk | |
| 3672 | #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ | |
| 3673 | #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ | |
| 3674 | #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ | |
| 3675 | ||
| 3676 | /* Legacy defines */ | |
| 3677 | #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos | |
| 3678 | #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk | |
| 3679 | #define RTC_CR_BCK RTC_CR_BKP | |
| 3680 | ||
| 3681 | /******************** Bits definition for RTC_ISR register *****************/ | |
| 3682 | #define RTC_ISR_RECALPF_Pos (16U) | |
| 3683 | #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ | |
| 3684 | #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk | |
| 3685 | #define RTC_ISR_TAMP2F_Pos (14U) | |
| 3686 | #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ | |
| 3687 | #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk | |
| 3688 | #define RTC_ISR_TAMP1F_Pos (13U) | |
| 3689 | #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ | |
| 3690 | #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk | |
| 3691 | #define RTC_ISR_TSOVF_Pos (12U) | |
| 3692 | #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ | |
| 3693 | #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk | |
| 3694 | #define RTC_ISR_TSF_Pos (11U) | |
| 3695 | #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ | |
| 3696 | #define RTC_ISR_TSF RTC_ISR_TSF_Msk | |
| 3697 | #define RTC_ISR_WUTF_Pos (10U) | |
| 3698 | #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ | |
| 3699 | #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk | |
| 3700 | #define RTC_ISR_ALRAF_Pos (8U) | |
| 3701 | #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ | |
| 3702 | #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk | |
| 3703 | #define RTC_ISR_INIT_Pos (7U) | |
| 3704 | #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ | |
| 3705 | #define RTC_ISR_INIT RTC_ISR_INIT_Msk | |
| 3706 | #define RTC_ISR_INITF_Pos (6U) | |
| 3707 | #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ | |
| 3708 | #define RTC_ISR_INITF RTC_ISR_INITF_Msk | |
| 3709 | #define RTC_ISR_RSF_Pos (5U) | |
| 3710 | #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ | |
| 3711 | #define RTC_ISR_RSF RTC_ISR_RSF_Msk | |
| 3712 | #define RTC_ISR_INITS_Pos (4U) | |
| 3713 | #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ | |
| 3714 | #define RTC_ISR_INITS RTC_ISR_INITS_Msk | |
| 3715 | #define RTC_ISR_SHPF_Pos (3U) | |
| 3716 | #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ | |
| 3717 | #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk | |
| 3718 | #define RTC_ISR_WUTWF_Pos (2U) | |
| 3719 | #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ | |
| 3720 | #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk | |
| 3721 | #define RTC_ISR_ALRAWF_Pos (0U) | |
| 3722 | #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ | |
| 3723 | #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk | |
| 3724 | ||
| 3725 | /******************** Bits definition for RTC_PRER register ****************/ | |
| 3726 | #define RTC_PRER_PREDIV_A_Pos (16U) | |
| 3727 | #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ | |
| 3728 | #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk | |
| 3729 | #define RTC_PRER_PREDIV_S_Pos (0U) | |
| 3730 | #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ | |
| 3731 | #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk | |
| 3732 | ||
| 3733 | /******************** Bits definition for RTC_WUTR register ****************/ | |
| 3734 | #define RTC_WUTR_WUT_Pos (0U) | |
| 3735 | #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ | |
| 3736 | #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk | |
| 3737 | ||
| 3738 | /******************** Bits definition for RTC_ALRMAR register **************/ | |
| 3739 | #define RTC_ALRMAR_MSK4_Pos (31U) | |
| 3740 | #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ | |
| 3741 | #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk | |
| 3742 | #define RTC_ALRMAR_WDSEL_Pos (30U) | |
| 3743 | #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ | |
| 3744 | #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk | |
| 3745 | #define RTC_ALRMAR_DT_Pos (28U) | |
| 3746 | #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ | |
| 3747 | #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk | |
| 3748 | #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ | |
| 3749 | #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ | |
| 3750 | #define RTC_ALRMAR_DU_Pos (24U) | |
| 3751 | #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ | |
| 3752 | #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk | |
| 3753 | #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ | |
| 3754 | #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ | |
| 3755 | #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ | |
| 3756 | #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ | |
| 3757 | #define RTC_ALRMAR_MSK3_Pos (23U) | |
| 3758 | #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ | |
| 3759 | #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk | |
| 3760 | #define RTC_ALRMAR_PM_Pos (22U) | |
| 3761 | #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ | |
| 3762 | #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk | |
| 3763 | #define RTC_ALRMAR_HT_Pos (20U) | |
| 3764 | #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ | |
| 3765 | #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk | |
| 3766 | #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ | |
| 3767 | #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ | |
| 3768 | #define RTC_ALRMAR_HU_Pos (16U) | |
| 3769 | #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ | |
| 3770 | #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk | |
| 3771 | #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ | |
| 3772 | #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ | |
| 3773 | #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ | |
| 3774 | #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ | |
| 3775 | #define RTC_ALRMAR_MSK2_Pos (15U) | |
| 3776 | #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ | |
| 3777 | #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk | |
| 3778 | #define RTC_ALRMAR_MNT_Pos (12U) | |
| 3779 | #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ | |
| 3780 | #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk | |
| 3781 | #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ | |
| 3782 | #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ | |
| 3783 | #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ | |
| 3784 | #define RTC_ALRMAR_MNU_Pos (8U) | |
| 3785 | #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ | |
| 3786 | #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk | |
| 3787 | #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ | |
| 3788 | #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ | |
| 3789 | #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ | |
| 3790 | #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ | |
| 3791 | #define RTC_ALRMAR_MSK1_Pos (7U) | |
| 3792 | #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ | |
| 3793 | #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk | |
| 3794 | #define RTC_ALRMAR_ST_Pos (4U) | |
| 3795 | #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ | |
| 3796 | #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk | |
| 3797 | #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ | |
| 3798 | #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ | |
| 3799 | #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ | |
| 3800 | #define RTC_ALRMAR_SU_Pos (0U) | |
| 3801 | #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ | |
| 3802 | #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk | |
| 3803 | #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ | |
| 3804 | #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ | |
| 3805 | #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ | |
| 3806 | #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ | |
| 3807 | ||
| 3808 | /******************** Bits definition for RTC_WPR register *****************/ | |
| 3809 | #define RTC_WPR_KEY_Pos (0U) | |
| 3810 | #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ | |
| 3811 | #define RTC_WPR_KEY RTC_WPR_KEY_Msk | |
| 3812 | ||
| 3813 | /******************** Bits definition for RTC_SSR register *****************/ | |
| 3814 | #define RTC_SSR_SS_Pos (0U) | |
| 3815 | #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ | |
| 3816 | #define RTC_SSR_SS RTC_SSR_SS_Msk | |
| 3817 | ||
| 3818 | /******************** Bits definition for RTC_SHIFTR register **************/ | |
| 3819 | #define RTC_SHIFTR_SUBFS_Pos (0U) | |
| 3820 | #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ | |
| 3821 | #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk | |
| 3822 | #define RTC_SHIFTR_ADD1S_Pos (31U) | |
| 3823 | #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ | |
| 3824 | #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk | |
| 3825 | ||
| 3826 | /******************** Bits definition for RTC_TSTR register ****************/ | |
| 3827 | #define RTC_TSTR_PM_Pos (22U) | |
| 3828 | #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ | |
| 3829 | #define RTC_TSTR_PM RTC_TSTR_PM_Msk | |
| 3830 | #define RTC_TSTR_HT_Pos (20U) | |
| 3831 | #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ | |
| 3832 | #define RTC_TSTR_HT RTC_TSTR_HT_Msk | |
| 3833 | #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ | |
| 3834 | #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ | |
| 3835 | #define RTC_TSTR_HU_Pos (16U) | |
| 3836 | #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ | |
| 3837 | #define RTC_TSTR_HU RTC_TSTR_HU_Msk | |
| 3838 | #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ | |
| 3839 | #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ | |
| 3840 | #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ | |
| 3841 | #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ | |
| 3842 | #define RTC_TSTR_MNT_Pos (12U) | |
| 3843 | #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ | |
| 3844 | #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk | |
| 3845 | #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ | |
| 3846 | #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ | |
| 3847 | #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ | |
| 3848 | #define RTC_TSTR_MNU_Pos (8U) | |
| 3849 | #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ | |
| 3850 | #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk | |
| 3851 | #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ | |
| 3852 | #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ | |
| 3853 | #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ | |
| 3854 | #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ | |
| 3855 | #define RTC_TSTR_ST_Pos (4U) | |
| 3856 | #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ | |
| 3857 | #define RTC_TSTR_ST RTC_TSTR_ST_Msk | |
| 3858 | #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ | |
| 3859 | #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ | |
| 3860 | #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ | |
| 3861 | #define RTC_TSTR_SU_Pos (0U) | |
| 3862 | #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ | |
| 3863 | #define RTC_TSTR_SU RTC_TSTR_SU_Msk | |
| 3864 | #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ | |
| 3865 | #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ | |
| 3866 | #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ | |
| 3867 | #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ | |
| 3868 | ||
| 3869 | /******************** Bits definition for RTC_TSDR register ****************/ | |
| 3870 | #define RTC_TSDR_WDU_Pos (13U) | |
| 3871 | #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ | |
| 3872 | #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk | |
| 3873 | #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ | |
| 3874 | #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ | |
| 3875 | #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ | |
| 3876 | #define RTC_TSDR_MT_Pos (12U) | |
| 3877 | #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ | |
| 3878 | #define RTC_TSDR_MT RTC_TSDR_MT_Msk | |
| 3879 | #define RTC_TSDR_MU_Pos (8U) | |
| 3880 | #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ | |
| 3881 | #define RTC_TSDR_MU RTC_TSDR_MU_Msk | |
| 3882 | #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ | |
| 3883 | #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ | |
| 3884 | #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ | |
| 3885 | #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ | |
| 3886 | #define RTC_TSDR_DT_Pos (4U) | |
| 3887 | #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ | |
| 3888 | #define RTC_TSDR_DT RTC_TSDR_DT_Msk | |
| 3889 | #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ | |
| 3890 | #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ | |
| 3891 | #define RTC_TSDR_DU_Pos (0U) | |
| 3892 | #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ | |
| 3893 | #define RTC_TSDR_DU RTC_TSDR_DU_Msk | |
| 3894 | #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ | |
| 3895 | #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ | |
| 3896 | #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ | |
| 3897 | #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ | |
| 3898 | ||
| 3899 | /******************** Bits definition for RTC_TSSSR register ***************/ | |
| 3900 | #define RTC_TSSSR_SS_Pos (0U) | |
| 3901 | #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ | |
| 3902 | #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk | |
| 3903 | ||
| 3904 | /******************** Bits definition for RTC_CALR register ****************/ | |
| 3905 | #define RTC_CALR_CALP_Pos (15U) | |
| 3906 | #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ | |
| 3907 | #define RTC_CALR_CALP RTC_CALR_CALP_Msk | |
| 3908 | #define RTC_CALR_CALW8_Pos (14U) | |
| 3909 | #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ | |
| 3910 | #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk | |
| 3911 | #define RTC_CALR_CALW16_Pos (13U) | |
| 3912 | #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ | |
| 3913 | #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk | |
| 3914 | #define RTC_CALR_CALM_Pos (0U) | |
| 3915 | #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ | |
| 3916 | #define RTC_CALR_CALM RTC_CALR_CALM_Msk | |
| 3917 | #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ | |
| 3918 | #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ | |
| 3919 | #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ | |
| 3920 | #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ | |
| 3921 | #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ | |
| 3922 | #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ | |
| 3923 | #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ | |
| 3924 | #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ | |
| 3925 | #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ | |
| 3926 | ||
| 3927 | /******************** Bits definition for RTC_TAFCR register ***************/ | |
| 3928 | #define RTC_TAFCR_PC15MODE_Pos (23U) | |
| 3929 | #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ | |
| 3930 | #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk | |
| 3931 | #define RTC_TAFCR_PC15VALUE_Pos (22U) | |
| 3932 | #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ | |
| 3933 | #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk | |
| 3934 | #define RTC_TAFCR_PC14MODE_Pos (21U) | |
| 3935 | #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ | |
| 3936 | #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk | |
| 3937 | #define RTC_TAFCR_PC14VALUE_Pos (20U) | |
| 3938 | #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ | |
| 3939 | #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk | |
| 3940 | #define RTC_TAFCR_PC13MODE_Pos (19U) | |
| 3941 | #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ | |
| 3942 | #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk | |
| 3943 | #define RTC_TAFCR_PC13VALUE_Pos (18U) | |
| 3944 | #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ | |
| 3945 | #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk | |
| 3946 | #define RTC_TAFCR_TAMPPUDIS_Pos (15U) | |
| 3947 | #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ | |
| 3948 | #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk | |
| 3949 | #define RTC_TAFCR_TAMPPRCH_Pos (13U) | |
| 3950 | #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ | |
| 3951 | #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk | |
| 3952 | #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ | |
| 3953 | #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ | |
| 3954 | #define RTC_TAFCR_TAMPFLT_Pos (11U) | |
| 3955 | #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ | |
| 3956 | #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk | |
| 3957 | #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ | |
| 3958 | #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ | |
| 3959 | #define RTC_TAFCR_TAMPFREQ_Pos (8U) | |
| 3960 | #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ | |
| 3961 | #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk | |
| 3962 | #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ | |
| 3963 | #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ | |
| 3964 | #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ | |
| 3965 | #define RTC_TAFCR_TAMPTS_Pos (7U) | |
| 3966 | #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ | |
| 3967 | #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk | |
| 3968 | #define RTC_TAFCR_TAMP2TRG_Pos (4U) | |
| 3969 | #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ | |
| 3970 | #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk | |
| 3971 | #define RTC_TAFCR_TAMP2E_Pos (3U) | |
| 3972 | #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ | |
| 3973 | #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk | |
| 3974 | #define RTC_TAFCR_TAMPIE_Pos (2U) | |
| 3975 | #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ | |
| 3976 | #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk | |
| 3977 | #define RTC_TAFCR_TAMP1TRG_Pos (1U) | |
| 3978 | #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ | |
| 3979 | #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk | |
| 3980 | #define RTC_TAFCR_TAMP1E_Pos (0U) | |
| 3981 | #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ | |
| 3982 | #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk | |
| 3983 | ||
| 3984 | /* Reference defines */ | |
| 3985 | #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE | |
| 3986 | ||
| 3987 | /******************** Bits definition for RTC_ALRMASSR register ************/ | |
| 3988 | #define RTC_ALRMASSR_MASKSS_Pos (24U) | |
| 3989 | #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ | |
| 3990 | #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk | |
| 3991 | #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ | |
| 3992 | #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ | |
| 3993 | #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ | |
| 3994 | #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ | |
| 3995 | #define RTC_ALRMASSR_SS_Pos (0U) | |
| 3996 | #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ | |
| 3997 | #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk | |
| 3998 | ||
| 3999 | /*****************************************************************************/ | |
| 4000 | /* */ | |
| 4001 | /* Serial Peripheral Interface (SPI) */ | |
| 4002 | /* */ | |
| 4003 | /*****************************************************************************/ | |
| 4004 | ||
| 4005 | /* | |
| 4006 | * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) | |
| 4007 | */ | |
| 4008 | /* Note: No specific macro feature on this device */ | |
| 4009 | ||
| 4010 | /******************* Bit definition for SPI_CR1 register *******************/ | |
| 4011 | #define SPI_CR1_CPHA_Pos (0U) | |
| 4012 | #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ | |
| 4013 | #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ | |
| 4014 | #define SPI_CR1_CPOL_Pos (1U) | |
| 4015 | #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ | |
| 4016 | #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ | |
| 4017 | #define SPI_CR1_MSTR_Pos (2U) | |
| 4018 | #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ | |
| 4019 | #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ | |
| 4020 | #define SPI_CR1_BR_Pos (3U) | |
| 4021 | #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ | |
| 4022 | #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ | |
| 4023 | #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ | |
| 4024 | #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ | |
| 4025 | #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ | |
| 4026 | #define SPI_CR1_SPE_Pos (6U) | |
| 4027 | #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ | |
| 4028 | #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ | |
| 4029 | #define SPI_CR1_LSBFIRST_Pos (7U) | |
| 4030 | #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ | |
| 4031 | #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ | |
| 4032 | #define SPI_CR1_SSI_Pos (8U) | |
| 4033 | #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ | |
| 4034 | #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ | |
| 4035 | #define SPI_CR1_SSM_Pos (9U) | |
| 4036 | #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ | |
| 4037 | #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ | |
| 4038 | #define SPI_CR1_RXONLY_Pos (10U) | |
| 4039 | #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ | |
| 4040 | #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ | |
| 4041 | #define SPI_CR1_CRCL_Pos (11U) | |
| 4042 | #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ | |
| 4043 | #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ | |
| 4044 | #define SPI_CR1_CRCNEXT_Pos (12U) | |
| 4045 | #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ | |
| 4046 | #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ | |
| 4047 | #define SPI_CR1_CRCEN_Pos (13U) | |
| 4048 | #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ | |
| 4049 | #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ | |
| 4050 | #define SPI_CR1_BIDIOE_Pos (14U) | |
| 4051 | #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ | |
| 4052 | #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ | |
| 4053 | #define SPI_CR1_BIDIMODE_Pos (15U) | |
| 4054 | #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ | |
| 4055 | #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ | |
| 4056 | ||
| 4057 | /******************* Bit definition for SPI_CR2 register *******************/ | |
| 4058 | #define SPI_CR2_RXDMAEN_Pos (0U) | |
| 4059 | #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ | |
| 4060 | #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ | |
| 4061 | #define SPI_CR2_TXDMAEN_Pos (1U) | |
| 4062 | #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ | |
| 4063 | #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ | |
| 4064 | #define SPI_CR2_SSOE_Pos (2U) | |
| 4065 | #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ | |
| 4066 | #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ | |
| 4067 | #define SPI_CR2_NSSP_Pos (3U) | |
| 4068 | #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ | |
| 4069 | #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ | |
| 4070 | #define SPI_CR2_FRF_Pos (4U) | |
| 4071 | #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ | |
| 4072 | #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ | |
| 4073 | #define SPI_CR2_ERRIE_Pos (5U) | |
| 4074 | #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ | |
| 4075 | #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ | |
| 4076 | #define SPI_CR2_RXNEIE_Pos (6U) | |
| 4077 | #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ | |
| 4078 | #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ | |
| 4079 | #define SPI_CR2_TXEIE_Pos (7U) | |
| 4080 | #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ | |
| 4081 | #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ | |
| 4082 | #define SPI_CR2_DS_Pos (8U) | |
| 4083 | #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ | |
| 4084 | #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ | |
| 4085 | #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */ | |
| 4086 | #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */ | |
| 4087 | #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */ | |
| 4088 | #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */ | |
| 4089 | #define SPI_CR2_FRXTH_Pos (12U) | |
| 4090 | #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ | |
| 4091 | #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ | |
| 4092 | #define SPI_CR2_LDMARX_Pos (13U) | |
| 4093 | #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ | |
| 4094 | #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ | |
| 4095 | #define SPI_CR2_LDMATX_Pos (14U) | |
| 4096 | #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ | |
| 4097 | #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ | |
| 4098 | ||
| 4099 | /******************** Bit definition for SPI_SR register *******************/ | |
| 4100 | #define SPI_SR_RXNE_Pos (0U) | |
| 4101 | #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ | |
| 4102 | #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ | |
| 4103 | #define SPI_SR_TXE_Pos (1U) | |
| 4104 | #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ | |
| 4105 | #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ | |
| 4106 | #define SPI_SR_CRCERR_Pos (4U) | |
| 4107 | #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ | |
| 4108 | #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ | |
| 4109 | #define SPI_SR_MODF_Pos (5U) | |
| 4110 | #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ | |
| 4111 | #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ | |
| 4112 | #define SPI_SR_OVR_Pos (6U) | |
| 4113 | #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ | |
| 4114 | #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ | |
| 4115 | #define SPI_SR_BSY_Pos (7U) | |
| 4116 | #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ | |
| 4117 | #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ | |
| 4118 | #define SPI_SR_FRE_Pos (8U) | |
| 4119 | #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ | |
| 4120 | #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ | |
| 4121 | #define SPI_SR_FRLVL_Pos (9U) | |
| 4122 | #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ | |
| 4123 | #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ | |
| 4124 | #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ | |
| 4125 | #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ | |
| 4126 | #define SPI_SR_FTLVL_Pos (11U) | |
| 4127 | #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ | |
| 4128 | #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ | |
| 4129 | #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ | |
| 4130 | #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ | |
| 4131 | ||
| 4132 | /******************** Bit definition for SPI_DR register *******************/ | |
| 4133 | #define SPI_DR_DR_Pos (0U) | |
| 4134 | #define SPI_DR_DR_Msk (0xFFFFFFFFU << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ | |
| 4135 | #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ | |
| 4136 | ||
| 4137 | /******************* Bit definition for SPI_CRCPR register *****************/ | |
| 4138 | #define SPI_CRCPR_CRCPOLY_Pos (0U) | |
| 4139 | #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */ | |
| 4140 | #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ | |
| 4141 | ||
| 4142 | /****************** Bit definition for SPI_RXCRCR register *****************/ | |
| 4143 | #define SPI_RXCRCR_RXCRC_Pos (0U) | |
| 4144 | #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */ | |
| 4145 | #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ | |
| 4146 | ||
| 4147 | /****************** Bit definition for SPI_TXCRCR register *****************/ | |
| 4148 | #define SPI_TXCRCR_TXCRC_Pos (0U) | |
| 4149 | #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */ | |
| 4150 | #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ | |
| 4151 | ||
| 4152 | /****************** Bit definition for SPI_I2SCFGR register ****************/ | |
| 4153 | #define SPI_I2SCFGR_I2SMOD_Pos (11U) | |
| 4154 | #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ | |
| 4155 | #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< Keep for compatibility */ | |
| 4156 | ||
| 4157 | /*****************************************************************************/ | |
| 4158 | /* */ | |
| 4159 | /* System Configuration (SYSCFG) */ | |
| 4160 | /* */ | |
| 4161 | /*****************************************************************************/ | |
| 4162 | /***************** Bit definition for SYSCFG_CFGR1 register ****************/ | |
| 4163 | #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) | |
| 4164 | #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ | |
| 4165 | #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ | |
| 4166 | #define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ | |
| 4167 | #define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ | |
| 4168 | ||
| 4169 | #define SYSCFG_CFGR1_DMA_RMP_Pos (8U) | |
| 4170 | #define SYSCFG_CFGR1_DMA_RMP_Msk (0x4001FU << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x04001F00 */ | |
| 4171 | #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */ | |
| 4172 | #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U) | |
| 4173 | #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */ | |
| 4174 | #define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk /*!< ADC DMA remap */ | |
| 4175 | #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U) | |
| 4176 | #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */ | |
| 4177 | #define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */ | |
| 4178 | #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U) | |
| 4179 | #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */ | |
| 4180 | #define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */ | |
| 4181 | #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U) | |
| 4182 | #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */ | |
| 4183 | #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */ | |
| 4184 | #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U) | |
| 4185 | #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */ | |
| 4186 | #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */ | |
| 4187 | #define SYSCFG_CFGR1_USART3_DMA_RMP_Pos (26U) | |
| 4188 | #define SYSCFG_CFGR1_USART3_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART3_DMA_RMP_Pos) /*!< 0x04000000 */ | |
| 4189 | #define SYSCFG_CFGR1_USART3_DMA_RMP SYSCFG_CFGR1_USART3_DMA_RMP_Msk /*!< USART3 DMA remap */ | |
| 4190 | ||
| 4191 | #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U) | |
| 4192 | #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */ | |
| 4193 | #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */ | |
| 4194 | #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U) | |
| 4195 | #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */ | |
| 4196 | #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */ | |
| 4197 | #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U) | |
| 4198 | #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */ | |
| 4199 | #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */ | |
| 4200 | #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U) | |
| 4201 | #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */ | |
| 4202 | #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */ | |
| 4203 | #define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos (20U) | |
| 4204 | #define SYSCFG_CFGR1_I2C_FMP_I2C1_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_I2C1_Pos) /*!< 0x00100000 */ | |
| 4205 | #define SYSCFG_CFGR1_I2C_FMP_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ | |
| 4206 | ||
| 4207 | /***************** Bit definition for SYSCFG_EXTICR1 register **************/ | |
| 4208 | #define SYSCFG_EXTICR1_EXTI0_Pos (0U) | |
| 4209 | #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ | |
| 4210 | #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ | |
| 4211 | #define SYSCFG_EXTICR1_EXTI1_Pos (4U) | |
| 4212 | #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ | |
| 4213 | #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ | |
| 4214 | #define SYSCFG_EXTICR1_EXTI2_Pos (8U) | |
| 4215 | #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ | |
| 4216 | #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ | |
| 4217 | #define SYSCFG_EXTICR1_EXTI3_Pos (12U) | |
| 4218 | #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ | |
| 4219 | #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ | |
| 4220 | ||
| 4221 | /** | |
| 4222 | * @brief EXTI0 configuration | |
| 4223 | */ | |
| 4224 | #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ | |
| 4225 | #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ | |
| 4226 | #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ | |
| 4227 | #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ | |
| 4228 | #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */ | |
| 4229 | ||
| 4230 | /** | |
| 4231 | * @brief EXTI1 configuration | |
| 4232 | */ | |
| 4233 | #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ | |
| 4234 | #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ | |
| 4235 | #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ | |
| 4236 | #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ | |
| 4237 | #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */ | |
| 4238 | ||
| 4239 | /** | |
| 4240 | * @brief EXTI2 configuration | |
| 4241 | */ | |
| 4242 | #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ | |
| 4243 | #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ | |
| 4244 | #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ | |
| 4245 | #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ | |
| 4246 | #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */ | |
| 4247 | ||
| 4248 | /** | |
| 4249 | * @brief EXTI3 configuration | |
| 4250 | */ | |
| 4251 | #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ | |
| 4252 | #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ | |
| 4253 | #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ | |
| 4254 | #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ | |
| 4255 | #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */ | |
| 4256 | ||
| 4257 | /***************** Bit definition for SYSCFG_EXTICR2 register **************/ | |
| 4258 | #define SYSCFG_EXTICR2_EXTI4_Pos (0U) | |
| 4259 | #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ | |
| 4260 | #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ | |
| 4261 | #define SYSCFG_EXTICR2_EXTI5_Pos (4U) | |
| 4262 | #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ | |
| 4263 | #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ | |
| 4264 | #define SYSCFG_EXTICR2_EXTI6_Pos (8U) | |
| 4265 | #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ | |
| 4266 | #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ | |
| 4267 | #define SYSCFG_EXTICR2_EXTI7_Pos (12U) | |
| 4268 | #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ | |
| 4269 | #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ | |
| 4270 | ||
| 4271 | /** | |
| 4272 | * @brief EXTI4 configuration | |
| 4273 | */ | |
| 4274 | #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ | |
| 4275 | #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ | |
| 4276 | #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ | |
| 4277 | #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ | |
| 4278 | #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */ | |
| 4279 | ||
| 4280 | /** | |
| 4281 | * @brief EXTI5 configuration | |
| 4282 | */ | |
| 4283 | #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ | |
| 4284 | #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ | |
| 4285 | #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ | |
| 4286 | #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ | |
| 4287 | #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */ | |
| 4288 | ||
| 4289 | /** | |
| 4290 | * @brief EXTI6 configuration | |
| 4291 | */ | |
| 4292 | #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ | |
| 4293 | #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ | |
| 4294 | #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ | |
| 4295 | #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ | |
| 4296 | #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */ | |
| 4297 | ||
| 4298 | /** | |
| 4299 | * @brief EXTI7 configuration | |
| 4300 | */ | |
| 4301 | #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ | |
| 4302 | #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ | |
| 4303 | #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ | |
| 4304 | #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ | |
| 4305 | #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */ | |
| 4306 | ||
| 4307 | /***************** Bit definition for SYSCFG_EXTICR3 register **************/ | |
| 4308 | #define SYSCFG_EXTICR3_EXTI8_Pos (0U) | |
| 4309 | #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ | |
| 4310 | #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ | |
| 4311 | #define SYSCFG_EXTICR3_EXTI9_Pos (4U) | |
| 4312 | #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ | |
| 4313 | #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ | |
| 4314 | #define SYSCFG_EXTICR3_EXTI10_Pos (8U) | |
| 4315 | #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ | |
| 4316 | #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ | |
| 4317 | #define SYSCFG_EXTICR3_EXTI11_Pos (12U) | |
| 4318 | #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ | |
| 4319 | #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ | |
| 4320 | ||
| 4321 | /** | |
| 4322 | * @brief EXTI8 configuration | |
| 4323 | */ | |
| 4324 | #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ | |
| 4325 | #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ | |
| 4326 | #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ | |
| 4327 | #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ | |
| 4328 | #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!< PF[8] pin */ | |
| 4329 | ||
| 4330 | ||
| 4331 | /** | |
| 4332 | * @brief EXTI9 configuration | |
| 4333 | */ | |
| 4334 | #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ | |
| 4335 | #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ | |
| 4336 | #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ | |
| 4337 | #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ | |
| 4338 | #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */ | |
| 4339 | ||
| 4340 | /** | |
| 4341 | * @brief EXTI10 configuration | |
| 4342 | */ | |
| 4343 | #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ | |
| 4344 | #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ | |
| 4345 | #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ | |
| 4346 | #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ | |
| 4347 | #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */ | |
| 4348 | ||
| 4349 | /** | |
| 4350 | * @brief EXTI11 configuration | |
| 4351 | */ | |
| 4352 | #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ | |
| 4353 | #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ | |
| 4354 | #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ | |
| 4355 | #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ | |
| 4356 | #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!< PF[11] pin */ | |
| 4357 | ||
| 4358 | /***************** Bit definition for SYSCFG_EXTICR4 register **************/ | |
| 4359 | #define SYSCFG_EXTICR4_EXTI12_Pos (0U) | |
| 4360 | #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ | |
| 4361 | #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ | |
| 4362 | #define SYSCFG_EXTICR4_EXTI13_Pos (4U) | |
| 4363 | #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ | |
| 4364 | #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ | |
| 4365 | #define SYSCFG_EXTICR4_EXTI14_Pos (8U) | |
| 4366 | #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ | |
| 4367 | #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ | |
| 4368 | #define SYSCFG_EXTICR4_EXTI15_Pos (12U) | |
| 4369 | #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ | |
| 4370 | #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ | |
| 4371 | ||
| 4372 | /** | |
| 4373 | * @brief EXTI12 configuration | |
| 4374 | */ | |
| 4375 | #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ | |
| 4376 | #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ | |
| 4377 | #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ | |
| 4378 | #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ | |
| 4379 | #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!< PF[12] pin */ | |
| 4380 | ||
| 4381 | /** | |
| 4382 | * @brief EXTI13 configuration | |
| 4383 | */ | |
| 4384 | #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ | |
| 4385 | #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ | |
| 4386 | #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ | |
| 4387 | #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ | |
| 4388 | #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!< PF[13] pin */ | |
| 4389 | ||
| 4390 | /** | |
| 4391 | * @brief EXTI14 configuration | |
| 4392 | */ | |
| 4393 | #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ | |
| 4394 | #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ | |
| 4395 | #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ | |
| 4396 | #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ | |
| 4397 | #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!< PF[14] pin */ | |
| 4398 | ||
| 4399 | /** | |
| 4400 | * @brief EXTI15 configuration | |
| 4401 | */ | |
| 4402 | #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ | |
| 4403 | #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ | |
| 4404 | #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ | |
| 4405 | #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ | |
| 4406 | #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!< PF[15] pin */ | |
| 4407 | ||
| 4408 | /***************** Bit definition for SYSCFG_CFGR2 register ****************/ | |
| 4409 | #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) | |
| 4410 | #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ | |
| 4411 | #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */ | |
| 4412 | #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U) | |
| 4413 | #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */ | |
| 4414 | #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */ | |
| 4415 | #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U) | |
| 4416 | #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1U << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */ | |
| 4417 | #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */ | |
| 4418 | #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */ | |
| 4419 | ||
| 4420 | /*****************************************************************************/ | |
| 4421 | /* */ | |
| 4422 | /* Timers (TIM) */ | |
| 4423 | /* */ | |
| 4424 | /*****************************************************************************/ | |
| 4425 | /******************* Bit definition for TIM_CR1 register *******************/ | |
| 4426 | #define TIM_CR1_CEN_Pos (0U) | |
| 4427 | #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ | |
| 4428 | #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ | |
| 4429 | #define TIM_CR1_UDIS_Pos (1U) | |
| 4430 | #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ | |
| 4431 | #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ | |
| 4432 | #define TIM_CR1_URS_Pos (2U) | |
| 4433 | #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ | |
| 4434 | #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ | |
| 4435 | #define TIM_CR1_OPM_Pos (3U) | |
| 4436 | #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ | |
| 4437 | #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ | |
| 4438 | #define TIM_CR1_DIR_Pos (4U) | |
| 4439 | #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ | |
| 4440 | #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ | |
| 4441 | ||
| 4442 | #define TIM_CR1_CMS_Pos (5U) | |
| 4443 | #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ | |
| 4444 | #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ | |
| 4445 | #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ | |
| 4446 | #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ | |
| 4447 | ||
| 4448 | #define TIM_CR1_ARPE_Pos (7U) | |
| 4449 | #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ | |
| 4450 | #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ | |
| 4451 | ||
| 4452 | #define TIM_CR1_CKD_Pos (8U) | |
| 4453 | #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ | |
| 4454 | #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ | |
| 4455 | #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ | |
| 4456 | #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ | |
| 4457 | ||
| 4458 | /******************* Bit definition for TIM_CR2 register *******************/ | |
| 4459 | #define TIM_CR2_CCPC_Pos (0U) | |
| 4460 | #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ | |
| 4461 | #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ | |
| 4462 | #define TIM_CR2_CCUS_Pos (2U) | |
| 4463 | #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ | |
| 4464 | #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ | |
| 4465 | #define TIM_CR2_CCDS_Pos (3U) | |
| 4466 | #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ | |
| 4467 | #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ | |
| 4468 | ||
| 4469 | #define TIM_CR2_MMS_Pos (4U) | |
| 4470 | #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ | |
| 4471 | #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ | |
| 4472 | #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ | |
| 4473 | #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ | |
| 4474 | #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ | |
| 4475 | ||
| 4476 | #define TIM_CR2_TI1S_Pos (7U) | |
| 4477 | #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ | |
| 4478 | #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ | |
| 4479 | #define TIM_CR2_OIS1_Pos (8U) | |
| 4480 | #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ | |
| 4481 | #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ | |
| 4482 | #define TIM_CR2_OIS1N_Pos (9U) | |
| 4483 | #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ | |
| 4484 | #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ | |
| 4485 | #define TIM_CR2_OIS2_Pos (10U) | |
| 4486 | #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ | |
| 4487 | #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ | |
| 4488 | #define TIM_CR2_OIS2N_Pos (11U) | |
| 4489 | #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ | |
| 4490 | #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ | |
| 4491 | #define TIM_CR2_OIS3_Pos (12U) | |
| 4492 | #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ | |
| 4493 | #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ | |
| 4494 | #define TIM_CR2_OIS3N_Pos (13U) | |
| 4495 | #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ | |
| 4496 | #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ | |
| 4497 | #define TIM_CR2_OIS4_Pos (14U) | |
| 4498 | #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ | |
| 4499 | #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ | |
| 4500 | ||
| 4501 | /******************* Bit definition for TIM_SMCR register ******************/ | |
| 4502 | #define TIM_SMCR_SMS_Pos (0U) | |
| 4503 | #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ | |
| 4504 | #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ | |
| 4505 | #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ | |
| 4506 | #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ | |
| 4507 | #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ | |
| 4508 | ||
| 4509 | #define TIM_SMCR_OCCS_Pos (3U) | |
| 4510 | #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ | |
| 4511 | #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ | |
| 4512 | ||
| 4513 | #define TIM_SMCR_TS_Pos (4U) | |
| 4514 | #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ | |
| 4515 | #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ | |
| 4516 | #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ | |
| 4517 | #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ | |
| 4518 | #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ | |
| 4519 | ||
| 4520 | #define TIM_SMCR_MSM_Pos (7U) | |
| 4521 | #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ | |
| 4522 | #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ | |
| 4523 | ||
| 4524 | #define TIM_SMCR_ETF_Pos (8U) | |
| 4525 | #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ | |
| 4526 | #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ | |
| 4527 | #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ | |
| 4528 | #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ | |
| 4529 | #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ | |
| 4530 | #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ | |
| 4531 | ||
| 4532 | #define TIM_SMCR_ETPS_Pos (12U) | |
| 4533 | #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ | |
| 4534 | #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ | |
| 4535 | #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ | |
| 4536 | #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ | |
| 4537 | ||
| 4538 | #define TIM_SMCR_ECE_Pos (14U) | |
| 4539 | #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ | |
| 4540 | #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ | |
| 4541 | #define TIM_SMCR_ETP_Pos (15U) | |
| 4542 | #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ | |
| 4543 | #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ | |
| 4544 | ||
| 4545 | /******************* Bit definition for TIM_DIER register ******************/ | |
| 4546 | #define TIM_DIER_UIE_Pos (0U) | |
| 4547 | #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ | |
| 4548 | #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ | |
| 4549 | #define TIM_DIER_CC1IE_Pos (1U) | |
| 4550 | #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ | |
| 4551 | #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ | |
| 4552 | #define TIM_DIER_CC2IE_Pos (2U) | |
| 4553 | #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ | |
| 4554 | #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ | |
| 4555 | #define TIM_DIER_CC3IE_Pos (3U) | |
| 4556 | #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ | |
| 4557 | #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ | |
| 4558 | #define TIM_DIER_CC4IE_Pos (4U) | |
| 4559 | #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ | |
| 4560 | #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ | |
| 4561 | #define TIM_DIER_COMIE_Pos (5U) | |
| 4562 | #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ | |
| 4563 | #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ | |
| 4564 | #define TIM_DIER_TIE_Pos (6U) | |
| 4565 | #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ | |
| 4566 | #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ | |
| 4567 | #define TIM_DIER_BIE_Pos (7U) | |
| 4568 | #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ | |
| 4569 | #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ | |
| 4570 | #define TIM_DIER_UDE_Pos (8U) | |
| 4571 | #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ | |
| 4572 | #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ | |
| 4573 | #define TIM_DIER_CC1DE_Pos (9U) | |
| 4574 | #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ | |
| 4575 | #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ | |
| 4576 | #define TIM_DIER_CC2DE_Pos (10U) | |
| 4577 | #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ | |
| 4578 | #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ | |
| 4579 | #define TIM_DIER_CC3DE_Pos (11U) | |
| 4580 | #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ | |
| 4581 | #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ | |
| 4582 | #define TIM_DIER_CC4DE_Pos (12U) | |
| 4583 | #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ | |
| 4584 | #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ | |
| 4585 | #define TIM_DIER_COMDE_Pos (13U) | |
| 4586 | #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ | |
| 4587 | #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ | |
| 4588 | #define TIM_DIER_TDE_Pos (14U) | |
| 4589 | #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ | |
| 4590 | #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ | |
| 4591 | ||
| 4592 | /******************** Bit definition for TIM_SR register *******************/ | |
| 4593 | #define TIM_SR_UIF_Pos (0U) | |
| 4594 | #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ | |
| 4595 | #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ | |
| 4596 | #define TIM_SR_CC1IF_Pos (1U) | |
| 4597 | #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ | |
| 4598 | #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ | |
| 4599 | #define TIM_SR_CC2IF_Pos (2U) | |
| 4600 | #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ | |
| 4601 | #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ | |
| 4602 | #define TIM_SR_CC3IF_Pos (3U) | |
| 4603 | #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ | |
| 4604 | #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ | |
| 4605 | #define TIM_SR_CC4IF_Pos (4U) | |
| 4606 | #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ | |
| 4607 | #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ | |
| 4608 | #define TIM_SR_COMIF_Pos (5U) | |
| 4609 | #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ | |
| 4610 | #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ | |
| 4611 | #define TIM_SR_TIF_Pos (6U) | |
| 4612 | #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ | |
| 4613 | #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ | |
| 4614 | #define TIM_SR_BIF_Pos (7U) | |
| 4615 | #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */ | |
| 4616 | #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ | |
| 4617 | #define TIM_SR_CC1OF_Pos (9U) | |
| 4618 | #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ | |
| 4619 | #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ | |
| 4620 | #define TIM_SR_CC2OF_Pos (10U) | |
| 4621 | #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ | |
| 4622 | #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ | |
| 4623 | #define TIM_SR_CC3OF_Pos (11U) | |
| 4624 | #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ | |
| 4625 | #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ | |
| 4626 | #define TIM_SR_CC4OF_Pos (12U) | |
| 4627 | #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ | |
| 4628 | #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ | |
| 4629 | ||
| 4630 | /******************* Bit definition for TIM_EGR register *******************/ | |
| 4631 | #define TIM_EGR_UG_Pos (0U) | |
| 4632 | #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ | |
| 4633 | #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ | |
| 4634 | #define TIM_EGR_CC1G_Pos (1U) | |
| 4635 | #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ | |
| 4636 | #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ | |
| 4637 | #define TIM_EGR_CC2G_Pos (2U) | |
| 4638 | #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ | |
| 4639 | #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ | |
| 4640 | #define TIM_EGR_CC3G_Pos (3U) | |
| 4641 | #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ | |
| 4642 | #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ | |
| 4643 | #define TIM_EGR_CC4G_Pos (4U) | |
| 4644 | #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ | |
| 4645 | #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ | |
| 4646 | #define TIM_EGR_COMG_Pos (5U) | |
| 4647 | #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ | |
| 4648 | #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ | |
| 4649 | #define TIM_EGR_TG_Pos (6U) | |
| 4650 | #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ | |
| 4651 | #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ | |
| 4652 | #define TIM_EGR_BG_Pos (7U) | |
| 4653 | #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */ | |
| 4654 | #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ | |
| 4655 | ||
| 4656 | /****************** Bit definition for TIM_CCMR1 register ******************/ | |
| 4657 | #define TIM_CCMR1_CC1S_Pos (0U) | |
| 4658 | #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ | |
| 4659 | #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ | |
| 4660 | #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ | |
| 4661 | #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ | |
| 4662 | ||
| 4663 | #define TIM_CCMR1_OC1FE_Pos (2U) | |
| 4664 | #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ | |
| 4665 | #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ | |
| 4666 | #define TIM_CCMR1_OC1PE_Pos (3U) | |
| 4667 | #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ | |
| 4668 | #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ | |
| 4669 | ||
| 4670 | #define TIM_CCMR1_OC1M_Pos (4U) | |
| 4671 | #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ | |
| 4672 | #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ | |
| 4673 | #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ | |
| 4674 | #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ | |
| 4675 | #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ | |
| 4676 | ||
| 4677 | #define TIM_CCMR1_OC1CE_Pos (7U) | |
| 4678 | #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ | |
| 4679 | #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ | |
| 4680 | ||
| 4681 | #define TIM_CCMR1_CC2S_Pos (8U) | |
| 4682 | #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ | |
| 4683 | #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ | |
| 4684 | #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ | |
| 4685 | #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ | |
| 4686 | ||
| 4687 | #define TIM_CCMR1_OC2FE_Pos (10U) | |
| 4688 | #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ | |
| 4689 | #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ | |
| 4690 | #define TIM_CCMR1_OC2PE_Pos (11U) | |
| 4691 | #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ | |
| 4692 | #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ | |
| 4693 | ||
| 4694 | #define TIM_CCMR1_OC2M_Pos (12U) | |
| 4695 | #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ | |
| 4696 | #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ | |
| 4697 | #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ | |
| 4698 | #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ | |
| 4699 | #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ | |
| 4700 | ||
| 4701 | #define TIM_CCMR1_OC2CE_Pos (15U) | |
| 4702 | #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ | |
| 4703 | #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ | |
| 4704 | ||
| 4705 | /*---------------------------------------------------------------------------*/ | |
| 4706 | ||
| 4707 | #define TIM_CCMR1_IC1PSC_Pos (2U) | |
| 4708 | #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ | |
| 4709 | #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ | |
| 4710 | #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ | |
| 4711 | #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ | |
| 4712 | ||
| 4713 | #define TIM_CCMR1_IC1F_Pos (4U) | |
| 4714 | #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ | |
| 4715 | #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ | |
| 4716 | #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ | |
| 4717 | #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ | |
| 4718 | #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ | |
| 4719 | #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ | |
| 4720 | ||
| 4721 | #define TIM_CCMR1_IC2PSC_Pos (10U) | |
| 4722 | #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ | |
| 4723 | #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ | |
| 4724 | #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ | |
| 4725 | #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ | |
| 4726 | ||
| 4727 | #define TIM_CCMR1_IC2F_Pos (12U) | |
| 4728 | #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ | |
| 4729 | #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ | |
| 4730 | #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ | |
| 4731 | #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ | |
| 4732 | #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ | |
| 4733 | #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ | |
| 4734 | ||
| 4735 | /****************** Bit definition for TIM_CCMR2 register ******************/ | |
| 4736 | #define TIM_CCMR2_CC3S_Pos (0U) | |
| 4737 | #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ | |
| 4738 | #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ | |
| 4739 | #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ | |
| 4740 | #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ | |
| 4741 | ||
| 4742 | #define TIM_CCMR2_OC3FE_Pos (2U) | |
| 4743 | #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ | |
| 4744 | #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ | |
| 4745 | #define TIM_CCMR2_OC3PE_Pos (3U) | |
| 4746 | #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ | |
| 4747 | #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ | |
| 4748 | ||
| 4749 | #define TIM_CCMR2_OC3M_Pos (4U) | |
| 4750 | #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ | |
| 4751 | #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ | |
| 4752 | #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ | |
| 4753 | #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ | |
| 4754 | #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ | |
| 4755 | ||
| 4756 | #define TIM_CCMR2_OC3CE_Pos (7U) | |
| 4757 | #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ | |
| 4758 | #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ | |
| 4759 | ||
| 4760 | #define TIM_CCMR2_CC4S_Pos (8U) | |
| 4761 | #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ | |
| 4762 | #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ | |
| 4763 | #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ | |
| 4764 | #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ | |
| 4765 | ||
| 4766 | #define TIM_CCMR2_OC4FE_Pos (10U) | |
| 4767 | #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ | |
| 4768 | #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ | |
| 4769 | #define TIM_CCMR2_OC4PE_Pos (11U) | |
| 4770 | #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ | |
| 4771 | #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ | |
| 4772 | ||
| 4773 | #define TIM_CCMR2_OC4M_Pos (12U) | |
| 4774 | #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ | |
| 4775 | #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ | |
| 4776 | #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ | |
| 4777 | #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ | |
| 4778 | #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ | |
| 4779 | ||
| 4780 | #define TIM_CCMR2_OC4CE_Pos (15U) | |
| 4781 | #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ | |
| 4782 | #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ | |
| 4783 | ||
| 4784 | /*---------------------------------------------------------------------------*/ | |
| 4785 | ||
| 4786 | #define TIM_CCMR2_IC3PSC_Pos (2U) | |
| 4787 | #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ | |
| 4788 | #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ | |
| 4789 | #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ | |
| 4790 | #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ | |
| 4791 | ||
| 4792 | #define TIM_CCMR2_IC3F_Pos (4U) | |
| 4793 | #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ | |
| 4794 | #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ | |
| 4795 | #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ | |
| 4796 | #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ | |
| 4797 | #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ | |
| 4798 | #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ | |
| 4799 | ||
| 4800 | #define TIM_CCMR2_IC4PSC_Pos (10U) | |
| 4801 | #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ | |
| 4802 | #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ | |
| 4803 | #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ | |
| 4804 | #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ | |
| 4805 | ||
| 4806 | #define TIM_CCMR2_IC4F_Pos (12U) | |
| 4807 | #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ | |
| 4808 | #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ | |
| 4809 | #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ | |
| 4810 | #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ | |
| 4811 | #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ | |
| 4812 | #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ | |
| 4813 | ||
| 4814 | /******************* Bit definition for TIM_CCER register ******************/ | |
| 4815 | #define TIM_CCER_CC1E_Pos (0U) | |
| 4816 | #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ | |
| 4817 | #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ | |
| 4818 | #define TIM_CCER_CC1P_Pos (1U) | |
| 4819 | #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ | |
| 4820 | #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ | |
| 4821 | #define TIM_CCER_CC1NE_Pos (2U) | |
| 4822 | #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ | |
| 4823 | #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ | |
| 4824 | #define TIM_CCER_CC1NP_Pos (3U) | |
| 4825 | #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ | |
| 4826 | #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ | |
| 4827 | #define TIM_CCER_CC2E_Pos (4U) | |
| 4828 | #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ | |
| 4829 | #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ | |
| 4830 | #define TIM_CCER_CC2P_Pos (5U) | |
| 4831 | #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ | |
| 4832 | #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ | |
| 4833 | #define TIM_CCER_CC2NE_Pos (6U) | |
| 4834 | #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ | |
| 4835 | #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ | |
| 4836 | #define TIM_CCER_CC2NP_Pos (7U) | |
| 4837 | #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ | |
| 4838 | #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ | |
| 4839 | #define TIM_CCER_CC3E_Pos (8U) | |
| 4840 | #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ | |
| 4841 | #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ | |
| 4842 | #define TIM_CCER_CC3P_Pos (9U) | |
| 4843 | #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ | |
| 4844 | #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ | |
| 4845 | #define TIM_CCER_CC3NE_Pos (10U) | |
| 4846 | #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ | |
| 4847 | #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ | |
| 4848 | #define TIM_CCER_CC3NP_Pos (11U) | |
| 4849 | #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ | |
| 4850 | #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ | |
| 4851 | #define TIM_CCER_CC4E_Pos (12U) | |
| 4852 | #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ | |
| 4853 | #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ | |
| 4854 | #define TIM_CCER_CC4P_Pos (13U) | |
| 4855 | #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ | |
| 4856 | #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ | |
| 4857 | #define TIM_CCER_CC4NP_Pos (15U) | |
| 4858 | #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ | |
| 4859 | #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ | |
| 4860 | ||
| 4861 | /******************* Bit definition for TIM_CNT register *******************/ | |
| 4862 | #define TIM_CNT_CNT_Pos (0U) | |
| 4863 | #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ | |
| 4864 | #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ | |
| 4865 | ||
| 4866 | /******************* Bit definition for TIM_PSC register *******************/ | |
| 4867 | #define TIM_PSC_PSC_Pos (0U) | |
| 4868 | #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ | |
| 4869 | #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ | |
| 4870 | ||
| 4871 | /******************* Bit definition for TIM_ARR register *******************/ | |
| 4872 | #define TIM_ARR_ARR_Pos (0U) | |
| 4873 | #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ | |
| 4874 | #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ | |
| 4875 | ||
| 4876 | /******************* Bit definition for TIM_RCR register *******************/ | |
| 4877 | #define TIM_RCR_REP_Pos (0U) | |
| 4878 | #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */ | |
| 4879 | #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ | |
| 4880 | ||
| 4881 | /******************* Bit definition for TIM_CCR1 register ******************/ | |
| 4882 | #define TIM_CCR1_CCR1_Pos (0U) | |
| 4883 | #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ | |
| 4884 | #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ | |
| 4885 | ||
| 4886 | /******************* Bit definition for TIM_CCR2 register ******************/ | |
| 4887 | #define TIM_CCR2_CCR2_Pos (0U) | |
| 4888 | #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ | |
| 4889 | #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ | |
| 4890 | ||
| 4891 | /******************* Bit definition for TIM_CCR3 register ******************/ | |
| 4892 | #define TIM_CCR3_CCR3_Pos (0U) | |
| 4893 | #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ | |
| 4894 | #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ | |
| 4895 | ||
| 4896 | /******************* Bit definition for TIM_CCR4 register ******************/ | |
| 4897 | #define TIM_CCR4_CCR4_Pos (0U) | |
| 4898 | #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ | |
| 4899 | #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ | |
| 4900 | ||
| 4901 | /******************* Bit definition for TIM_BDTR register ******************/ | |
| 4902 | #define TIM_BDTR_DTG_Pos (0U) | |
| 4903 | #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ | |
| 4904 | #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ | |
| 4905 | #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ | |
| 4906 | #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ | |
| 4907 | #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ | |
| 4908 | #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ | |
| 4909 | #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ | |
| 4910 | #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ | |
| 4911 | #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ | |
| 4912 | #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ | |
| 4913 | ||
| 4914 | #define TIM_BDTR_LOCK_Pos (8U) | |
| 4915 | #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ | |
| 4916 | #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ | |
| 4917 | #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ | |
| 4918 | #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ | |
| 4919 | ||
| 4920 | #define TIM_BDTR_OSSI_Pos (10U) | |
| 4921 | #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ | |
| 4922 | #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ | |
| 4923 | #define TIM_BDTR_OSSR_Pos (11U) | |
| 4924 | #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ | |
| 4925 | #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ | |
| 4926 | #define TIM_BDTR_BKE_Pos (12U) | |
| 4927 | #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ | |
| 4928 | #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ | |
| 4929 | #define TIM_BDTR_BKP_Pos (13U) | |
| 4930 | #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ | |
| 4931 | #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ | |
| 4932 | #define TIM_BDTR_AOE_Pos (14U) | |
| 4933 | #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ | |
| 4934 | #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ | |
| 4935 | #define TIM_BDTR_MOE_Pos (15U) | |
| 4936 | #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ | |
| 4937 | #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ | |
| 4938 | ||
| 4939 | /******************* Bit definition for TIM_DCR register *******************/ | |
| 4940 | #define TIM_DCR_DBA_Pos (0U) | |
| 4941 | #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ | |
| 4942 | #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ | |
| 4943 | #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ | |
| 4944 | #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ | |
| 4945 | #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ | |
| 4946 | #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ | |
| 4947 | #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ | |
| 4948 | ||
| 4949 | #define TIM_DCR_DBL_Pos (8U) | |
| 4950 | #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ | |
| 4951 | #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ | |
| 4952 | #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ | |
| 4953 | #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ | |
| 4954 | #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ | |
| 4955 | #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ | |
| 4956 | #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ | |
| 4957 | ||
| 4958 | /******************* Bit definition for TIM_DMAR register ******************/ | |
| 4959 | #define TIM_DMAR_DMAB_Pos (0U) | |
| 4960 | #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ | |
| 4961 | #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ | |
| 4962 | ||
| 4963 | /******************* Bit definition for TIM14_OR register ********************/ | |
| 4964 | #define TIM14_OR_TI1_RMP_Pos (0U) | |
| 4965 | #define TIM14_OR_TI1_RMP_Msk (0x3U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */ | |
| 4966 | #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */ | |
| 4967 | #define TIM14_OR_TI1_RMP_0 (0x1U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */ | |
| 4968 | #define TIM14_OR_TI1_RMP_1 (0x2U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */ | |
| 4969 | ||
| 4970 | /******************************************************************************/ | |
| 4971 | /* */ | |
| 4972 | /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ | |
| 4973 | /* */ | |
| 4974 | /******************************************************************************/ | |
| 4975 | ||
| 4976 | /* | |
| 4977 | * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) | |
| 4978 | */ | |
| 4979 | ||
| 4980 | /* Support of 7 bits data length feature */ | |
| 4981 | #define USART_7BITS_SUPPORT | |
| 4982 | ||
| 4983 | /* Support of Full Auto Baud rate feature (4 modes) activation */ | |
| 4984 | #define USART_FABR_SUPPORT | |
| 4985 | ||
| 4986 | /****************** Bit definition for USART_CR1 register *******************/ | |
| 4987 | #define USART_CR1_UE_Pos (0U) | |
| 4988 | #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */ | |
| 4989 | #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ | |
| 4990 | #define USART_CR1_RE_Pos (2U) | |
| 4991 | #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ | |
| 4992 | #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ | |
| 4993 | #define USART_CR1_TE_Pos (3U) | |
| 4994 | #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ | |
| 4995 | #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ | |
| 4996 | #define USART_CR1_IDLEIE_Pos (4U) | |
| 4997 | #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ | |
| 4998 | #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ | |
| 4999 | #define USART_CR1_RXNEIE_Pos (5U) | |
| 5000 | #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ | |
| 5001 | #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ | |
| 5002 | #define USART_CR1_TCIE_Pos (6U) | |
| 5003 | #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ | |
| 5004 | #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ | |
| 5005 | #define USART_CR1_TXEIE_Pos (7U) | |
| 5006 | #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ | |
| 5007 | #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ | |
| 5008 | #define USART_CR1_PEIE_Pos (8U) | |
| 5009 | #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ | |
| 5010 | #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ | |
| 5011 | #define USART_CR1_PS_Pos (9U) | |
| 5012 | #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ | |
| 5013 | #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ | |
| 5014 | #define USART_CR1_PCE_Pos (10U) | |
| 5015 | #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ | |
| 5016 | #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ | |
| 5017 | #define USART_CR1_WAKE_Pos (11U) | |
| 5018 | #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ | |
| 5019 | #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ | |
| 5020 | #define USART_CR1_M0_Pos (12U) | |
| 5021 | #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */ | |
| 5022 | #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length bit 0 */ | |
| 5023 | #define USART_CR1_MME_Pos (13U) | |
| 5024 | #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */ | |
| 5025 | #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ | |
| 5026 | #define USART_CR1_CMIE_Pos (14U) | |
| 5027 | #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ | |
| 5028 | #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ | |
| 5029 | #define USART_CR1_OVER8_Pos (15U) | |
| 5030 | #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ | |
| 5031 | #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ | |
| 5032 | #define USART_CR1_DEDT_Pos (16U) | |
| 5033 | #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ | |
| 5034 | #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ | |
| 5035 | #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ | |
| 5036 | #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ | |
| 5037 | #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ | |
| 5038 | #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ | |
| 5039 | #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ | |
| 5040 | #define USART_CR1_DEAT_Pos (21U) | |
| 5041 | #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ | |
| 5042 | #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ | |
| 5043 | #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ | |
| 5044 | #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ | |
| 5045 | #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ | |
| 5046 | #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ | |
| 5047 | #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ | |
| 5048 | #define USART_CR1_RTOIE_Pos (26U) | |
| 5049 | #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ | |
| 5050 | #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ | |
| 5051 | #define USART_CR1_EOBIE_Pos (27U) | |
| 5052 | #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ | |
| 5053 | #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ | |
| 5054 | #define USART_CR1_M1_Pos (28U) | |
| 5055 | #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */ | |
| 5056 | #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length bit 1 */ | |
| 5057 | #define USART_CR1_M_Pos (12U) | |
| 5058 | #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */ | |
| 5059 | #define USART_CR1_M USART_CR1_M_Msk /*!< [M1:M0] Word length */ | |
| 5060 | ||
| 5061 | /****************** Bit definition for USART_CR2 register *******************/ | |
| 5062 | #define USART_CR2_ADDM7_Pos (4U) | |
| 5063 | #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ | |
| 5064 | #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ | |
| 5065 | #define USART_CR2_LBCL_Pos (8U) | |
| 5066 | #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ | |
| 5067 | #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ | |
| 5068 | #define USART_CR2_CPHA_Pos (9U) | |
| 5069 | #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ | |
| 5070 | #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ | |
| 5071 | #define USART_CR2_CPOL_Pos (10U) | |
| 5072 | #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ | |
| 5073 | #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ | |
| 5074 | #define USART_CR2_CLKEN_Pos (11U) | |
| 5075 | #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ | |
| 5076 | #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ | |
| 5077 | #define USART_CR2_STOP_Pos (12U) | |
| 5078 | #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ | |
| 5079 | #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ | |
| 5080 | #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */ | |
| 5081 | #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */ | |
| 5082 | #define USART_CR2_SWAP_Pos (15U) | |
| 5083 | #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ | |
| 5084 | #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ | |
| 5085 | #define USART_CR2_RXINV_Pos (16U) | |
| 5086 | #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ | |
| 5087 | #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ | |
| 5088 | #define USART_CR2_TXINV_Pos (17U) | |
| 5089 | #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ | |
| 5090 | #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ | |
| 5091 | #define USART_CR2_DATAINV_Pos (18U) | |
| 5092 | #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ | |
| 5093 | #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ | |
| 5094 | #define USART_CR2_MSBFIRST_Pos (19U) | |
| 5095 | #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ | |
| 5096 | #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ | |
| 5097 | #define USART_CR2_ABREN_Pos (20U) | |
| 5098 | #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ | |
| 5099 | #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ | |
| 5100 | #define USART_CR2_ABRMODE_Pos (21U) | |
| 5101 | #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ | |
| 5102 | #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ | |
| 5103 | #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ | |
| 5104 | #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ | |
| 5105 | #define USART_CR2_RTOEN_Pos (23U) | |
| 5106 | #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ | |
| 5107 | #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ | |
| 5108 | #define USART_CR2_ADD_Pos (24U) | |
| 5109 | #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ | |
| 5110 | #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ | |
| 5111 | ||
| 5112 | /****************** Bit definition for USART_CR3 register *******************/ | |
| 5113 | #define USART_CR3_EIE_Pos (0U) | |
| 5114 | #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ | |
| 5115 | #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ | |
| 5116 | #define USART_CR3_HDSEL_Pos (3U) | |
| 5117 | #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ | |
| 5118 | #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ | |
| 5119 | #define USART_CR3_DMAR_Pos (6U) | |
| 5120 | #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ | |
| 5121 | #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ | |
| 5122 | #define USART_CR3_DMAT_Pos (7U) | |
| 5123 | #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ | |
| 5124 | #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ | |
| 5125 | #define USART_CR3_RTSE_Pos (8U) | |
| 5126 | #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ | |
| 5127 | #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ | |
| 5128 | #define USART_CR3_CTSE_Pos (9U) | |
| 5129 | #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ | |
| 5130 | #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ | |
| 5131 | #define USART_CR3_CTSIE_Pos (10U) | |
| 5132 | #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ | |
| 5133 | #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ | |
| 5134 | #define USART_CR3_ONEBIT_Pos (11U) | |
| 5135 | #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ | |
| 5136 | #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ | |
| 5137 | #define USART_CR3_OVRDIS_Pos (12U) | |
| 5138 | #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ | |
| 5139 | #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ | |
| 5140 | #define USART_CR3_DDRE_Pos (13U) | |
| 5141 | #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ | |
| 5142 | #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ | |
| 5143 | #define USART_CR3_DEM_Pos (14U) | |
| 5144 | #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */ | |
| 5145 | #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ | |
| 5146 | #define USART_CR3_DEP_Pos (15U) | |
| 5147 | #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */ | |
| 5148 | #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ | |
| 5149 | ||
| 5150 | /****************** Bit definition for USART_BRR register *******************/ | |
| 5151 | #define USART_BRR_DIV_FRACTION_Pos (0U) | |
| 5152 | #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ | |
| 5153 | #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ | |
| 5154 | #define USART_BRR_DIV_MANTISSA_Pos (4U) | |
| 5155 | #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ | |
| 5156 | #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ | |
| 5157 | ||
| 5158 | /****************** Bit definition for USART_GTPR register ******************/ | |
| 5159 | #define USART_GTPR_PSC_Pos (0U) | |
| 5160 | #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ | |
| 5161 | #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ | |
| 5162 | #define USART_GTPR_GT_Pos (8U) | |
| 5163 | #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ | |
| 5164 | #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ | |
| 5165 | ||
| 5166 | ||
| 5167 | /******************* Bit definition for USART_RTOR register *****************/ | |
| 5168 | #define USART_RTOR_RTO_Pos (0U) | |
| 5169 | #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ | |
| 5170 | #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ | |
| 5171 | #define USART_RTOR_BLEN_Pos (24U) | |
| 5172 | #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ | |
| 5173 | #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ | |
| 5174 | ||
| 5175 | /******************* Bit definition for USART_RQR register ******************/ | |
| 5176 | #define USART_RQR_ABRRQ_Pos (0U) | |
| 5177 | #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ | |
| 5178 | #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ | |
| 5179 | #define USART_RQR_SBKRQ_Pos (1U) | |
| 5180 | #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ | |
| 5181 | #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ | |
| 5182 | #define USART_RQR_MMRQ_Pos (2U) | |
| 5183 | #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ | |
| 5184 | #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ | |
| 5185 | #define USART_RQR_RXFRQ_Pos (3U) | |
| 5186 | #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ | |
| 5187 | #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ | |
| 5188 | ||
| 5189 | /******************* Bit definition for USART_ISR register ******************/ | |
| 5190 | #define USART_ISR_PE_Pos (0U) | |
| 5191 | #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */ | |
| 5192 | #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ | |
| 5193 | #define USART_ISR_FE_Pos (1U) | |
| 5194 | #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */ | |
| 5195 | #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ | |
| 5196 | #define USART_ISR_NE_Pos (2U) | |
| 5197 | #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */ | |
| 5198 | #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ | |
| 5199 | #define USART_ISR_ORE_Pos (3U) | |
| 5200 | #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */ | |
| 5201 | #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ | |
| 5202 | #define USART_ISR_IDLE_Pos (4U) | |
| 5203 | #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ | |
| 5204 | #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ | |
| 5205 | #define USART_ISR_RXNE_Pos (5U) | |
| 5206 | #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ | |
| 5207 | #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ | |
| 5208 | #define USART_ISR_TC_Pos (6U) | |
| 5209 | #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */ | |
| 5210 | #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ | |
| 5211 | #define USART_ISR_TXE_Pos (7U) | |
| 5212 | #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */ | |
| 5213 | #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ | |
| 5214 | #define USART_ISR_CTSIF_Pos (9U) | |
| 5215 | #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ | |
| 5216 | #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ | |
| 5217 | #define USART_ISR_CTS_Pos (10U) | |
| 5218 | #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */ | |
| 5219 | #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ | |
| 5220 | #define USART_ISR_RTOF_Pos (11U) | |
| 5221 | #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ | |
| 5222 | #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ | |
| 5223 | #define USART_ISR_ABRE_Pos (14U) | |
| 5224 | #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ | |
| 5225 | #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ | |
| 5226 | #define USART_ISR_ABRF_Pos (15U) | |
| 5227 | #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ | |
| 5228 | #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ | |
| 5229 | #define USART_ISR_BUSY_Pos (16U) | |
| 5230 | #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ | |
| 5231 | #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ | |
| 5232 | #define USART_ISR_CMF_Pos (17U) | |
| 5233 | #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */ | |
| 5234 | #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ | |
| 5235 | #define USART_ISR_SBKF_Pos (18U) | |
| 5236 | #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ | |
| 5237 | #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ | |
| 5238 | #define USART_ISR_RWU_Pos (19U) | |
| 5239 | #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */ | |
| 5240 | #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ | |
| 5241 | #define USART_ISR_TEACK_Pos (21U) | |
| 5242 | #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ | |
| 5243 | #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ | |
| 5244 | #define USART_ISR_REACK_Pos (22U) | |
| 5245 | #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */ | |
| 5246 | #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ | |
| 5247 | ||
| 5248 | /******************* Bit definition for USART_ICR register ******************/ | |
| 5249 | #define USART_ICR_PECF_Pos (0U) | |
| 5250 | #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */ | |
| 5251 | #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ | |
| 5252 | #define USART_ICR_FECF_Pos (1U) | |
| 5253 | #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */ | |
| 5254 | #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ | |
| 5255 | #define USART_ICR_NCF_Pos (2U) | |
| 5256 | #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */ | |
| 5257 | #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */ | |
| 5258 | #define USART_ICR_ORECF_Pos (3U) | |
| 5259 | #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ | |
| 5260 | #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ | |
| 5261 | #define USART_ICR_IDLECF_Pos (4U) | |
| 5262 | #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ | |
| 5263 | #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ | |
| 5264 | #define USART_ICR_TCCF_Pos (6U) | |
| 5265 | #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ | |
| 5266 | #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ | |
| 5267 | #define USART_ICR_CTSCF_Pos (9U) | |
| 5268 | #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ | |
| 5269 | #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ | |
| 5270 | #define USART_ICR_RTOCF_Pos (11U) | |
| 5271 | #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ | |
| 5272 | #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ | |
| 5273 | #define USART_ICR_CMCF_Pos (17U) | |
| 5274 | #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ | |
| 5275 | #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ | |
| 5276 | ||
| 5277 | /******************* Bit definition for USART_RDR register ******************/ | |
| 5278 | #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */ | |
| 5279 | ||
| 5280 | /******************* Bit definition for USART_TDR register ******************/ | |
| 5281 | #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */ | |
| 5282 | ||
| 5283 | /******************************************************************************/ | |
| 5284 | /* */ | |
| 5285 | /* USB Device General registers */ | |
| 5286 | /* */ | |
| 5287 | /******************************************************************************/ | |
| 5288 | #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */ | |
| 5289 | #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */ | |
| 5290 | #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */ | |
| 5291 | #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */ | |
| 5292 | #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */ | |
| 5293 | #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */ | |
| 5294 | #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/ | |
| 5295 | ||
| 5296 | /**************************** ISTR interrupt events *************************/ | |
| 5297 | #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */ | |
| 5298 | #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */ | |
| 5299 | #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */ | |
| 5300 | #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */ | |
| 5301 | #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */ | |
| 5302 | #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */ | |
| 5303 | #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */ | |
| 5304 | #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */ | |
| 5305 | #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */ | |
| 5306 | #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */ | |
| 5307 | #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */ | |
| 5308 | ||
| 5309 | #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ | |
| 5310 | #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ | |
| 5311 | #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ | |
| 5312 | #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ | |
| 5313 | #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ | |
| 5314 | #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ | |
| 5315 | #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ | |
| 5316 | #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ | |
| 5317 | #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */ | |
| 5318 | ||
| 5319 | /************************* CNTR control register bits definitions ***********/ | |
| 5320 | #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */ | |
| 5321 | #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */ | |
| 5322 | #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */ | |
| 5323 | #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */ | |
| 5324 | #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */ | |
| 5325 | #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */ | |
| 5326 | #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */ | |
| 5327 | #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */ | |
| 5328 | #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */ | |
| 5329 | #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */ | |
| 5330 | #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */ | |
| 5331 | #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */ | |
| 5332 | #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */ | |
| 5333 | #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */ | |
| 5334 | #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */ | |
| 5335 | ||
| 5336 | /************************* BCDR control register bits definitions ***********/ | |
| 5337 | #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */ | |
| 5338 | #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */ | |
| 5339 | #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */ | |
| 5340 | #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */ | |
| 5341 | #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */ | |
| 5342 | #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */ | |
| 5343 | #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */ | |
| 5344 | #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */ | |
| 5345 | #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */ | |
| 5346 | ||
| 5347 | /*************************** LPM register bits definitions ******************/ | |
| 5348 | #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */ | |
| 5349 | #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */ | |
| 5350 | #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/ | |
| 5351 | #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */ | |
| 5352 | ||
| 5353 | /******************** FNR Frame Number Register bit definitions ************/ | |
| 5354 | #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */ | |
| 5355 | #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */ | |
| 5356 | #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */ | |
| 5357 | #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */ | |
| 5358 | #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */ | |
| 5359 | ||
| 5360 | /******************** DADDR Device ADDRess bit definitions ****************/ | |
| 5361 | #define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */ | |
| 5362 | #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */ | |
| 5363 | ||
| 5364 | /****************************** Endpoint register *************************/ | |
| 5365 | #define USB_EP0R USB_BASE /*!< endpoint 0 register address */ | |
| 5366 | #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */ | |
| 5367 | #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */ | |
| 5368 | #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */ | |
| 5369 | #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */ | |
| 5370 | #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */ | |
| 5371 | #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */ | |
| 5372 | #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */ | |
| 5373 | /* bit positions */ | |
| 5374 | #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */ | |
| 5375 | #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */ | |
| 5376 | #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */ | |
| 5377 | #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */ | |
| 5378 | #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */ | |
| 5379 | #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */ | |
| 5380 | #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */ | |
| 5381 | #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */ | |
| 5382 | #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */ | |
| 5383 | #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */ | |
| 5384 | ||
| 5385 | /* EndPoint REGister MASK (no toggle fields) */ | |
| 5386 | #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) | |
| 5387 | /*!< EP_TYPE[1:0] EndPoint TYPE */ | |
| 5388 | #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */ | |
| 5389 | #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */ | |
| 5390 | #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */ | |
| 5391 | #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */ | |
| 5392 | #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */ | |
| 5393 | #define USB_EP_T_MASK (((uint16_t)(~USB_EP_T_FIELD)) & USB_EPREG_MASK) | |
| 5394 | ||
| 5395 | #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ | |
| 5396 | /*!< STAT_TX[1:0] STATus for TX transfer */ | |
| 5397 | #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */ | |
| 5398 | #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */ | |
| 5399 | #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */ | |
| 5400 | #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */ | |
| 5401 | #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */ | |
| 5402 | #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */ | |
| 5403 | #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) | |
| 5404 | /*!< STAT_RX[1:0] STATus for RX transfer */ | |
| 5405 | #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */ | |
| 5406 | #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */ | |
| 5407 | #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */ | |
| 5408 | #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */ | |
| 5409 | #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */ | |
| 5410 | #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */ | |
| 5411 | #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) | |
| 5412 | ||
| 5413 | /******************************************************************************/ | |
| 5414 | /* */ | |
| 5415 | /* Window WATCHDOG (WWDG) */ | |
| 5416 | /* */ | |
| 5417 | /******************************************************************************/ | |
| 5418 | ||
| 5419 | /******************* Bit definition for WWDG_CR register ********************/ | |
| 5420 | #define WWDG_CR_T_Pos (0U) | |
| 5421 | #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ | |
| 5422 | #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ | |
| 5423 | #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */ | |
| 5424 | #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */ | |
| 5425 | #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */ | |
| 5426 | #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */ | |
| 5427 | #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */ | |
| 5428 | #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */ | |
| 5429 | #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */ | |
| 5430 | ||
| 5431 | /* Legacy defines */ | |
| 5432 | #define WWDG_CR_T0 WWDG_CR_T_0 | |
| 5433 | #define WWDG_CR_T1 WWDG_CR_T_1 | |
| 5434 | #define WWDG_CR_T2 WWDG_CR_T_2 | |
| 5435 | #define WWDG_CR_T3 WWDG_CR_T_3 | |
| 5436 | #define WWDG_CR_T4 WWDG_CR_T_4 | |
| 5437 | #define WWDG_CR_T5 WWDG_CR_T_5 | |
| 5438 | #define WWDG_CR_T6 WWDG_CR_T_6 | |
| 5439 | ||
| 5440 | #define WWDG_CR_WDGA_Pos (7U) | |
| 5441 | #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ | |
| 5442 | #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ | |
| 5443 | ||
| 5444 | /******************* Bit definition for WWDG_CFR register *******************/ | |
| 5445 | #define WWDG_CFR_W_Pos (0U) | |
| 5446 | #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ | |
| 5447 | #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ | |
| 5448 | #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */ | |
| 5449 | #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */ | |
| 5450 | #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */ | |
| 5451 | #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */ | |
| 5452 | #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */ | |
| 5453 | #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */ | |
| 5454 | #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */ | |
| 5455 | ||
| 5456 | /* Legacy defines */ | |
| 5457 | #define WWDG_CFR_W0 WWDG_CFR_W_0 | |
| 5458 | #define WWDG_CFR_W1 WWDG_CFR_W_1 | |
| 5459 | #define WWDG_CFR_W2 WWDG_CFR_W_2 | |
| 5460 | #define WWDG_CFR_W3 WWDG_CFR_W_3 | |
| 5461 | #define WWDG_CFR_W4 WWDG_CFR_W_4 | |
| 5462 | #define WWDG_CFR_W5 WWDG_CFR_W_5 | |
| 5463 | #define WWDG_CFR_W6 WWDG_CFR_W_6 | |
| 5464 | ||
| 5465 | #define WWDG_CFR_WDGTB_Pos (7U) | |
| 5466 | #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ | |
| 5467 | #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ | |
| 5468 | #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ | |
| 5469 | #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ | |
| 5470 | ||
| 5471 | /* Legacy defines */ | |
| 5472 | #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 | |
| 5473 | #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 | |
| 5474 | ||
| 5475 | #define WWDG_CFR_EWI_Pos (9U) | |
| 5476 | #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ | |
| 5477 | #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ | |
| 5478 | ||
| 5479 | /******************* Bit definition for WWDG_SR register ********************/ | |
| 5480 | #define WWDG_SR_EWIF_Pos (0U) | |
| 5481 | #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ | |
| 5482 | #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ | |
| 5483 | ||
| 5484 | /** | |
| 5485 | * @} | |
| 5486 | */ | |
| 5487 | ||
| 5488 | /** | |
| 5489 | * @} | |
| 5490 | */ | |
| 5491 | ||
| 5492 | ||
| 5493 | /** @addtogroup Exported_macro | |
| 5494 | * @{ | |
| 5495 | */ | |
| 5496 | ||
| 5497 | /****************************** ADC Instances *********************************/ | |
| 5498 | #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) | |
| 5499 | ||
| 5500 | #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC) | |
| 5501 | ||
| 5502 | /****************************** CRC Instances *********************************/ | |
| 5503 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) | |
| 5504 | ||
| 5505 | /******************************* DMA Instances ********************************/ | |
| 5506 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ | |
| 5507 | ((INSTANCE) == DMA1_Channel2) || \ | |
| 5508 | ((INSTANCE) == DMA1_Channel3) || \ | |
| 5509 | ((INSTANCE) == DMA1_Channel4) || \ | |
| 5510 | ((INSTANCE) == DMA1_Channel5)) | |
| 5511 | ||
| 5512 | /****************************** GPIO Instances ********************************/ | |
| 5513 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ | |
| 5514 | ((INSTANCE) == GPIOB) || \ | |
| 5515 | ((INSTANCE) == GPIOC) || \ | |
| 5516 | ((INSTANCE) == GPIOD) || \ | |
| 5517 | ((INSTANCE) == GPIOF)) | |
| 5518 | ||
| 5519 | /**************************** GPIO Alternate Function Instances ***************/ | |
| 5520 | #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ | |
| 5521 | ((INSTANCE) == GPIOB) || \ | |
| 5522 | ((INSTANCE) == GPIOC) || \ | |
| 5523 | ((INSTANCE) == GPIOD) || \ | |
| 5524 | ((INSTANCE) == GPIOF)) | |
| 5525 | ||
| 5526 | /****************************** GPIO Lock Instances ***************************/ | |
| 5527 | #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ | |
| 5528 | ((INSTANCE) == GPIOB)) | |
| 5529 | ||
| 5530 | /****************************** I2C Instances *********************************/ | |
| 5531 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ | |
| 5532 | ((INSTANCE) == I2C2)) | |
| 5533 | ||
| 5534 | ||
| 5535 | /****************************** IWDG Instances ********************************/ | |
| 5536 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) | |
| 5537 | ||
| 5538 | /****************************** RTC Instances *********************************/ | |
| 5539 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) | |
| 5540 | ||
| 5541 | /****************************** SMBUS Instances *********************************/ | |
| 5542 | #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) | |
| 5543 | ||
| 5544 | /****************************** SPI Instances *********************************/ | |
| 5545 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ | |
| 5546 | ((INSTANCE) == SPI2)) | |
| 5547 | ||
| 5548 | /****************************** TIM Instances *********************************/ | |
| 5549 | #define IS_TIM_INSTANCE(INSTANCE)\ | |
| 5550 | (((INSTANCE) == TIM1) || \ | |
| 5551 | ((INSTANCE) == TIM3) || \ | |
| 5552 | ((INSTANCE) == TIM6) || \ | |
| 5553 | ((INSTANCE) == TIM7) || \ | |
| 5554 | ((INSTANCE) == TIM14) || \ | |
| 5555 | ((INSTANCE) == TIM15) || \ | |
| 5556 | ((INSTANCE) == TIM16) || \ | |
| 5557 | ((INSTANCE) == TIM17)) | |
| 5558 | ||
| 5559 | #define IS_TIM_CC1_INSTANCE(INSTANCE)\ | |
| 5560 | (((INSTANCE) == TIM1) || \ | |
| 5561 | ((INSTANCE) == TIM3) || \ | |
| 5562 | ((INSTANCE) == TIM14) || \ | |
| 5563 | ((INSTANCE) == TIM15) || \ | |
| 5564 | ((INSTANCE) == TIM16) || \ | |
| 5565 | ((INSTANCE) == TIM17)) | |
| 5566 | ||
| 5567 | #define IS_TIM_CC2_INSTANCE(INSTANCE)\ | |
| 5568 | (((INSTANCE) == TIM1) || \ | |
| 5569 | ((INSTANCE) == TIM3) || \ | |
| 5570 | ((INSTANCE) == TIM15)) | |
| 5571 | ||
| 5572 | #define IS_TIM_CC3_INSTANCE(INSTANCE)\ | |
| 5573 | (((INSTANCE) == TIM1) || \ | |
| 5574 | ((INSTANCE) == TIM3)) | |
| 5575 | ||
| 5576 | #define IS_TIM_CC4_INSTANCE(INSTANCE)\ | |
| 5577 | (((INSTANCE) == TIM1) || \ | |
| 5578 | ((INSTANCE) == TIM3)) | |
| 5579 | ||
| 5580 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ | |
| 5581 | (((INSTANCE) == TIM1) || \ | |
| 5582 | ((INSTANCE) == TIM3)) | |
| 5583 | ||
| 5584 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ | |
| 5585 | (((INSTANCE) == TIM1) || \ | |
| 5586 | ((INSTANCE) == TIM3)) | |
| 5587 | ||
| 5588 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ | |
| 5589 | (((INSTANCE) == TIM1) || \ | |
| 5590 | ((INSTANCE) == TIM3) || \ | |
| 5591 | ((INSTANCE) == TIM15)) | |
| 5592 | ||
| 5593 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ | |
| 5594 | (((INSTANCE) == TIM1) || \ | |
| 5595 | ((INSTANCE) == TIM3) || \ | |
| 5596 | ((INSTANCE) == TIM15)) | |
| 5597 | ||
| 5598 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ | |
| 5599 | (((INSTANCE) == TIM1) || \ | |
| 5600 | ((INSTANCE) == TIM3)) | |
| 5601 | ||
| 5602 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ | |
| 5603 | (((INSTANCE) == TIM1) || \ | |
| 5604 | ((INSTANCE) == TIM3)) | |
| 5605 | ||
| 5606 | #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ | |
| 5607 | (((INSTANCE) == TIM1)) | |
| 5608 | ||
| 5609 | #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ | |
| 5610 | (((INSTANCE) == TIM1)) | |
| 5611 | ||
| 5612 | #define IS_TIM_XOR_INSTANCE(INSTANCE)\ | |
| 5613 | (((INSTANCE) == TIM1) || \ | |
| 5614 | ((INSTANCE) == TIM3)) | |
| 5615 | ||
| 5616 | #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ | |
| 5617 | (((INSTANCE) == TIM1) || \ | |
| 5618 | ((INSTANCE) == TIM3) || \ | |
| 5619 | ((INSTANCE) == TIM6) || \ | |
| 5620 | ((INSTANCE) == TIM7) || \ | |
| 5621 | ((INSTANCE) == TIM15)) | |
| 5622 | ||
| 5623 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ | |
| 5624 | (((INSTANCE) == TIM1) || \ | |
| 5625 | ((INSTANCE) == TIM3) || \ | |
| 5626 | ((INSTANCE) == TIM15)) | |
| 5627 | ||
| 5628 | #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(0) | |
| 5629 | ||
| 5630 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ | |
| 5631 | (((INSTANCE) == TIM1) || \ | |
| 5632 | ((INSTANCE) == TIM3) || \ | |
| 5633 | ((INSTANCE) == TIM15) || \ | |
| 5634 | ((INSTANCE) == TIM16) || \ | |
| 5635 | ((INSTANCE) == TIM17)) | |
| 5636 | ||
| 5637 | #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ | |
| 5638 | (((INSTANCE) == TIM1) || \ | |
| 5639 | ((INSTANCE) == TIM15) || \ | |
| 5640 | ((INSTANCE) == TIM16) || \ | |
| 5641 | ((INSTANCE) == TIM17)) | |
| 5642 | ||
| 5643 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ | |
| 5644 | ((((INSTANCE) == TIM1) && \ | |
| 5645 | (((CHANNEL) == TIM_CHANNEL_1) || \ | |
| 5646 | ((CHANNEL) == TIM_CHANNEL_2) || \ | |
| 5647 | ((CHANNEL) == TIM_CHANNEL_3) || \ | |
| 5648 | ((CHANNEL) == TIM_CHANNEL_4))) \ | |
| 5649 | || \ | |
| 5650 | (((INSTANCE) == TIM3) && \ | |
| 5651 | (((CHANNEL) == TIM_CHANNEL_1) || \ | |
| 5652 | ((CHANNEL) == TIM_CHANNEL_2) || \ | |
| 5653 | ((CHANNEL) == TIM_CHANNEL_3) || \ | |
| 5654 | ((CHANNEL) == TIM_CHANNEL_4))) \ | |
| 5655 | || \ | |
| 5656 | (((INSTANCE) == TIM14) && \ | |
| 5657 | (((CHANNEL) == TIM_CHANNEL_1))) \ | |
| 5658 | || \ | |
| 5659 | (((INSTANCE) == TIM15) && \ | |
| 5660 | (((CHANNEL) == TIM_CHANNEL_1) || \ | |
| 5661 | ((CHANNEL) == TIM_CHANNEL_2))) \ | |
| 5662 | || \ | |
| 5663 | (((INSTANCE) == TIM16) && \ | |
| 5664 | (((CHANNEL) == TIM_CHANNEL_1))) \ | |
| 5665 | || \ | |
| 5666 | (((INSTANCE) == TIM17) && \ | |
| 5667 | (((CHANNEL) == TIM_CHANNEL_1)))) | |
| 5668 | ||
| 5669 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ | |
| 5670 | ((((INSTANCE) == TIM1) && \ | |
| 5671 | (((CHANNEL) == TIM_CHANNEL_1) || \ | |
| 5672 | ((CHANNEL) == TIM_CHANNEL_2) || \ | |
| 5673 | ((CHANNEL) == TIM_CHANNEL_3))) \ | |
| 5674 | || \ | |
| 5675 | (((INSTANCE) == TIM15) && \ | |
| 5676 | ((CHANNEL) == TIM_CHANNEL_1)) \ | |
| 5677 | || \ | |
| 5678 | (((INSTANCE) == TIM16) && \ | |
| 5679 | ((CHANNEL) == TIM_CHANNEL_1)) \ | |
| 5680 | || \ | |
| 5681 | (((INSTANCE) == TIM17) && \ | |
| 5682 | ((CHANNEL) == TIM_CHANNEL_1))) | |
| 5683 | ||
| 5684 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ | |
| 5685 | (((INSTANCE) == TIM1) || \ | |
| 5686 | ((INSTANCE) == TIM3)) | |
| 5687 | ||
| 5688 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ | |
| 5689 | (((INSTANCE) == TIM1) || \ | |
| 5690 | ((INSTANCE) == TIM15) || \ | |
| 5691 | ((INSTANCE) == TIM16) || \ | |
| 5692 | ((INSTANCE) == TIM17)) | |
| 5693 | ||
| 5694 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ | |
| 5695 | (((INSTANCE) == TIM1) || \ | |
| 5696 | ((INSTANCE) == TIM3) || \ | |
| 5697 | ((INSTANCE) == TIM14) || \ | |
| 5698 | ((INSTANCE) == TIM15) || \ | |
| 5699 | ((INSTANCE) == TIM16) || \ | |
| 5700 | ((INSTANCE) == TIM17)) | |
| 5701 | ||
| 5702 | #define IS_TIM_DMA_INSTANCE(INSTANCE)\ | |
| 5703 | (((INSTANCE) == TIM1) || \ | |
| 5704 | ((INSTANCE) == TIM3) || \ | |
| 5705 | ((INSTANCE) == TIM6) || \ | |
| 5706 | ((INSTANCE) == TIM7) || \ | |
| 5707 | ((INSTANCE) == TIM15) || \ | |
| 5708 | ((INSTANCE) == TIM16) || \ | |
| 5709 | ((INSTANCE) == TIM17)) | |
| 5710 | ||
| 5711 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ | |
| 5712 | (((INSTANCE) == TIM1) || \ | |
| 5713 | ((INSTANCE) == TIM3) || \ | |
| 5714 | ((INSTANCE) == TIM15) || \ | |
| 5715 | ((INSTANCE) == TIM16) || \ | |
| 5716 | ((INSTANCE) == TIM17)) | |
| 5717 | ||
| 5718 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ | |
| 5719 | (((INSTANCE) == TIM1) || \ | |
| 5720 | ((INSTANCE) == TIM15) || \ | |
| 5721 | ((INSTANCE) == TIM16) || \ | |
| 5722 | ((INSTANCE) == TIM17)) | |
| 5723 | ||
| 5724 | #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ | |
| 5725 | ((INSTANCE) == TIM14) | |
| 5726 | ||
| 5727 | #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ | |
| 5728 | ((INSTANCE) == TIM1) | |
| 5729 | ||
| 5730 | /******************** USART Instances : Synchronous mode **********************/ | |
| 5731 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ | |
| 5732 | ((INSTANCE) == USART2) || \ | |
| 5733 | ((INSTANCE) == USART3) || \ | |
| 5734 | ((INSTANCE) == USART4)) | |
| 5735 | ||
| 5736 | /******************** USART Instances : auto Baud rate detection **************/ | |
| 5737 | #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ | |
| 5738 | ((INSTANCE) == USART2)) | |
| 5739 | ||
| 5740 | /******************** UART Instances : Asynchronous mode **********************/ | |
| 5741 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ | |
| 5742 | ((INSTANCE) == USART2) || \ | |
| 5743 | ((INSTANCE) == USART3) || \ | |
| 5744 | ((INSTANCE) == USART4)) | |
| 5745 | ||
| 5746 | /******************** UART Instances : Half-Duplex mode **********************/ | |
| 5747 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ | |
| 5748 | ((INSTANCE) == USART2) || \ | |
| 5749 | ((INSTANCE) == USART3) || \ | |
| 5750 | ((INSTANCE) == USART4)) | |
| 5751 | ||
| 5752 | /****************** UART Instances : Hardware Flow control ********************/ | |
| 5753 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ | |
| 5754 | ((INSTANCE) == USART2) || \ | |
| 5755 | ((INSTANCE) == USART3) || \ | |
| 5756 | ((INSTANCE) == USART4)) | |
| 5757 | ||
| 5758 | /****************** UART Instances : Driver enable detection ********************/ | |
| 5759 | #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ | |
| 5760 | ((INSTANCE) == USART2) || \ | |
| 5761 | ((INSTANCE) == USART3) || \ | |
| 5762 | ((INSTANCE) == USART4)) | |
| 5763 | ||
| 5764 | /****************************** USB Instances ********************************/ | |
| 5765 | #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) | |
| 5766 | ||
| 5767 | /****************************** WWDG Instances ********************************/ | |
| 5768 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) | |
| 5769 | ||
| 5770 | /** | |
| 5771 | * @} | |
| 5772 | */ | |
| 5773 | ||
| 5774 | ||
| 5775 | /******************************************************************************/ | |
| 5776 | /* For a painless codes migration between the STM32F0xx device product */ | |
| 5777 | /* lines, the aliases defined below are put in place to overcome the */ | |
| 5778 | /* differences in the interrupt handlers and IRQn definitions. */ | |
| 5779 | /* No need to update developed interrupt code when moving across */ | |
| 5780 | /* product lines within the same STM32F0 Family */ | |
| 5781 | /******************************************************************************/ | |
| 5782 | ||
| 5783 | /* Aliases for __IRQn */ | |
| 5784 | #define ADC1_COMP_IRQn ADC1_IRQn | |
| 5785 | #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn | |
| 5786 | #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn | |
| 5787 | #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn | |
| 5788 | #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn | |
| 5789 | #define RCC_CRS_IRQn RCC_IRQn | |
| 5790 | #define TIM6_DAC_IRQn TIM6_IRQn | |
| 5791 | #define USART3_6_IRQn USART3_4_IRQn | |
| 5792 | #define USART3_8_IRQn USART3_4_IRQn | |
| 5793 | ||
| 5794 | ||
| 5795 | /* Aliases for __IRQHandler */ | |
| 5796 | #define ADC1_COMP_IRQHandler ADC1_IRQHandler | |
| 5797 | #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler | |
| 5798 | #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler | |
| 5799 | #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler | |
| 5800 | #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler | |
| 5801 | #define RCC_CRS_IRQHandler RCC_IRQHandler | |
| 5802 | #define TIM6_DAC_IRQHandler TIM6_IRQHandler | |
| 5803 | #define USART3_6_IRQHandler USART3_4_IRQHandler | |
| 5804 | #define USART3_8_IRQHandler USART3_4_IRQHandler | |
| 5805 | ||
| 5806 | ||
| 5807 | #ifdef __cplusplus | |
| 5808 | } | |
| 5809 | #endif /* __cplusplus */ | |
| 5810 | ||
| 5811 | #endif /* __STM32F070xB_H */ | |
| 5812 | ||
| 5813 | /** | |
| 5814 | * @} | |
| 5815 | */ | |
| 5816 | ||
| 5817 | /** | |
| 5818 | * @} | |
| 5819 | */ | |
| 5820 | ||
| 5821 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ | |
