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2023-02-22 0c20567d27fd79adfa954c5e5c5c5b82bff5311e

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bfc108	1	;****************** (C) COPYRIGHT 2016 STMicroelectronics ******************
Q	2	;* File Name : startup_stm32f030x8.s
	3	;* Author : MCD Application Team
	4	;* Description : STM32F030x8 devices vector table for MDK-ARM toolchain.
	5	;* This module performs:
	6	;* - Set the initial SP
	7	;* - Set the initial PC == Reset_Handler
	8	;* - Set the vector table entries with the exceptions ISR address
	9	;* - Branches to __main in the C library (which eventually
	10	;* calls main()).
	11	;* After Reset the CortexM0 processor is in Thread mode,
	12	;* priority is Privileged, and the Stack is set to Main.
	13	;* <<< Use Configuration Wizard in Context Menu >>>
	14	;*******************************************************************************
	15	;*
	16	;* Redistribution and use in source and binary forms, with or without modification,
	17	;* are permitted provided that the following conditions are met:
	18	;* 1. Redistributions of source code must retain the above copyright notice,
	19	;* this list of conditions and the following disclaimer.
	20	;* 2. Redistributions in binary form must reproduce the above copyright notice,
	21	;* this list of conditions and the following disclaimer in the documentation
	22	;* and/or other materials provided with the distribution.
	23	;* 3. Neither the name of STMicroelectronics nor the names of its contributors
	24	;* may be used to endorse or promote products derived from this software
	25	;* without specific prior written permission.
	26	;*
	27	;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	28	;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	29	;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	30	;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	31	;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	32	;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	33	;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	34	;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	35	;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	36	;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	37	;
	38	;*******************************************************************************
	39
	40	; Amount of memory (in bytes) allocated for Stack
	41	; Tailor this value to your application needs
	42	; <h> Stack Configuration
	43	; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
	44	; </h>
	45
	46	Stack_Size EQU 0x400
	47
	48	AREA STACK, NOINIT, READWRITE, ALIGN=3
	49	Stack_Mem SPACE Stack_Size
	50	__initial_sp
	51
	52
	53	; <h> Heap Configuration
	54	; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
	55	; </h>
	56
	57	Heap_Size EQU 0x200
	58
	59	AREA HEAP, NOINIT, READWRITE, ALIGN=3
	60	__heap_base
	61	Heap_Mem SPACE Heap_Size
	62	__heap_limit
	63
	64	PRESERVE8
	65	THUMB
	66
	67
	68	; Vector Table Mapped to Address 0 at Reset
	69	AREA RESET, DATA, READONLY
	70	EXPORT __Vectors
	71	EXPORT __Vectors_End
	72	EXPORT __Vectors_Size
	73
	74	__Vectors DCD __initial_sp ; Top of Stack
	75	DCD Reset_Handler ; Reset Handler
	76	DCD NMI_Handler ; NMI Handler
	77	DCD HardFault_Handler ; Hard Fault Handler
	78	DCD 0 ; Reserved
	79	DCD 0 ; Reserved
	80	DCD 0 ; Reserved
	81	DCD 0 ; Reserved
	82	DCD 0 ; Reserved
	83	DCD 0 ; Reserved
	84	DCD 0 ; Reserved
	85	DCD SVC_Handler ; SVCall Handler
	86	DCD 0 ; Reserved
	87	DCD 0 ; Reserved
	88	DCD PendSV_Handler ; PendSV Handler
	89	DCD SysTick_Handler ; SysTick Handler
	90
	91	; External Interrupts
	92	DCD WWDG_IRQHandler ; Window Watchdog
	93	DCD 0 ; Reserved
	94	DCD RTC_IRQHandler ; RTC through EXTI Line
	95	DCD FLASH_IRQHandler ; FLASH
	96	DCD RCC_IRQHandler ; RCC
	97	DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
	98	DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
	99	DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
	100	DCD 0 ; Reserved
	101	DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
	102	DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
	103	DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
	104	DCD ADC1_IRQHandler ; ADC1
	105	DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
	106	DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
	107	DCD 0 ; Reserved
	108	DCD TIM3_IRQHandler ; TIM3
	109	DCD TIM6_IRQHandler ; TIM6
	110	DCD 0 ; Reserved
	111	DCD TIM14_IRQHandler ; TIM14
	112	DCD TIM15_IRQHandler ; TIM15
	113	DCD TIM16_IRQHandler ; TIM16
	114	DCD TIM17_IRQHandler ; TIM17
	115	DCD I2C1_IRQHandler ; I2C1
	116	DCD I2C2_IRQHandler ; I2C2
	117	DCD SPI1_IRQHandler ; SPI1
	118	DCD SPI2_IRQHandler ; SPI2
	119	DCD USART1_IRQHandler ; USART1
	120	DCD USART2_IRQHandler ; USART2
	121
	122	__Vectors_End
	123
	124	__Vectors_Size EQU __Vectors_End - __Vectors
	125
	126	AREA \|.text\|, CODE, READONLY
	127
	128	; Reset handler routine
	129	Reset_Handler PROC
	130	EXPORT Reset_Handler [WEAK]
	131	IMPORT __main
	132	IMPORT SystemInit
	133	LDR R0, =SystemInit
	134	BLX R0
	135	LDR R0, =__main
	136	BX R0
	137	ENDP
	138
	139	; Dummy Exception Handlers (infinite loops which can be modified)
	140
	141	NMI_Handler PROC
	142	EXPORT NMI_Handler [WEAK]
	143	B .
	144	ENDP
	145	HardFault_Handler\
	146	PROC
	147	EXPORT HardFault_Handler [WEAK]
	148	B .
	149	ENDP
	150	SVC_Handler PROC
	151	EXPORT SVC_Handler [WEAK]
	152	B .
	153	ENDP
	154	PendSV_Handler PROC
	155	EXPORT PendSV_Handler [WEAK]
	156	B .
	157	ENDP
	158	SysTick_Handler PROC
	159	EXPORT SysTick_Handler [WEAK]
	160	B .
	161	ENDP
	162
	163	Default_Handler PROC
	164
	165	EXPORT WWDG_IRQHandler [WEAK]
	166	EXPORT RTC_IRQHandler [WEAK]
	167	EXPORT FLASH_IRQHandler [WEAK]
	168	EXPORT RCC_IRQHandler [WEAK]
	169	EXPORT EXTI0_1_IRQHandler [WEAK]
	170	EXPORT EXTI2_3_IRQHandler [WEAK]
	171	EXPORT EXTI4_15_IRQHandler [WEAK]
	172	EXPORT DMA1_Channel1_IRQHandler [WEAK]
	173	EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
	174	EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
	175	EXPORT ADC1_IRQHandler [WEAK]
	176	EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
	177	EXPORT TIM1_CC_IRQHandler [WEAK]
	178	EXPORT TIM3_IRQHandler [WEAK]
	179	EXPORT TIM6_IRQHandler [WEAK]
	180	EXPORT TIM14_IRQHandler [WEAK]
	181	EXPORT TIM15_IRQHandler [WEAK]
	182	EXPORT TIM16_IRQHandler [WEAK]
	183	EXPORT TIM17_IRQHandler [WEAK]
	184	EXPORT I2C1_IRQHandler [WEAK]
	185	EXPORT I2C2_IRQHandler [WEAK]
	186	EXPORT SPI1_IRQHandler [WEAK]
	187	EXPORT SPI2_IRQHandler [WEAK]
	188	EXPORT USART1_IRQHandler [WEAK]
	189	EXPORT USART2_IRQHandler [WEAK]
	190
	191
	192	WWDG_IRQHandler
	193	RTC_IRQHandler
	194	FLASH_IRQHandler
	195	RCC_IRQHandler
	196	EXTI0_1_IRQHandler
	197	EXTI2_3_IRQHandler
	198	EXTI4_15_IRQHandler
	199	DMA1_Channel1_IRQHandler
	200	DMA1_Channel2_3_IRQHandler
	201	DMA1_Channel4_5_IRQHandler
	202	ADC1_IRQHandler
	203	TIM1_BRK_UP_TRG_COM_IRQHandler
	204	TIM1_CC_IRQHandler
	205	TIM3_IRQHandler
	206	TIM6_IRQHandler
	207	TIM14_IRQHandler
	208	TIM15_IRQHandler
	209	TIM16_IRQHandler
	210	TIM17_IRQHandler
	211	I2C1_IRQHandler
	212	I2C2_IRQHandler
	213	SPI1_IRQHandler
	214	SPI2_IRQHandler
	215	USART1_IRQHandler
	216	USART2_IRQHandler
	217
	218	B .
	219
	220	ENDP
	221
	222	ALIGN
	223
	224	;*******************************************************************************
	225	; User Stack and Heap initialization
	226	;*******************************************************************************
	227	IF :DEF:__MICROLIB
	228
	229	EXPORT __initial_sp
	230	EXPORT __heap_base
	231	EXPORT __heap_limit
	232
	233	ELSE
	234
	235	IMPORT __use_two_region_memory
	236	EXPORT __user_initial_stackheap
	237
	238	__user_initial_stackheap
	239
	240	LDR R0, = Heap_Mem
	241	LDR R1, =(Stack_Mem + Stack_Size)
	242	LDR R2, = (Heap_Mem + Heap_Size)
	243	LDR R3, = Stack_Mem
	244	BX LR
	245
	246	ALIGN
	247
	248	ENDIF
	249
	250	END
	251
	252	;********************** (C) COPYRIGHT STMicroelectronics *END OF FILE***