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2022-10-17 c97b4c545c76ab6dbf5ce168015d87818034f3e2

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bfc108	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_ll_rcc.h
	4	* @author MCD Application Team
	5	* @brief Header file of RCC LL module.
	6	******************************************************************************
	7	* @attention
	8	*
	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	10	*
	11	* Redistribution and use in source and binary forms, with or without modification,
	12	* are permitted provided that the following conditions are met:
	13	* 1. Redistributions of source code must retain the above copyright notice,
	14	* this list of conditions and the following disclaimer.
	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	19	* may be used to endorse or promote products derived from this software
	20	* without specific prior written permission.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	******************************************************************************
	34	*/
	35
	36	/* Define to prevent recursive inclusion -------------------------------------*/
	37	#ifndef __STM32F0xx_LL_RCC_H
	38	#define __STM32F0xx_LL_RCC_H
	39
	40	#ifdef __cplusplus
	41	extern "C" {
	42	#endif
	43
	44	/* Includes ------------------------------------------------------------------*/
	45	#include "stm32f0xx.h"
	46
	47	/** @addtogroup STM32F0xx_LL_Driver
	48	* @{
	49	*/
	50
	51	#if defined(RCC)
	52
	53	/** @defgroup RCC_LL RCC
	54	* @{
	55	*/
	56
	57	/* Private types -------------------------------------------------------------*/
	58	/* Private variables ---------------------------------------------------------*/
	59	/* Private constants ---------------------------------------------------------*/
	60	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
	61	* @{
	62	*/
	63	/* Defines used for the bit position in the register and perform offsets*/
	64	#define RCC_POSITION_HPRE (uint32_t)4U /!< field position in register RCC_CFGR /
	65	#define RCC_POSITION_PPRE1 (uint32_t)8U /!< field position in register RCC_CFGR /
	66	#define RCC_POSITION_PLLMUL (uint32_t)18U /!< field position in register RCC_CFGR /
	67	#define RCC_POSITION_HSICAL (uint32_t)8U /!< field position in register RCC_CR /
	68	#define RCC_POSITION_HSITRIM (uint32_t)3U /!< field position in register RCC_CR /
	69	#define RCC_POSITION_HSI14TRIM (uint32_t)3U /!< field position in register RCC_CR2 /
	70	#define RCC_POSITION_HSI14CAL (uint32_t)8U /!< field position in register RCC_CR2 /
	71	#if defined(RCC_HSI48_SUPPORT)
	72	#define RCC_POSITION_HSI48CAL (uint32_t)24U /!< field position in register RCC_CR2 /
	73	#endif /* RCC_HSI48_SUPPORT */
	74	#define RCC_POSITION_USART1SW (uint32_t)0U /!< field position in register RCC_CFGR3 /
	75	#define RCC_POSITION_USART2SW (uint32_t)16U /!< field position in register RCC_CFGR3 /
	76	#define RCC_POSITION_USART3SW (uint32_t)18U /!< field position in register RCC_CFGR3 /
	77
	78	/**
	79	* @}
	80	*/
	81
	82	/* Private macros ------------------------------------------------------------*/
	83	#if defined(USE_FULL_LL_DRIVER)
	84	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
	85	* @{
	86	*/
	87	/**
	88	* @}
	89	*/
	90	#endif /USE_FULL_LL_DRIVER/
	91	/* Exported types ------------------------------------------------------------*/
	92	#if defined(USE_FULL_LL_DRIVER)
	93	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
	94	* @{
	95	*/
	96
	97	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
	98	* @{
	99	*/
	100
	101	/**
	102	* @brief RCC Clocks Frequency Structure
	103	*/
	104	typedef struct
	105	{
	106	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
	107	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
	108	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
	109	} LL_RCC_ClocksTypeDef;
	110
	111	/**
	112	* @}
	113	*/
	114
	115	/**
	116	* @}
	117	*/
	118	#endif /* USE_FULL_LL_DRIVER */
	119
	120	/* Exported constants --------------------------------------------------------*/
	121	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
	122	* @{
	123	*/
	124
	125	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
	126	* @brief Defines used to adapt values of different oscillators
	127	* @note These values could be modified in the user environment according to
	128	* HW set-up.
	129	* @{
	130	*/
	131	#if !defined (HSE_VALUE)
c97b4c	132	#define HSE_VALUE 8000000U /!< Value of the HSE oscillator in Hz /
bfc108	133	#endif /* HSE_VALUE */
Q	134
	135	#if !defined (HSI_VALUE)
	136	#define HSI_VALUE 8000000U /!< Value of the HSI oscillator in Hz /
	137	#endif /* HSI_VALUE */
	138
	139	#if !defined (LSE_VALUE)
	140	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
	141	#endif /* LSE_VALUE */
	142
	143	#if !defined (LSI_VALUE)
	144	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
	145	#endif /* LSI_VALUE */
	146	#if defined(RCC_HSI48_SUPPORT)
	147
	148	#if !defined (HSI48_VALUE)
	149	#define HSI48_VALUE 48000000U /!< Value of the HSI48 oscillator in Hz /
	150	#endif /* HSI48_VALUE */
	151	#endif /* RCC_HSI48_SUPPORT */
	152	/**
	153	* @}
	154	*/
	155
	156	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
	157	* @brief Flags defines which can be used with LL_RCC_WriteReg function
	158	* @{
	159	*/
	160	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
	161	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
	162	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
	163	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
	164	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
	165	#define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /!< HSI14 Ready Interrupt Clear /
	166	#if defined(RCC_HSI48_SUPPORT)
	167	#define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /!< HSI48 Ready Interrupt Clear /
	168	#endif /* RCC_HSI48_SUPPORT */
	169	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
	170	/**
	171	* @}
	172	*/
	173
	174	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
	175	* @brief Flags defines which can be used with LL_RCC_ReadReg function
	176	* @{
	177	*/
	178	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
	179	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
	180	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
	181	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
	182	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
	183	#define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /!< HSI14 Ready Interrupt flag /
	184	#if defined(RCC_HSI48_SUPPORT)
	185	#define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
	186	#endif /* RCC_HSI48_SUPPORT */
	187	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
	188	#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /!< OBL reset flag /
	189	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
	190	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
	191	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
	192	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
	193	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
	194	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
	195	#if defined(RCC_CSR_V18PWRRSTF)
	196	#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /!< Reset flag of the 1.8 V domain. /
	197	#endif /* RCC_CSR_V18PWRRSTF */
	198	/**
	199	* @}
	200	*/
	201
	202	/** @defgroup RCC_LL_EC_IT IT Defines
	203	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
	204	* @{
	205	*/
	206	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
	207	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
	208	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
	209	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
	210	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
	211	#define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /!< HSI14 Ready Interrupt Enable /
	212	#if defined(RCC_HSI48_SUPPORT)
	213	#define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /!< HSI48 Ready Interrupt Enable /
	214	#endif /* RCC_HSI48_SUPPORT */
	215	/**
	216	* @}
	217	*/
	218
	219	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
	220	* @{
	221	*/
	222	#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /!< Xtal mode lower driving capability /
	223	#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /!< Xtal mode medium low driving capability /
	224	#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /!< Xtal mode medium high driving capability /
	225	#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
	226	/**
	227	* @}
	228	*/
	229
	230	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
	231	* @{
	232	*/
	233	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
	234	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
	235	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
	236	#if defined(RCC_CFGR_SW_HSI48)
	237	#define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /!< HSI48 selection as system clock /
	238	#endif /* RCC_CFGR_SW_HSI48 */
	239	/**
	240	* @}
	241	*/
	242
	243	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
	244	* @{
	245	*/
	246	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
	247	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
	248	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
	249	#if defined(RCC_CFGR_SWS_HSI48)
	250	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /!< HSI48 used as system clock /
	251	#endif /* RCC_CFGR_SWS_HSI48 */
	252	/**
	253	* @}
	254	*/
	255
	256	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
	257	* @{
	258	*/
	259	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
	260	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
	261	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
	262	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
	263	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
	264	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
	265	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
	266	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
	267	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
	268	/**
	269	* @}
	270	*/
	271
	272	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
	273	* @{
	274	*/
	275	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /!< HCLK not divided /
	276	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /!< HCLK divided by 2 /
	277	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /!< HCLK divided by 4 /
	278	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /!< HCLK divided by 8 /
	279	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /!< HCLK divided by 16 /
	280	/**
	281	* @}
	282	*/
	283
	284	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
	285	* @{
	286	*/
	287	#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /!< MCO output disabled, no clock on MCO /
	288	#define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /!< HSI14 oscillator clock selected /
	289	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /!< SYSCLK selection as MCO source /
	290	#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /!< HSI selection as MCO source /
	291	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /!< HSE selection as MCO source /
	292	#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /!< LSI selection as MCO source /
	293	#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /!< LSE selection as MCO source /
	294	#if defined(RCC_CFGR_MCOSEL_HSI48)
	295	#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /!< HSI48 selection as MCO source /
	296	#endif /* RCC_CFGR_MCOSEL_HSI48 */
	297	#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /!< PLL clock divided by 2/
	298	#if defined(RCC_CFGR_PLLNODIV)
	299	#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 \| RCC_CFGR_PLLNODIV) /!< PLL clock selected/
	300	#endif /* RCC_CFGR_PLLNODIV */
	301	/**
	302	* @}
	303	*/
	304
	305	/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
	306	* @{
	307	*/
	308	#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/!< MCO Clock divided by 1 /
	309	#if defined(RCC_CFGR_MCOPRE)
	310	#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO Clock divided by 2 /
	311	#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO Clock divided by 4 /
	312	#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO Clock divided by 8 /
	313	#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO Clock divided by 16 /
	314	#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /!< MCO Clock divided by 32 /
	315	#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /!< MCO Clock divided by 64 /
	316	#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /!< MCO Clock divided by 128 /
	317	#endif /* RCC_CFGR_MCOPRE */
	318	/**
	319	* @}
	320	*/
	321
	322	#if defined(USE_FULL_LL_DRIVER)
	323	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
	324	* @{
	325	*/
	326	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
	327	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
	328	/**
	329	* @}
	330	*/
	331	#endif /* USE_FULL_LL_DRIVER */
	332
	333	/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
	334	* @{
	335	*/
	336	#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) \| RCC_CFGR3_USART1SW_PCLK) /!< PCLK1 clock used as USART1 clock source /
	337	#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) \| RCC_CFGR3_USART1SW_SYSCLK) /!< System clock selected as USART1 clock source /
	338	#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) \| RCC_CFGR3_USART1SW_LSE) /!< LSE oscillator clock used as USART1 clock source /
	339	#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) \| RCC_CFGR3_USART1SW_HSI) /!< HSI oscillator clock used as USART1 clock source /
	340	#if defined(RCC_CFGR3_USART2SW)
	341	#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) \| RCC_CFGR3_USART2SW_PCLK) /!< PCLK1 clock used as USART2 clock source /
	342	#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) \| RCC_CFGR3_USART2SW_SYSCLK) /!< System clock selected as USART2 clock source /
	343	#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) \| RCC_CFGR3_USART2SW_LSE) /!< LSE oscillator clock used as USART2 clock source /
	344	#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) \| RCC_CFGR3_USART2SW_HSI) /!< HSI oscillator clock used as USART2 clock source /
	345	#endif /* RCC_CFGR3_USART2SW */
	346	#if defined(RCC_CFGR3_USART3SW)
	347	#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) \| RCC_CFGR3_USART3SW_PCLK) /!< PCLK1 clock used as USART3 clock source /
	348	#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) \| RCC_CFGR3_USART3SW_SYSCLK) /!< System clock selected as USART3 clock source /
	349	#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) \| RCC_CFGR3_USART3SW_LSE) /!< LSE oscillator clock used as USART3 clock source /
	350	#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) \| RCC_CFGR3_USART3SW_HSI) /!< HSI oscillator clock used as USART3 clock source /
	351	#endif /* RCC_CFGR3_USART3SW */
	352	/**
	353	* @}
	354	*/
	355
	356	/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
	357	* @{
	358	*/
	359	#define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /!< HSI oscillator clock used as I2C1 clock source /
	360	#define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /!< System clock selected as I2C1 clock source /
	361	/**
	362	* @}
	363	*/
	364
	365	#if defined(CEC)
	366	/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
	367	* @{
	368	*/
	369	#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /!< HSI clock divided by 244 selected as HDMI CEC entry clock source /
	370	#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /!< LSE clock selected as HDMI CEC entry clock source /
	371	/**
	372	* @}
	373	*/
	374
	375	#endif /* CEC */
	376
	377	#if defined(USB)
	378	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
	379	* @{
	380	*/
	381	#if defined(RCC_CFGR3_USBSW_HSI48)
	382	#define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /!< HSI48 oscillator clock used as USB clock source /
	383	#else
	384	#define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /!< USB Clock disabled /
	385	#endif /RCC_CFGR3_USBSW_HSI48/
	386	#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /!< PLL selected as USB clock source /
	387	/**
	388	* @}
	389	*/
	390
	391	#endif /* USB */
	392
	393	/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
	394	* @{
	395	*/
	396	#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /!< USART1 Clock source selection /
	397	#if defined(RCC_CFGR3_USART2SW)
	398	#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /!< USART2 Clock source selection /
	399	#endif /* RCC_CFGR3_USART2SW */
	400	#if defined(RCC_CFGR3_USART3SW)
	401	#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /!< USART3 Clock source selection /
	402	#endif /* RCC_CFGR3_USART3SW */
	403	/**
	404	* @}
	405	*/
	406
	407	/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
	408	* @{
	409	*/
	410	#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /!< I2C1 Clock source selection /
	411	/**
	412	* @}
	413	*/
	414
	415	#if defined(CEC)
	416	/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
	417	* @{
	418	*/
	419	#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /!< CEC Clock source selection /
	420	/**
	421	* @}
	422	*/
	423	#endif /* CEC */
	424
	425	#if defined(USB)
	426	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
	427	* @{
	428	*/
	429	#define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /!< USB Clock source selection /
	430	/**
	431	* @}
	432	*/
	433	#endif /* USB */
	434
	435	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
	436	* @{
	437	*/
	438	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
	439	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
	440	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
	441	#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
	442	/**
	443	* @}
	444	*/
	445
	446	/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
	447	* @{
	448	*/
	449	#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /!< PLL input clock2 */
	450	#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /!< PLL input clock3 */
	451	#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /!< PLL input clock4 */
	452	#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /!< PLL input clock5 */
	453	#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /!< PLL input clock6 */
	454	#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /!< PLL input clock7 */
	455	#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /!< PLL input clock8 */
	456	#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /!< PLL input clock9 */
	457	#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /!< PLL input clock10 */
	458	#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /!< PLL input clock11 */
	459	#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /!< PLL input clock12 */
	460	#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /!< PLL input clock13 */
	461	#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /!< PLL input clock14 */
	462	#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /!< PLL input clock15 */
	463	#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /!< PLL input clock16 */
	464	/**
	465	* @}
	466	*/
	467
	468	/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
	469	* @{
	470	*/
	471	#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /!< HSE/PREDIV clock selected as PLL entry clock source /
	472	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
	473	#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /!< HSI/PREDIV clock selected as PLL entry clock source /
	474	#if defined(RCC_CFGR_SW_HSI48)
	475	#define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /!< HSI48/PREDIV clock selected as PLL entry clock source /
	476	#endif /* RCC_CFGR_SW_HSI48 */
	477	#else
	478	#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /!< HSI clock divided by 2 selected as PLL entry clock source /
	479	#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV1) /!< HSE clock selected as PLL entry clock source /
	480	#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV2) /!< HSE/2 clock selected as PLL entry clock source /
	481	#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV3) /!< HSE/3 clock selected as PLL entry clock source /
	482	#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV4) /!< HSE/4 clock selected as PLL entry clock source /
	483	#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV5) /!< HSE/5 clock selected as PLL entry clock source /
	484	#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV6) /!< HSE/6 clock selected as PLL entry clock source /
	485	#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV7) /!< HSE/7 clock selected as PLL entry clock source /
	486	#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV8) /!< HSE/8 clock selected as PLL entry clock source /
	487	#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV9) /!< HSE/9 clock selected as PLL entry clock source /
	488	#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV10) /!< HSE/10 clock selected as PLL entry clock source /
	489	#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV11) /!< HSE/11 clock selected as PLL entry clock source /
	490	#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV12) /!< HSE/12 clock selected as PLL entry clock source /
	491	#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV13) /!< HSE/13 clock selected as PLL entry clock source /
	492	#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV14) /!< HSE/14 clock selected as PLL entry clock source /
	493	#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV15) /!< HSE/15 clock selected as PLL entry clock source /
	494	#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV16) /!< HSE/16 clock selected as PLL entry clock source /
	495	#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
	496	/**
	497	* @}
	498	*/
	499
	500	/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
	501	* @{
	502	*/
	503	#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /!< PREDIV input clock not divided /
	504	#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /!< PREDIV input clock divided by 2 /
	505	#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /!< PREDIV input clock divided by 3 /
	506	#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /!< PREDIV input clock divided by 4 /
	507	#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /!< PREDIV input clock divided by 5 /
	508	#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /!< PREDIV input clock divided by 6 /
	509	#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /!< PREDIV input clock divided by 7 /
	510	#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /!< PREDIV input clock divided by 8 /
	511	#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /!< PREDIV input clock divided by 9 /
	512	#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /!< PREDIV input clock divided by 10 /
	513	#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /!< PREDIV input clock divided by 11 /
	514	#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /!< PREDIV input clock divided by 12 /
	515	#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /!< PREDIV input clock divided by 13 /
	516	#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /!< PREDIV input clock divided by 14 /
	517	#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /!< PREDIV input clock divided by 15 /
	518	#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /!< PREDIV input clock divided by 16 /
	519	/**
	520	* @}
	521	*/
	522
	523	/**
	524	* @}
	525	*/
	526
	527	/* Exported macro ------------------------------------------------------------*/
	528	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
	529	* @{
	530	*/
	531
	532	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
	533	* @{
	534	*/
	535
	536	/**
	537	* @brief Write a value in RCC register
	538	* @param __REG__ Register to be written
	539	* @param __VALUE__ Value to be written in the register
	540	* @retval None
	541	*/
	542	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
	543
	544	/**
	545	* @brief Read a value in RCC register
	546	* @param __REG__ Register to be read
	547	* @retval Register value
	548	*/
	549	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
	550	/**
	551	* @}
	552	*/
	553
	554	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
	555	* @{
	556	*/
	557
	558	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
	559	/**
	560	* @brief Helper macro to calculate the PLLCLK frequency
	561	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator()
	562	* , @ref LL_RCC_PLL_GetPrediv());
	563	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48)
	564	* @param __PLLMUL__ This parameter can be one of the following values:
	565	* @arg @ref LL_RCC_PLL_MUL_2
	566	* @arg @ref LL_RCC_PLL_MUL_3
	567	* @arg @ref LL_RCC_PLL_MUL_4
	568	* @arg @ref LL_RCC_PLL_MUL_5
	569	* @arg @ref LL_RCC_PLL_MUL_6
	570	* @arg @ref LL_RCC_PLL_MUL_7
	571	* @arg @ref LL_RCC_PLL_MUL_8
	572	* @arg @ref LL_RCC_PLL_MUL_9
	573	* @arg @ref LL_RCC_PLL_MUL_10
	574	* @arg @ref LL_RCC_PLL_MUL_11
	575	* @arg @ref LL_RCC_PLL_MUL_12
	576	* @arg @ref LL_RCC_PLL_MUL_13
	577	* @arg @ref LL_RCC_PLL_MUL_14
	578	* @arg @ref LL_RCC_PLL_MUL_15
	579	* @arg @ref LL_RCC_PLL_MUL_16
	580	* @param __PLLPREDIV__ This parameter can be one of the following values:
	581	* @arg @ref LL_RCC_PREDIV_DIV_1
	582	* @arg @ref LL_RCC_PREDIV_DIV_2
	583	* @arg @ref LL_RCC_PREDIV_DIV_3
	584	* @arg @ref LL_RCC_PREDIV_DIV_4
	585	* @arg @ref LL_RCC_PREDIV_DIV_5
	586	* @arg @ref LL_RCC_PREDIV_DIV_6
	587	* @arg @ref LL_RCC_PREDIV_DIV_7
	588	* @arg @ref LL_RCC_PREDIV_DIV_8
	589	* @arg @ref LL_RCC_PREDIV_DIV_9
	590	* @arg @ref LL_RCC_PREDIV_DIV_10
	591	* @arg @ref LL_RCC_PREDIV_DIV_11
	592	* @arg @ref LL_RCC_PREDIV_DIV_12
	593	* @arg @ref LL_RCC_PREDIV_DIV_13
	594	* @arg @ref LL_RCC_PREDIV_DIV_14
	595	* @arg @ref LL_RCC_PREDIV_DIV_15
	596	* @arg @ref LL_RCC_PREDIV_DIV_16
	597	* @retval PLL clock frequency (in Hz)
	598	*/
	599	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
	600	(((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
	601
	602	#else
	603	/**
	604	* @brief Helper macro to calculate the PLLCLK frequency
	605	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
	606	* @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
	607	* @param __PLLMUL__ This parameter can be one of the following values:
	608	* @arg @ref LL_RCC_PLL_MUL_2
	609	* @arg @ref LL_RCC_PLL_MUL_3
	610	* @arg @ref LL_RCC_PLL_MUL_4
	611	* @arg @ref LL_RCC_PLL_MUL_5
	612	* @arg @ref LL_RCC_PLL_MUL_6
	613	* @arg @ref LL_RCC_PLL_MUL_7
	614	* @arg @ref LL_RCC_PLL_MUL_8
	615	* @arg @ref LL_RCC_PLL_MUL_9
	616	* @arg @ref LL_RCC_PLL_MUL_10
	617	* @arg @ref LL_RCC_PLL_MUL_11
	618	* @arg @ref LL_RCC_PLL_MUL_12
	619	* @arg @ref LL_RCC_PLL_MUL_13
	620	* @arg @ref LL_RCC_PLL_MUL_14
	621	* @arg @ref LL_RCC_PLL_MUL_15
	622	* @arg @ref LL_RCC_PLL_MUL_16
	623	* @retval PLL clock frequency (in Hz)
	624	*/
	625	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
	626	((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
	627	#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
	628	/**
	629	* @brief Helper macro to calculate the HCLK frequency
	630	* @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
	631	* ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
	632	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
	633	* @param __AHBPRESCALER__ This parameter can be one of the following values:
	634	* @arg @ref LL_RCC_SYSCLK_DIV_1
	635	* @arg @ref LL_RCC_SYSCLK_DIV_2
	636	* @arg @ref LL_RCC_SYSCLK_DIV_4
	637	* @arg @ref LL_RCC_SYSCLK_DIV_8
	638	* @arg @ref LL_RCC_SYSCLK_DIV_16
	639	* @arg @ref LL_RCC_SYSCLK_DIV_64
	640	* @arg @ref LL_RCC_SYSCLK_DIV_128
	641	* @arg @ref LL_RCC_SYSCLK_DIV_256
	642	* @arg @ref LL_RCC_SYSCLK_DIV_512
	643	* @retval HCLK clock frequency (in Hz)
	644	*/
	645	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
	646
	647	/**
	648	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
	649	* @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
	650	* ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
	651	* @param __HCLKFREQ__ HCLK frequency
	652	* @param __APB1PRESCALER__ This parameter can be one of the following values:
	653	* @arg @ref LL_RCC_APB1_DIV_1
	654	* @arg @ref LL_RCC_APB1_DIV_2
	655	* @arg @ref LL_RCC_APB1_DIV_4
	656	* @arg @ref LL_RCC_APB1_DIV_8
	657	* @arg @ref LL_RCC_APB1_DIV_16
	658	* @retval PCLK1 clock frequency (in Hz)
	659	*/
	660	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos])
	661
	662	/**
	663	* @}
	664	*/
	665
	666	/**
	667	* @}
	668	*/
	669
	670	/* Exported functions --------------------------------------------------------*/
	671	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
	672	* @{
	673	*/
	674
	675	/** @defgroup RCC_LL_EF_HSE HSE
	676	* @{
	677	*/
	678
	679	/**
	680	* @brief Enable the Clock Security System.
	681	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
	682	* @retval None
	683	*/
	684	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
	685	{
	686	SET_BIT(RCC->CR, RCC_CR_CSSON);
	687	}
	688
	689	/**
	690	* @brief Disable the Clock Security System.
	691	* @note Cannot be disabled in HSE is ready (only by hardware)
	692	* @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
	693	* @retval None
	694	*/
	695	__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
	696	{
	697	CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
	698	}
	699
	700	/**
	701	* @brief Enable HSE external oscillator (HSE Bypass)
	702	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
	703	* @retval None
	704	*/
	705	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
	706	{
	707	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
	708	}
	709
	710	/**
	711	* @brief Disable HSE external oscillator (HSE Bypass)
	712	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
	713	* @retval None
	714	*/
	715	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
	716	{
	717	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
	718	}
	719
	720	/**
	721	* @brief Enable HSE crystal oscillator (HSE ON)
	722	* @rmtoll CR HSEON LL_RCC_HSE_Enable
	723	* @retval None
	724	*/
	725	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
	726	{
	727	SET_BIT(RCC->CR, RCC_CR_HSEON);
	728	}
	729
	730	/**
	731	* @brief Disable HSE crystal oscillator (HSE ON)
	732	* @rmtoll CR HSEON LL_RCC_HSE_Disable
	733	* @retval None
	734	*/
	735	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
	736	{
	737	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
	738	}
	739
	740	/**
	741	* @brief Check if HSE oscillator Ready
	742	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
	743	* @retval State of bit (1 or 0).
	744	*/
	745	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
	746	{
	747	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
	748	}
	749
	750	/**
	751	* @}
	752	*/
	753
	754	/** @defgroup RCC_LL_EF_HSI HSI
	755	* @{
	756	*/
	757
	758	/**
	759	* @brief Enable HSI oscillator
	760	* @rmtoll CR HSION LL_RCC_HSI_Enable
	761	* @retval None
	762	*/
	763	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
	764	{
	765	SET_BIT(RCC->CR, RCC_CR_HSION);
	766	}
	767
	768	/**
	769	* @brief Disable HSI oscillator
	770	* @rmtoll CR HSION LL_RCC_HSI_Disable
	771	* @retval None
	772	*/
	773	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
	774	{
	775	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
	776	}
	777
	778	/**
	779	* @brief Check if HSI clock is ready
	780	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
	781	* @retval State of bit (1 or 0).
	782	*/
	783	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
	784	{
	785	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
	786	}
	787
	788	/**
	789	* @brief Get HSI Calibration value
	790	* @note When HSITRIM is written, HSICAL is updated with the sum of
	791	* HSITRIM and the factory trim value
	792	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
	793	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
	794	*/
	795	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
	796	{
	797	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
	798	}
	799
	800	/**
	801	* @brief Set HSI Calibration trimming
	802	* @note user-programmable trimming value that is added to the HSICAL
	803	* @note Default value is 16, which, when added to the HSICAL value,
	804	* should trim the HSI to 16 MHz +/- 1 %
	805	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
	806	* @param Value between Min_Data = 0x00 and Max_Data = 0x1F
	807	* @retval None
	808	*/
	809	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
	810	{
	811	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
	812	}
	813
	814	/**
	815	* @brief Get HSI Calibration trimming
	816	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
	817	* @retval Between Min_Data = 0x00 and Max_Data = 0x1F
	818	*/
	819	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
	820	{
	821	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
	822	}
	823
	824	/**
	825	* @}
	826	*/
	827
	828	#if defined(RCC_HSI48_SUPPORT)
	829	/** @defgroup RCC_LL_EF_HSI48 HSI48
	830	* @{
	831	*/
	832
	833	/**
	834	* @brief Enable HSI48
	835	* @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable
	836	* @retval None
	837	*/
	838	__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
	839	{
	840	SET_BIT(RCC->CR2, RCC_CR2_HSI48ON);
	841	}
	842
	843	/**
	844	* @brief Disable HSI48
	845	* @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable
	846	* @retval None
	847	*/
	848	__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
	849	{
	850	CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON);
	851	}
	852
	853	/**
	854	* @brief Check if HSI48 oscillator Ready
	855	* @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady
	856	* @retval State of bit (1 or 0).
	857	*/
	858	__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
	859	{
	860	return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY));
	861	}
	862
	863	/**
	864	* @brief Get HSI48 Calibration value
	865	* @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration
	866	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
	867	*/
	868	__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
	869	{
	870	return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL);
	871	}
	872
	873	/**
	874	* @}
	875	*/
	876
	877	#endif /* RCC_HSI48_SUPPORT */
	878
	879	/** @defgroup RCC_LL_EF_HSI14 HSI14
	880	* @{
	881	*/
	882
	883	/**
	884	* @brief Enable HSI14
	885	* @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable
	886	* @retval None
	887	*/
	888	__STATIC_INLINE void LL_RCC_HSI14_Enable(void)
	889	{
	890	SET_BIT(RCC->CR2, RCC_CR2_HSI14ON);
	891	}
	892
	893	/**
	894	* @brief Disable HSI14
	895	* @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable
	896	* @retval None
	897	*/
	898	__STATIC_INLINE void LL_RCC_HSI14_Disable(void)
	899	{
	900	CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON);
	901	}
	902
	903	/**
	904	* @brief Check if HSI14 oscillator Ready
	905	* @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady
	906	* @retval State of bit (1 or 0).
	907	*/
	908	__STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void)
	909	{
	910	return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY));
	911	}
	912
	913	/**
	914	* @brief ADC interface can turn on the HSI14 oscillator
	915	* @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl
	916	* @retval None
	917	*/
	918	__STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void)
	919	{
	920	CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS);
	921	}
	922
	923	/**
	924	* @brief ADC interface can not turn on the HSI14 oscillator
	925	* @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl
	926	* @retval None
	927	*/
	928	__STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void)
	929	{
	930	SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS);
	931	}
	932
	933	/**
	934	* @brief Set HSI14 Calibration trimming
	935	* @note user-programmable trimming value that is added to the HSI14CAL
	936	* @note Default value is 16, which, when added to the HSI14CAL value,
	937	* should trim the HSI14 to 14 MHz +/- 1 %
	938	* @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming
	939	* @param Value between Min_Data = 0x00 and Max_Data = 0xFF
	940	* @retval None
	941	*/
	942	__STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value)
	943	{
	944	MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM);
	945	}
	946
	947	/**
	948	* @brief Get HSI14 Calibration value
	949	* @note When HSI14TRIM is written, HSI14CAL is updated with the sum of
	950	* HSI14TRIM and the factory trim value
	951	* @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming
	952	* @retval Between Min_Data = 0x00 and Max_Data = 0x1F
	953	*/
	954	__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void)
	955	{
	956	return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM);
	957	}
	958
	959	/**
	960	* @brief Get HSI14 Calibration trimming
	961	* @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration
	962	* @retval Between Min_Data = 0x00 and Max_Data = 0x1F
	963	*/
	964	__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void)
	965	{
	966	return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL);
	967	}
	968
	969	/**
	970	* @}
	971	*/
	972
	973	/** @defgroup RCC_LL_EF_LSE LSE
	974	* @{
	975	*/
	976
	977	/**
	978	* @brief Enable Low Speed External (LSE) crystal.
	979	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
	980	* @retval None
	981	*/
	982	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
	983	{
	984	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
	985	}
	986
	987	/**
	988	* @brief Disable Low Speed External (LSE) crystal.
	989	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
	990	* @retval None
	991	*/
	992	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
	993	{
	994	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
	995	}
	996
	997	/**
	998	* @brief Enable external clock source (LSE bypass).
	999	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
	1000	* @retval None
	1001	*/
	1002	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
	1003	{
	1004	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
	1005	}
	1006
	1007	/**
	1008	* @brief Disable external clock source (LSE bypass).
	1009	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
	1010	* @retval None
	1011	*/
	1012	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
	1013	{
	1014	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
	1015	}
	1016
	1017	/**
	1018	* @brief Set LSE oscillator drive capability
	1019	* @note The oscillator is in Xtal mode when it is not in bypass mode.
	1020	* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
	1021	* @param LSEDrive This parameter can be one of the following values:
	1022	* @arg @ref LL_RCC_LSEDRIVE_LOW
	1023	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
	1024	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
	1025	* @arg @ref LL_RCC_LSEDRIVE_HIGH
	1026	* @retval None
	1027	*/
	1028	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
	1029	{
	1030	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
	1031	}
	1032
	1033	/**
	1034	* @brief Get LSE oscillator drive capability
	1035	* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
	1036	* @retval Returned value can be one of the following values:
	1037	* @arg @ref LL_RCC_LSEDRIVE_LOW
	1038	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
	1039	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
	1040	* @arg @ref LL_RCC_LSEDRIVE_HIGH
	1041	*/
	1042	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
	1043	{
	1044	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
	1045	}
	1046
	1047	/**
	1048	* @brief Check if LSE oscillator Ready
	1049	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
	1050	* @retval State of bit (1 or 0).
	1051	*/
	1052	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
	1053	{
	1054	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
	1055	}
	1056
	1057	/**
	1058	* @}
	1059	*/
	1060
	1061	/** @defgroup RCC_LL_EF_LSI LSI
	1062	* @{
	1063	*/
	1064
	1065	/**
	1066	* @brief Enable LSI Oscillator
	1067	* @rmtoll CSR LSION LL_RCC_LSI_Enable
	1068	* @retval None
	1069	*/
	1070	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
	1071	{
	1072	SET_BIT(RCC->CSR, RCC_CSR_LSION);
	1073	}
	1074
	1075	/**
	1076	* @brief Disable LSI Oscillator
	1077	* @rmtoll CSR LSION LL_RCC_LSI_Disable
	1078	* @retval None
	1079	*/
	1080	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
	1081	{
	1082	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
	1083	}
	1084
	1085	/**
	1086	* @brief Check if LSI is Ready
	1087	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
	1088	* @retval State of bit (1 or 0).
	1089	*/
	1090	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
	1091	{
	1092	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
	1093	}
	1094
	1095	/**
	1096	* @}
	1097	*/
	1098
	1099	/** @defgroup RCC_LL_EF_System System
	1100	* @{
	1101	*/
	1102
	1103	/**
	1104	* @brief Configure the system clock source
	1105	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
	1106	* @param Source This parameter can be one of the following values:
	1107	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
	1108	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
	1109	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
	1110	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*)
	1111	*
	1112	* (*) value not defined in all devices
	1113	* @retval None
	1114	*/
	1115	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
	1116	{
	1117	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
	1118	}
	1119
	1120	/**
	1121	* @brief Get the system clock source
	1122	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
	1123	* @retval Returned value can be one of the following values:
	1124	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
	1125	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
	1126	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
	1127	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*)
	1128	*
	1129	* (*) value not defined in all devices
	1130	*/
	1131	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
	1132	{
	1133	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
	1134	}
	1135
	1136	/**
	1137	* @brief Set AHB prescaler
	1138	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
	1139	* @param Prescaler This parameter can be one of the following values:
	1140	* @arg @ref LL_RCC_SYSCLK_DIV_1
	1141	* @arg @ref LL_RCC_SYSCLK_DIV_2
	1142	* @arg @ref LL_RCC_SYSCLK_DIV_4
	1143	* @arg @ref LL_RCC_SYSCLK_DIV_8
	1144	* @arg @ref LL_RCC_SYSCLK_DIV_16
	1145	* @arg @ref LL_RCC_SYSCLK_DIV_64
	1146	* @arg @ref LL_RCC_SYSCLK_DIV_128
	1147	* @arg @ref LL_RCC_SYSCLK_DIV_256
	1148	* @arg @ref LL_RCC_SYSCLK_DIV_512
	1149	* @retval None
	1150	*/
	1151	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
	1152	{
	1153	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
	1154	}
	1155
	1156	/**
	1157	* @brief Set APB1 prescaler
	1158	* @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler
	1159	* @param Prescaler This parameter can be one of the following values:
	1160	* @arg @ref LL_RCC_APB1_DIV_1
	1161	* @arg @ref LL_RCC_APB1_DIV_2
	1162	* @arg @ref LL_RCC_APB1_DIV_4
	1163	* @arg @ref LL_RCC_APB1_DIV_8
	1164	* @arg @ref LL_RCC_APB1_DIV_16
	1165	* @retval None
	1166	*/
	1167	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
	1168	{
	1169	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
	1170	}
	1171
	1172	/**
	1173	* @brief Get AHB prescaler
	1174	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
	1175	* @retval Returned value can be one of the following values:
	1176	* @arg @ref LL_RCC_SYSCLK_DIV_1
	1177	* @arg @ref LL_RCC_SYSCLK_DIV_2
	1178	* @arg @ref LL_RCC_SYSCLK_DIV_4
	1179	* @arg @ref LL_RCC_SYSCLK_DIV_8
	1180	* @arg @ref LL_RCC_SYSCLK_DIV_16
	1181	* @arg @ref LL_RCC_SYSCLK_DIV_64
	1182	* @arg @ref LL_RCC_SYSCLK_DIV_128
	1183	* @arg @ref LL_RCC_SYSCLK_DIV_256
	1184	* @arg @ref LL_RCC_SYSCLK_DIV_512
	1185	*/
	1186	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
	1187	{
	1188	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
	1189	}
	1190
	1191	/**
	1192	* @brief Get APB1 prescaler
	1193	* @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler
	1194	* @retval Returned value can be one of the following values:
	1195	* @arg @ref LL_RCC_APB1_DIV_1
	1196	* @arg @ref LL_RCC_APB1_DIV_2
	1197	* @arg @ref LL_RCC_APB1_DIV_4
	1198	* @arg @ref LL_RCC_APB1_DIV_8
	1199	* @arg @ref LL_RCC_APB1_DIV_16
	1200	*/
	1201	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
	1202	{
	1203	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
	1204	}
	1205
	1206	/**
	1207	* @}
	1208	*/
	1209
	1210	/** @defgroup RCC_LL_EF_MCO MCO
	1211	* @{
	1212	*/
	1213
	1214	/**
	1215	* @brief Configure MCOx
	1216	* @rmtoll CFGR MCO LL_RCC_ConfigMCO\n
	1217	* CFGR MCOPRE LL_RCC_ConfigMCO\n
	1218	* CFGR PLLNODIV LL_RCC_ConfigMCO
	1219	* @param MCOxSource This parameter can be one of the following values:
	1220	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
	1221	* @arg @ref LL_RCC_MCO1SOURCE_HSI14
	1222	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
	1223	* @arg @ref LL_RCC_MCO1SOURCE_HSI
	1224	* @arg @ref LL_RCC_MCO1SOURCE_HSE
	1225	* @arg @ref LL_RCC_MCO1SOURCE_LSI
	1226	* @arg @ref LL_RCC_MCO1SOURCE_LSE
	1227	* @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
	1228	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*)
	1229	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
	1230	*
	1231	* (*) value not defined in all devices
	1232	* @param MCOxPrescaler This parameter can be one of the following values:
	1233	* @arg @ref LL_RCC_MCO1_DIV_1
	1234	* @arg @ref LL_RCC_MCO1_DIV_2 (*)
	1235	* @arg @ref LL_RCC_MCO1_DIV_4 (*)
	1236	* @arg @ref LL_RCC_MCO1_DIV_8 (*)
	1237	* @arg @ref LL_RCC_MCO1_DIV_16 (*)
	1238	* @arg @ref LL_RCC_MCO1_DIV_32 (*)
	1239	* @arg @ref LL_RCC_MCO1_DIV_64 (*)
	1240	* @arg @ref LL_RCC_MCO1_DIV_128 (*)
	1241	*
	1242	* (*) value not defined in all devices
	1243	* @retval None
	1244	*/
	1245	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
	1246	{
	1247	#if defined(RCC_CFGR_MCOPRE)
	1248	#if defined(RCC_CFGR_PLLNODIV)
	1249	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE \| RCC_CFGR_PLLNODIV, MCOxSource \| MCOxPrescaler);
	1250	#else
	1251	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE, MCOxSource \| MCOxPrescaler);
	1252	#endif /* RCC_CFGR_PLLNODIV */
	1253	#else
	1254	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
	1255	#endif /* RCC_CFGR_MCOPRE */
	1256	}
	1257
	1258	/**
	1259	* @}
	1260	*/
	1261
	1262	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
	1263	* @{
	1264	*/
	1265
	1266	/**
	1267	* @brief Configure USARTx clock source
	1268	* @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n
	1269	* CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n
	1270	* CFGR3 USART3SW LL_RCC_SetUSARTClockSource
	1271	* @param USARTxSource This parameter can be one of the following values:
	1272	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
	1273	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
	1274	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
	1275	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
	1276	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
	1277	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
	1278	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
	1279	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
	1280	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
	1281	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
	1282	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
	1283	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
	1284	*
	1285	* (*) value not defined in all devices.
	1286	* @retval None
	1287	*/
	1288	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
	1289	{
	1290	MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU));
	1291	}
	1292
	1293	/**
	1294	* @brief Configure I2Cx clock source
	1295	* @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource
	1296	* @param I2CxSource This parameter can be one of the following values:
	1297	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
	1298	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
	1299	* @retval None
	1300	*/
	1301	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
	1302	{
	1303	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, I2CxSource);
	1304	}
	1305
	1306	#if defined(CEC)
	1307	/**
	1308	* @brief Configure CEC clock source
	1309	* @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource
	1310	* @param CECxSource This parameter can be one of the following values:
	1311	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
	1312	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
	1313	* @retval None
	1314	*/
	1315	__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
	1316	{
	1317	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource);
	1318	}
	1319	#endif /* CEC */
	1320
	1321	#if defined(USB)
	1322	/**
	1323	* @brief Configure USB clock source
	1324	* @rmtoll CFGR3 USBSW LL_RCC_SetUSBClockSource
	1325	* @param USBxSource This parameter can be one of the following values:
	1326	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
	1327	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
	1328	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
	1329	*
	1330	* (*) value not defined in all devices.
	1331	* @retval None
	1332	*/
	1333	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
	1334	{
	1335	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, USBxSource);
	1336	}
	1337	#endif /* USB */
	1338
	1339	/**
	1340	* @brief Get USARTx clock source
	1341	* @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n
	1342	* CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n
	1343	* CFGR3 USART3SW LL_RCC_GetUSARTClockSource
	1344	* @param USARTx This parameter can be one of the following values:
	1345	* @arg @ref LL_RCC_USART1_CLKSOURCE
	1346	* @arg @ref LL_RCC_USART2_CLKSOURCE (*)
	1347	* @arg @ref LL_RCC_USART3_CLKSOURCE (*)
	1348	*
	1349	* (*) value not defined in all devices.
	1350	* @retval Returned value can be one of the following values:
	1351	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
	1352	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
	1353	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
	1354	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
	1355	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
	1356	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
	1357	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
	1358	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
	1359	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
	1360	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
	1361	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
	1362	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
	1363	*
	1364	* (*) value not defined in all devices.
	1365	*/
	1366	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
	1367	{
	1368	return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) \| (USARTx << 24U));
	1369	}
	1370
	1371	/**
	1372	* @brief Get I2Cx clock source
	1373	* @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource
	1374	* @param I2Cx This parameter can be one of the following values:
	1375	* @arg @ref LL_RCC_I2C1_CLKSOURCE
	1376	* @retval Returned value can be one of the following values:
	1377	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
	1378	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
	1379	*/
	1380	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
	1381	{
	1382	return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx));
	1383	}
	1384
	1385	#if defined(CEC)
	1386	/**
	1387	* @brief Get CEC clock source
	1388	* @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource
	1389	* @param CECx This parameter can be one of the following values:
	1390	* @arg @ref LL_RCC_CEC_CLKSOURCE
	1391	* @retval Returned value can be one of the following values:
	1392	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
	1393	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
	1394	*/
	1395	__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
	1396	{
	1397	return (uint32_t)(READ_BIT(RCC->CFGR3, CECx));
	1398	}
	1399	#endif /* CEC */
	1400
	1401	#if defined(USB)
	1402	/**
	1403	* @brief Get USBx clock source
	1404	* @rmtoll CFGR3 USBSW LL_RCC_GetUSBClockSource
	1405	* @param USBx This parameter can be one of the following values:
	1406	* @arg @ref LL_RCC_USB_CLKSOURCE
	1407	* @retval Returned value can be one of the following values:
	1408	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
	1409	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
	1410	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
	1411	*
	1412	* (*) value not defined in all devices.
	1413	*/
	1414	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
	1415	{
	1416	return (uint32_t)(READ_BIT(RCC->CFGR3, USBx));
	1417	}
	1418	#endif /* USB */
	1419
	1420	/**
	1421	* @}
	1422	*/
	1423
	1424	/** @defgroup RCC_LL_EF_RTC RTC
	1425	* @{
	1426	*/
	1427
	1428	/**
	1429	* @brief Set RTC Clock Source
	1430	* @note Once the RTC clock source has been selected, it cannot be changed any more unless
	1431	* the Backup domain is reset. The BDRST bit can be used to reset them.
	1432	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
	1433	* @param Source This parameter can be one of the following values:
	1434	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
	1435	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
	1436	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
	1437	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
	1438	* @retval None
	1439	*/
	1440	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
	1441	{
	1442	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
	1443	}
	1444
	1445	/**
	1446	* @brief Get RTC Clock Source
	1447	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
	1448	* @retval Returned value can be one of the following values:
	1449	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
	1450	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
	1451	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
	1452	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
	1453	*/
	1454	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
	1455	{
	1456	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
	1457	}
	1458
	1459	/**
	1460	* @brief Enable RTC
	1461	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
	1462	* @retval None
	1463	*/
	1464	__STATIC_INLINE void LL_RCC_EnableRTC(void)
	1465	{
	1466	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
	1467	}
	1468
	1469	/**
	1470	* @brief Disable RTC
	1471	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
	1472	* @retval None
	1473	*/
	1474	__STATIC_INLINE void LL_RCC_DisableRTC(void)
	1475	{
	1476	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
	1477	}
	1478
	1479	/**
	1480	* @brief Check if RTC has been enabled or not
	1481	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
	1482	* @retval State of bit (1 or 0).
	1483	*/
	1484	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
	1485	{
	1486	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
	1487	}
	1488
	1489	/**
	1490	* @brief Force the Backup domain reset
	1491	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
	1492	* @retval None
	1493	*/
	1494	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
	1495	{
	1496	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
	1497	}
	1498
	1499	/**
	1500	* @brief Release the Backup domain reset
	1501	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
	1502	* @retval None
	1503	*/
	1504	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
	1505	{
	1506	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
	1507	}
	1508
	1509	/**
	1510	* @}
	1511	*/
	1512
	1513	/** @defgroup RCC_LL_EF_PLL PLL
	1514	* @{
	1515	*/
	1516
	1517	/**
	1518	* @brief Enable PLL
	1519	* @rmtoll CR PLLON LL_RCC_PLL_Enable
	1520	* @retval None
	1521	*/
	1522	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
	1523	{
	1524	SET_BIT(RCC->CR, RCC_CR_PLLON);
	1525	}
	1526
	1527	/**
	1528	* @brief Disable PLL
	1529	* @note Cannot be disabled if the PLL clock is used as the system clock
	1530	* @rmtoll CR PLLON LL_RCC_PLL_Disable
	1531	* @retval None
	1532	*/
	1533	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
	1534	{
	1535	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
	1536	}
	1537
	1538	/**
	1539	* @brief Check if PLL Ready
	1540	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
	1541	* @retval State of bit (1 or 0).
	1542	*/
	1543	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
	1544	{
	1545	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
	1546	}
	1547
	1548	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
	1549	/**
	1550	* @brief Configure PLL used for SYSCLK Domain
	1551	* @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
	1552	* CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
	1553	* CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
	1554	* @param Source This parameter can be one of the following values:
	1555	* @arg @ref LL_RCC_PLLSOURCE_HSI
	1556	* @arg @ref LL_RCC_PLLSOURCE_HSE
	1557	* @arg @ref LL_RCC_PLLSOURCE_HSI48 (*)
	1558	*
	1559	* (*) value not defined in all devices
	1560	* @param PLLMul This parameter can be one of the following values:
	1561	* @arg @ref LL_RCC_PLL_MUL_2
	1562	* @arg @ref LL_RCC_PLL_MUL_3
	1563	* @arg @ref LL_RCC_PLL_MUL_4
	1564	* @arg @ref LL_RCC_PLL_MUL_5
	1565	* @arg @ref LL_RCC_PLL_MUL_6
	1566	* @arg @ref LL_RCC_PLL_MUL_7
	1567	* @arg @ref LL_RCC_PLL_MUL_8
	1568	* @arg @ref LL_RCC_PLL_MUL_9
	1569	* @arg @ref LL_RCC_PLL_MUL_10
	1570	* @arg @ref LL_RCC_PLL_MUL_11
	1571	* @arg @ref LL_RCC_PLL_MUL_12
	1572	* @arg @ref LL_RCC_PLL_MUL_13
	1573	* @arg @ref LL_RCC_PLL_MUL_14
	1574	* @arg @ref LL_RCC_PLL_MUL_15
	1575	* @arg @ref LL_RCC_PLL_MUL_16
	1576	* @param PLLDiv This parameter can be one of the following values:
	1577	* @arg @ref LL_RCC_PREDIV_DIV_1
	1578	* @arg @ref LL_RCC_PREDIV_DIV_2
	1579	* @arg @ref LL_RCC_PREDIV_DIV_3
	1580	* @arg @ref LL_RCC_PREDIV_DIV_4
	1581	* @arg @ref LL_RCC_PREDIV_DIV_5
	1582	* @arg @ref LL_RCC_PREDIV_DIV_6
	1583	* @arg @ref LL_RCC_PREDIV_DIV_7
	1584	* @arg @ref LL_RCC_PREDIV_DIV_8
	1585	* @arg @ref LL_RCC_PREDIV_DIV_9
	1586	* @arg @ref LL_RCC_PREDIV_DIV_10
	1587	* @arg @ref LL_RCC_PREDIV_DIV_11
	1588	* @arg @ref LL_RCC_PREDIV_DIV_12
	1589	* @arg @ref LL_RCC_PREDIV_DIV_13
	1590	* @arg @ref LL_RCC_PREDIV_DIV_14
	1591	* @arg @ref LL_RCC_PREDIV_DIV_15
	1592	* @arg @ref LL_RCC_PREDIV_DIV_16
	1593	* @retval None
	1594	*/
	1595	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
	1596	{
	1597	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMUL, Source \| PLLMul);
	1598	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv);
	1599	}
	1600
	1601	#else
	1602
	1603	/**
	1604	* @brief Configure PLL used for SYSCLK Domain
	1605	* @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
	1606	* CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
	1607	* CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
	1608	* @param Source This parameter can be one of the following values:
	1609	* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
	1610	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
	1611	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2
	1612	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3
	1613	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4
	1614	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5
	1615	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6
	1616	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7
	1617	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8
	1618	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9
	1619	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10
	1620	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11
	1621	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12
	1622	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13
	1623	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14
	1624	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15
	1625	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16
	1626	* @param PLLMul This parameter can be one of the following values:
	1627	* @arg @ref LL_RCC_PLL_MUL_2
	1628	* @arg @ref LL_RCC_PLL_MUL_3
	1629	* @arg @ref LL_RCC_PLL_MUL_4
	1630	* @arg @ref LL_RCC_PLL_MUL_5
	1631	* @arg @ref LL_RCC_PLL_MUL_6
	1632	* @arg @ref LL_RCC_PLL_MUL_7
	1633	* @arg @ref LL_RCC_PLL_MUL_8
	1634	* @arg @ref LL_RCC_PLL_MUL_9
	1635	* @arg @ref LL_RCC_PLL_MUL_10
	1636	* @arg @ref LL_RCC_PLL_MUL_11
	1637	* @arg @ref LL_RCC_PLL_MUL_12
	1638	* @arg @ref LL_RCC_PLL_MUL_13
	1639	* @arg @ref LL_RCC_PLL_MUL_14
	1640	* @arg @ref LL_RCC_PLL_MUL_15
	1641	* @arg @ref LL_RCC_PLL_MUL_16
	1642	* @retval None
	1643	*/
	1644	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
	1645	{
	1646	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) \| PLLMul);
	1647	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
	1648	}
	1649	#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
	1650
	1651	/**
	1652	* @brief Get the oscillator used as PLL clock source.
	1653	* @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
	1654	* @retval Returned value can be one of the following values:
	1655	* @arg @ref LL_RCC_PLLSOURCE_HSI (*)
	1656	* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
	1657	* @arg @ref LL_RCC_PLLSOURCE_HSE
	1658	* @arg @ref LL_RCC_PLLSOURCE_HSI48 (*)
	1659	*
	1660	* (*) value not defined in all devices
	1661	*/
	1662	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
	1663	{
	1664	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
	1665	}
	1666
	1667	/**
	1668	* @brief Get PLL multiplication Factor
	1669	* @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
	1670	* @retval Returned value can be one of the following values:
	1671	* @arg @ref LL_RCC_PLL_MUL_2
	1672	* @arg @ref LL_RCC_PLL_MUL_3
	1673	* @arg @ref LL_RCC_PLL_MUL_4
	1674	* @arg @ref LL_RCC_PLL_MUL_5
	1675	* @arg @ref LL_RCC_PLL_MUL_6
	1676	* @arg @ref LL_RCC_PLL_MUL_7
	1677	* @arg @ref LL_RCC_PLL_MUL_8
	1678	* @arg @ref LL_RCC_PLL_MUL_9
	1679	* @arg @ref LL_RCC_PLL_MUL_10
	1680	* @arg @ref LL_RCC_PLL_MUL_11
	1681	* @arg @ref LL_RCC_PLL_MUL_12
	1682	* @arg @ref LL_RCC_PLL_MUL_13
	1683	* @arg @ref LL_RCC_PLL_MUL_14
	1684	* @arg @ref LL_RCC_PLL_MUL_15
	1685	* @arg @ref LL_RCC_PLL_MUL_16
	1686	*/
	1687	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
	1688	{
	1689	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
	1690	}
	1691
	1692	/**
	1693	* @brief Get PREDIV division factor for the main PLL
	1694	* @note They can be written only when the PLL is disabled
	1695	* @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv
	1696	* @retval Returned value can be one of the following values:
	1697	* @arg @ref LL_RCC_PREDIV_DIV_1
	1698	* @arg @ref LL_RCC_PREDIV_DIV_2
	1699	* @arg @ref LL_RCC_PREDIV_DIV_3
	1700	* @arg @ref LL_RCC_PREDIV_DIV_4
	1701	* @arg @ref LL_RCC_PREDIV_DIV_5
	1702	* @arg @ref LL_RCC_PREDIV_DIV_6
	1703	* @arg @ref LL_RCC_PREDIV_DIV_7
	1704	* @arg @ref LL_RCC_PREDIV_DIV_8
	1705	* @arg @ref LL_RCC_PREDIV_DIV_9
	1706	* @arg @ref LL_RCC_PREDIV_DIV_10
	1707	* @arg @ref LL_RCC_PREDIV_DIV_11
	1708	* @arg @ref LL_RCC_PREDIV_DIV_12
	1709	* @arg @ref LL_RCC_PREDIV_DIV_13
	1710	* @arg @ref LL_RCC_PREDIV_DIV_14
	1711	* @arg @ref LL_RCC_PREDIV_DIV_15
	1712	* @arg @ref LL_RCC_PREDIV_DIV_16
	1713	*/
	1714	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
	1715	{
	1716	return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV));
	1717	}
	1718
	1719	/**
	1720	* @}
	1721	*/
	1722
	1723	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
	1724	* @{
	1725	*/
	1726
	1727	/**
	1728	* @brief Clear LSI ready interrupt flag
	1729	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
	1730	* @retval None
	1731	*/
	1732	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
	1733	{
	1734	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
	1735	}
	1736
	1737	/**
	1738	* @brief Clear LSE ready interrupt flag
	1739	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
	1740	* @retval None
	1741	*/
	1742	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
	1743	{
	1744	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
	1745	}
	1746
	1747	/**
	1748	* @brief Clear HSI ready interrupt flag
	1749	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
	1750	* @retval None
	1751	*/
	1752	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
	1753	{
	1754	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
	1755	}
	1756
	1757	/**
	1758	* @brief Clear HSE ready interrupt flag
	1759	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
	1760	* @retval None
	1761	*/
	1762	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
	1763	{
	1764	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
	1765	}
	1766
	1767	/**
	1768	* @brief Clear PLL ready interrupt flag
	1769	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
	1770	* @retval None
	1771	*/
	1772	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
	1773	{
	1774	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
	1775	}
	1776
	1777	/**
	1778	* @brief Clear HSI14 ready interrupt flag
	1779	* @rmtoll CIR HSI14RDYC LL_RCC_ClearFlag_HSI14RDY
	1780	* @retval None
	1781	*/
	1782	__STATIC_INLINE void LL_RCC_ClearFlag_HSI14RDY(void)
	1783	{
	1784	SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYC);
	1785	}
	1786
	1787	#if defined(RCC_HSI48_SUPPORT)
	1788	/**
	1789	* @brief Clear HSI48 ready interrupt flag
	1790	* @rmtoll CIR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
	1791	* @retval None
	1792	*/
	1793	__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
	1794	{
	1795	SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYC);
	1796	}
	1797	#endif /* RCC_HSI48_SUPPORT */
	1798
	1799	/**
	1800	* @brief Clear Clock security system interrupt flag
	1801	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
	1802	* @retval None
	1803	*/
	1804	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
	1805	{
	1806	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
	1807	}
	1808
	1809	/**
	1810	* @brief Check if LSI ready interrupt occurred or not
	1811	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
	1812	* @retval State of bit (1 or 0).
	1813	*/
	1814	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
	1815	{
	1816	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
	1817	}
	1818
	1819	/**
	1820	* @brief Check if LSE ready interrupt occurred or not
	1821	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
	1822	* @retval State of bit (1 or 0).
	1823	*/
	1824	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
	1825	{
	1826	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
	1827	}
	1828
	1829	/**
	1830	* @brief Check if HSI ready interrupt occurred or not
	1831	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
	1832	* @retval State of bit (1 or 0).
	1833	*/
	1834	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
	1835	{
	1836	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
	1837	}
	1838
	1839	/**
	1840	* @brief Check if HSE ready interrupt occurred or not
	1841	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
	1842	* @retval State of bit (1 or 0).
	1843	*/
	1844	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
	1845	{
	1846	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
	1847	}
	1848
	1849	/**
	1850	* @brief Check if PLL ready interrupt occurred or not
	1851	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
	1852	* @retval State of bit (1 or 0).
	1853	*/
	1854	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
	1855	{
	1856	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
	1857	}
	1858
	1859	/**
	1860	* @brief Check if HSI14 ready interrupt occurred or not
	1861	* @rmtoll CIR HSI14RDYF LL_RCC_IsActiveFlag_HSI14RDY
	1862	* @retval State of bit (1 or 0).
	1863	*/
	1864	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI14RDY(void)
	1865	{
	1866	return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYF) == (RCC_CIR_HSI14RDYF));
	1867	}
	1868
	1869	#if defined(RCC_HSI48_SUPPORT)
	1870	/**
	1871	* @brief Check if HSI48 ready interrupt occurred or not
	1872	* @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
	1873	* @retval State of bit (1 or 0).
	1874	*/
	1875	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
	1876	{
	1877	return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYF) == (RCC_CIR_HSI48RDYF));
	1878	}
	1879	#endif /* RCC_HSI48_SUPPORT */
	1880
	1881	/**
	1882	* @brief Check if Clock security system interrupt occurred or not
	1883	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
	1884	* @retval State of bit (1 or 0).
	1885	*/
	1886	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
	1887	{
	1888	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
	1889	}
	1890
	1891	/**
	1892	* @brief Check if RCC flag Independent Watchdog reset is set or not.
	1893	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
	1894	* @retval State of bit (1 or 0).
	1895	*/
	1896	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
	1897	{
	1898	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
	1899	}
	1900
	1901	/**
	1902	* @brief Check if RCC flag Low Power reset is set or not.
	1903	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
	1904	* @retval State of bit (1 or 0).
	1905	*/
	1906	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
	1907	{
	1908	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
	1909	}
	1910
	1911	/**
	1912	* @brief Check if RCC flag is set or not.
	1913	* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
	1914	* @retval State of bit (1 or 0).
	1915	*/
	1916	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
	1917	{
	1918	return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
	1919	}
	1920
	1921	/**
	1922	* @brief Check if RCC flag Pin reset is set or not.
	1923	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
	1924	* @retval State of bit (1 or 0).
	1925	*/
	1926	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
	1927	{
	1928	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
	1929	}
	1930
	1931	/**
	1932	* @brief Check if RCC flag POR/PDR reset is set or not.
	1933	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
	1934	* @retval State of bit (1 or 0).
	1935	*/
	1936	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
	1937	{
	1938	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
	1939	}
	1940
	1941	/**
	1942	* @brief Check if RCC flag Software reset is set or not.
	1943	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
	1944	* @retval State of bit (1 or 0).
	1945	*/
	1946	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
	1947	{
	1948	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
	1949	}
	1950
	1951	/**
	1952	* @brief Check if RCC flag Window Watchdog reset is set or not.
	1953	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
	1954	* @retval State of bit (1 or 0).
	1955	*/
	1956	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
	1957	{
	1958	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
	1959	}
	1960
	1961	#if defined(RCC_CSR_V18PWRRSTF)
	1962	/**
	1963	* @brief Check if RCC Reset flag of the 1.8 V domain is set or not.
	1964	* @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST
	1965	* @retval State of bit (1 or 0).
	1966	*/
	1967	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void)
	1968	{
	1969	return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF));
	1970	}
	1971	#endif /* RCC_CSR_V18PWRRSTF */
	1972
	1973	/**
	1974	* @brief Set RMVF bit to clear the reset flags.
	1975	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
	1976	* @retval None
	1977	*/
	1978	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
	1979	{
	1980	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
	1981	}
	1982
	1983	/**
	1984	* @}
	1985	*/
	1986
	1987	/** @defgroup RCC_LL_EF_IT_Management IT Management
	1988	* @{
	1989	*/
	1990
	1991	/**
	1992	* @brief Enable LSI ready interrupt
	1993	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
	1994	* @retval None
	1995	*/
	1996	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
	1997	{
	1998	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
	1999	}
	2000
	2001	/**
	2002	* @brief Enable LSE ready interrupt
	2003	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
	2004	* @retval None
	2005	*/
	2006	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
	2007	{
	2008	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
	2009	}
	2010
	2011	/**
	2012	* @brief Enable HSI ready interrupt
	2013	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
	2014	* @retval None
	2015	*/
	2016	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
	2017	{
	2018	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
	2019	}
	2020
	2021	/**
	2022	* @brief Enable HSE ready interrupt
	2023	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
	2024	* @retval None
	2025	*/
	2026	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
	2027	{
	2028	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
	2029	}
	2030
	2031	/**
	2032	* @brief Enable PLL ready interrupt
	2033	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
	2034	* @retval None
	2035	*/
	2036	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
	2037	{
	2038	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
	2039	}
	2040
	2041	/**
	2042	* @brief Enable HSI14 ready interrupt
	2043	* @rmtoll CIR HSI14RDYIE LL_RCC_EnableIT_HSI14RDY
	2044	* @retval None
	2045	*/
	2046	__STATIC_INLINE void LL_RCC_EnableIT_HSI14RDY(void)
	2047	{
	2048	SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE);
	2049	}
	2050
	2051	#if defined(RCC_HSI48_SUPPORT)
	2052	/**
	2053	* @brief Enable HSI48 ready interrupt
	2054	* @rmtoll CIR HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
	2055	* @retval None
	2056	*/
	2057	__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
	2058	{
	2059	SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE);
	2060	}
	2061	#endif /* RCC_HSI48_SUPPORT */
	2062
	2063	/**
	2064	* @brief Disable LSI ready interrupt
	2065	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
	2066	* @retval None
	2067	*/
	2068	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
	2069	{
	2070	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
	2071	}
	2072
	2073	/**
	2074	* @brief Disable LSE ready interrupt
	2075	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
	2076	* @retval None
	2077	*/
	2078	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
	2079	{
	2080	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
	2081	}
	2082
	2083	/**
	2084	* @brief Disable HSI ready interrupt
	2085	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
	2086	* @retval None
	2087	*/
	2088	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
	2089	{
	2090	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
	2091	}
	2092
	2093	/**
	2094	* @brief Disable HSE ready interrupt
	2095	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
	2096	* @retval None
	2097	*/
	2098	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
	2099	{
	2100	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
	2101	}
	2102
	2103	/**
	2104	* @brief Disable PLL ready interrupt
	2105	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
	2106	* @retval None
	2107	*/
	2108	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
	2109	{
	2110	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
	2111	}
	2112
	2113	/**
	2114	* @brief Disable HSI14 ready interrupt
	2115	* @rmtoll CIR HSI14RDYIE LL_RCC_DisableIT_HSI14RDY
	2116	* @retval None
	2117	*/
	2118	__STATIC_INLINE void LL_RCC_DisableIT_HSI14RDY(void)
	2119	{
	2120	CLEAR_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE);
	2121	}
	2122
	2123	#if defined(RCC_HSI48_SUPPORT)
	2124	/**
	2125	* @brief Disable HSI48 ready interrupt
	2126	* @rmtoll CIR HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
	2127	* @retval None
	2128	*/
	2129	__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
	2130	{
	2131	CLEAR_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE);
	2132	}
	2133	#endif /* RCC_HSI48_SUPPORT */
	2134
	2135	/**
	2136	* @brief Checks if LSI ready interrupt source is enabled or disabled.
	2137	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
	2138	* @retval State of bit (1 or 0).
	2139	*/
	2140	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
	2141	{
	2142	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
	2143	}
	2144
	2145	/**
	2146	* @brief Checks if LSE ready interrupt source is enabled or disabled.
	2147	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
	2148	* @retval State of bit (1 or 0).
	2149	*/
	2150	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
	2151	{
	2152	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
	2153	}
	2154
	2155	/**
	2156	* @brief Checks if HSI ready interrupt source is enabled or disabled.
	2157	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
	2158	* @retval State of bit (1 or 0).
	2159	*/
	2160	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
	2161	{
	2162	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
	2163	}
	2164
	2165	/**
	2166	* @brief Checks if HSE ready interrupt source is enabled or disabled.
	2167	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
	2168	* @retval State of bit (1 or 0).
	2169	*/
	2170	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
	2171	{
	2172	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
	2173	}
	2174
	2175	/**
	2176	* @brief Checks if PLL ready interrupt source is enabled or disabled.
	2177	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
	2178	* @retval State of bit (1 or 0).
	2179	*/
	2180	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
	2181	{
	2182	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
	2183	}
	2184
	2185	/**
	2186	* @brief Checks if HSI14 ready interrupt source is enabled or disabled.
	2187	* @rmtoll CIR HSI14RDYIE LL_RCC_IsEnabledIT_HSI14RDY
	2188	* @retval State of bit (1 or 0).
	2189	*/
	2190	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI14RDY(void)
	2191	{
	2192	return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE) == (RCC_CIR_HSI14RDYIE));
	2193	}
	2194
	2195	#if defined(RCC_HSI48_SUPPORT)
	2196	/**
	2197	* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
	2198	* @rmtoll CIR HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
	2199	* @retval State of bit (1 or 0).
	2200	*/
	2201	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
	2202	{
	2203	return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE) == (RCC_CIR_HSI48RDYIE));
	2204	}
	2205	#endif /* RCC_HSI48_SUPPORT */
	2206
	2207	/**
	2208	* @}
	2209	*/
	2210
	2211	#if defined(USE_FULL_LL_DRIVER)
	2212	/** @defgroup RCC_LL_EF_Init De-initialization function
	2213	* @{
	2214	*/
	2215	ErrorStatus LL_RCC_DeInit(void);
	2216	/**
	2217	* @}
	2218	*/
	2219
	2220	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
	2221	* @{
	2222	*/
	2223	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
	2224	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
	2225	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
	2226	#if defined(USB_OTG_FS) \|\| defined(USB)
	2227	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
	2228	#endif /* USB_OTG_FS \|\| USB */
	2229	#if defined(CEC)
	2230	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
	2231	#endif /* CEC */
	2232	/**
	2233	* @}
	2234	*/
	2235	#endif /* USE_FULL_LL_DRIVER */
	2236
	2237	/**
	2238	* @}
	2239	*/
	2240
	2241	/**
	2242	* @}
	2243	*/
	2244
	2245	#endif /* RCC */
	2246
	2247	/**
	2248	* @}
	2249	*/
	2250
	2251	#ifdef __cplusplus
	2252	}
	2253	#endif
	2254
	2255	#endif /* __STM32F0xx_LL_RCC_H */
	2256
	2257	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/