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2021-06-20 bfc108e6097eff2bec73050e261f3b9e5db447b7

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bfc108	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_ll_system.h
	4	* @author MCD Application Team
	5	* @brief Header file of SYSTEM LL module.
	6	@verbatim
	7	==============================================================================
	8	##### How to use this driver #####
	9	==============================================================================
	10	[..]
	11	The LL SYSTEM driver contains a set of generic APIs that can be
	12	used by user:
	13	(+) Some of the FLASH features need to be handled in the SYSTEM file.
	14	(+) Access to DBGCMU registers
	15	(+) Access to SYSCFG registers
	16
	17	@endverbatim
	18	******************************************************************************
	19	* @attention
	20	*
	21	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	22	*
	23	* Redistribution and use in source and binary forms, with or without modification,
	24	* are permitted provided that the following conditions are met:
	25	* 1. Redistributions of source code must retain the above copyright notice,
	26	* this list of conditions and the following disclaimer.
	27	* 2. Redistributions in binary form must reproduce the above copyright notice,
	28	* this list of conditions and the following disclaimer in the documentation
	29	* and/or other materials provided with the distribution.
	30	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	31	* may be used to endorse or promote products derived from this software
	32	* without specific prior written permission.
	33	*
	34	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	35	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	36	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	37	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	38	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	39	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	40	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	41	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	42	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	43	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	44	*
	45	******************************************************************************
	46	*/
	47
	48	/* Define to prevent recursive inclusion -------------------------------------*/
	49	#ifndef __STM32F0xx_LL_SYSTEM_H
	50	#define __STM32F0xx_LL_SYSTEM_H
	51
	52	#ifdef __cplusplus
	53	extern "C" {
	54	#endif
	55
	56	/* Includes ------------------------------------------------------------------*/
	57	#include "stm32f0xx.h"
	58
	59	/** @addtogroup STM32F0xx_LL_Driver
	60	* @{
	61	*/
	62
	63	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU)
	64
	65	/** @defgroup SYSTEM_LL SYSTEM
	66	* @{
	67	*/
	68
	69	/* Private types -------------------------------------------------------------*/
	70	/* Private variables ---------------------------------------------------------*/
	71
	72	/* Private constants ---------------------------------------------------------*/
	73	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
	74	* @{
	75	*/
	76
	77	/**
	78	* @}
	79	*/
	80
	81	/* Private macros ------------------------------------------------------------*/
	82
	83	/* Exported types ------------------------------------------------------------*/
	84	/* Exported constants --------------------------------------------------------*/
	85	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
	86	* @{
	87	*/
	88
	89	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap
	90	* @{
	91	*/
	92	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /!< Main Flash memory mapped at 0x00000000 /
	93	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
	94	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 \| SYSCFG_CFGR1_MEM_MODE_0) /!< Embedded SRAM mapped at 0x00000000 /
	95	/**
	96	* @}
	97	*/
	98
	99	#if defined(SYSCFG_CFGR1_IR_MOD)
	100	/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
	101	* @{
	102	*/
	103	#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /!< Timer16 is selected as IR Modulation enveloppe source /
	104	#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /!< USART1 is selected as IR Modulation enveloppe source /
	105	#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /!< USART4 is selected as IR Modulation enveloppe source /
	106	/**
	107	* @}
	108	*/
	109
	110	#endif /* SYSCFG_CFGR1_IR_MOD */
	111
	112	#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART3_DMA_RMP)
	113	/** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap
	114	* @{
	115	*/
	116	#if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP)
	117	#define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART1_TX DMA request mapped on DMA channel 2U /
	118	#define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART1TX_DMA_RMP) /!< USART1_TX DMA request mapped on DMA channel 4U /
	119	#endif /SYSCFG_CFGR1_USART1TX_DMA_RMP/
	120	#if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP)
	121	#define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART1_RX DMA request mapped on DMA channel 3U /
	122	#define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART1RX_DMA_RMP) /!< USART1_RX DMA request mapped on DMA channel 5 /
	123	#endif /SYSCFG_CFGR1_USART1RX_DMA_RMP/
	124	#if defined (SYSCFG_CFGR1_USART2_DMA_RMP)
	125	#define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4U respectively /
	126	#define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART2_DMA_RMP) /!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively /
	127	#endif /SYSCFG_CFGR1_USART2_DMA_RMP/
	128	#if defined (SYSCFG_CFGR1_USART3_DMA_RMP)
	129	#define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively /
	130	#define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART3_DMA_RMP) /!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 3U and 2U respectively /
	131	#endif /* SYSCFG_CFGR1_USART3_DMA_RMP */
	132	/**
	133	* @}
	134	*/
	135	#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP \|\| SYSCFG_CFGR1_USART1RX_DMA_RMP \|\| SYSCFG_CFGR1_USART2_DMA_RMP \|\| SYSCFG_CFGR1_USART3_DMA_RMP */
	136
	137	#if defined (SYSCFG_CFGR1_SPI2_DMA_RMP)
	138	/** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap
	139	* @{
	140	*/
	141	#define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4U and 5 respectively /
	142	#define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively /
	143	/**
	144	* @}
	145	*/
	146
	147	#endif /SYSCFG_CFGR1_SPI2_DMA_RMP/
	148
	149	#if defined (SYSCFG_CFGR1_I2C1_DMA_RMP)
	150	/** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap
	151	* @{
	152	*/
	153	#define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3U and 2U respectively /
	154	#define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively /
	155	/**
	156	* @}
	157	*/
	158
	159	#endif /SYSCFG_CFGR1_I2C1_DMA_RMP/
	160
	161	#if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
	162	/** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap
	163	* @{
	164	*/
	165	#define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /!< ADC DMA request mapped on DMA channel 1U /
	166	#define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /!< ADC DMA request mapped on DMA channel 2U /
	167	/**
	168	* @}
	169	*/
	170
	171	#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
	172
	173	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM17_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM1_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
	174	/** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap
	175	* @{
	176	*/
	177	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP)
	178	#if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2)
	179	#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP \| SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) \| (uint32_t)0x00000000U) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 /
	180	#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP \| SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 /
	181	#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP2) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6 /
	182	#else
	183	#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 /
	184	#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 /
	185	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */
	186	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */
	187	#if defined(SYSCFG_CFGR1_TIM17_DMA_RMP)
	188	#if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2)
	189	#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP \| SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) \| (uint32_t)0x00000000U) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 /
	190	#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP \| SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 /
	191	#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP2) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7 /
	192	#else
	193	#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 /
	194	#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 /
	195	#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */
	196	#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */
	197	#if defined (SYSCFG_CFGR1_TIM1_DMA_RMP)
	198	#define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMAchannel 2, 3 and 4 respectively /
	199	#define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM1_DMA_RMP) /!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 /
	200	#endif /SYSCFG_CFGR1_TIM1_DMA_RMP/
	201	#if defined (SYSCFG_CFGR1_TIM2_DMA_RMP)
	202	#define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively /
	203	#define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM2_DMA_RMP) /!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 /
	204	#endif /SYSCFG_CFGR1_TIM2_DMA_RMP/
	205	#if defined (SYSCFG_CFGR1_TIM3_DMA_RMP)
	206	#define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 /
	207	#define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM3_DMA_RMP) /!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 /
	208	#endif /SYSCFG_CFGR1_TIM3_DMA_RMP/
	209	/**
	210	* @}
	211	*/
	212
	213	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP \|\| SYSCFG_CFGR1_TIM17_DMA_RMP \|\| SYSCFG_CFGR1_TIM1_DMA_RMP \|\| SYSCFG_CFGR1_TIM2_DMA_RMP \|\| SYSCFG_CFGR1_TIM3_DMA_RMP */
	214
	215	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
	216	* @{
	217	*/
	218	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /!< I2C PB6 Fast mode plus /
	219	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /!< I2C PB7 Fast mode plus /
	220	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /!< I2C PB8 Fast mode plus /
	221	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /!< I2C PB9 Fast mode plus /
	222	#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
	223	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 /
	224	#endif /SYSCFG_CFGR1_I2C_FMP_I2C1/
	225	#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
	226	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /!< Enable I2C2 Fast mode plus /
	227	#endif /SYSCFG_CFGR1_I2C_FMP_I2C2/
	228	#if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
	229	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /!< Enable Fast Mode Plus on PA9 /
	230	#endif /SYSCFG_CFGR1_I2C_FMP_PA9/
	231	#if defined(SYSCFG_CFGR1_I2C_FMP_PA10)
	232	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /!< Enable Fast Mode Plus on PA10 /
	233	#endif /SYSCFG_CFGR1_I2C_FMP_PA10/
	234	/**
	235	* @}
	236	*/
	237
	238	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
	239	* @{
	240	*/
	241	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /!< EXTI PORT A /
	242	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /!< EXTI PORT B /
	243	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /!< EXTI PORT C /
	244	#if defined(GPIOD_BASE)
	245	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /!< EXTI PORT D /
	246	#endif /GPIOD_BASE/
	247	#if defined(GPIOE_BASE)
	248	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /!< EXTI PORT E /
	249	#endif /GPIOE_BASE/
	250	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /!< EXTI PORT F /
	251	/**
	252	* @}
	253	*/
	254
	255	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
	256	* @{
	257	*/
	258	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U \| 0U) /!< EXTI_POSITION_0 \| EXTICR[0] /
	259	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U \| 0U) /!< EXTI_POSITION_4 \| EXTICR[0] /
	260	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U \| 0U) /!< EXTI_POSITION_8 \| EXTICR[0] /
	261	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U \| 0U) /!< EXTI_POSITION_12 \| EXTICR[0] /
	262	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U \| 1U) /!< EXTI_POSITION_0 \| EXTICR[1] /
	263	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U \| 1U) /!< EXTI_POSITION_4 \| EXTICR[1] /
	264	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U \| 1U) /!< EXTI_POSITION_8 \| EXTICR[1] /
	265	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U \| 1U) /!< EXTI_POSITION_12 \| EXTICR[1] /
	266	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U \| 2U) /!< EXTI_POSITION_0 \| EXTICR[2] /
	267	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U \| 2U) /!< EXTI_POSITION_4 \| EXTICR[2] /
	268	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U \| 2U) /!< EXTI_POSITION_8 \| EXTICR[2] /
	269	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U \| 2U) /!< EXTI_POSITION_12 \| EXTICR[2] /
	270	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U \| 3U) /!< EXTI_POSITION_0 \| EXTICR[3] /
	271	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U \| 3U) /!< EXTI_POSITION_4 \| EXTICR[3] /
	272	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U \| 3U) /!< EXTI_POSITION_8 \| EXTICR[3] /
	273	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U \| 3U) /!< EXTI_POSITION_12 \| EXTICR[3] /
	274	/**
	275	* @}
	276	*/
	277
	278	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
	279	* @{
	280	*/
	281	#if defined(SYSCFG_CFGR2_PVD_LOCK)
	282	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection
	283	with TIM1/15/16U/17 Break Input and also
	284	the PVDE and PLS bits of the Power Control Interface */
	285	#endif /SYSCFG_CFGR2_PVD_LOCK/
	286	#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal
	287	with Break Input of TIM1/15/16/17 */
	288	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of
	289	CortexM0 with Break Input of TIM1/15/16/17 */
	290	/**
	291	* @}
	292	*/
	293
	294	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
	295	* @{
	296	*/
	297	#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
	298	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
	299	#endif /DBGMCU_APB1_FZ_DBG_TIM2_STOP/
	300	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
	301	#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
	302	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
	303	#endif /DBGMCU_APB1_FZ_DBG_TIM6_STOP/
	304	#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
	305	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
	306	#endif /DBGMCU_APB1_FZ_DBG_TIM7_STOP/
	307	#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /!< TIM14 counter stopped when core is halted /
	308	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /!< RTC Calendar frozen when core is halted /
	309	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
	310	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
	311	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /!< I2C1 SMBUS timeout mode stopped when Core is halted /
	312	#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
	313	#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /!< CAN debug stopped when Core is halted /
	314	#endif /DBGMCU_APB1_FZ_DBG_CAN_STOP/
	315	/**
	316	* @}
	317	*/
	318
	319	/** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
	320	* @{
	321	*/
	322	#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /!< TIM1 counter stopped when core is halted /
	323	#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
	324	#define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /!< TIM15 counter stopped when core is halted /
	325	#endif /DBGMCU_APB2_FZ_DBG_TIM15_STOP/
	326	#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /!< TIM16 counter stopped when core is halted /
	327	#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /!< TIM17 counter stopped when core is halted /
	328	/**
	329	* @}
	330	*/
	331
	332	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
	333	* @{
	334	*/
	335	#define LL_FLASH_LATENCY_0 0x00000000U /!< FLASH Zero Latency cycle /
	336	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /!< FLASH One Latency cycle /
	337	/**
	338	* @}
	339	*/
	340
	341	/**
	342	* @}
	343	*/
	344
	345	/* Exported macro ------------------------------------------------------------*/
	346
	347	/* Exported functions --------------------------------------------------------*/
	348	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
	349	* @{
	350	*/
	351
	352	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
	353	* @{
	354	*/
	355
	356	/**
	357	* @brief Set memory mapping at address 0x00000000
	358	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
	359	* @param Memory This parameter can be one of the following values:
	360	* @arg @ref LL_SYSCFG_REMAP_FLASH
	361	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
	362	* @arg @ref LL_SYSCFG_REMAP_SRAM
	363	* @retval None
	364	*/
	365	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
	366	{
	367	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
	368	}
	369
	370	/**
	371	* @brief Get memory mapping at address 0x00000000
	372	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
	373	* @retval Returned value can be one of the following values:
	374	* @arg @ref LL_SYSCFG_REMAP_FLASH
	375	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
	376	* @arg @ref LL_SYSCFG_REMAP_SRAM
	377	*/
	378	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
	379	{
	380	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
	381	}
	382
	383	#if defined(SYSCFG_CFGR1_IR_MOD)
	384	/**
	385	* @brief Set IR Modulation Envelope signal source.
	386	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal
	387	* @param Source This parameter can be one of the following values:
	388	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
	389	* @arg @ref LL_SYSCFG_IR_MOD_USART1
	390	* @arg @ref LL_SYSCFG_IR_MOD_USART4
	391	* @retval None
	392	*/
	393	__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
	394	{
	395	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
	396	}
	397
	398	/**
	399	* @brief Get IR Modulation Envelope signal source.
	400	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal
	401	* @retval Returned value can be one of the following values:
	402	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
	403	* @arg @ref LL_SYSCFG_IR_MOD_USART1
	404	* @arg @ref LL_SYSCFG_IR_MOD_USART4
	405	*/
	406	__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
	407	{
	408	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
	409	}
	410	#endif /* SYSCFG_CFGR1_IR_MOD */
	411
	412	#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART3_DMA_RMP)
	413	/**
	414	* @brief Set DMA request remapping bits for USART
	415	* @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
	416	* SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
	417	* SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
	418	* SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART
	419	* @param Remap This parameter can be one of the following values:
	420	* @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*)
	421	* @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*)
	422	* @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*)
	423	* @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*)
	424	* @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*)
	425	* @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*)
	426	* @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*)
	427	* @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*)
	428	*
	429	* (*) value not defined in all devices.
	430	* @retval None
	431	*/
	432	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap)
	433	{
	434	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
	435	}
	436	#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP \|\| SYSCFG_CFGR1_USART1RX_DMA_RMP \|\| SYSCFG_CFGR1_USART2_DMA_RMP \|\| SYSCFG_CFGR1_USART3_DMA_RMP */
	437
	438	#if defined(SYSCFG_CFGR1_SPI2_DMA_RMP)
	439	/**
	440	* @brief Set DMA request remapping bits for SPI
	441	* @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
	442	* @param Remap This parameter can be one of the following values:
	443	* @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45
	444	* @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67
	445	* @retval None
	446	*/
	447	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
	448	{
	449	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap);
	450	}
	451	#endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */
	452
	453	#if defined(SYSCFG_CFGR1_I2C1_DMA_RMP)
	454	/**
	455	* @brief Set DMA request remapping bits for I2C
	456	* @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
	457	* @param Remap This parameter can be one of the following values:
	458	* @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32
	459	* @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76
	460	* @retval None
	461	*/
	462	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
	463	{
	464	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap);
	465	}
	466	#endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */
	467
	468	#if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
	469	/**
	470	* @brief Set DMA request remapping bits for ADC
	471	* @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
	472	* @param Remap This parameter can be one of the following values:
	473	* @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1
	474	* @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2
	475	* @retval None
	476	*/
	477	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
	478	{
	479	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap);
	480	}
	481	#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
	482
	483	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM17_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM1_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
	484	/**
	485	* @brief Set DMA request remapping bits for TIM
	486	* @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
	487	* SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
	488	* SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
	489	* SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
	490	* SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
	491	* SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
	492	* SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
	493	* @param Remap This parameter can be one of the following values:
	494	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*)
	495	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*)
	496	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*)
	497	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*)
	498	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*)
	499	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*)
	500	* @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*)
	501	* @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*)
	502	* @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*)
	503	* @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*)
	504	* @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*)
	505	* @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*)
	506	*
	507	* (*) value not defined in all devices.
	508	* @retval None
	509	*/
	510	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
	511	{
	512	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
	513	}
	514	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP \|\| SYSCFG_CFGR1_TIM17_DMA_RMP \|\| SYSCFG_CFGR1_TIM1_DMA_RMP \|\| SYSCFG_CFGR1_TIM2_DMA_RMP \|\| SYSCFG_CFGR1_TIM3_DMA_RMP */
	515
	516	#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
	517	/**
	518	* @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
	519	* PA9/10 or PA11/12 pin pair on small pin-count packages)
	520	* @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap
	521	* @retval None
	522	*/
	523	__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void)
	524	{
	525	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
	526	}
	527
	528	/**
	529	* @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
	530	* PA9/10 or PA11/12 pin pair on small pin-count packages)
	531	* @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap
	532	* @retval None
	533	*/
	534	__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void)
	535	{
	536	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
	537	}
	538	#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
	539
	540	/**
	541	* @brief Enable the I2C fast mode plus driving capability.
	542	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n
	543	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n
	544	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n
	545	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n
	546	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n
	547	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n
	548	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n
	549	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus
	550	* @param ConfigFastModePlus This parameter can be a combination of the following values:
	551	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
	552	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
	553	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
	554	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
	555	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
	556	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
	557	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
	558	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
	559	*
	560	* (*) value not defined in all devices
	561	* @retval None
	562	*/
	563	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
	564	{
	565	SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
	566	}
	567
	568	/**
	569	* @brief Disable the I2C fast mode plus driving capability.
	570	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n
	571	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n
	572	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n
	573	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n
	574	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n
	575	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n
	576	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n
	577	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus
	578	* @param ConfigFastModePlus This parameter can be a combination of the following values:
	579	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
	580	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
	581	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
	582	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
	583	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
	584	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
	585	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
	586	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
	587	*
	588	* (*) value not defined in all devices
	589	* @retval None
	590	*/
	591	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
	592	{
	593	CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
	594	}
	595
	596	/**
	597	* @brief Configure source input for the EXTI external interrupt.
	598	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
	599	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
	600	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
	601	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
	602	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
	603	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
	604	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
	605	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
	606	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
	607	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
	608	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
	609	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
	610	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
	611	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
	612	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
	613	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
	614	* @param Port This parameter can be one of the following values:
	615	* @arg @ref LL_SYSCFG_EXTI_PORTA
	616	* @arg @ref LL_SYSCFG_EXTI_PORTB
	617	* @arg @ref LL_SYSCFG_EXTI_PORTC
	618	* @arg @ref LL_SYSCFG_EXTI_PORTD (*)
	619	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
	620	* @arg @ref LL_SYSCFG_EXTI_PORTF
	621	*
	622	* (*) value not defined in all devices
	623	* @param Line This parameter can be one of the following values:
	624	* @arg @ref LL_SYSCFG_EXTI_LINE0
	625	* @arg @ref LL_SYSCFG_EXTI_LINE1
	626	* @arg @ref LL_SYSCFG_EXTI_LINE2
	627	* @arg @ref LL_SYSCFG_EXTI_LINE3
	628	* @arg @ref LL_SYSCFG_EXTI_LINE4
	629	* @arg @ref LL_SYSCFG_EXTI_LINE5
	630	* @arg @ref LL_SYSCFG_EXTI_LINE6
	631	* @arg @ref LL_SYSCFG_EXTI_LINE7
	632	* @arg @ref LL_SYSCFG_EXTI_LINE8
	633	* @arg @ref LL_SYSCFG_EXTI_LINE9
	634	* @arg @ref LL_SYSCFG_EXTI_LINE10
	635	* @arg @ref LL_SYSCFG_EXTI_LINE11
	636	* @arg @ref LL_SYSCFG_EXTI_LINE12
	637	* @arg @ref LL_SYSCFG_EXTI_LINE13
	638	* @arg @ref LL_SYSCFG_EXTI_LINE14
	639	* @arg @ref LL_SYSCFG_EXTI_LINE15
	640	* @retval None
	641	*/
	642	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
	643	{
	644	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16));
	645	}
	646
	647	/**
	648	* @brief Get the configured defined for specific EXTI Line
	649	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
	650	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
	651	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
	652	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
	653	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
	654	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
	655	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
	656	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
	657	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
	658	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
	659	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
	660	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
	661	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
	662	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
	663	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
	664	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
	665	* @param Line This parameter can be one of the following values:
	666	* @arg @ref LL_SYSCFG_EXTI_LINE0
	667	* @arg @ref LL_SYSCFG_EXTI_LINE1
	668	* @arg @ref LL_SYSCFG_EXTI_LINE2
	669	* @arg @ref LL_SYSCFG_EXTI_LINE3
	670	* @arg @ref LL_SYSCFG_EXTI_LINE4
	671	* @arg @ref LL_SYSCFG_EXTI_LINE5
	672	* @arg @ref LL_SYSCFG_EXTI_LINE6
	673	* @arg @ref LL_SYSCFG_EXTI_LINE7
	674	* @arg @ref LL_SYSCFG_EXTI_LINE8
	675	* @arg @ref LL_SYSCFG_EXTI_LINE9
	676	* @arg @ref LL_SYSCFG_EXTI_LINE10
	677	* @arg @ref LL_SYSCFG_EXTI_LINE11
	678	* @arg @ref LL_SYSCFG_EXTI_LINE12
	679	* @arg @ref LL_SYSCFG_EXTI_LINE13
	680	* @arg @ref LL_SYSCFG_EXTI_LINE14
	681	* @arg @ref LL_SYSCFG_EXTI_LINE15
	682	* @retval Returned value can be one of the following values:
	683	* @arg @ref LL_SYSCFG_EXTI_PORTA
	684	* @arg @ref LL_SYSCFG_EXTI_PORTB
	685	* @arg @ref LL_SYSCFG_EXTI_PORTC
	686	* @arg @ref LL_SYSCFG_EXTI_PORTD (*)
	687	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
	688	* @arg @ref LL_SYSCFG_EXTI_PORTF
	689	*
	690	* (*) value not defined in all devices
	691	*/
	692	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
	693	{
	694	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) >> (Line >> 16));
	695	}
	696
	697	#if defined(SYSCFG_ITLINE0_SR_EWDG)
	698	/**
	699	* @brief Check if Window watchdog interrupt occurred or not.
	700	* @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG
	701	* @retval State of bit (1 or 0).
	702	*/
	703	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
	704	{
	705	return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG));
	706	}
	707	#endif /* SYSCFG_ITLINE0_SR_EWDG */
	708
	709	#if defined(SYSCFG_ITLINE1_SR_PVDOUT)
	710	/**
	711	* @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
	712	* @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT
	713	* @retval State of bit (1 or 0).
	714	*/
	715	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void)
	716	{
	717	return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT));
	718	}
	719	#endif /* SYSCFG_ITLINE1_SR_PVDOUT */
	720
	721	#if defined(SYSCFG_ITLINE1_SR_VDDIO2)
	722	/**
	723	* @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31).
	724	* @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2
	725	* @retval State of bit (1 or 0).
	726	*/
	727	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void)
	728	{
	729	return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2));
	730	}
	731	#endif /* SYSCFG_ITLINE1_SR_VDDIO2 */
	732
	733	#if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP)
	734	/**
	735	* @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20).
	736	* @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP
	737	* @retval State of bit (1 or 0).
	738	*/
	739	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)
	740	{
	741	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_WAKEUP));
	742	}
	743	#endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */
	744
	745	#if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP)
	746	/**
	747	* @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19).
	748	* @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP
	749	* @retval State of bit (1 or 0).
	750	*/
	751	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void)
	752	{
	753	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_TSTAMP));
	754	}
	755	#endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */
	756
	757	#if defined(SYSCFG_ITLINE2_SR_RTC_ALRA)
	758	/**
	759	* @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17).
	760	* @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA
	761	* @retval State of bit (1 or 0).
	762	*/
	763	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void)
	764	{
	765	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALRA));
	766	}
	767	#endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */
	768
	769	#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF)
	770	/**
	771	* @brief Check if Flash interface interrupt occurred or not.
	772	* @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF
	773	* @retval State of bit (1 or 0).
	774	*/
	775	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
	776	{
	777	return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF));
	778	}
	779	#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */
	780
	781	#if defined(SYSCFG_ITLINE4_SR_CRS)
	782	/**
	783	* @brief Check if Clock recovery system interrupt occurred or not.
	784	* @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS
	785	* @retval State of bit (1 or 0).
	786	*/
	787	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void)
	788	{
	789	return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS));
	790	}
	791	#endif /* SYSCFG_ITLINE4_SR_CRS */
	792
	793	#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL)
	794	/**
	795	* @brief Check if Reset and clock control interrupt occurred or not.
	796	* @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL
	797	* @retval State of bit (1 or 0).
	798	*/
	799	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
	800	{
	801	return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL));
	802	}
	803	#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */
	804
	805	#if defined(SYSCFG_ITLINE5_SR_EXTI0)
	806	/**
	807	* @brief Check if EXTI line 0 interrupt occurred or not.
	808	* @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0
	809	* @retval State of bit (1 or 0).
	810	*/
	811	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
	812	{
	813	return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0));
	814	}
	815	#endif /* SYSCFG_ITLINE5_SR_EXTI0 */
	816
	817	#if defined(SYSCFG_ITLINE5_SR_EXTI1)
	818	/**
	819	* @brief Check if EXTI line 1 interrupt occurred or not.
	820	* @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1
	821	* @retval State of bit (1 or 0).
	822	*/
	823	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
	824	{
	825	return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1));
	826	}
	827	#endif /* SYSCFG_ITLINE5_SR_EXTI1 */
	828
	829	#if defined(SYSCFG_ITLINE6_SR_EXTI2)
	830	/**
	831	* @brief Check if EXTI line 2 interrupt occurred or not.
	832	* @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2
	833	* @retval State of bit (1 or 0).
	834	*/
	835	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
	836	{
	837	return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2));
	838	}
	839	#endif /* SYSCFG_ITLINE6_SR_EXTI2 */
	840
	841	#if defined(SYSCFG_ITLINE6_SR_EXTI3)
	842	/**
	843	* @brief Check if EXTI line 3 interrupt occurred or not.
	844	* @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3
	845	* @retval State of bit (1 or 0).
	846	*/
	847	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
	848	{
	849	return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3));
	850	}
	851	#endif /* SYSCFG_ITLINE6_SR_EXTI3 */
	852
	853	#if defined(SYSCFG_ITLINE7_SR_EXTI4)
	854	/**
	855	* @brief Check if EXTI line 4 interrupt occurred or not.
	856	* @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4
	857	* @retval State of bit (1 or 0).
	858	*/
	859	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
	860	{
	861	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4));
	862	}
	863	#endif /* SYSCFG_ITLINE7_SR_EXTI4 */
	864
	865	#if defined(SYSCFG_ITLINE7_SR_EXTI5)
	866	/**
	867	* @brief Check if EXTI line 5 interrupt occurred or not.
	868	* @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5
	869	* @retval State of bit (1 or 0).
	870	*/
	871	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
	872	{
	873	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5));
	874	}
	875	#endif /* SYSCFG_ITLINE7_SR_EXTI5 */
	876
	877	#if defined(SYSCFG_ITLINE7_SR_EXTI6)
	878	/**
	879	* @brief Check if EXTI line 6 interrupt occurred or not.
	880	* @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6
	881	* @retval State of bit (1 or 0).
	882	*/
	883	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
	884	{
	885	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6));
	886	}
	887	#endif /* SYSCFG_ITLINE7_SR_EXTI6 */
	888
	889	#if defined(SYSCFG_ITLINE7_SR_EXTI7)
	890	/**
	891	* @brief Check if EXTI line 7 interrupt occurred or not.
	892	* @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7
	893	* @retval State of bit (1 or 0).
	894	*/
	895	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
	896	{
	897	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7));
	898	}
	899	#endif /* SYSCFG_ITLINE7_SR_EXTI7 */
	900
	901	#if defined(SYSCFG_ITLINE7_SR_EXTI8)
	902	/**
	903	* @brief Check if EXTI line 8 interrupt occurred or not.
	904	* @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8
	905	* @retval State of bit (1 or 0).
	906	*/
	907	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
	908	{
	909	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8));
	910	}
	911	#endif /* SYSCFG_ITLINE7_SR_EXTI8 */
	912
	913	#if defined(SYSCFG_ITLINE7_SR_EXTI9)
	914	/**
	915	* @brief Check if EXTI line 9 interrupt occurred or not.
	916	* @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9
	917	* @retval State of bit (1 or 0).
	918	*/
	919	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
	920	{
	921	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9));
	922	}
	923	#endif /* SYSCFG_ITLINE7_SR_EXTI9 */
	924
	925	#if defined(SYSCFG_ITLINE7_SR_EXTI10)
	926	/**
	927	* @brief Check if EXTI line 10 interrupt occurred or not.
	928	* @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10
	929	* @retval State of bit (1 or 0).
	930	*/
	931	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
	932	{
	933	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10));
	934	}
	935	#endif /* SYSCFG_ITLINE7_SR_EXTI10 */
	936
	937	#if defined(SYSCFG_ITLINE7_SR_EXTI11)
	938	/**
	939	* @brief Check if EXTI line 11 interrupt occurred or not.
	940	* @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11
	941	* @retval State of bit (1 or 0).
	942	*/
	943	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
	944	{
	945	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11));
	946	}
	947	#endif /* SYSCFG_ITLINE7_SR_EXTI11 */
	948
	949	#if defined(SYSCFG_ITLINE7_SR_EXTI12)
	950	/**
	951	* @brief Check if EXTI line 12 interrupt occurred or not.
	952	* @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12
	953	* @retval State of bit (1 or 0).
	954	*/
	955	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
	956	{
	957	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12));
	958	}
	959	#endif /* SYSCFG_ITLINE7_SR_EXTI12 */
	960
	961	#if defined(SYSCFG_ITLINE7_SR_EXTI13)
	962	/**
	963	* @brief Check if EXTI line 13 interrupt occurred or not.
	964	* @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13
	965	* @retval State of bit (1 or 0).
	966	*/
	967	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
	968	{
	969	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13));
	970	}
	971	#endif /* SYSCFG_ITLINE7_SR_EXTI13 */
	972
	973	#if defined(SYSCFG_ITLINE7_SR_EXTI14)
	974	/**
	975	* @brief Check if EXTI line 14 interrupt occurred or not.
	976	* @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14
	977	* @retval State of bit (1 or 0).
	978	*/
	979	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
	980	{
	981	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14));
	982	}
	983	#endif /* SYSCFG_ITLINE7_SR_EXTI14 */
	984
	985	#if defined(SYSCFG_ITLINE7_SR_EXTI15)
	986	/**
	987	* @brief Check if EXTI line 15 interrupt occurred or not.
	988	* @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15
	989	* @retval State of bit (1 or 0).
	990	*/
	991	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
	992	{
	993	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15));
	994	}
	995	#endif /* SYSCFG_ITLINE7_SR_EXTI15 */
	996
	997	#if defined(SYSCFG_ITLINE8_SR_TSC_EOA)
	998	/**
	999	* @brief Check if Touch sensing controller end of acquisition interrupt occurred or not.
	1000	* @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA
	1001	* @retval State of bit (1 or 0).
	1002	*/
	1003	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void)
	1004	{
	1005	return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA));
	1006	}
	1007	#endif /* SYSCFG_ITLINE8_SR_TSC_EOA */
	1008
	1009	#if defined(SYSCFG_ITLINE8_SR_TSC_MCE)
	1010	/**
	1011	* @brief Check if Touch sensing controller max counterror interrupt occurred or not.
	1012	* @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE
	1013	* @retval State of bit (1 or 0).
	1014	*/
	1015	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void)
	1016	{
	1017	return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE));
	1018	}
	1019	#endif /* SYSCFG_ITLINE8_SR_TSC_MCE */
	1020
	1021	#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1)
	1022	/**
	1023	* @brief Check if DMA1 channel 1 interrupt occurred or not.
	1024	* @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1
	1025	* @retval State of bit (1 or 0).
	1026	*/
	1027	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
	1028	{
	1029	return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1));
	1030	}
	1031	#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */
	1032
	1033	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2)
	1034	/**
	1035	* @brief Check if DMA1 channel 2 interrupt occurred or not.
	1036	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2
	1037	* @retval State of bit (1 or 0).
	1038	*/
	1039	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
	1040	{
	1041	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2));
	1042	}
	1043	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */
	1044
	1045	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3)
	1046	/**
	1047	* @brief Check if DMA1 channel 3 interrupt occurred or not.
	1048	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3
	1049	* @retval State of bit (1 or 0).
	1050	*/
	1051	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
	1052	{
	1053	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3));
	1054	}
	1055	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */
	1056
	1057	#if defined(SYSCFG_ITLINE10_SR_DMA2_CH1)
	1058	/**
	1059	* @brief Check if DMA2 channel 1 interrupt occurred or not.
	1060	* @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1
	1061	* @retval State of bit (1 or 0).
	1062	*/
	1063	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)
	1064	{
	1065	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2_CH1));
	1066	}
	1067	#endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */
	1068
	1069	#if defined(SYSCFG_ITLINE10_SR_DMA2_CH2)
	1070	/**
	1071	* @brief Check if DMA2 channel 2 interrupt occurred or not.
	1072	* @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2
	1073	* @retval State of bit (1 or 0).
	1074	*/
	1075	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)
	1076	{
	1077	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2_CH2));
	1078	}
	1079	#endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */
	1080
	1081	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4)
	1082	/**
	1083	* @brief Check if DMA1 channel 4 interrupt occurred or not.
	1084	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4
	1085	* @retval State of bit (1 or 0).
	1086	*/
	1087	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)
	1088	{
	1089	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4));
	1090	}
	1091	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */
	1092
	1093	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
	1094	/**
	1095	* @brief Check if DMA1 channel 5 interrupt occurred or not.
	1096	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5
	1097	* @retval State of bit (1 or 0).
	1098	*/
	1099	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)
	1100	{
	1101	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5));
	1102	}
	1103	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */
	1104
	1105	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6)
	1106	/**
	1107	* @brief Check if DMA1 channel 6 interrupt occurred or not.
	1108	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6
	1109	* @retval State of bit (1 or 0).
	1110	*/
	1111	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)
	1112	{
	1113	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6));
	1114	}
	1115	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */
	1116
	1117	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7)
	1118	/**
	1119	* @brief Check if DMA1 channel 7 interrupt occurred or not.
	1120	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7
	1121	* @retval State of bit (1 or 0).
	1122	*/
	1123	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)
	1124	{
	1125	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7));
	1126	}
	1127	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */
	1128
	1129	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3)
	1130	/**
	1131	* @brief Check if DMA2 channel 3 interrupt occurred or not.
	1132	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3
	1133	* @retval State of bit (1 or 0).
	1134	*/
	1135	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)
	1136	{
	1137	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3));
	1138	}
	1139	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */
	1140
	1141	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4)
	1142	/**
	1143	* @brief Check if DMA2 channel 4 interrupt occurred or not.
	1144	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4
	1145	* @retval State of bit (1 or 0).
	1146	*/
	1147	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)
	1148	{
	1149	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4));
	1150	}
	1151	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */
	1152
	1153	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5)
	1154	/**
	1155	* @brief Check if DMA2 channel 5 interrupt occurred or not.
	1156	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5
	1157	* @retval State of bit (1 or 0).
	1158	*/
	1159	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)
	1160	{
	1161	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5));
	1162	}
	1163	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */
	1164
	1165	#if defined(SYSCFG_ITLINE12_SR_ADC)
	1166	/**
	1167	* @brief Check if ADC interrupt occurred or not.
	1168	* @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC
	1169	* @retval State of bit (1 or 0).
	1170	*/
	1171	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
	1172	{
	1173	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC));
	1174	}
	1175	#endif /* SYSCFG_ITLINE12_SR_ADC */
	1176
	1177	#if defined(SYSCFG_ITLINE12_SR_COMP1)
	1178	/**
	1179	* @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21).
	1180	* @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1
	1181	* @retval State of bit (1 or 0).
	1182	*/
	1183	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void)
	1184	{
	1185	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1));
	1186	}
	1187	#endif /* SYSCFG_ITLINE12_SR_COMP1 */
	1188
	1189	#if defined(SYSCFG_ITLINE12_SR_COMP2)
	1190	/**
	1191	* @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22).
	1192	* @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2
	1193	* @retval State of bit (1 or 0).
	1194	*/
	1195	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void)
	1196	{
	1197	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2));
	1198	}
	1199	#endif /* SYSCFG_ITLINE12_SR_COMP2 */
	1200
	1201	#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK)
	1202	/**
	1203	* @brief Check if Timer 1 break interrupt occurred or not.
	1204	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK
	1205	* @retval State of bit (1 or 0).
	1206	*/
	1207	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
	1208	{
	1209	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK));
	1210	}
	1211	#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */
	1212
	1213	#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD)
	1214	/**
	1215	* @brief Check if Timer 1 update interrupt occurred or not.
	1216	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD
	1217	* @retval State of bit (1 or 0).
	1218	*/
	1219	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
	1220	{
	1221	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD));
	1222	}
	1223	#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */
	1224
	1225	#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG)
	1226	/**
	1227	* @brief Check if Timer 1 trigger interrupt occurred or not.
	1228	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG
	1229	* @retval State of bit (1 or 0).
	1230	*/
	1231	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
	1232	{
	1233	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG));
	1234	}
	1235	#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */
	1236
	1237	#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU)
	1238	/**
	1239	* @brief Check if Timer 1 commutation interrupt occurred or not.
	1240	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU
	1241	* @retval State of bit (1 or 0).
	1242	*/
	1243	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
	1244	{
	1245	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU));
	1246	}
	1247	#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */
	1248
	1249	#if defined(SYSCFG_ITLINE14_SR_TIM1_CC)
	1250	/**
	1251	* @brief Check if Timer 1 capture compare interrupt occurred or not.
	1252	* @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC
	1253	* @retval State of bit (1 or 0).
	1254	*/
	1255	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void)
	1256	{
	1257	return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC));
	1258	}
	1259	#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */
	1260
	1261	#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB)
	1262	/**
	1263	* @brief Check if Timer 2 interrupt occurred or not.
	1264	* @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2
	1265	* @retval State of bit (1 or 0).
	1266	*/
	1267	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void)
	1268	{
	1269	return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB));
	1270	}
	1271	#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */
	1272
	1273	#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB)
	1274	/**
	1275	* @brief Check if Timer 3 interrupt occurred or not.
	1276	* @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3
	1277	* @retval State of bit (1 or 0).
	1278	*/
	1279	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
	1280	{
	1281	return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB));
	1282	}
	1283	#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */
	1284
	1285	#if defined(SYSCFG_ITLINE17_SR_DAC)
	1286	/**
	1287	* @brief Check if DAC underrun interrupt occurred or not.
	1288	* @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC
	1289	* @retval State of bit (1 or 0).
	1290	*/
	1291	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void)
	1292	{
	1293	return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC));
	1294	}
	1295	#endif /* SYSCFG_ITLINE17_SR_DAC */
	1296
	1297	#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB)
	1298	/**
	1299	* @brief Check if Timer 6 interrupt occurred or not.
	1300	* @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6
	1301	* @retval State of bit (1 or 0).
	1302	*/
	1303	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void)
	1304	{
	1305	return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB));
	1306	}
	1307	#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */
	1308
	1309	#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB)
	1310	/**
	1311	* @brief Check if Timer 7 interrupt occurred or not.
	1312	* @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7
	1313	* @retval State of bit (1 or 0).
	1314	*/
	1315	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void)
	1316	{
	1317	return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB));
	1318	}
	1319	#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */
	1320
	1321	#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB)
	1322	/**
	1323	* @brief Check if Timer 14 interrupt occurred or not.
	1324	* @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14
	1325	* @retval State of bit (1 or 0).
	1326	*/
	1327	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void)
	1328	{
	1329	return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB));
	1330	}
	1331	#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */
	1332
	1333	#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB)
	1334	/**
	1335	* @brief Check if Timer 15 interrupt occurred or not.
	1336	* @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15
	1337	* @retval State of bit (1 or 0).
	1338	*/
	1339	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void)
	1340	{
	1341	return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB));
	1342	}
	1343	#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */
	1344
	1345	#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB)
	1346	/**
	1347	* @brief Check if Timer 16 interrupt occurred or not.
	1348	* @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16
	1349	* @retval State of bit (1 or 0).
	1350	*/
	1351	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
	1352	{
	1353	return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB));
	1354	}
	1355	#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */
	1356
	1357	#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB)
	1358	/**
	1359	* @brief Check if Timer 17 interrupt occurred or not.
	1360	* @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17
	1361	* @retval State of bit (1 or 0).
	1362	*/
	1363	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void)
	1364	{
	1365	return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB));
	1366	}
	1367	#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */
	1368
	1369	#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB)
	1370	/**
	1371	* @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
	1372	* @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1
	1373	* @retval State of bit (1 or 0).
	1374	*/
	1375	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
	1376	{
	1377	return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB));
	1378	}
	1379	#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */
	1380
	1381	#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB)
	1382	/**
	1383	* @brief Check if I2C2 interrupt occurred or not.
	1384	* @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2
	1385	* @retval State of bit (1 or 0).
	1386	*/
	1387	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void)
	1388	{
	1389	return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB));
	1390	}
	1391	#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */
	1392
	1393	#if defined(SYSCFG_ITLINE25_SR_SPI1)
	1394	/**
	1395	* @brief Check if SPI1 interrupt occurred or not.
	1396	* @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1
	1397	* @retval State of bit (1 or 0).
	1398	*/
	1399	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
	1400	{
	1401	return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1));
	1402	}
	1403	#endif /* SYSCFG_ITLINE25_SR_SPI1 */
	1404
	1405	#if defined(SYSCFG_ITLINE26_SR_SPI2)
	1406	/**
	1407	* @brief Check if SPI2 interrupt occurred or not.
	1408	* @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2
	1409	* @retval State of bit (1 or 0).
	1410	*/
	1411	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void)
	1412	{
	1413	return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2));
	1414	}
	1415	#endif /* SYSCFG_ITLINE26_SR_SPI2 */
	1416
	1417	#if defined(SYSCFG_ITLINE27_SR_USART1_GLB)
	1418	/**
	1419	* @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25.
	1420	* @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1
	1421	* @retval State of bit (1 or 0).
	1422	*/
	1423	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
	1424	{
	1425	return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB));
	1426	}
	1427	#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */
	1428
	1429	#if defined(SYSCFG_ITLINE28_SR_USART2_GLB)
	1430	/**
	1431	* @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26.
	1432	* @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2
	1433	* @retval State of bit (1 or 0).
	1434	*/
	1435	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
	1436	{
	1437	return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB));
	1438	}
	1439	#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */
	1440
	1441	#if defined(SYSCFG_ITLINE29_SR_USART3_GLB)
	1442	/**
	1443	* @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28.
	1444	* @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3
	1445	* @retval State of bit (1 or 0).
	1446	*/
	1447	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void)
	1448	{
	1449	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB));
	1450	}
	1451	#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */
	1452
	1453	#if defined(SYSCFG_ITLINE29_SR_USART4_GLB)
	1454	/**
	1455	* @brief Check if USART4 interrupt occurred or not.
	1456	* @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4
	1457	* @retval State of bit (1 or 0).
	1458	*/
	1459	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void)
	1460	{
	1461	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB));
	1462	}
	1463	#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */
	1464
	1465	#if defined(SYSCFG_ITLINE29_SR_USART5_GLB)
	1466	/**
	1467	* @brief Check if USART5 interrupt occurred or not.
	1468	* @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5
	1469	* @retval State of bit (1 or 0).
	1470	*/
	1471	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void)
	1472	{
	1473	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB));
	1474	}
	1475	#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */
	1476
	1477	#if defined(SYSCFG_ITLINE29_SR_USART6_GLB)
	1478	/**
	1479	* @brief Check if USART6 interrupt occurred or not.
	1480	* @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6
	1481	* @retval State of bit (1 or 0).
	1482	*/
	1483	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void)
	1484	{
	1485	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB));
	1486	}
	1487	#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */
	1488
	1489	#if defined(SYSCFG_ITLINE29_SR_USART7_GLB)
	1490	/**
	1491	* @brief Check if USART7 interrupt occurred or not.
	1492	* @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7
	1493	* @retval State of bit (1 or 0).
	1494	*/
	1495	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void)
	1496	{
	1497	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_USART7_GLB));
	1498	}
	1499	#endif /* SYSCFG_ITLINE29_SR_USART7_GLB */
	1500
	1501	#if defined(SYSCFG_ITLINE29_SR_USART8_GLB)
	1502	/**
	1503	* @brief Check if USART8 interrupt occurred or not.
	1504	* @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8
	1505	* @retval State of bit (1 or 0).
	1506	*/
	1507	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void)
	1508	{
	1509	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_USART8_GLB));
	1510	}
	1511	#endif /* SYSCFG_ITLINE29_SR_USART8_GLB */
	1512
	1513	#if defined(SYSCFG_ITLINE30_SR_CAN)
	1514	/**
	1515	* @brief Check if CAN interrupt occurred or not.
	1516	* @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN
	1517	* @retval State of bit (1 or 0).
	1518	*/
	1519	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void)
	1520	{
	1521	return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN));
	1522	}
	1523	#endif /* SYSCFG_ITLINE30_SR_CAN */
	1524
	1525	#if defined(SYSCFG_ITLINE30_SR_CEC)
	1526	/**
	1527	* @brief Check if CEC interrupt occurred or not, combined with EXTI line 27.
	1528	* @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC
	1529	* @retval State of bit (1 or 0).
	1530	*/
	1531	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void)
	1532	{
	1533	return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC));
	1534	}
	1535	#endif /* SYSCFG_ITLINE30_SR_CEC */
	1536
	1537	/**
	1538	* @brief Set connections to TIMx Break inputs
	1539	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
	1540	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
	1541	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
	1542	* @param Break This parameter can be a combination of the following values:
	1543	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
	1544	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
	1545	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
	1546	*
	1547	* (*) value not defined in all devices
	1548	* @retval None
	1549	*/
	1550	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
	1551	{
	1552	#if defined(SYSCFG_CFGR2_PVD_LOCK)
	1553	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK \| SYSCFG_CFGR2_PVD_LOCK, Break);
	1554	#else
	1555	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break);
	1556	#endif /SYSCFG_CFGR2_PVD_LOCK/
	1557	}
	1558
	1559	/**
	1560	* @brief Get connections to TIMx Break inputs
	1561	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
	1562	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
	1563	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
	1564	* @retval Returned value can be can be a combination of the following values:
	1565	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
	1566	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
	1567	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
	1568	*
	1569	* (*) value not defined in all devices
	1570	*/
	1571	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
	1572	{
	1573	#if defined(SYSCFG_CFGR2_PVD_LOCK)
	1574	return (uint32_t)(READ_BIT(SYSCFG->CFGR2,
	1575	SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK \| SYSCFG_CFGR2_PVD_LOCK));
	1576	#else
	1577	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK));
	1578	#endif /SYSCFG_CFGR2_PVD_LOCK/
	1579	}
	1580
	1581	/**
	1582	* @brief Check if SRAM parity error detected
	1583	* @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP
	1584	* @retval State of bit (1 or 0).
	1585	*/
	1586	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
	1587	{
	1588	return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF));
	1589	}
	1590
	1591	/**
	1592	* @brief Clear SRAM parity error flag
	1593	* @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP
	1594	* @retval None
	1595	*/
	1596	__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
	1597	{
	1598	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF);
	1599	}
	1600
	1601	/**
	1602	* @}
	1603	*/
	1604
	1605	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
	1606	* @{
	1607	*/
	1608
	1609	/**
	1610	* @brief Return the device identifier
	1611	* @note For STM32F03x devices, the device ID is 0x444
	1612	* @note For STM32F04x devices, the device ID is 0x445.
	1613	* @note For STM32F05x devices, the device ID is 0x440
	1614	* @note For STM32F07x devices, the device ID is 0x448
	1615	* @note For STM32F09x devices, the device ID is 0x442
	1616	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
	1617	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
	1618	*/
	1619	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
	1620	{
	1621	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
	1622	}
	1623
	1624	/**
	1625	* @brief Return the device revision identifier
	1626	* @note This field indicates the revision of the device.
	1627	For example, it is read as 0x1000 for Revision 1.0.
	1628	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
	1629	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
	1630	*/
	1631	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
	1632	{
	1633	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
	1634	}
	1635
	1636	/**
	1637	* @brief Enable the Debug Module during STOP mode
	1638	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
	1639	* @retval None
	1640	*/
	1641	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
	1642	{
	1643	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
	1644	}
	1645
	1646	/**
	1647	* @brief Disable the Debug Module during STOP mode
	1648	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
	1649	* @retval None
	1650	*/
	1651	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
	1652	{
	1653	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
	1654	}
	1655
	1656	/**
	1657	* @brief Enable the Debug Module during STANDBY mode
	1658	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
	1659	* @retval None
	1660	*/
	1661	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
	1662	{
	1663	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
	1664	}
	1665
	1666	/**
	1667	* @brief Disable the Debug Module during STANDBY mode
	1668	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
	1669	* @retval None
	1670	*/
	1671	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
	1672	{
	1673	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
	1674	}
	1675
	1676	/**
	1677	* @brief Freeze APB1 peripherals (group1 peripherals)
	1678	* @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
	1679	* DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
	1680	* DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
	1681	* DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
	1682	* DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
	1683	* DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
	1684	* DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
	1685	* DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
	1686	* DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
	1687	* DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
	1688	* @param Periphs This parameter can be a combination of the following values:
	1689	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
	1690	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
	1691	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
	1692	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
	1693	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
	1694	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
	1695	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
	1696	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
	1697	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
	1698	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
	1699	*
	1700	* (*) value not defined in all devices
	1701	* @retval None
	1702	*/
	1703	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
	1704	{
	1705	SET_BIT(DBGMCU->APB1FZ, Periphs);
	1706	}
	1707
	1708	/**
	1709	* @brief Unfreeze APB1 peripherals (group1 peripherals)
	1710	* @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
	1711	* DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
	1712	* DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
	1713	* DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
	1714	* DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
	1715	* DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
	1716	* DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
	1717	* DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
	1718	* DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
	1719	* DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
	1720	* @param Periphs This parameter can be a combination of the following values:
	1721	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
	1722	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
	1723	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
	1724	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
	1725	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
	1726	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
	1727	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
	1728	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
	1729	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
	1730	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
	1731	*
	1732	* (*) value not defined in all devices
	1733	* @retval None
	1734	*/
	1735	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
	1736	{
	1737	CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
	1738	}
	1739
	1740	/**
	1741	* @brief Freeze APB1 peripherals (group2 peripherals)
	1742	* @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
	1743	* DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
	1744	* DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
	1745	* DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
	1746	* @param Periphs This parameter can be a combination of the following values:
	1747	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
	1748	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
	1749	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
	1750	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
	1751	*
	1752	* (*) value not defined in all devices
	1753	* @retval None
	1754	*/
	1755	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
	1756	{
	1757	SET_BIT(DBGMCU->APB2FZ, Periphs);
	1758	}
	1759
	1760	/**
	1761	* @brief Unfreeze APB1 peripherals (group2 peripherals)
	1762	* @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
	1763	* DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
	1764	* DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
	1765	* DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
	1766	* @param Periphs This parameter can be a combination of the following values:
	1767	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
	1768	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
	1769	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
	1770	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
	1771	*
	1772	* (*) value not defined in all devices
	1773	* @retval None
	1774	*/
	1775	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
	1776	{
	1777	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
	1778	}
	1779	/**
	1780	* @}
	1781	*/
	1782
	1783	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
	1784	* @{
	1785	*/
	1786
	1787	/**
	1788	* @brief Set FLASH Latency
	1789	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
	1790	* @param Latency This parameter can be one of the following values:
	1791	* @arg @ref LL_FLASH_LATENCY_0
	1792	* @arg @ref LL_FLASH_LATENCY_1
	1793	* @retval None
	1794	*/
	1795	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
	1796	{
	1797	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
	1798	}
	1799
	1800	/**
	1801	* @brief Get FLASH Latency
	1802	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
	1803	* @retval Returned value can be one of the following values:
	1804	* @arg @ref LL_FLASH_LATENCY_0
	1805	* @arg @ref LL_FLASH_LATENCY_1
	1806	*/
	1807	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
	1808	{
	1809	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
	1810	}
	1811
	1812	/**
	1813	* @brief Enable Prefetch
	1814	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
	1815	* @retval None
	1816	*/
	1817	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
	1818	{
	1819	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
	1820	}
	1821
	1822	/**
	1823	* @brief Disable Prefetch
	1824	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
	1825	* @retval None
	1826	*/
	1827	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
	1828	{
	1829	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
	1830	}
	1831
	1832	/**
	1833	* @brief Check if Prefetch buffer is enabled
	1834	* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
	1835	* @retval State of bit (1 or 0).
	1836	*/
	1837	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
	1838	{
	1839	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
	1840	}
	1841
	1842
	1843
	1844	/**
	1845	* @}
	1846	*/
	1847
	1848	/**
	1849	* @}
	1850	*/
	1851
	1852	/**
	1853	* @}
	1854	*/
	1855
	1856	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) */
	1857
	1858	/**
	1859	* @}
	1860	*/
	1861
	1862	#ifdef __cplusplus
	1863	}
	1864	#endif
	1865
	1866	#endif /* __STM32F0xx_LL_SYSTEM_H */
	1867
	1868	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/