F030C8xx_KBus.git

QuakeGod

2022-10-17 7b8b07ea2942458c4d5f0ebe17e37d078f399775

提交 \| 用户 \| age
bfc108	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_hal_i2s.c
	4	* @author MCD Application Team
	5	* @brief I2S HAL module driver.
	6	* This file provides firmware functions to manage the following
	7	* functionalities of the Integrated Interchip Sound (I2S) peripheral:
	8	* + Initialization and de-initialization functions
	9	* + IO operation functions
	10	* + Peripheral State and Errors functions
	11	@verbatim
	12	===============================================================================
	13	##### How to use this driver #####
	14	===============================================================================
	15	[..]
	16	The I2S HAL driver can be used as follow:
	17
	18	(#) Declare a I2S_HandleTypeDef handle structure.
	19	(#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
	20	(##) Enable the SPIx interface clock.
	21	(##) I2S pins configuration:
	22	(+++) Enable the clock for the I2S GPIOs.
	23	(+++) Configure these I2S pins as alternate function pull-up.
	24	(##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
	25	and HAL_I2S_Receive_IT() APIs).
	26	(+++) Configure the I2Sx interrupt priority.
	27	(+++) Enable the NVIC I2S IRQ handle.
	28	(##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
	29	and HAL_I2S_Receive_DMA() APIs:
	30	(+++) Declare a DMA handle structure for the Tx/Rx Channel.
	31	(+++) Enable the DMAx interface clock.
	32	(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
	33	(+++) Configure the DMA Tx/Rx Channel.
	34	(+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
	35	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
	36	DMA Tx/Rx Channel.
	37
	38	(#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
	39	using HAL_I2S_Init() function.
	40
	41	-@- The specific I2S interrupts (Transmission complete interrupt,
	42	RXNE interrupt and Error Interrupts) will be managed using the macros
	43	__HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
	44	-@- Make sure that either:
	45	(+@) External clock source is configured after setting correctly
	46	the define constant EXTERNAL_CLOCK_VALUE in the stm32f0xx_hal_conf.h file.
	47
	48	(#) Three mode of operations are available within this driver :
	49
	50	* Polling mode IO operation *
	51	=================================
	52	[..]
	53	(+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
	54	(+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
	55
	56	* Interrupt mode IO operation *
	57	===================================
	58	[..]
	59	(+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
	60	(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
	61	add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
	62	(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
	63	add his own code by customization of function pointer HAL_I2S_TxCpltCallback
	64	(+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
	65	(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
	66	add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
	67	(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
	68	add his own code by customization of function pointer HAL_I2S_RxCpltCallback
	69	(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
	70	add his own code by customization of function pointer HAL_I2S_ErrorCallback
	71
	72	* DMA mode IO operation *
	73	==============================
	74	[..]
	75	(+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
	76	(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
	77	add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
	78	(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
	79	add his own code by customization of function pointer HAL_I2S_TxCpltCallback
	80	(+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
	81	(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
	82	add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
	83	(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
	84	add his own code by customization of function pointer HAL_I2S_RxCpltCallback
	85	(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
	86	add his own code by customization of function pointer HAL_I2S_ErrorCallback
	87	(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
	88	(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
	89	(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
	90
	91	* I2S HAL driver macros list *
	92	=============================================
	93	[..]
	94	Below the list of most used macros in I2S HAL driver.
	95
	96	(+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
	97	(+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
	98	(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
	99	(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
	100	(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
	101
	102	[..]
	103	(@) You can refer to the I2S HAL driver header file for more useful macros
	104
	105	@endverbatim
	106	******************************************************************************
	107	* @attention
	108	*
	109	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	110	*
	111	* Redistribution and use in source and binary forms, with or without modification,
	112	* are permitted provided that the following conditions are met:
	113	* 1. Redistributions of source code must retain the above copyright notice,
	114	* this list of conditions and the following disclaimer.
	115	* 2. Redistributions in binary form must reproduce the above copyright notice,
	116	* this list of conditions and the following disclaimer in the documentation
	117	* and/or other materials provided with the distribution.
	118	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	119	* may be used to endorse or promote products derived from this software
	120	* without specific prior written permission.
	121	*
	122	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	123	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	124	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	125	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	126	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	127	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	128	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	129	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	130	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	131	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	132	*
	133	******************************************************************************
	134	*/
	135
	136	/* Includes ------------------------------------------------------------------*/
	137	#include "stm32f0xx_hal.h"
	138
	139	#ifdef HAL_I2S_MODULE_ENABLED
	140
	141	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
	142	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
	143	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
	144	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
	145	defined(STM32F091xC) \|\| defined(STM32F098xx)
	146
	147	/** @addtogroup STM32F0xx_HAL_Driver
	148	* @{
	149	*/
	150
	151	/** @defgroup I2S I2S
	152	* @brief I2S HAL module driver
	153	* @{
	154	*/
	155
	156	/* Private typedef -----------------------------------------------------------*/
	157	/* Private define ------------------------------------------------------------*/
	158	/* Private macro -------------------------------------------------------------*/
	159	/* Private variables ---------------------------------------------------------*/
	160	/* Private function prototypes -----------------------------------------------*/
	161	/** @defgroup I2S_Private_Functions I2S Private Functions
	162	* @{
	163	*/
	164	static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
	165	static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
	166	static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
	167	static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
	168	static void I2S_DMAError(DMA_HandleTypeDef *hdma);
	169	static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
	170	static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
	171	static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
	172	/**
	173	* @}
	174	*/
	175
	176	/* Exported functions ---------------------------------------------------------*/
	177
	178	/** @defgroup I2S_Exported_Functions I2S Exported Functions
	179	* @{
	180	*/
	181
	182	/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
	183	* @brief Initialization and Configuration functions
	184	*
	185	@verbatim
	186	===============================================================================
	187	##### Initialization and de-initialization functions #####
	188	===============================================================================
	189	[..] This subsection provides a set of functions allowing to initialize and
	190	de-initialiaze the I2Sx peripheral in simplex mode:
	191
	192	(+) User must Implement HAL_I2S_MspInit() function in which he configures
	193	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
	194
	195	(+) Call the function HAL_I2S_Init() to configure the selected device with
	196	the selected configuration:
	197	(++) Mode
	198	(++) Standard
	199	(++) Data Format
	200	(++) MCLK Output
	201	(++) Audio frequency
	202	(++) Polarity
	203
	204	(+) Call the function HAL_I2S_DeInit() to restore the default configuration
	205	of the selected I2Sx periperal.
	206	@endverbatim
	207	* @{
	208	*/
	209
	210	/**
	211	* @brief Initializes the I2S according to the specified parameters
	212	* in the I2S_InitTypeDef and create the associated handle.
	213	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	214	* the configuration information for I2S module
	215	* @retval HAL status
	216	*/
	217	HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
	218	{
	219	uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
	220	uint32_t tmp = 0U, i2sclk = 0U;
	221
	222	/* Check the I2S handle allocation */
	223	if(hi2s == NULL)
	224	{
	225	return HAL_ERROR;
	226	}
	227
	228	/* Check the I2S parameters */
	229	assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
	230	assert_param(IS_I2S_MODE(hi2s->Init.Mode));
	231	assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
	232	assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
	233	assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
	234	assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
	235	assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
	236
	237	if(hi2s->State == HAL_I2S_STATE_RESET)
	238	{
	239	/* Allocate lock resource and initialize it */
	240	hi2s->Lock = HAL_UNLOCKED;
	241
	242	/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
	243	HAL_I2S_MspInit(hi2s);
	244	}
	245
	246	hi2s->State = HAL_I2S_STATE_BUSY;
	247
	248	/----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------/
	249	/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
	250	hi2s->Instance->I2SCFGR &= (uint16_t)(~(SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CKPOL \| \
	251	SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC \| SPI_I2SCFGR_I2SCFG \| \
	252	SPI_I2SCFGR_I2SE \| SPI_I2SCFGR_I2SMOD));
	253	hi2s->Instance->I2SPR = 0x0002U;
	254
	255	/* Get the I2SCFGR register value */
	256	tmpreg = hi2s->Instance->I2SCFGR;
	257
	258	/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
	259	if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
	260	{
	261	i2sodd = (uint16_t)0U;
	262	i2sdiv = (uint16_t)2U;
	263	}
	264	/* If the requested audio frequency is not the default, compute the prescaler */
	265	else
	266	{
	267	/* Check the frame length (For the Prescaler computing) *******************/
	268	if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
	269	{
	270	/* Packet length is 16 bits */
	271	packetlength = 1U;
	272	}
	273	else
	274	{
	275	/* Packet length is 32 bits */
	276	packetlength = 2U;
	277	}
	278
	279	/* Get I2S source Clock frequency ****************************************/
	280	i2sclk = HAL_RCC_GetSysClockFreq();
	281
	282	/* Compute the Real divider depending on the MCLK output state, with a floating point */
	283	if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
	284	{
	285	/* MCLK output is enabled */
	286	tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
	287	}
	288	else
	289	{
	290	/* MCLK output is disabled */
	291	tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
	292	}
	293
	294	/* Remove the flatting point */
	295	tmp = tmp / 10U;
	296
	297	/* Check the parity of the divider */
	298	i2sodd = (uint32_t)(tmp & 1U);
	299
	300	/* Compute the i2sdiv prescaler */
	301	i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
	302
	303	/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
	304	i2sodd = (uint32_t) (i2sodd << 8U);
	305	}
	306
	307	/* Test if the divider is 1 or 0 or greater than 0xFF */
	308	if((i2sdiv < 2U) \|\| (i2sdiv > 0xFFU))
	309	{
	310	/* Set the default values */
	311	i2sdiv = 2U;
	312	i2sodd = 0U;
	313	}
	314
	315	/* Write to SPIx I2SPR register the computed value */
	316	hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv \| (uint32_t)(i2sodd \| (uint32_t)hi2s->Init.MCLKOutput));
	317
	318	/* Configure the I2S with the I2S_InitStruct values */
	319	tmpreg \|= (uint32_t)(SPI_I2SCFGR_I2SMOD \| hi2s->Init.Mode \| hi2s->Init.Standard \| hi2s->Init.DataFormat \| hi2s->Init.CPOL);
	320
	321	/* Write to SPIx I2SCFGR */
	322	hi2s->Instance->I2SCFGR = tmpreg;
	323
	324	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
	325	hi2s->State= HAL_I2S_STATE_READY;
	326
	327	return HAL_OK;
	328	}
	329
	330	/**
	331	* @brief DeInitializes the I2S peripheral
	332	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	333	* the configuration information for I2S module
	334	* @retval HAL status
	335	*/
	336	HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
	337	{
	338	/* Check the I2S handle allocation */
	339	if(hi2s == NULL)
	340	{
	341	return HAL_ERROR;
	342	}
	343
	344	/* Check the parameters */
	345	assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
	346
	347	hi2s->State = HAL_I2S_STATE_BUSY;
	348
	349	/* Disable the I2S Peripheral Clock */
	350	__HAL_I2S_DISABLE(hi2s);
	351
	352	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
	353	HAL_I2S_MspDeInit(hi2s);
	354
	355	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
	356	hi2s->State = HAL_I2S_STATE_RESET;
	357
	358	/* Release Lock */
	359	__HAL_UNLOCK(hi2s);
	360
	361	return HAL_OK;
	362	}
	363
	364	/**
	365	* @brief I2S MSP Init
	366	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	367	* the configuration information for I2S module
	368	* @retval None
	369	*/
	370	__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
	371	{
	372	/* Prevent unused argument(s) compilation warning */
	373	UNUSED(hi2s);
	374
	375	/* NOTE : This function Should not be modified, when the callback is needed,
	376	the HAL_I2S_MspInit could be implemented in the user file
	377	*/
	378	}
	379
	380	/**
	381	* @brief I2S MSP DeInit
	382	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	383	* the configuration information for I2S module
	384	* @retval None
	385	*/
	386	__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
	387	{
	388	/* Prevent unused argument(s) compilation warning */
	389	UNUSED(hi2s);
	390
	391	/* NOTE : This function Should not be modified, when the callback is needed,
	392	the HAL_I2S_MspDeInit could be implemented in the user file
	393	*/
	394	}
	395
	396	/**
	397	* @}
	398	*/
	399
	400	/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
	401	* @brief Data transfers functions
	402	*
	403	@verbatim
	404	===============================================================================
	405	##### IO operation functions #####
	406	===============================================================================
	407	[..]
	408	This subsection provides a set of functions allowing to manage the I2S data
	409	transfers.
	410
	411	(#) There are two modes of transfer:
	412	(++) Blocking mode : The communication is performed in the polling mode.
	413	The status of all data processing is returned by the same function
	414	after finishing transfer.
	415	(++) No-Blocking mode : The communication is performed using Interrupts
	416	or DMA. These functions return the status of the transfer startup.
	417	The end of the data processing will be indicated through the
	418	dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
	419	using DMA mode.
	420
	421	(#) Blocking mode functions are :
	422	(++) HAL_I2S_Transmit()
	423	(++) HAL_I2S_Receive()
	424
	425	(#) No-Blocking mode functions with Interrupt are :
	426	(++) HAL_I2S_Transmit_IT()
	427	(++) HAL_I2S_Receive_IT()
	428
	429	(#) No-Blocking mode functions with DMA are :
	430	(++) HAL_I2S_Transmit_DMA()
	431	(++) HAL_I2S_Receive_DMA()
	432
	433	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
	434	(++) HAL_I2S_TxCpltCallback()
	435	(++) HAL_I2S_RxCpltCallback()
	436	(++) HAL_I2S_ErrorCallback()
	437
	438	@endverbatim
	439	* @{
	440	*/
	441
	442	/**
	443	* @brief Transmit an amount of data in blocking mode
	444	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	445	* the configuration information for I2S module
	446	* @param pData a 16-bit pointer to data buffer.
	447	* @param Size number of data sample to be sent:
	448	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
	449	* configuration phase, the Size parameter means the number of 16-bit data length
	450	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
	451	* the Size parameter means the number of 16-bit data length.
	452	* @param Timeout Timeout duration
	453	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
	454	* between Master and Slave(example: audio streaming).
	455	* @retval HAL status
	456	*/
	457	HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size, uint32_t Timeout)
	458	{
	459	if((pData == NULL ) \|\| (Size == 0U))
	460	{
	461	return HAL_ERROR;
	462	}
	463
	464	/* Process Locked */
	465	__HAL_LOCK(hi2s);
	466
	467	if(hi2s->State == HAL_I2S_STATE_READY)
	468	{
	469	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
	470	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
	471	{
	472	hi2s->TxXferSize = (Size << 1U);
	473	hi2s->TxXferCount = (Size << 1U);
	474	}
	475	else
	476	{
	477	hi2s->TxXferSize = Size;
	478	hi2s->TxXferCount = Size;
	479	}
	480
	481	/* Set state and reset error code */
	482	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
	483	hi2s->State = HAL_I2S_STATE_BUSY_TX;
	484	hi2s->pTxBuffPtr = pData;
	485
	486	/* Check if the I2S is already enabled */
	487	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
	488	{
	489	/* Enable I2S peripheral */
	490	__HAL_I2S_ENABLE(hi2s);
	491	}
	492
	493	while(hi2s->TxXferCount > 0U)
	494	{
	495	/* Wait until TXE flag is set */
	496	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
	497	{
	498	return HAL_TIMEOUT;
	499	}
	500	hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
	501	hi2s->TxXferCount--;
	502	}
	503
	504	/* Wait until TXE flag is set, to confirm the end of the transcation */
	505	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
	506	{
	507	return HAL_TIMEOUT;
	508	}
	509	/* Wait until Busy flag is reset */
	510	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
	511	{
	512	return HAL_TIMEOUT;
	513	}
	514
	515	hi2s->State = HAL_I2S_STATE_READY;
	516
	517	/* Process Unlocked */
	518	__HAL_UNLOCK(hi2s);
	519
	520	return HAL_OK;
	521	}
	522	else
	523	{
	524	/* Process Unlocked */
	525	__HAL_UNLOCK(hi2s);
	526	return HAL_BUSY;
	527	}
	528	}
	529
	530	/**
	531	* @brief Receive an amount of data in blocking mode
	532	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	533	* the configuration information for I2S module
	534	* @param pData a 16-bit pointer to data buffer.
	535	* @param Size number of data sample to be sent:
	536	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
	537	* configuration phase, the Size parameter means the number of 16-bit data length
	538	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
	539	* the Size parameter means the number of 16-bit data length.
	540	* @param Timeout Timeout duration
	541	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
	542	* between Master and Slave(example: audio streaming).
	543	* @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
	544	* in continouse way and as the I2S is not disabled at the end of the I2S transaction.
	545	* @retval HAL status
	546	*/
	547	HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size, uint32_t Timeout)
	548	{
	549	if((pData == NULL ) \|\| (Size == 0U))
	550	{
	551	return HAL_ERROR;
	552	}
	553
	554	/* Process Locked */
	555	__HAL_LOCK(hi2s);
	556
	557	if(hi2s->State == HAL_I2S_STATE_READY)
	558	{
	559	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
	560	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
	561	{
	562	hi2s->RxXferSize = (Size << 1U);
	563	hi2s->RxXferCount = (Size << 1U);
	564	}
	565	else
	566	{
	567	hi2s->RxXferSize = Size;
	568	hi2s->RxXferCount = Size;
	569	}
	570
	571	/* Set state and reset error code */
	572	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
	573	hi2s->State = HAL_I2S_STATE_BUSY_RX;
	574	hi2s->pRxBuffPtr = pData;
	575
	576	/* Check if the I2S is already enabled */
	577	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
	578	{
	579	/* Enable I2S peripheral */
	580	__HAL_I2S_ENABLE(hi2s);
	581	}
	582
	583	/* Receive data */
	584	while(hi2s->RxXferCount > 0U)
	585	{
	586	/* Wait until RXNE flag is set */
	587	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
	588	{
	589	return HAL_TIMEOUT;
	590	}
	591
	592	(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
	593	hi2s->RxXferCount--;
	594	}
	595
	596	hi2s->State = HAL_I2S_STATE_READY;
	597
	598	/* Process Unlocked */
	599	__HAL_UNLOCK(hi2s);
	600
	601	return HAL_OK;
	602	}
	603	else
	604	{
	605	/* Process Unlocked */
	606	__HAL_UNLOCK(hi2s);
	607	return HAL_BUSY;
	608	}
	609	}
	610
	611	/**
	612	* @brief Transmit an amount of data in non-blocking mode with Interrupt
	613	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	614	* the configuration information for I2S module
	615	* @param pData a 16-bit pointer to data buffer.
	616	* @param Size number of data sample to be sent:
	617	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
	618	* configuration phase, the Size parameter means the number of 16-bit data length
	619	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
	620	* the Size parameter means the number of 16-bit data length.
	621	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
	622	* between Master and Slave(example: audio streaming).
	623	* @retval HAL status
	624	*/
	625	HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
	626	{
	627	if((pData == NULL) \|\| (Size == 0U))
	628	{
	629	return HAL_ERROR;
	630	}
	631
	632	/* Process Locked */
	633	__HAL_LOCK(hi2s);
	634
	635	if(hi2s->State == HAL_I2S_STATE_READY)
	636	{
	637	hi2s->pTxBuffPtr = pData;
	638	hi2s->State = HAL_I2S_STATE_BUSY_TX;
	639	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
	640
	641	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
	642	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
	643	{
	644	hi2s->TxXferSize = (Size << 1U);
	645	hi2s->TxXferCount = (Size << 1U);
	646	}
	647	else
	648	{
	649	hi2s->TxXferSize = Size;
	650	hi2s->TxXferCount = Size;
	651	}
	652
	653	/* Enable TXE and ERR interrupt */
	654	__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
	655
	656	/* Check if the I2S is already enabled */
	657	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
	658	{
	659	/* Enable I2S peripheral */
	660	__HAL_I2S_ENABLE(hi2s);
	661	}
	662
	663	/* Process Unlocked */
	664	__HAL_UNLOCK(hi2s);
	665
	666	return HAL_OK;
	667	}
	668	else
	669	{
	670	/* Process Unlocked */
	671	__HAL_UNLOCK(hi2s);
	672	return HAL_BUSY;
	673	}
	674	}
	675
	676	/**
	677	* @brief Receive an amount of data in non-blocking mode with Interrupt
	678	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	679	* the configuration information for I2S module
	680	* @param pData a 16-bit pointer to the Receive data buffer.
	681	* @param Size number of data sample to be sent:
	682	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
	683	* configuration phase, the Size parameter means the number of 16-bit data length
	684	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
	685	* the Size parameter means the number of 16-bit data length.
	686	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
	687	* between Master and Slave(example: audio streaming).
	688	* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
	689	* between Master and Slave otherwise the I2S interrupt should be optimized.
	690	* @retval HAL status
	691	*/
	692	HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
	693	{
	694	if((pData == NULL) \|\| (Size == 0U))
	695	{
	696	return HAL_ERROR;
	697	}
	698
	699	/* Process Locked */
	700	__HAL_LOCK(hi2s);
	701
	702	if(hi2s->State == HAL_I2S_STATE_READY)
	703	{
	704	hi2s->pRxBuffPtr = pData;
	705	hi2s->State = HAL_I2S_STATE_BUSY_RX;
	706	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
	707
	708	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
	709	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
	710	{
	711	hi2s->RxXferSize = (Size << 1U);
	712	hi2s->RxXferCount = (Size << 1U);
	713	}
	714	else
	715	{
	716	hi2s->RxXferSize = Size;
	717	hi2s->RxXferCount = Size;
	718	}
	719
	720	/* Enable TXE and ERR interrupt */
	721	__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
	722
	723	/* Check if the I2S is already enabled */
	724	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
	725	{
	726	/* Enable I2S peripheral */
	727	__HAL_I2S_ENABLE(hi2s);
	728	}
	729
	730	/* Process Unlocked */
	731	__HAL_UNLOCK(hi2s);
	732
	733	return HAL_OK;
	734	}
	735	else
	736	{
	737	/* Process Unlocked */
	738	__HAL_UNLOCK(hi2s);
	739	return HAL_BUSY;
	740	}
	741	}
	742
	743	/**
	744	* @brief Transmit an amount of data in non-blocking mode with DMA
	745	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	746	* the configuration information for I2S module
	747	* @param pData a 16-bit pointer to the Transmit data buffer.
	748	* @param Size number of data sample to be sent:
	749	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
	750	* configuration phase, the Size parameter means the number of 16-bit data length
	751	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
	752	* the Size parameter means the number of 16-bit data length.
	753	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
	754	* between Master and Slave(example: audio streaming).
	755	* @retval HAL status
	756	*/
	757	HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
	758	{
	759	if((pData == NULL) \|\| (Size == 0U))
	760	{
	761	return HAL_ERROR;
	762	}
	763
	764	/* Process Locked */
	765	__HAL_LOCK(hi2s);
	766
	767	if(hi2s->State == HAL_I2S_STATE_READY)
	768	{
	769	hi2s->pTxBuffPtr = pData;
	770	hi2s->State = HAL_I2S_STATE_BUSY_TX;
	771	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
	772
	773	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
	774	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
	775	{
	776	hi2s->TxXferSize = (Size << 1U);
	777	hi2s->TxXferCount = (Size << 1U);
	778	}
	779	else
	780	{
	781	hi2s->TxXferSize = Size;
	782	hi2s->TxXferCount = Size;
	783	}
	784
	785	/* Set the I2S Tx DMA Half transfert complete callback */
	786	hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
	787
	788	/* Set the I2S Tx DMA transfert complete callback */
	789	hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
	790
	791	/* Set the DMA error callback */
	792	hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
	793
	794	/* Enable the Tx DMA Channel */
	795	HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
	796
	797	/* Check if the I2S is already enabled */
	798	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
	799	{
	800	/* Enable I2S peripheral */
	801	__HAL_I2S_ENABLE(hi2s);
	802	}
	803
	804	/* Check if the I2S Tx request is already enabled */
	805	if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
	806	{
	807	/* Enable Tx DMA Request */
	808	hi2s->Instance->CR2 \|= SPI_CR2_TXDMAEN;
	809	}
	810
	811	/* Process Unlocked */
	812	__HAL_UNLOCK(hi2s);
	813
	814	return HAL_OK;
	815	}
	816	else
	817	{
	818	/* Process Unlocked */
	819	__HAL_UNLOCK(hi2s);
	820	return HAL_BUSY;
	821	}
	822	}
	823
	824	/**
	825	* @brief Receive an amount of data in non-blocking mode with DMA
	826	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	827	* the configuration information for I2S module
	828	* @param pData a 16-bit pointer to the Receive data buffer.
	829	* @param Size number of data sample to be sent:
	830	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
	831	* configuration phase, the Size parameter means the number of 16-bit data length
	832	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
	833	* the Size parameter means the number of 16-bit data length.
	834	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
	835	* between Master and Slave(example: audio streaming).
	836	* @retval HAL status
	837	*/
	838	HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
	839	{
	840	if((pData == NULL) \|\| (Size == 0U))
	841	{
	842	return HAL_ERROR;
	843	}
	844
	845	/* Process Locked */
	846	__HAL_LOCK(hi2s);
	847
	848	if(hi2s->State == HAL_I2S_STATE_READY)
	849	{
	850	hi2s->pRxBuffPtr = pData;
	851	hi2s->State = HAL_I2S_STATE_BUSY_RX;
	852	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
	853
	854	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
	855	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
	856	{
	857	hi2s->RxXferSize = (Size << 1U);
	858	hi2s->RxXferCount = (Size << 1U);
	859	}
	860	else
	861	{
	862	hi2s->RxXferSize = Size;
	863	hi2s->RxXferCount = Size;
	864	}
	865
	866
	867	/* Set the I2S Rx DMA Half transfert complete callback */
	868	hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
	869
	870	/* Set the I2S Rx DMA transfert complete callback */
	871	hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
	872
	873	/* Set the DMA error callback */
	874	hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
	875
	876	/* Check if Master Receiver mode is selected */
	877	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
	878	{
	879	/* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
	880	access to the SPI_SR register. */
	881	__HAL_I2S_CLEAR_OVRFLAG(hi2s);
	882	}
	883
	884	/* Enable the Rx DMA Channel */
	885	HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
	886
	887	/* Check if the I2S is already enabled */
	888	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
	889	{
	890	/* Enable I2S peripheral */
	891	__HAL_I2S_ENABLE(hi2s);
	892	}
	893
	894	/* Check if the I2S Rx request is already enabled */
	895	if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
	896	{
	897	/* Enable Rx DMA Request */
	898	hi2s->Instance->CR2 \|= SPI_CR2_RXDMAEN;
	899	}
	900
	901	/* Process Unlocked */
	902	__HAL_UNLOCK(hi2s);
	903
	904	return HAL_OK;
	905	}
	906	else
	907	{
	908	/* Process Unlocked */
	909	__HAL_UNLOCK(hi2s);
	910	return HAL_BUSY;
	911	}
	912	}
	913
	914	/**
	915	* @brief Pauses the audio stream playing from the Media.
	916	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	917	* the configuration information for I2S module
	918	* @retval HAL status
	919	*/
	920	HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
	921	{
	922	/* Process Locked */
	923	__HAL_LOCK(hi2s);
	924
	925	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
	926	{
	927	/* Disable the I2S DMA Tx request */
	928	hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
	929	}
	930	else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
	931	{
	932	/* Disable the I2S DMA Rx request */
	933	hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
	934	}
	935
	936	/* Process Unlocked */
	937	__HAL_UNLOCK(hi2s);
	938
	939	return HAL_OK;
	940	}
	941
	942	/**
	943	* @brief Resumes the audio stream playing from the Media.
	944	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	945	* the configuration information for I2S module
	946	* @retval HAL status
	947	*/
	948	HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
	949	{
	950	/* Process Locked */
	951	__HAL_LOCK(hi2s);
	952
	953	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
	954	{
	955	/* Enable the I2S DMA Tx request */
	956	hi2s->Instance->CR2 \|= SPI_CR2_TXDMAEN;
	957	}
	958	else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
	959	{
	960	/* Enable the I2S DMA Rx request */
	961	hi2s->Instance->CR2 \|= SPI_CR2_RXDMAEN;
	962	}
	963
	964	/* If the I2S peripheral is still not enabled, enable it */
	965	if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
	966	{
	967	/* Enable I2S peripheral */
	968	__HAL_I2S_ENABLE(hi2s);
	969	}
	970
	971	/* Process Unlocked */
	972	__HAL_UNLOCK(hi2s);
	973
	974	return HAL_OK;
	975	}
	976
	977	/**
	978	* @brief Resumes the audio stream playing from the Media.
	979	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	980	* the configuration information for I2S module
	981	* @retval HAL status
	982	*/
	983	HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
	984	{
	985	/* Process Locked */
	986	__HAL_LOCK(hi2s);
	987
	988	/* Disable the I2S Tx/Rx DMA requests */
	989	hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
	990	hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
	991
	992	/* Abort the I2S DMA tx channel */
	993	if(hi2s->hdmatx != NULL)
	994	{
	995	/* Disable the I2S DMA channel */
	996	__HAL_DMA_DISABLE(hi2s->hdmatx);
	997	HAL_DMA_Abort(hi2s->hdmatx);
	998	}
	999	/* Abort the I2S DMA rx channel */
	1000	if(hi2s->hdmarx != NULL)
	1001	{
	1002	/* Disable the I2S DMA channel */
	1003	__HAL_DMA_DISABLE(hi2s->hdmarx);
	1004	HAL_DMA_Abort(hi2s->hdmarx);
	1005	}
	1006
	1007	/* Disable I2S peripheral */
	1008	__HAL_I2S_DISABLE(hi2s);
	1009
	1010	hi2s->State = HAL_I2S_STATE_READY;
	1011
	1012	/* Process Unlocked */
	1013	__HAL_UNLOCK(hi2s);
	1014
	1015	return HAL_OK;
	1016	}
	1017
	1018	/**
	1019	* @brief This function handles I2S interrupt request.
	1020	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	1021	* the configuration information for I2S module
	1022	* @retval None
	1023	*/
	1024	void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
	1025	{
	1026	uint32_t i2ssr = hi2s->Instance->SR;
	1027
	1028	/* I2S in mode Receiver ------------------------------------------------*/
	1029	if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
	1030	((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
	1031	{
	1032	I2S_Receive_IT(hi2s);
	1033	return;
	1034	}
	1035
	1036	/* I2S in mode Tramitter -----------------------------------------------*/
	1037	if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
	1038	{
	1039	I2S_Transmit_IT(hi2s);
	1040	return;
	1041	}
	1042
	1043	/* I2S Overrun error interrupt occured ---------------------------------*/
	1044	if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
	1045	{
	1046	/* Disable RXNE and ERR interrupt */
	1047	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
	1048
	1049	/* Set the I2S State ready */
	1050	hi2s->State = HAL_I2S_STATE_READY;
	1051
	1052	/* Set the error code and execute error callback*/
	1053	hi2s->ErrorCode \|= HAL_I2S_ERROR_OVR;
	1054	HAL_I2S_ErrorCallback(hi2s);
	1055	}
	1056
	1057	/* I2S Underrun error interrupt occured --------------------------------*/
	1058	if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
	1059	{
	1060	/* Disable TXE and ERR interrupt */
	1061	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
	1062
	1063	/* Set the I2S State ready */
	1064	hi2s->State = HAL_I2S_STATE_READY;
	1065
	1066	/* Set the error code and execute error callback*/
	1067	hi2s->ErrorCode \|= HAL_I2S_ERROR_UDR;
	1068	HAL_I2S_ErrorCallback(hi2s);
	1069	}
	1070	}
	1071
	1072	/**
	1073	* @brief Tx Transfer Half completed callbacks
	1074	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	1075	* the configuration information for I2S module
	1076	* @retval None
	1077	*/
	1078	__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
	1079	{
	1080	/* Prevent unused argument(s) compilation warning */
	1081	UNUSED(hi2s);
	1082
	1083	/* NOTE : This function Should not be modified, when the callback is needed,
	1084	the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
	1085	*/
	1086	}
	1087
	1088	/**
	1089	* @brief Tx Transfer completed callbacks
	1090	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	1091	* the configuration information for I2S module
	1092	* @retval None
	1093	*/
	1094	__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
	1095	{
	1096	/* Prevent unused argument(s) compilation warning */
	1097	UNUSED(hi2s);
	1098
	1099	/* NOTE : This function Should not be modified, when the callback is needed,
	1100	the HAL_I2S_TxCpltCallback could be implemented in the user file
	1101	*/
	1102	}
	1103
	1104	/**
	1105	* @brief Rx Transfer half completed callbacks
	1106	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	1107	* the configuration information for I2S module
	1108	* @retval None
	1109	*/
	1110	__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
	1111	{
	1112	/* Prevent unused argument(s) compilation warning */
	1113	UNUSED(hi2s);
	1114
	1115	/* NOTE : This function Should not be modified, when the callback is needed,
	1116	the HAL_I2S_RxCpltCallback could be implemented in the user file
	1117	*/
	1118	}
	1119
	1120	/**
	1121	* @brief Rx Transfer completed callbacks
	1122	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	1123	* the configuration information for I2S module
	1124	* @retval None
	1125	*/
	1126	__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
	1127	{
	1128	/* Prevent unused argument(s) compilation warning */
	1129	UNUSED(hi2s);
	1130
	1131	/* NOTE : This function Should not be modified, when the callback is needed,
	1132	the HAL_I2S_RxCpltCallback could be implemented in the user file
	1133	*/
	1134	}
	1135
	1136	/**
	1137	* @brief I2S error callbacks
	1138	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	1139	* the configuration information for I2S module
	1140	* @retval None
	1141	*/
	1142	__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
	1143	{
	1144	/* Prevent unused argument(s) compilation warning */
	1145	UNUSED(hi2s);
	1146
	1147	/* NOTE : This function Should not be modified, when the callback is needed,
	1148	the HAL_I2S_ErrorCallback could be implemented in the user file
	1149	*/
	1150	}
	1151
	1152	/**
	1153	* @}
	1154	*/
	1155
	1156	/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
	1157	* @brief Peripheral State functions
	1158	*
	1159	@verbatim
	1160	===============================================================================
	1161	##### Peripheral State and Errors functions #####
	1162	===============================================================================
	1163	[..]
	1164	This subsection permits to get in run-time the status of the peripheral
	1165	and the data flow.
	1166
	1167	@endverbatim
	1168	* @{
	1169	*/
	1170
	1171	/**
	1172	* @brief Return the I2S state
	1173	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	1174	* the configuration information for I2S module
	1175	* @retval HAL state
	1176	*/
	1177	HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
	1178	{
	1179	return hi2s->State;
	1180	}
	1181
	1182	/**
	1183	* @brief Return the I2S error code
	1184	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	1185	* the configuration information for I2S module
	1186	* @retval I2S Error Code
	1187	*/
	1188	uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
	1189	{
	1190	return hi2s->ErrorCode;
	1191	}
	1192	/**
	1193	* @}
	1194	*/
	1195
	1196	/**
	1197	* @}
	1198	*/
	1199
	1200	/** @addtogroup I2S_Private_Functions I2S Private Functions
	1201	* @{
	1202	*/
	1203	/**
	1204	* @brief DMA I2S transmit process complete callback
	1205	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	1206	* the configuration information for the specified DMA module.
	1207	* @retval None
	1208	*/
	1209	static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
	1210	{
	1211	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
	1212
	1213	if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
	1214	{
	1215	/* Disable Tx DMA Request */
	1216	hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
	1217
	1218	hi2s->TxXferCount = 0U;
	1219	hi2s->State = HAL_I2S_STATE_READY;
	1220	}
	1221	HAL_I2S_TxCpltCallback(hi2s);
	1222	}
	1223
	1224	/**
	1225	* @brief DMA I2S transmit process half complete callback
	1226	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	1227	* the configuration information for the specified DMA module.
	1228	* @retval None
	1229	*/
	1230	static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
	1231	{
	1232	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
	1233
	1234	HAL_I2S_TxHalfCpltCallback(hi2s);
	1235	}
	1236
	1237	/**
	1238	* @brief DMA I2S receive process complete callback
	1239	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	1240	* the configuration information for the specified DMA module.
	1241	* @retval None
	1242	*/
	1243	static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
	1244	{
	1245	I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
	1246
	1247	if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
	1248	{
	1249	/* Disable Rx DMA Request */
	1250	hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
	1251	hi2s->RxXferCount = 0;
	1252	hi2s->State = HAL_I2S_STATE_READY;
	1253	}
	1254	HAL_I2S_RxCpltCallback(hi2s);
	1255	}
	1256
	1257	/**
	1258	* @brief DMA I2S receive process half complete callback
	1259	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	1260	* the configuration information for the specified DMA module.
	1261	* @retval None
	1262	*/
	1263	static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
	1264	{
	1265	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
	1266
	1267	HAL_I2S_RxHalfCpltCallback(hi2s);
	1268	}
	1269
	1270	/**
	1271	* @brief DMA I2S communication error callback
	1272	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
	1273	* the configuration information for the specified DMA module.
	1274	* @retval None
	1275	*/
	1276	static void I2S_DMAError(DMA_HandleTypeDef *hdma)
	1277	{
	1278	I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
	1279
	1280	/* Disable Rx and Tx DMA Request */
	1281	hi2s->Instance->CR2 &= (uint16_t)(~(SPI_CR2_RXDMAEN \| SPI_CR2_TXDMAEN));
	1282	hi2s->TxXferCount = 0U;
	1283	hi2s->RxXferCount = 0U;
	1284
	1285	hi2s->State= HAL_I2S_STATE_READY;
	1286
	1287	/* Set the error code and execute error callback*/
	1288	hi2s->ErrorCode \|= HAL_I2S_ERROR_DMA;
	1289	HAL_I2S_ErrorCallback(hi2s);
	1290	}
	1291
	1292	/**
	1293	* @brief Transmit an amount of data in non-blocking mode with Interrupt
	1294	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	1295	* the configuration information for I2S module
	1296	* @retval None
	1297	*/
	1298	static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
	1299	{
	1300	/* Transmit data */
	1301	hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
	1302	hi2s->TxXferCount--;
	1303
	1304	if(hi2s->TxXferCount == 0)
	1305	{
	1306	/* Disable TXE and ERR interrupt */
	1307	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
	1308
	1309	hi2s->State = HAL_I2S_STATE_READY;
	1310	HAL_I2S_TxCpltCallback(hi2s);
	1311	}
	1312	}
	1313
	1314	/**
	1315	* @brief Receive an amount of data in non-blocking mode with Interrupt
	1316	* @param hi2s I2S handle
	1317	* @retval None
	1318	*/
	1319	static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
	1320	{
	1321	/* Receive data */
	1322	(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
	1323	hi2s->RxXferCount--;
	1324
	1325	if(hi2s->RxXferCount == 0U)
	1326	{
	1327	/* Disable RXNE and ERR interrupt */
	1328	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
	1329
	1330	hi2s->State = HAL_I2S_STATE_READY;
	1331	HAL_I2S_RxCpltCallback(hi2s);
	1332	}
	1333	}
	1334
	1335
	1336	/**
	1337	* @brief This function handles I2S Communication Timeout.
	1338	* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
	1339	* the configuration information for I2S module
	1340	* @param Flag Flag checked
	1341	* @param State Value of the flag expected
	1342	* @param Timeout Duration of the timeout
	1343	* @retval HAL status
	1344	*/
	1345	static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
	1346	{
	1347	uint32_t tickstart = HAL_GetTick();
	1348
	1349	/* Wait until flag is set */
	1350	if(State == RESET)
	1351	{
	1352	while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
	1353	{
	1354	if(Timeout != HAL_MAX_DELAY)
	1355	{
	1356	if((Timeout == 0U) \|\| ((HAL_GetTick() - tickstart) > Timeout))
	1357	{
	1358	/* Set the I2S State ready */
	1359	hi2s->State= HAL_I2S_STATE_READY;
	1360
	1361	/* Process Unlocked */
	1362	__HAL_UNLOCK(hi2s);
	1363
	1364	return HAL_TIMEOUT;
	1365	}
	1366	}
	1367	}
	1368	}
	1369	else
	1370	{
	1371	while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
	1372	{
	1373	if(Timeout != HAL_MAX_DELAY)
	1374	{
	1375	if((Timeout == 0U) \|\| ((HAL_GetTick() - tickstart) > Timeout))
	1376	{
	1377	/* Set the I2S State ready */
	1378	hi2s->State= HAL_I2S_STATE_READY;
	1379
	1380	/* Process Unlocked */
	1381	__HAL_UNLOCK(hi2s);
	1382
	1383	return HAL_TIMEOUT;
	1384	}
	1385	}
	1386	}
	1387	}
	1388	return HAL_OK;
	1389	}
	1390
	1391	/**
	1392	* @}
	1393	*/
	1394
	1395	/**
	1396	* @}
	1397	*/
	1398
	1399	/**
	1400	* @}
	1401	*/
	1402
	1403	#endif /* defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| */
	1404	/* defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| */
	1405	/* defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| */
	1406	/* defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| */
	1407	/* defined(STM32F091xC) \|\| defined(STM32F098xx) */
	1408
	1409	#endif /* HAL_I2S_MODULE_ENABLED */
	1410
	1411	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/