F030C8xx_KBus.git

QuakeGod

2022-10-17 6a62617e99d79314d1e10995fbc29fbb00419a6e

提交 \| 用户 \| age
bfc108	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_ll_dma.c
	4	* @author MCD Application Team
	5	* @brief DMA LL module driver.
	6	******************************************************************************
	7	* @attention
	8	*
	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	10	*
	11	* Redistribution and use in source and binary forms, with or without modification,
	12	* are permitted provided that the following conditions are met:
	13	* 1. Redistributions of source code must retain the above copyright notice,
	14	* this list of conditions and the following disclaimer.
	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	19	* may be used to endorse or promote products derived from this software
	20	* without specific prior written permission.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	******************************************************************************
	34	*/
	35	#if defined(USE_FULL_LL_DRIVER)
	36
	37	/* Includes ------------------------------------------------------------------*/
	38	#include "stm32f0xx_ll_dma.h"
	39	#include "stm32f0xx_ll_bus.h"
	40	#ifdef USE_FULL_ASSERT
	41	#include "stm32_assert.h"
	42	#else
	43	#define assert_param(expr) ((void)0U)
	44	#endif
	45
	46	/** @addtogroup STM32F0xx_LL_Driver
	47	* @{
	48	*/
	49
	50	#if defined (DMA1) \|\| defined (DMA2)
	51
	52	/** @defgroup DMA_LL DMA
	53	* @{
	54	*/
	55
	56	/* Private types -------------------------------------------------------------*/
	57	/* Private variables ---------------------------------------------------------*/
	58	/* Private constants ---------------------------------------------------------*/
	59	/* Private macros ------------------------------------------------------------*/
	60	/** @addtogroup DMA_LL_Private_Macros
	61	* @{
	62	*/
	63	#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) \|\| \
	64	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) \|\| \
	65	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
	66
	67	#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) \|\| \
	68	((__VALUE__) == LL_DMA_MODE_CIRCULAR))
	69
	70	#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) \|\| \
	71	((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
	72
	73	#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) \|\| \
	74	((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
	75
	76	#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) \|\| \
	77	((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) \|\| \
	78	((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
	79
	80	#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) \|\| \
	81	((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) \|\| \
	82	((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
	83
	84	#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
	85
	86	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
	87	#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) \|\| \
	88	((__VALUE__) == LL_DMA_REQUEST_1) \|\| \
	89	((__VALUE__) == LL_DMA_REQUEST_2) \|\| \
	90	((__VALUE__) == LL_DMA_REQUEST_3) \|\| \
	91	((__VALUE__) == LL_DMA_REQUEST_4) \|\| \
	92	((__VALUE__) == LL_DMA_REQUEST_5) \|\| \
	93	((__VALUE__) == LL_DMA_REQUEST_6) \|\| \
	94	((__VALUE__) == LL_DMA_REQUEST_7) \|\| \
	95	((__VALUE__) == LL_DMA_REQUEST_8) \|\| \
	96	((__VALUE__) == LL_DMA_REQUEST_9) \|\| \
	97	((__VALUE__) == LL_DMA_REQUEST_10) \|\| \
	98	((__VALUE__) == LL_DMA_REQUEST_11) \|\| \
	99	((__VALUE__) == LL_DMA_REQUEST_12) \|\| \
	100	((__VALUE__) == LL_DMA_REQUEST_13) \|\| \
	101	((__VALUE__) == LL_DMA_REQUEST_14) \|\| \
	102	((__VALUE__) == LL_DMA_REQUEST_15))
	103	#endif
	104
	105	#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) \|\| \
	106	((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) \|\| \
	107	((__VALUE__) == LL_DMA_PRIORITY_HIGH) \|\| \
	108	((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
	109
	110	#if defined (DMA2)
	111	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
	112	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
	113	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
	114	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
	115	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
	116	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
	117	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
	118	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
	119	((CHANNEL) == LL_DMA_CHANNEL_7))) \|\| \
	120	(((INSTANCE) == DMA2) && \
	121	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
	122	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
	123	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
	124	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
	125	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
	126	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
	127	((CHANNEL) == LL_DMA_CHANNEL_7))))
	128	#else
	129	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
	130	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
	131	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
	132	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
	133	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
	134	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
	135	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
	136	((CHANNEL) == LL_DMA_CHANNEL_7))) \|\| \
	137	(((INSTANCE) == DMA2) && \
	138	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
	139	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
	140	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
	141	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
	142	((CHANNEL) == LL_DMA_CHANNEL_5))))
	143	#endif
	144	#else
	145	#if defined(DMA1_Channel6) && defined(DMA1_Channel7)
	146	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
	147	(((CHANNEL) == LL_DMA_CHANNEL_1)\|\| \
	148	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
	149	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
	150	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
	151	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
	152	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
	153	((CHANNEL) == LL_DMA_CHANNEL_7))))
	154	#elif defined (DMA1_Channel6)
	155	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
	156	(((CHANNEL) == LL_DMA_CHANNEL_1)\|\| \
	157	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
	158	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
	159	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
	160	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
	161	((CHANNEL) == LL_DMA_CHANNEL_6))))
	162	#else
	163	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
	164	(((CHANNEL) == LL_DMA_CHANNEL_1)\|\| \
	165	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
	166	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
	167	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
	168	((CHANNEL) == LL_DMA_CHANNEL_5))))
	169	#endif /* DMA1_Channel6 && DMA1_Channel7 */
	170	#endif
	171	/**
	172	* @}
	173	*/
	174
	175	/* Private function prototypes -----------------------------------------------*/
	176
	177	/* Exported functions --------------------------------------------------------*/
	178	/** @addtogroup DMA_LL_Exported_Functions
	179	* @{
	180	*/
	181
	182	/** @addtogroup DMA_LL_EF_Init
	183	* @{
	184	*/
	185
	186	/**
	187	* @brief De-initialize the DMA registers to their default reset values.
	188	* @param DMAx DMAx Instance
	189	* @param Channel This parameter can be one of the following values:
	190	* @arg @ref LL_DMA_CHANNEL_1
	191	* @arg @ref LL_DMA_CHANNEL_2
	192	* @arg @ref LL_DMA_CHANNEL_3
	193	* @arg @ref LL_DMA_CHANNEL_4
	194	* @arg @ref LL_DMA_CHANNEL_5
	195	* @arg @ref LL_DMA_CHANNEL_6 (*)
	196	* @arg @ref LL_DMA_CHANNEL_7 (*)
	197	*
	198	* (*) value not defined in all devices
	199	* @retval An ErrorStatus enumeration value:
	200	* - SUCCESS: DMA registers are de-initialized
	201	* - ERROR: DMA registers are not de-initialized
	202	*/
	203	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
	204	{
	205	DMA_Channel_TypeDef tmp = (DMA_Channel_TypeDef )DMA1_Channel1;
	206	ErrorStatus status = SUCCESS;
	207
	208	/* Check the DMA Instance DMAx and Channel parameters*/
	209	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
	210
	211	tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
	212
	213	/* Disable the selected DMAx_Channely */
	214	CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
	215
	216	/* Reset DMAx_Channely control register */
	217	LL_DMA_WriteReg(tmp, CCR, 0U);
	218
	219	/* Reset DMAx_Channely remaining bytes register */
	220	LL_DMA_WriteReg(tmp, CNDTR, 0U);
	221
	222	/* Reset DMAx_Channely peripheral address register */
	223	LL_DMA_WriteReg(tmp, CPAR, 0U);
	224
	225	/* Reset DMAx_Channely memory address register */
	226	LL_DMA_WriteReg(tmp, CMAR, 0U);
	227
	228	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
	229	/* Reset Request register field for DMAx Channel */
	230	LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
	231	#endif
	232
	233	if (Channel == LL_DMA_CHANNEL_1)
	234	{
	235	/* Reset interrupt pending bits for DMAx Channel1 */
	236	LL_DMA_ClearFlag_GI1(DMAx);
	237	}
	238	else if (Channel == LL_DMA_CHANNEL_2)
	239	{
	240	/* Reset interrupt pending bits for DMAx Channel2 */
	241	LL_DMA_ClearFlag_GI2(DMAx);
	242	}
	243	else if (Channel == LL_DMA_CHANNEL_3)
	244	{
	245	/* Reset interrupt pending bits for DMAx Channel3 */
	246	LL_DMA_ClearFlag_GI3(DMAx);
	247	}
	248	else if (Channel == LL_DMA_CHANNEL_4)
	249	{
	250	/* Reset interrupt pending bits for DMAx Channel4 */
	251	LL_DMA_ClearFlag_GI4(DMAx);
	252	}
	253	else if (Channel == LL_DMA_CHANNEL_5)
	254	{
	255	/* Reset interrupt pending bits for DMAx Channel5 */
	256	LL_DMA_ClearFlag_GI5(DMAx);
	257	}
	258
	259	#if defined(DMA1_Channel6)
	260	else if (Channel == LL_DMA_CHANNEL_6)
	261	{
	262	/* Reset interrupt pending bits for DMAx Channel6 */
	263	LL_DMA_ClearFlag_GI6(DMAx);
	264	}
	265	#endif
	266	#if defined(DMA1_Channel7)
	267	else if (Channel == LL_DMA_CHANNEL_7)
	268	{
	269	/* Reset interrupt pending bits for DMAx Channel7 */
	270	LL_DMA_ClearFlag_GI7(DMAx);
	271	}
	272	#endif
	273	else
	274	{
	275	status = ERROR;
	276	}
	277
	278	return status;
	279	}
	280
	281	/**
	282	* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
	283	* @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
	284	* @arg @ref __LL_DMA_GET_INSTANCE
	285	* @arg @ref __LL_DMA_GET_CHANNEL
	286	* @param DMAx DMAx Instance
	287	* @param Channel This parameter can be one of the following values:
	288	* @arg @ref LL_DMA_CHANNEL_1
	289	* @arg @ref LL_DMA_CHANNEL_2
	290	* @arg @ref LL_DMA_CHANNEL_3
	291	* @arg @ref LL_DMA_CHANNEL_4
	292	* @arg @ref LL_DMA_CHANNEL_5
	293	* @arg @ref LL_DMA_CHANNEL_6 (*)
	294	* @arg @ref LL_DMA_CHANNEL_7 (*)
	295	*
	296	* (*) value not defined in all devices
	297	* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
	298	* @retval An ErrorStatus enumeration value:
	299	* - SUCCESS: DMA registers are initialized
	300	* - ERROR: Not applicable
	301	*/
	302	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct)
	303	{
	304	/* Check the DMA Instance DMAx and Channel parameters*/
	305	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
	306
	307	/* Check the DMA parameters from DMA_InitStruct */
	308	assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
	309	assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
	310	assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
	311	assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
	312	assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
	313	assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
	314	assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
	315	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
	316	assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
	317	#endif
	318	assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
	319
	320	/*---------------------------- DMAx CCR Configuration ------------------------
	321	* Configure DMAx_Channely: data transfer direction, data transfer mode,
	322	* peripheral and memory increment mode,
	323	* data size alignment and priority level with parameters :
	324	* - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
	325	* - Mode: DMA_CCR_CIRC bit
	326	* - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
	327	* - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
	328	* - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
	329	* - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
	330	* - Priority: DMA_CCR_PL[1:0] bits
	331	*/
	332	LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction \| \
	333	DMA_InitStruct->Mode \| \
	334	DMA_InitStruct->PeriphOrM2MSrcIncMode \| \
	335	DMA_InitStruct->MemoryOrM2MDstIncMode \| \
	336	DMA_InitStruct->PeriphOrM2MSrcDataSize \| \
	337	DMA_InitStruct->MemoryOrM2MDstDataSize \| \
	338	DMA_InitStruct->Priority);
	339
	340	/*-------------------------- DMAx CMAR Configuration -------------------------
	341	* Configure the memory or destination base address with parameter :
	342	* - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
	343	*/
	344	LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
	345
	346	/*-------------------------- DMAx CPAR Configuration -------------------------
	347	* Configure the peripheral or source base address with parameter :
	348	* - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
	349	*/
	350	LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
	351
	352	/*--------------------------- DMAx CNDTR Configuration -----------------------
	353	* Configure the peripheral base address with parameter :
	354	* - NbData: DMA_CNDTR_NDT[15:0] bits
	355	*/
	356	LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
	357
	358	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
	359	/*--------------------------- DMAx CSELR Configuration -----------------------
	360	* Configure the DMA request for DMA instance on Channel x with parameter :
	361	* - PeriphRequest: DMA_CSELR[31:0] bits
	362	*/
	363	LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
	364	#endif
	365
	366	return SUCCESS;
	367	}
	368
	369	/**
	370	* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
	371	* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
	372	* @retval None
	373	*/
	374	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
	375	{
	376	/* Set DMA_InitStruct fields to default values */
	377	DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
	378	DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
	379	DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
	380	DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
	381	DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
	382	DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
	383	DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
	384	DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
	385	DMA_InitStruct->NbData = 0x00000000U;
	386	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
	387	DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0;
	388	#endif
	389	DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
	390	}
	391
	392	/**
	393	* @}
	394	*/
	395
	396	/**
	397	* @}
	398	*/
	399
	400	/**
	401	* @}
	402	*/
	403
	404	#endif /* DMA1 \|\| DMA2 */
	405
	406	/**
	407	* @}
	408	*/
	409
	410	#endif /* USE_FULL_LL_DRIVER */
	411
	412	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/