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2022-10-17 6a62617e99d79314d1e10995fbc29fbb00419a6e

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bfc108	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_hal_tim.c
	4	* @author MCD Application Team
	5	* @brief TIM HAL module driver.
	6	* This file provides firmware functions to manage the following
	7	* functionalities of the Timer (TIM) peripheral:
	8	* + Time Base Initialization
	9	* + Time Base Start
	10	* + Time Base Start Interruption
	11	* + Time Base Start DMA
	12	* + Time Output Compare/PWM Initialization
	13	* + Time Output Compare/PWM Channel Configuration
	14	* + Time Output Compare/PWM Start
	15	* + Time Output Compare/PWM Start Interruption
	16	* + Time Output Compare/PWM Start DMA
	17	* + Time Input Capture Initialization
	18	* + Time Input Capture Channel Configuration
	19	* + Time Input Capture Start
	20	* + Time Input Capture Start Interruption
	21	* + Time Input Capture Start DMA
	22	* + Time One Pulse Initialization
	23	* + Time One Pulse Channel Configuration
	24	* + Time One Pulse Start
	25	* + Time Encoder Interface Initialization
	26	* + Time Encoder Interface Start
	27	* + Time Encoder Interface Start Interruption
	28	* + Time Encoder Interface Start DMA
	29	* + Commutation Event configuration with Interruption and DMA
	30	* + Time OCRef clear configuration
	31	* + Time External Clock configuration
	32	@verbatim
	33	==============================================================================
	34	##### TIMER Generic features #####
	35	==============================================================================
	36	[..] The Timer features include:
	37	(#) 16-bit up, down, up/down auto-reload counter.
	38	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
	39	counter clock frequency either by any factor between 1 and 65536.
	40	(#) Up to 4 independent channels for:
	41	(++) Input Capture
	42	(++) Output Compare
	43	(++) PWM generation (Edge and Center-aligned Mode)
	44	(++) One-pulse mode output
	45
	46	##### How to use this driver #####
	47	==============================================================================
	48	[..]
	49	(#) Initialize the TIM low level resources by implementing the following functions
	50	depending from feature used :
	51	(++) Time Base : HAL_TIM_Base_MspInit()
	52	(++) Input Capture : HAL_TIM_IC_MspInit()
	53	(++) Output Compare : HAL_TIM_OC_MspInit()
	54	(++) PWM generation : HAL_TIM_PWM_MspInit()
	55	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
	56	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
	57
	58	(#) Initialize the TIM low level resources :
	59	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
	60	(##) TIM pins configuration
	61	(+++) Enable the clock for the TIM GPIOs using the following function:
	62	__HAL_RCC_GPIOx_CLK_ENABLE();
	63	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
	64
	65	(#) The external Clock can be configured, if needed (the default clock is the
	66	internal clock from the APBx), using the following function:
	67	HAL_TIM_ConfigClockSource, the clock configuration should be done before
	68	any start function.
	69
	70	(#) Configure the TIM in the desired functioning mode using one of the
	71	Initialization function of this driver:
	72	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
	73	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
	74	Output Compare signal.
	75	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
	76	PWM signal.
	77	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
	78	external signal.
	79	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
	80	in One Pulse Mode.
	81	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
	82
	83	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
	84	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
	85	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
	86	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
	87	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
	88	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
	89	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
	90
	91	(#) The DMA Burst is managed with the two following functions:
	92	HAL_TIM_DMABurst_WriteStart()
	93	HAL_TIM_DMABurst_ReadStart()
	94
	95	@endverbatim
	96	******************************************************************************
	97	* @attention
	98	*
	99	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	100	*
	101	* Redistribution and use in source and binary forms, with or without modification,
	102	* are permitted provided that the following conditions are met:
	103	* 1. Redistributions of source code must retain the above copyright notice,
	104	* this list of conditions and the following disclaimer.
	105	* 2. Redistributions in binary form must reproduce the above copyright notice,
	106	* this list of conditions and the following disclaimer in the documentation
	107	* and/or other materials provided with the distribution.
	108	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	109	* may be used to endorse or promote products derived from this software
	110	* without specific prior written permission.
	111	*
	112	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	113	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	114	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	115	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	116	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	117	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	118	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	119	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	120	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	121	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	122	*
	123	******************************************************************************
	124	*/
	125
	126	/* Includes ------------------------------------------------------------------*/
	127	#include "stm32f0xx_hal.h"
	128
	129	/** @addtogroup STM32F0xx_HAL_Driver
	130	* @{
	131	*/
	132
	133	/** @defgroup TIM TIM
	134	* @brief TIM HAL module driver
	135	* @{
	136	*/
	137
	138	#ifdef HAL_TIM_MODULE_ENABLED
	139
	140	/* Private typedef -----------------------------------------------------------*/
	141	/* Private define ------------------------------------------------------------*/
	142	/* Private macro -------------------------------------------------------------*/
	143	/* Private variables ---------------------------------------------------------*/
	144	/* Private function prototypes -----------------------------------------------*/
	145
	146	/** @defgroup TIM_Private_Functions TIM_Private_Functions
	147	* @{
	148	*/
	149	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
	150	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
	151	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
	152	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
	153	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
	154	uint32_t TIM_ICFilter);
	155	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
	156	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
	157	uint32_t TIM_ICFilter);
	158	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
	159	uint32_t TIM_ICFilter);
	160	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
	161	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
	162	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
	163	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
	164	TIM_SlaveConfigTypeDef * sSlaveConfig);
	165
	166	/**
	167	* @}
	168	*/
	169
	170	/* Exported functions ---------------------------------------------------------*/
	171
	172	/** @defgroup TIM_Exported_Functions TIM Exported Functions
	173	* @{
	174	*/
	175
	176	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
	177	* @brief Time Base functions
	178	*
	179	@verbatim
	180	==============================================================================
	181	##### Time Base functions #####
	182	==============================================================================
	183	[..]
	184	This section provides functions allowing to:
	185	(+) Initialize and configure the TIM base.
	186	(+) De-initialize the TIM base.
	187	(+) Start the Time Base.
	188	(+) Stop the Time Base.
	189	(+) Start the Time Base and enable interrupt.
	190	(+) Stop the Time Base and disable interrupt.
	191	(+) Start the Time Base and enable DMA transfer.
	192	(+) Stop the Time Base and disable DMA transfer.
	193
	194	@endverbatim
	195	* @{
	196	*/
	197	/**
	198	* @brief Initializes the TIM Time base Unit according to the specified
	199	* parameters in the TIM_HandleTypeDef and create the associated handle.
	200	* @param htim TIM Base handle
	201	* @retval HAL status
	202	*/
	203	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
	204	{
	205	/* Check the TIM handle allocation */
	206	if(htim == NULL)
	207	{
	208	return HAL_ERROR;
	209	}
	210
	211	/* Check the parameters */
	212	assert_param(IS_TIM_INSTANCE(htim->Instance));
	213	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
	214	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
	215	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
	216
	217	if(htim->State == HAL_TIM_STATE_RESET)
	218	{
	219	/* Allocate lock resource and initialize it */
	220	htim->Lock = HAL_UNLOCKED;
	221
	222	/* Init the low level hardware : GPIO, CLOCK, NVIC */
	223	HAL_TIM_Base_MspInit(htim);
	224	}
	225
	226	/* Set the TIM state */
	227	htim->State= HAL_TIM_STATE_BUSY;
	228
	229	/* Set the Time Base configuration */
	230	TIM_Base_SetConfig(htim->Instance, &htim->Init);
	231
	232	/* Initialize the TIM state*/
	233	htim->State= HAL_TIM_STATE_READY;
	234
	235	return HAL_OK;
	236	}
	237
	238	/**
	239	* @brief DeInitializes the TIM Base peripheral
	240	* @param htim TIM Base handle
	241	* @retval HAL status
	242	*/
	243	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
	244	{
	245	/* Check the parameters */
	246	assert_param(IS_TIM_INSTANCE(htim->Instance));
	247
	248	htim->State = HAL_TIM_STATE_BUSY;
	249
	250	/* Disable the TIM Peripheral Clock */
	251	__HAL_TIM_DISABLE(htim);
	252
	253	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
	254	HAL_TIM_Base_MspDeInit(htim);
	255
	256	/* Change TIM state */
	257	htim->State = HAL_TIM_STATE_RESET;
	258
	259	/* Release Lock */
	260	__HAL_UNLOCK(htim);
	261
	262	return HAL_OK;
	263	}
	264
	265	/**
	266	* @brief Initializes the TIM Base MSP.
	267	* @param htim TIM handle
	268	* @retval None
	269	*/
	270	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
	271	{
	272	/* Prevent unused argument(s) compilation warning */
	273	UNUSED(htim);
	274
	275	/* NOTE : This function Should not be modified, when the callback is needed,
	276	the HAL_TIM_Base_MspInit could be implemented in the user file
	277	*/
	278	}
	279
	280	/**
	281	* @brief DeInitializes TIM Base MSP.
	282	* @param htim TIM handle
	283	* @retval None
	284	*/
	285	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
	286	{
	287	/* Prevent unused argument(s) compilation warning */
	288	UNUSED(htim);
	289
	290	/* NOTE : This function Should not be modified, when the callback is needed,
	291	the HAL_TIM_Base_MspDeInit could be implemented in the user file
	292	*/
	293	}
	294
	295
	296	/**
	297	* @brief Starts the TIM Base generation.
	298	* @param htim TIM handle
	299	* @retval HAL status
	300	*/
	301	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
	302	{
	303	/* Check the parameters */
	304	assert_param(IS_TIM_INSTANCE(htim->Instance));
	305
	306	/* Set the TIM state */
	307	htim->State= HAL_TIM_STATE_BUSY;
	308
	309	/* Enable the Peripheral */
	310	__HAL_TIM_ENABLE(htim);
	311
	312	/* Change the TIM state*/
	313	htim->State= HAL_TIM_STATE_READY;
	314
	315	/* Return function status */
	316	return HAL_OK;
	317	}
	318
	319	/**
	320	* @brief Stops the TIM Base generation.
	321	* @param htim TIM handle
	322	* @retval HAL status
	323	*/
	324	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
	325	{
	326	/* Check the parameters */
	327	assert_param(IS_TIM_INSTANCE(htim->Instance));
	328
	329	/* Set the TIM state */
	330	htim->State= HAL_TIM_STATE_BUSY;
	331
	332	/* Disable the Peripheral */
	333	__HAL_TIM_DISABLE(htim);
	334
	335	/* Change the TIM state*/
	336	htim->State= HAL_TIM_STATE_READY;
	337
	338	/* Return function status */
	339	return HAL_OK;
	340	}
	341
	342	/**
	343	* @brief Starts the TIM Base generation in interrupt mode.
	344	* @param htim TIM handle
	345	* @retval HAL status
	346	*/
	347	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
	348	{
	349	/* Check the parameters */
	350	assert_param(IS_TIM_INSTANCE(htim->Instance));
	351
	352	/* Enable the TIM Update interrupt */
	353	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
	354
	355	/* Enable the Peripheral */
	356	__HAL_TIM_ENABLE(htim);
	357
	358	/* Return function status */
	359	return HAL_OK;
	360	}
	361
	362	/**
	363	* @brief Stops the TIM Base generation in interrupt mode.
	364	* @param htim TIM handle
	365	* @retval HAL status
	366	*/
	367	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
	368	{
	369	/* Check the parameters */
	370	assert_param(IS_TIM_INSTANCE(htim->Instance));
	371	/* Disable the TIM Update interrupt */
	372	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
	373
	374	/* Disable the Peripheral */
	375	__HAL_TIM_DISABLE(htim);
	376
	377	/* Return function status */
	378	return HAL_OK;
	379	}
	380
	381	/**
	382	* @brief Starts the TIM Base generation in DMA mode.
	383	* @param htim TIM handle
	384	* @param pData The source Buffer address.
	385	* @param Length The length of data to be transferred from memory to peripheral.
	386	* @retval HAL status
	387	*/
	388	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
	389	{
	390	/* Check the parameters */
	391	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
	392
	393	if((htim->State == HAL_TIM_STATE_BUSY))
	394	{
	395	return HAL_BUSY;
	396	}
	397	else if((htim->State == HAL_TIM_STATE_READY))
	398	{
	399	if((pData == 0 ) && (Length > 0))
	400	{
	401	return HAL_ERROR;
	402	}
	403	else
	404	{
	405	htim->State = HAL_TIM_STATE_BUSY;
	406	}
	407	}
	408	/* Set the DMA Period elapsed callback */
	409	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
	410
	411	/* Set the DMA error callback */
	412	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
	413
	414	/* Enable the DMA channel */
	415	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
	416
	417	/* Enable the TIM Update DMA request */
	418	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
	419
	420	/* Enable the Peripheral */
	421	__HAL_TIM_ENABLE(htim);
	422
	423	/* Return function status */
	424	return HAL_OK;
	425	}
	426
	427	/**
	428	* @brief Stops the TIM Base generation in DMA mode.
	429	* @param htim TIM handle
	430	* @retval HAL status
	431	*/
	432	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
	433	{
	434	/* Check the parameters */
	435	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
	436
	437	/* Disable the TIM Update DMA request */
	438	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
	439
	440	/* Disable the Peripheral */
	441	__HAL_TIM_DISABLE(htim);
	442
	443	/* Change the htim state */
	444	htim->State = HAL_TIM_STATE_READY;
	445
	446	/* Return function status */
	447	return HAL_OK;
	448	}
	449
	450	/**
	451	* @}
	452	*/
	453
	454	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
	455	* @brief Time Output Compare functions
	456	*
	457	@verbatim
	458	==============================================================================
	459	##### Time Output Compare functions #####
	460	==============================================================================
	461	[..]
	462	This section provides functions allowing to:
	463	(+) Initialize and configure the TIM Output Compare.
	464	(+) De-initialize the TIM Output Compare.
	465	(+) Start the Time Output Compare.
	466	(+) Stop the Time Output Compare.
	467	(+) Start the Time Output Compare and enable interrupt.
	468	(+) Stop the Time Output Compare and disable interrupt.
	469	(+) Start the Time Output Compare and enable DMA transfer.
	470	(+) Stop the Time Output Compare and disable DMA transfer.
	471
	472	@endverbatim
	473	* @{
	474	*/
	475	/**
	476	* @brief Initializes the TIM Output Compare according to the specified
	477	* parameters in the TIM_HandleTypeDef and create the associated handle.
	478	* @param htim TIM Output Compare handle
	479	* @retval HAL status
	480	*/
	481	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
	482	{
	483	/* Check the TIM handle allocation */
	484	if(htim == NULL)
	485	{
	486	return HAL_ERROR;
	487	}
	488
	489	/* Check the parameters */
	490	assert_param(IS_TIM_INSTANCE(htim->Instance));
	491	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
	492	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
	493	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
	494
	495	if(htim->State == HAL_TIM_STATE_RESET)
	496	{
	497	/* Allocate lock resource and initialize it */
	498	htim->Lock = HAL_UNLOCKED;
	499
	500	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
	501	HAL_TIM_OC_MspInit(htim);
	502	}
	503
	504	/* Set the TIM state */
	505	htim->State= HAL_TIM_STATE_BUSY;
	506
	507	/* Init the base time for the Output Compare */
	508	TIM_Base_SetConfig(htim->Instance, &htim->Init);
	509
	510	/* Initialize the TIM state*/
	511	htim->State= HAL_TIM_STATE_READY;
	512
	513	return HAL_OK;
	514	}
	515
	516	/**
	517	* @brief DeInitializes the TIM peripheral
	518	* @param htim TIM Output Compare handle
	519	* @retval HAL status
	520	*/
	521	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
	522	{
	523	/* Check the parameters */
	524	assert_param(IS_TIM_INSTANCE(htim->Instance));
	525
	526	htim->State = HAL_TIM_STATE_BUSY;
	527
	528	/* Disable the TIM Peripheral Clock */
	529	__HAL_TIM_DISABLE(htim);
	530
	531	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
	532	HAL_TIM_OC_MspDeInit(htim);
	533
	534	/* Change TIM state */
	535	htim->State = HAL_TIM_STATE_RESET;
	536
	537	/* Release Lock */
	538	__HAL_UNLOCK(htim);
	539
	540	return HAL_OK;
	541	}
	542
	543	/**
	544	* @brief Initializes the TIM Output Compare MSP.
	545	* @param htim TIM handle
	546	* @retval None
	547	*/
	548	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
	549	{
	550	/* Prevent unused argument(s) compilation warning */
	551	UNUSED(htim);
	552
	553	/* NOTE : This function Should not be modified, when the callback is needed,
	554	the HAL_TIM_OC_MspInit could be implemented in the user file
	555	*/
	556	}
	557
	558	/**
	559	* @brief DeInitializes TIM Output Compare MSP.
	560	* @param htim TIM handle
	561	* @retval None
	562	*/
	563	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
	564	{
	565	/* Prevent unused argument(s) compilation warning */
	566	UNUSED(htim);
	567
	568	/* NOTE : This function Should not be modified, when the callback is needed,
	569	the HAL_TIM_OC_MspDeInit could be implemented in the user file
	570	*/
	571	}
	572
	573	/**
	574	* @brief Starts the TIM Output Compare signal generation.
	575	* @param htim TIM Output Compare handle
	576	* @param Channel TIM Channel to be enabled
	577	* This parameter can be one of the following values:
	578	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	579	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	580	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	581	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	582	* @retval HAL status
	583	*/
	584	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
	585	{
	586	/* Check the parameters */
	587	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	588
	589	/* Enable the Output compare channel */
	590	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
	591
	592	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	593	{
	594	/* Enable the main output */
	595	__HAL_TIM_MOE_ENABLE(htim);
	596	}
	597
	598	/* Enable the Peripheral */
	599	__HAL_TIM_ENABLE(htim);
	600
	601	/* Return function status */
	602	return HAL_OK;
	603	}
	604
	605	/**
	606	* @brief Stops the TIM Output Compare signal generation.
	607	* @param htim TIM handle
	608	* @param Channel TIM Channel to be disabled
	609	* This parameter can be one of the following values:
	610	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	611	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	612	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	613	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	614	* @retval HAL status
	615	*/
	616	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
	617	{
	618	/* Check the parameters */
	619	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	620
	621	/* Disable the Output compare channel */
	622	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
	623
	624	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	625	{
	626	/* Disable the Main Ouput */
	627	__HAL_TIM_MOE_DISABLE(htim);
	628	}
	629
	630	/* Disable the Peripheral */
	631	__HAL_TIM_DISABLE(htim);
	632
	633	/* Return function status */
	634	return HAL_OK;
	635	}
	636
	637	/**
	638	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
	639	* @param htim TIM OC handle
	640	* @param Channel TIM Channel to be enabled
	641	* This parameter can be one of the following values:
	642	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	643	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	644	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	645	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	646	* @retval HAL status
	647	*/
	648	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
	649	{
	650	/* Check the parameters */
	651	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	652
	653	switch (Channel)
	654	{
	655	case TIM_CHANNEL_1:
	656	{
	657	/* Enable the TIM Capture/Compare 1 interrupt */
	658	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
	659	}
	660	break;
	661
	662	case TIM_CHANNEL_2:
	663	{
	664	/* Enable the TIM Capture/Compare 2 interrupt */
	665	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
	666	}
	667	break;
	668
	669	case TIM_CHANNEL_3:
	670	{
	671	/* Enable the TIM Capture/Compare 3 interrupt */
	672	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
	673	}
	674	break;
	675
	676	case TIM_CHANNEL_4:
	677	{
	678	/* Enable the TIM Capture/Compare 4 interrupt */
	679	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
	680	}
	681	break;
	682
	683	default:
	684	break;
	685	}
	686
	687	/* Enable the Output compare channel */
	688	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
	689
	690	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	691	{
	692	/* Enable the main output */
	693	__HAL_TIM_MOE_ENABLE(htim);
	694	}
	695
	696	/* Enable the Peripheral */
	697	__HAL_TIM_ENABLE(htim);
	698
	699	/* Return function status */
	700	return HAL_OK;
	701	}
	702
	703	/**
	704	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
	705	* @param htim TIM Output Compare handle
	706	* @param Channel TIM Channel to be disabled
	707	* This parameter can be one of the following values:
	708	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	709	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	710	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	711	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	712	* @retval HAL status
	713	*/
	714	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
	715	{
	716	/* Check the parameters */
	717	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	718
	719	switch (Channel)
	720	{
	721	case TIM_CHANNEL_1:
	722	{
	723	/* Disable the TIM Capture/Compare 1 interrupt */
	724	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
	725	}
	726	break;
	727
	728	case TIM_CHANNEL_2:
	729	{
	730	/* Disable the TIM Capture/Compare 2 interrupt */
	731	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
	732	}
	733	break;
	734
	735	case TIM_CHANNEL_3:
	736	{
	737	/* Disable the TIM Capture/Compare 3 interrupt */
	738	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
	739	}
	740	break;
	741
	742	case TIM_CHANNEL_4:
	743	{
	744	/* Disable the TIM Capture/Compare 4 interrupt */
	745	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
	746	}
	747	break;
	748
	749	default:
	750	break;
	751	}
	752
	753	/* Disable the Output compare channel */
	754	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
	755
	756	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	757	{
	758	/* Disable the Main Ouput */
	759	__HAL_TIM_MOE_DISABLE(htim);
	760	}
	761
	762	/* Disable the Peripheral */
	763	__HAL_TIM_DISABLE(htim);
	764
	765	/* Return function status */
	766	return HAL_OK;
	767	}
	768
	769	/**
	770	* @brief Starts the TIM Output Compare signal generation in DMA mode.
	771	* @param htim TIM Output Compare handle
	772	* @param Channel TIM Channel to be enabled
	773	* This parameter can be one of the following values:
	774	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	775	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	776	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	777	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	778	* @param pData The source Buffer address.
	779	* @param Length The length of data to be transferred from memory to TIM peripheral
	780	* @retval HAL status
	781	*/
	782	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
	783	{
	784	/* Check the parameters */
	785	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	786
	787	if((htim->State == HAL_TIM_STATE_BUSY))
	788	{
	789	return HAL_BUSY;
	790	}
	791	else if((htim->State == HAL_TIM_STATE_READY))
	792	{
	793	if(((uint32_t)pData == 0U ) && (Length > 0U))
	794	{
	795	return HAL_ERROR;
	796	}
	797	else
	798	{
	799	htim->State = HAL_TIM_STATE_BUSY;
	800	}
	801	}
	802	switch (Channel)
	803	{
	804	case TIM_CHANNEL_1:
	805	{
	806	/* Set the DMA Period elapsed callback */
	807	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
	808
	809	/* Set the DMA error callback */
	810	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
	811
	812	/* Enable the DMA channel */
	813	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
	814
	815	/* Enable the TIM Capture/Compare 1 DMA request */
	816	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
	817	}
	818	break;
	819
	820	case TIM_CHANNEL_2:
	821	{
	822	/* Set the DMA Period elapsed callback */
	823	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
	824
	825	/* Set the DMA error callback */
	826	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
	827
	828	/* Enable the DMA channel */
	829	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
	830
	831	/* Enable the TIM Capture/Compare 2 DMA request */
	832	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
	833	}
	834	break;
	835
	836	case TIM_CHANNEL_3:
	837	{
	838	/* Set the DMA Period elapsed callback */
	839	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
	840
	841	/* Set the DMA error callback */
	842	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
	843
	844	/* Enable the DMA channel */
	845	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
	846
	847	/* Enable the TIM Capture/Compare 3 DMA request */
	848	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
	849	}
	850	break;
	851
	852	case TIM_CHANNEL_4:
	853	{
	854	/* Set the DMA Period elapsed callback */
	855	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
	856
	857	/* Set the DMA error callback */
	858	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
	859
	860	/* Enable the DMA channel */
	861	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
	862
	863	/* Enable the TIM Capture/Compare 4 DMA request */
	864	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
	865	}
	866	break;
	867
	868	default:
	869	break;
	870	}
	871
	872	/* Enable the Output compare channel */
	873	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
	874
	875	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	876	{
	877	/* Enable the main output */
	878	__HAL_TIM_MOE_ENABLE(htim);
	879	}
	880
	881	/* Enable the Peripheral */
	882	__HAL_TIM_ENABLE(htim);
	883
	884	/* Return function status */
	885	return HAL_OK;
	886	}
	887
	888	/**
	889	* @brief Stops the TIM Output Compare signal generation in DMA mode.
	890	* @param htim TIM Output Compare handle
	891	* @param Channel TIM Channel to be disabled
	892	* This parameter can be one of the following values:
	893	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	894	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	895	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	896	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	897	* @retval HAL status
	898	*/
	899	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
	900	{
	901	/* Check the parameters */
	902	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	903
	904	switch (Channel)
	905	{
	906	case TIM_CHANNEL_1:
	907	{
	908	/* Disable the TIM Capture/Compare 1 DMA request */
	909	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
	910	}
	911	break;
	912
	913	case TIM_CHANNEL_2:
	914	{
	915	/* Disable the TIM Capture/Compare 2 DMA request */
	916	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
	917	}
	918	break;
	919
	920	case TIM_CHANNEL_3:
	921	{
	922	/* Disable the TIM Capture/Compare 3 DMA request */
	923	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
	924	}
	925	break;
	926
	927	case TIM_CHANNEL_4:
	928	{
	929	/* Disable the TIM Capture/Compare 4 interrupt */
	930	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
	931	}
	932	break;
	933
	934	default:
	935	break;
	936	}
	937
	938	/* Disable the Output compare channel */
	939	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
	940
	941	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	942	{
	943	/* Disable the Main Ouput */
	944	__HAL_TIM_MOE_DISABLE(htim);
	945	}
	946
	947	/* Disable the Peripheral */
	948	__HAL_TIM_DISABLE(htim);
	949
	950	/* Change the htim state */
	951	htim->State = HAL_TIM_STATE_READY;
	952
	953	/* Return function status */
	954	return HAL_OK;
	955	}
	956
	957	/**
	958	* @}
	959	*/
	960
	961	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
	962	* @brief Time PWM functions
	963	*
	964	@verbatim
	965	==============================================================================
	966	##### Time PWM functions #####
	967	==============================================================================
	968	[..]
	969	This section provides functions allowing to:
	970	(+) Initialize and configure the TIM OPWM.
	971	(+) De-initialize the TIM PWM.
	972	(+) Start the Time PWM.
	973	(+) Stop the Time PWM.
	974	(+) Start the Time PWM and enable interrupt.
	975	(+) Stop the Time PWM and disable interrupt.
	976	(+) Start the Time PWM and enable DMA transfer.
	977	(+) Stop the Time PWM and disable DMA transfer.
	978
	979	@endverbatim
	980	* @{
	981	*/
	982	/**
	983	* @brief Initializes the TIM PWM Time Base according to the specified
	984	* parameters in the TIM_HandleTypeDef and create the associated handle.
	985	* @param htim TIM handle
	986	* @retval HAL status
	987	*/
	988	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
	989	{
	990	/* Check the TIM handle allocation */
	991	if(htim == NULL)
	992	{
	993	return HAL_ERROR;
	994	}
	995
	996	/* Check the parameters */
	997	assert_param(IS_TIM_INSTANCE(htim->Instance));
	998	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
	999	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
	1000	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
	1001
	1002	if(htim->State == HAL_TIM_STATE_RESET)
	1003	{
	1004	/* Allocate lock resource and initialize it */
	1005	htim->Lock = HAL_UNLOCKED;
	1006
	1007	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
	1008	HAL_TIM_PWM_MspInit(htim);
	1009	}
	1010
	1011	/* Set the TIM state */
	1012	htim->State= HAL_TIM_STATE_BUSY;
	1013
	1014	/* Init the base time for the PWM */
	1015	TIM_Base_SetConfig(htim->Instance, &htim->Init);
	1016
	1017	/* Initialize the TIM state*/
	1018	htim->State= HAL_TIM_STATE_READY;
	1019
	1020	return HAL_OK;
	1021	}
	1022
	1023	/**
	1024	* @brief DeInitializes the TIM peripheral
	1025	* @param htim TIM handle
	1026	* @retval HAL status
	1027	*/
	1028	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
	1029	{
	1030	/* Check the parameters */
	1031	assert_param(IS_TIM_INSTANCE(htim->Instance));
	1032
	1033	htim->State = HAL_TIM_STATE_BUSY;
	1034
	1035	/* Disable the TIM Peripheral Clock */
	1036	__HAL_TIM_DISABLE(htim);
	1037
	1038	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
	1039	HAL_TIM_PWM_MspDeInit(htim);
	1040
	1041	/* Change TIM state */
	1042	htim->State = HAL_TIM_STATE_RESET;
	1043
	1044	/* Release Lock */
	1045	__HAL_UNLOCK(htim);
	1046
	1047	return HAL_OK;
	1048	}
	1049
	1050	/**
	1051	* @brief Initializes the TIM PWM MSP.
	1052	* @param htim TIM handle
	1053	* @retval None
	1054	*/
	1055	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
	1056	{
	1057	/* Prevent unused argument(s) compilation warning */
	1058	UNUSED(htim);
	1059
	1060	/* NOTE : This function Should not be modified, when the callback is needed,
	1061	the HAL_TIM_PWM_MspInit could be implemented in the user file
	1062	*/
	1063	}
	1064
	1065	/**
	1066	* @brief DeInitializes TIM PWM MSP.
	1067	* @param htim TIM handle
	1068	* @retval None
	1069	*/
	1070	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
	1071	{
	1072	/* Prevent unused argument(s) compilation warning */
	1073	UNUSED(htim);
	1074
	1075	/* NOTE : This function Should not be modified, when the callback is needed,
	1076	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
	1077	*/
	1078	}
	1079
	1080	/**
	1081	* @brief Starts the PWM signal generation.
	1082	* @param htim TIM handle
	1083	* @param Channel TIM Channels to be enabled
	1084	* This parameter can be one of the following values:
	1085	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1086	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1087	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1088	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1089	* @retval HAL status
	1090	*/
	1091	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
	1092	{
	1093	/* Check the parameters */
	1094	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1095
	1096	/* Enable the Capture compare channel */
	1097	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
	1098
	1099	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	1100	{
	1101	/* Enable the main output */
	1102	__HAL_TIM_MOE_ENABLE(htim);
	1103	}
	1104
	1105	/* Enable the Peripheral */
	1106	__HAL_TIM_ENABLE(htim);
	1107
	1108	/* Return function status */
	1109	return HAL_OK;
	1110	}
	1111
	1112	/**
	1113	* @brief Stops the PWM signal generation.
	1114	* @param htim TIM handle
	1115	* @param Channel TIM Channels to be disabled
	1116	* This parameter can be one of the following values:
	1117	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1118	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1119	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1120	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1121	* @retval HAL status
	1122	*/
	1123	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
	1124	{
	1125	/* Check the parameters */
	1126	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1127
	1128	/* Disable the Capture compare channel */
	1129	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
	1130
	1131	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	1132	{
	1133	/* Disable the Main Ouput */
	1134	__HAL_TIM_MOE_DISABLE(htim);
	1135	}
	1136
	1137	/* Disable the Peripheral */
	1138	__HAL_TIM_DISABLE(htim);
	1139
	1140	/* Change the htim state */
	1141	htim->State = HAL_TIM_STATE_READY;
	1142
	1143	/* Return function status */
	1144	return HAL_OK;
	1145	}
	1146
	1147	/**
	1148	* @brief Starts the PWM signal generation in interrupt mode.
	1149	* @param htim TIM handle
	1150	* @param Channel TIM Channel to be enabled
	1151	* This parameter can be one of the following values:
	1152	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1153	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1154	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1155	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1156	* @retval HAL status
	1157	*/
	1158	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
	1159	{
	1160	/* Check the parameters */
	1161	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1162
	1163	switch (Channel)
	1164	{
	1165	case TIM_CHANNEL_1:
	1166	{
	1167	/* Enable the TIM Capture/Compare 1 interrupt */
	1168	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
	1169	}
	1170	break;
	1171
	1172	case TIM_CHANNEL_2:
	1173	{
	1174	/* Enable the TIM Capture/Compare 2 interrupt */
	1175	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
	1176	}
	1177	break;
	1178
	1179	case TIM_CHANNEL_3:
	1180	{
	1181	/* Enable the TIM Capture/Compare 3 interrupt */
	1182	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
	1183	}
	1184	break;
	1185
	1186	case TIM_CHANNEL_4:
	1187	{
	1188	/* Enable the TIM Capture/Compare 4 interrupt */
	1189	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
	1190	}
	1191	break;
	1192
	1193	default:
	1194	break;
	1195	}
	1196
	1197	/* Enable the Capture compare channel */
	1198	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
	1199
	1200	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	1201	{
	1202	/* Enable the main output */
	1203	__HAL_TIM_MOE_ENABLE(htim);
	1204	}
	1205
	1206	/* Enable the Peripheral */
	1207	__HAL_TIM_ENABLE(htim);
	1208
	1209	/* Return function status */
	1210	return HAL_OK;
	1211	}
	1212
	1213	/**
	1214	* @brief Stops the PWM signal generation in interrupt mode.
	1215	* @param htim TIM handle
	1216	* @param Channel TIM Channels to be disabled
	1217	* This parameter can be one of the following values:
	1218	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1219	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1220	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1221	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1222	* @retval HAL status
	1223	*/
	1224	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
	1225	{
	1226	/* Check the parameters */
	1227	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1228
	1229	switch (Channel)
	1230	{
	1231	case TIM_CHANNEL_1:
	1232	{
	1233	/* Disable the TIM Capture/Compare 1 interrupt */
	1234	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
	1235	}
	1236	break;
	1237
	1238	case TIM_CHANNEL_2:
	1239	{
	1240	/* Disable the TIM Capture/Compare 2 interrupt */
	1241	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
	1242	}
	1243	break;
	1244
	1245	case TIM_CHANNEL_3:
	1246	{
	1247	/* Disable the TIM Capture/Compare 3 interrupt */
	1248	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
	1249	}
	1250	break;
	1251
	1252	case TIM_CHANNEL_4:
	1253	{
	1254	/* Disable the TIM Capture/Compare 4 interrupt */
	1255	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
	1256	}
	1257	break;
	1258
	1259	default:
	1260	break;
	1261	}
	1262
	1263	/* Disable the Capture compare channel */
	1264	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
	1265
	1266	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	1267	{
	1268	/* Disable the Main Ouput */
	1269	__HAL_TIM_MOE_DISABLE(htim);
	1270	}
	1271
	1272	/* Disable the Peripheral */
	1273	__HAL_TIM_DISABLE(htim);
	1274
	1275	/* Return function status */
	1276	return HAL_OK;
	1277	}
	1278
	1279	/**
	1280	* @brief Starts the TIM PWM signal generation in DMA mode.
	1281	* @param htim TIM handle
	1282	* @param Channel TIM Channels to be enabled
	1283	* This parameter can be one of the following values:
	1284	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1285	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1286	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1287	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1288	* @param pData The source Buffer address.
	1289	* @param Length The length of data to be transferred from memory to TIM peripheral
	1290	* @retval HAL status
	1291	*/
	1292	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
	1293	{
	1294	/* Check the parameters */
	1295	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1296
	1297	if((htim->State == HAL_TIM_STATE_BUSY))
	1298	{
	1299	return HAL_BUSY;
	1300	}
	1301	else if((htim->State == HAL_TIM_STATE_READY))
	1302	{
	1303	if(((uint32_t)pData == 0U ) && (Length > 0U))
	1304	{
	1305	return HAL_ERROR;
	1306	}
	1307	else
	1308	{
	1309	htim->State = HAL_TIM_STATE_BUSY;
	1310	}
	1311	}
	1312	switch (Channel)
	1313	{
	1314	case TIM_CHANNEL_1:
	1315	{
	1316	/* Set the DMA Period elapsed callback */
	1317	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
	1318
	1319	/* Set the DMA error callback */
	1320	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
	1321
	1322	/* Enable the DMA channel */
	1323	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
	1324
	1325	/* Enable the TIM Capture/Compare 1 DMA request */
	1326	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
	1327	}
	1328	break;
	1329
	1330	case TIM_CHANNEL_2:
	1331	{
	1332	/* Set the DMA Period elapsed callback */
	1333	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
	1334
	1335	/* Set the DMA error callback */
	1336	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
	1337
	1338	/* Enable the DMA channel */
	1339	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
	1340
	1341	/* Enable the TIM Capture/Compare 2 DMA request */
	1342	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
	1343	}
	1344	break;
	1345
	1346	case TIM_CHANNEL_3:
	1347	{
	1348	/* Set the DMA Period elapsed callback */
	1349	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
	1350
	1351	/* Set the DMA error callback */
	1352	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
	1353
	1354	/* Enable the DMA channel */
	1355	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
	1356
	1357	/* Enable the TIM Output Capture/Compare 3 request */
	1358	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
	1359	}
	1360	break;
	1361
	1362	case TIM_CHANNEL_4:
	1363	{
	1364	/* Set the DMA Period elapsed callback */
	1365	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
	1366
	1367	/* Set the DMA error callback */
	1368	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
	1369
	1370	/* Enable the DMA channel */
	1371	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
	1372
	1373	/* Enable the TIM Capture/Compare 4 DMA request */
	1374	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
	1375	}
	1376	break;
	1377
	1378	default:
	1379	break;
	1380	}
	1381
	1382	/* Enable the Capture compare channel */
	1383	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
	1384
	1385	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	1386	{
	1387	/* Enable the main output */
	1388	__HAL_TIM_MOE_ENABLE(htim);
	1389	}
	1390
	1391	/* Enable the Peripheral */
	1392	__HAL_TIM_ENABLE(htim);
	1393
	1394	/* Return function status */
	1395	return HAL_OK;
	1396	}
	1397
	1398	/**
	1399	* @brief Stops the TIM PWM signal generation in DMA mode.
	1400	* @param htim TIM handle
	1401	* @param Channel TIM Channels to be disabled
	1402	* This parameter can be one of the following values:
	1403	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1404	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1405	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1406	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1407	* @retval HAL status
	1408	*/
	1409	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
	1410	{
	1411	/* Check the parameters */
	1412	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1413
	1414	switch (Channel)
	1415	{
	1416	case TIM_CHANNEL_1:
	1417	{
	1418	/* Disable the TIM Capture/Compare 1 DMA request */
	1419	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
	1420	}
	1421	break;
	1422
	1423	case TIM_CHANNEL_2:
	1424	{
	1425	/* Disable the TIM Capture/Compare 2 DMA request */
	1426	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
	1427	}
	1428	break;
	1429
	1430	case TIM_CHANNEL_3:
	1431	{
	1432	/* Disable the TIM Capture/Compare 3 DMA request */
	1433	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
	1434	}
	1435	break;
	1436
	1437	case TIM_CHANNEL_4:
	1438	{
	1439	/* Disable the TIM Capture/Compare 4 interrupt */
	1440	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
	1441	}
	1442	break;
	1443
	1444	default:
	1445	break;
	1446	}
	1447
	1448	/* Disable the Capture compare channel */
	1449	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
	1450
	1451	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	1452	{
	1453	/* Disable the Main Ouput */
	1454	__HAL_TIM_MOE_DISABLE(htim);
	1455	}
	1456
	1457	/* Disable the Peripheral */
	1458	__HAL_TIM_DISABLE(htim);
	1459
	1460	/* Change the htim state */
	1461	htim->State = HAL_TIM_STATE_READY;
	1462
	1463	/* Return function status */
	1464	return HAL_OK;
	1465	}
	1466
	1467	/**
	1468	* @}
	1469	*/
	1470
	1471	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
	1472	* @brief Time Input Capture functions
	1473	*
	1474	@verbatim
	1475	==============================================================================
	1476	##### Time Input Capture functions #####
	1477	==============================================================================
	1478	[..]
	1479	This section provides functions allowing to:
	1480	(+) Initialize and configure the TIM Input Capture.
	1481	(+) De-initialize the TIM Input Capture.
	1482	(+) Start the Time Input Capture.
	1483	(+) Stop the Time Input Capture.
	1484	(+) Start the Time Input Capture and enable interrupt.
	1485	(+) Stop the Time Input Capture and disable interrupt.
	1486	(+) Start the Time Input Capture and enable DMA transfer.
	1487	(+) Stop the Time Input Capture and disable DMA transfer.
	1488
	1489	@endverbatim
	1490	* @{
	1491	*/
	1492	/**
	1493	* @brief Initializes the TIM Input Capture Time base according to the specified
	1494	* parameters in the TIM_HandleTypeDef and create the associated handle.
	1495	* @param htim TIM Input Capture handle
	1496	* @retval HAL status
	1497	*/
	1498	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
	1499	{
	1500	/* Check the TIM handle allocation */
	1501	if(htim == NULL)
	1502	{
	1503	return HAL_ERROR;
	1504	}
	1505
	1506	/* Check the parameters */
	1507	assert_param(IS_TIM_INSTANCE(htim->Instance));
	1508	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
	1509	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
	1510	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
	1511
	1512	if(htim->State == HAL_TIM_STATE_RESET)
	1513	{
	1514	/* Allocate lock resource and initialize it */
	1515	htim->Lock = HAL_UNLOCKED;
	1516
	1517	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
	1518	HAL_TIM_IC_MspInit(htim);
	1519	}
	1520
	1521	/* Set the TIM state */
	1522	htim->State= HAL_TIM_STATE_BUSY;
	1523
	1524	/* Init the base time for the input capture */
	1525	TIM_Base_SetConfig(htim->Instance, &htim->Init);
	1526
	1527	/* Initialize the TIM state*/
	1528	htim->State= HAL_TIM_STATE_READY;
	1529
	1530	return HAL_OK;
	1531	}
	1532
	1533	/**
	1534	* @brief DeInitializes the TIM peripheral
	1535	* @param htim TIM Input Capture handle
	1536	* @retval HAL status
	1537	*/
	1538	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
	1539	{
	1540	/* Check the parameters */
	1541	assert_param(IS_TIM_INSTANCE(htim->Instance));
	1542
	1543	htim->State = HAL_TIM_STATE_BUSY;
	1544
	1545	/* Disable the TIM Peripheral Clock */
	1546	__HAL_TIM_DISABLE(htim);
	1547
	1548	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
	1549	HAL_TIM_IC_MspDeInit(htim);
	1550
	1551	/* Change TIM state */
	1552	htim->State = HAL_TIM_STATE_RESET;
	1553
	1554	/* Release Lock */
	1555	__HAL_UNLOCK(htim);
	1556
	1557	return HAL_OK;
	1558	}
	1559
	1560	/**
	1561	* @brief Initializes the TIM Input Capture MSP.
	1562	* @param htim TIM handle
	1563	* @retval None
	1564	*/
	1565	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
	1566	{
	1567	/* Prevent unused argument(s) compilation warning */
	1568	UNUSED(htim);
	1569
	1570	/* NOTE : This function Should not be modified, when the callback is needed,
	1571	the HAL_TIM_IC_MspInit could be implemented in the user file
	1572	*/
	1573	}
	1574
	1575	/**
	1576	* @brief DeInitializes TIM Input Capture MSP.
	1577	* @param htim TIM handle
	1578	* @retval None
	1579	*/
	1580	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
	1581	{
	1582	/* Prevent unused argument(s) compilation warning */
	1583	UNUSED(htim);
	1584
	1585	/* NOTE : This function Should not be modified, when the callback is needed,
	1586	the HAL_TIM_IC_MspDeInit could be implemented in the user file
	1587	*/
	1588	}
	1589
	1590	/**
	1591	* @brief Starts the TIM Input Capture measurement.
	1592	* @param htim TIM Input Capture handle
	1593	* @param Channel TIM Channels to be enabled
	1594	* This parameter can be one of the following values:
	1595	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1596	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1597	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1598	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1599	* @retval HAL status
	1600	*/
	1601	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
	1602	{
	1603	/* Check the parameters */
	1604	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1605
	1606	/* Enable the Input Capture channel */
	1607	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
	1608
	1609	/* Enable the Peripheral */
	1610	__HAL_TIM_ENABLE(htim);
	1611
	1612	/* Return function status */
	1613	return HAL_OK;
	1614	}
	1615
	1616	/**
	1617	* @brief Stops the TIM Input Capture measurement.
	1618	* @param htim TIM handle
	1619	* @param Channel TIM Channels to be disabled
	1620	* This parameter can be one of the following values:
	1621	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1622	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1623	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1624	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1625	* @retval HAL status
	1626	*/
	1627	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
	1628	{
	1629	/* Check the parameters */
	1630	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1631
	1632	/* Disable the Input Capture channel */
	1633	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
	1634
	1635	/* Disable the Peripheral */
	1636	__HAL_TIM_DISABLE(htim);
	1637
	1638	/* Return function status */
	1639	return HAL_OK;
	1640	}
	1641
	1642	/**
	1643	* @brief Starts the TIM Input Capture measurement in interrupt mode.
	1644	* @param htim TIM Input Capture handle
	1645	* @param Channel TIM Channels to be enabled
	1646	* This parameter can be one of the following values:
	1647	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1648	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1649	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1650	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1651	* @retval HAL status
	1652	*/
	1653	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
	1654	{
	1655	/* Check the parameters */
	1656	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1657
	1658	switch (Channel)
	1659	{
	1660	case TIM_CHANNEL_1:
	1661	{
	1662	/* Enable the TIM Capture/Compare 1 interrupt */
	1663	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
	1664	}
	1665	break;
	1666
	1667	case TIM_CHANNEL_2:
	1668	{
	1669	/* Enable the TIM Capture/Compare 2 interrupt */
	1670	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
	1671	}
	1672	break;
	1673
	1674	case TIM_CHANNEL_3:
	1675	{
	1676	/* Enable the TIM Capture/Compare 3 interrupt */
	1677	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
	1678	}
	1679	break;
	1680
	1681	case TIM_CHANNEL_4:
	1682	{
	1683	/* Enable the TIM Capture/Compare 4 interrupt */
	1684	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
	1685	}
	1686	break;
	1687
	1688	default:
	1689	break;
	1690	}
	1691	/* Enable the Input Capture channel */
	1692	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
	1693
	1694	/* Enable the Peripheral */
	1695	__HAL_TIM_ENABLE(htim);
	1696
	1697	/* Return function status */
	1698	return HAL_OK;
	1699	}
	1700
	1701	/**
	1702	* @brief Stops the TIM Input Capture measurement in interrupt mode.
	1703	* @param htim TIM handle
	1704	* @param Channel TIM Channels to be disabled
	1705	* This parameter can be one of the following values:
	1706	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1707	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1708	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1709	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1710	* @retval HAL status
	1711	*/
	1712	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
	1713	{
	1714	/* Check the parameters */
	1715	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1716
	1717	switch (Channel)
	1718	{
	1719	case TIM_CHANNEL_1:
	1720	{
	1721	/* Disable the TIM Capture/Compare 1 interrupt */
	1722	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
	1723	}
	1724	break;
	1725
	1726	case TIM_CHANNEL_2:
	1727	{
	1728	/* Disable the TIM Capture/Compare 2 interrupt */
	1729	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
	1730	}
	1731	break;
	1732
	1733	case TIM_CHANNEL_3:
	1734	{
	1735	/* Disable the TIM Capture/Compare 3 interrupt */
	1736	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
	1737	}
	1738	break;
	1739
	1740	case TIM_CHANNEL_4:
	1741	{
	1742	/* Disable the TIM Capture/Compare 4 interrupt */
	1743	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
	1744	}
	1745	break;
	1746
	1747	default:
	1748	break;
	1749	}
	1750
	1751	/* Disable the Input Capture channel */
	1752	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
	1753
	1754	/* Disable the Peripheral */
	1755	__HAL_TIM_DISABLE(htim);
	1756
	1757	/* Return function status */
	1758	return HAL_OK;
	1759	}
	1760
	1761	/**
	1762	* @brief Starts the TIM Input Capture measurement in DMA mode.
	1763	* @param htim TIM Input Capture handle
	1764	* @param Channel TIM Channels to be enabled
	1765	* This parameter can be one of the following values:
	1766	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1767	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1768	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1769	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1770	* @param pData The destination Buffer address.
	1771	* @param Length The length of data to be transferred from TIM peripheral to memory.
	1772	* @retval HAL status
	1773	*/
	1774	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
	1775	{
	1776	/* Check the parameters */
	1777	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1778	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
	1779
	1780	if((htim->State == HAL_TIM_STATE_BUSY))
	1781	{
	1782	return HAL_BUSY;
	1783	}
	1784	else if((htim->State == HAL_TIM_STATE_READY))
	1785	{
	1786	if((pData == 0U ) && (Length > 0U))
	1787	{
	1788	return HAL_ERROR;
	1789	}
	1790	else
	1791	{
	1792	htim->State = HAL_TIM_STATE_BUSY;
	1793	}
	1794	}
	1795
	1796	switch (Channel)
	1797	{
	1798	case TIM_CHANNEL_1:
	1799	{
	1800	/* Set the DMA Period elapsed callback */
	1801	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
	1802
	1803	/* Set the DMA error callback */
	1804	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
	1805
	1806	/* Enable the DMA channel */
	1807	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
	1808
	1809	/* Enable the TIM Capture/Compare 1 DMA request */
	1810	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
	1811	}
	1812	break;
	1813
	1814	case TIM_CHANNEL_2:
	1815	{
	1816	/* Set the DMA Period elapsed callback */
	1817	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
	1818
	1819	/* Set the DMA error callback */
	1820	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
	1821
	1822	/* Enable the DMA channel */
	1823	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
	1824
	1825	/* Enable the TIM Capture/Compare 2 DMA request */
	1826	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
	1827	}
	1828	break;
	1829
	1830	case TIM_CHANNEL_3:
	1831	{
	1832	/* Set the DMA Period elapsed callback */
	1833	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
	1834
	1835	/* Set the DMA error callback */
	1836	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
	1837
	1838	/* Enable the DMA channel */
	1839	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
	1840
	1841	/* Enable the TIM Capture/Compare 3 DMA request */
	1842	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
	1843	}
	1844	break;
	1845
	1846	case TIM_CHANNEL_4:
	1847	{
	1848	/* Set the DMA Period elapsed callback */
	1849	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
	1850
	1851	/* Set the DMA error callback */
	1852	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
	1853
	1854	/* Enable the DMA channel */
	1855	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
	1856
	1857	/* Enable the TIM Capture/Compare 4 DMA request */
	1858	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
	1859	}
	1860	break;
	1861
	1862	default:
	1863	break;
	1864	}
	1865
	1866	/* Enable the Input Capture channel */
	1867	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
	1868
	1869	/* Enable the Peripheral */
	1870	__HAL_TIM_ENABLE(htim);
	1871
	1872	/* Return function status */
	1873	return HAL_OK;
	1874	}
	1875
	1876	/**
	1877	* @brief Stops the TIM Input Capture measurement in DMA mode.
	1878	* @param htim TIM Input Capture handle
	1879	* @param Channel TIM Channels to be disabled
	1880	* This parameter can be one of the following values:
	1881	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1882	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1883	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1884	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1885	* @retval HAL status
	1886	*/
	1887	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
	1888	{
	1889	/* Check the parameters */
	1890	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
	1891	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
	1892
	1893	switch (Channel)
	1894	{
	1895	case TIM_CHANNEL_1:
	1896	{
	1897	/* Disable the TIM Capture/Compare 1 DMA request */
	1898	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
	1899	}
	1900	break;
	1901
	1902	case TIM_CHANNEL_2:
	1903	{
	1904	/* Disable the TIM Capture/Compare 2 DMA request */
	1905	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
	1906	}
	1907	break;
	1908
	1909	case TIM_CHANNEL_3:
	1910	{
	1911	/* Disable the TIM Capture/Compare 3 DMA request */
	1912	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
	1913	}
	1914	break;
	1915
	1916	case TIM_CHANNEL_4:
	1917	{
	1918	/* Disable the TIM Capture/Compare 4 DMA request */
	1919	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
	1920	}
	1921	break;
	1922
	1923	default:
	1924	break;
	1925	}
	1926
	1927	/* Disable the Input Capture channel */
	1928	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
	1929
	1930	/* Disable the Peripheral */
	1931	__HAL_TIM_DISABLE(htim);
	1932
	1933	/* Change the htim state */
	1934	htim->State = HAL_TIM_STATE_READY;
	1935
	1936	/* Return function status */
	1937	return HAL_OK;
	1938	}
	1939	/**
	1940	* @}
	1941	*/
	1942
	1943	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
	1944	* @brief Time One Pulse functions
	1945	*
	1946	@verbatim
	1947	==============================================================================
	1948	##### Time One Pulse functions #####
	1949	==============================================================================
	1950	[..]
	1951	This section provides functions allowing to:
	1952	(+) Initialize and configure the TIM One Pulse.
	1953	(+) De-initialize the TIM One Pulse.
	1954	(+) Start the Time One Pulse.
	1955	(+) Stop the Time One Pulse.
	1956	(+) Start the Time One Pulse and enable interrupt.
	1957	(+) Stop the Time One Pulse and disable interrupt.
	1958	(+) Start the Time One Pulse and enable DMA transfer.
	1959	(+) Stop the Time One Pulse and disable DMA transfer.
	1960
	1961	@endverbatim
	1962	* @{
	1963	*/
	1964	/**
	1965	* @brief Initializes the TIM One Pulse Time Base according to the specified
	1966	* parameters in the TIM_HandleTypeDef and create the associated handle.
	1967	* @param htim TIM OnePulse handle
	1968	* @param OnePulseMode Select the One pulse mode.
	1969	* This parameter can be one of the following values:
	1970	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
	1971	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
	1972	* @retval HAL status
	1973	*/
	1974	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
	1975	{
	1976	/* Check the TIM handle allocation */
	1977	if(htim == NULL)
	1978	{
	1979	return HAL_ERROR;
	1980	}
	1981
	1982	/* Check the parameters */
	1983	assert_param(IS_TIM_INSTANCE(htim->Instance));
	1984	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
	1985	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
	1986	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
	1987	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
	1988
	1989	if(htim->State == HAL_TIM_STATE_RESET)
	1990	{
	1991	/* Allocate lock resource and initialize it */
	1992	htim->Lock = HAL_UNLOCKED;
	1993
	1994	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
	1995	HAL_TIM_OnePulse_MspInit(htim);
	1996	}
	1997
	1998	/* Set the TIM state */
	1999	htim->State= HAL_TIM_STATE_BUSY;
	2000
	2001	/* Configure the Time base in the One Pulse Mode */
	2002	TIM_Base_SetConfig(htim->Instance, &htim->Init);
	2003
	2004	/* Reset the OPM Bit */
	2005	htim->Instance->CR1 &= ~TIM_CR1_OPM;
	2006
	2007	/* Configure the OPM Mode */
	2008	htim->Instance->CR1 \|= OnePulseMode;
	2009
	2010	/* Initialize the TIM state*/
	2011	htim->State= HAL_TIM_STATE_READY;
	2012
	2013	return HAL_OK;
	2014	}
	2015
	2016	/**
	2017	* @brief DeInitializes the TIM One Pulse
	2018	* @param htim TIM One Pulse handle
	2019	* @retval HAL status
	2020	*/
	2021	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
	2022	{
	2023	/* Check the parameters */
	2024	assert_param(IS_TIM_INSTANCE(htim->Instance));
	2025
	2026	htim->State = HAL_TIM_STATE_BUSY;
	2027
	2028	/* Disable the TIM Peripheral Clock */
	2029	__HAL_TIM_DISABLE(htim);
	2030
	2031	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
	2032	HAL_TIM_OnePulse_MspDeInit(htim);
	2033
	2034	/* Change TIM state */
	2035	htim->State = HAL_TIM_STATE_RESET;
	2036
	2037	/* Release Lock */
	2038	__HAL_UNLOCK(htim);
	2039
	2040	return HAL_OK;
	2041	}
	2042
	2043	/**
	2044	* @brief Initializes the TIM One Pulse MSP.
	2045	* @param htim TIM handle
	2046	* @retval None
	2047	*/
	2048	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
	2049	{
	2050	/* Prevent unused argument(s) compilation warning */
	2051	UNUSED(htim);
	2052
	2053	/* NOTE : This function Should not be modified, when the callback is needed,
	2054	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
	2055	*/
	2056	}
	2057
	2058	/**
	2059	* @brief DeInitializes TIM One Pulse MSP.
	2060	* @param htim TIM handle
	2061	* @retval None
	2062	*/
	2063	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
	2064	{
	2065	/* Prevent unused argument(s) compilation warning */
	2066	UNUSED(htim);
	2067
	2068	/* NOTE : This function Should not be modified, when the callback is needed,
	2069	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
	2070	*/
	2071	}
	2072
	2073	/**
	2074	* @brief Starts the TIM One Pulse signal generation.
	2075	* @param htim TIM One Pulse handle
	2076	* @param OutputChannel TIM Channels to be enabled
	2077	* This parameter can be one of the following values:
	2078	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2079	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2080	* @retval HAL status
	2081	*/
	2082	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
	2083	{
	2084	/* Enable the Capture compare and the Input Capture channels
	2085	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
	2086	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
	2087	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
	2088	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
	2089
	2090	No need to enable the counter, it's enabled automatically by hardware
	2091	(the counter starts in response to a stimulus and generate a pulse */
	2092
	2093	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
	2094	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
	2095
	2096	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	2097	{
	2098	/* Enable the main output */
	2099	__HAL_TIM_MOE_ENABLE(htim);
	2100	}
	2101
	2102	/* Return function status */
	2103	return HAL_OK;
	2104	}
	2105
	2106	/**
	2107	* @brief Stops the TIM One Pulse signal generation.
	2108	* @param htim TIM One Pulse handle
	2109	* @param OutputChannel TIM Channels to be disable
	2110	* This parameter can be one of the following values:
	2111	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2112	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2113	* @retval HAL status
	2114	*/
	2115	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
	2116	{
	2117	/* Disable the Capture compare and the Input Capture channels
	2118	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
	2119	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
	2120	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
	2121	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
	2122
	2123	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
	2124	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
	2125
	2126	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	2127	{
	2128	/* Disable the Main Ouput */
	2129	__HAL_TIM_MOE_DISABLE(htim);
	2130	}
	2131
	2132	/* Disable the Peripheral */
	2133	__HAL_TIM_DISABLE(htim);
	2134
	2135	/* Return function status */
	2136	return HAL_OK;
	2137	}
	2138
	2139	/**
	2140	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
	2141	* @param htim TIM One Pulse handle
	2142	* @param OutputChannel TIM Channels to be enabled
	2143	* This parameter can be one of the following values:
	2144	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2145	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2146	* @retval HAL status
	2147	*/
	2148	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
	2149	{
	2150	/* Enable the Capture compare and the Input Capture channels
	2151	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
	2152	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
	2153	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
	2154	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
	2155
	2156	No need to enable the counter, it's enabled automatically by hardware
	2157	(the counter starts in response to a stimulus and generate a pulse */
	2158
	2159	/* Enable the TIM Capture/Compare 1 interrupt */
	2160	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
	2161
	2162	/* Enable the TIM Capture/Compare 2 interrupt */
	2163	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
	2164
	2165	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
	2166	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
	2167
	2168	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	2169	{
	2170	/* Enable the main output */
	2171	__HAL_TIM_MOE_ENABLE(htim);
	2172	}
	2173
	2174	/* Return function status */
	2175	return HAL_OK;
	2176	}
	2177
	2178	/**
	2179	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
	2180	* @param htim TIM One Pulse handle
	2181	* @param OutputChannel TIM Channels to be enabled
	2182	* This parameter can be one of the following values:
	2183	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2184	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2185	* @retval HAL status
	2186	*/
	2187	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
	2188	{
	2189	/* Disable the TIM Capture/Compare 1 interrupt */
	2190	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
	2191
	2192	/* Disable the TIM Capture/Compare 2 interrupt */
	2193	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
	2194
	2195	/* Disable the Capture compare and the Input Capture channels
	2196	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
	2197	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
	2198	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
	2199	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
	2200	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
	2201	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
	2202
	2203	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
	2204	{
	2205	/* Disable the Main Ouput */
	2206	__HAL_TIM_MOE_DISABLE(htim);
	2207	}
	2208
	2209	/* Disable the Peripheral */
	2210	__HAL_TIM_DISABLE(htim);
	2211
	2212	/* Return function status */
	2213	return HAL_OK;
	2214	}
	2215
	2216	/**
	2217	* @}
	2218	*/
	2219
	2220	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
	2221	* @brief Time Encoder functions
	2222	*
	2223	@verbatim
	2224	==============================================================================
	2225	##### Time Encoder functions #####
	2226	==============================================================================
	2227	[..]
	2228	This section provides functions allowing to:
	2229	(+) Initialize and configure the TIM Encoder.
	2230	(+) De-initialize the TIM Encoder.
	2231	(+) Start the Time Encoder.
	2232	(+) Stop the Time Encoder.
	2233	(+) Start the Time Encoder and enable interrupt.
	2234	(+) Stop the Time Encoder and disable interrupt.
	2235	(+) Start the Time Encoder and enable DMA transfer.
	2236	(+) Stop the Time Encoder and disable DMA transfer.
	2237
	2238	@endverbatim
	2239	* @{
	2240	*/
	2241	/**
	2242	* @brief Initializes the TIM Encoder Interface and create the associated handle.
	2243	* @param htim TIM Encoder Interface handle
	2244	* @param sConfig TIM Encoder Interface configuration structure
	2245	* @retval HAL status
	2246	*/
	2247	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
	2248	{
	2249	uint32_t tmpsmcr = 0U;
	2250	uint32_t tmpccmr1 = 0U;
	2251	uint32_t tmpccer = 0U;
	2252
	2253	/* Check the TIM handle allocation */
	2254	if(htim == NULL)
	2255	{
	2256	return HAL_ERROR;
	2257	}
	2258
	2259	/* Check the parameters */
	2260	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	2261	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
	2262	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
	2263	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
	2264	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
	2265	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
	2266	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
	2267	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
	2268	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
	2269	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
	2270	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
	2271	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
	2272	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
	2273
	2274	if(htim->State == HAL_TIM_STATE_RESET)
	2275	{
	2276	/* Allocate lock resource and initialize it */
	2277	htim->Lock = HAL_UNLOCKED;
	2278
	2279	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
	2280	HAL_TIM_Encoder_MspInit(htim);
	2281	}
	2282
	2283	/* Set the TIM state */
	2284	htim->State= HAL_TIM_STATE_BUSY;
	2285
	2286	/* Reset the SMS bits */
	2287	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
	2288
	2289	/* Configure the Time base in the Encoder Mode */
	2290	TIM_Base_SetConfig(htim->Instance, &htim->Init);
	2291
	2292	/* Get the TIMx SMCR register value */
	2293	tmpsmcr = htim->Instance->SMCR;
	2294
	2295	/* Get the TIMx CCMR1 register value */
	2296	tmpccmr1 = htim->Instance->CCMR1;
	2297
	2298	/* Get the TIMx CCER register value */
	2299	tmpccer = htim->Instance->CCER;
	2300
	2301	/* Set the encoder Mode */
	2302	tmpsmcr \|= sConfig->EncoderMode;
	2303
	2304	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
	2305	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
	2306	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8U));
	2307
	2308	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
	2309	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
	2310	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
	2311	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8U);
	2312	tmpccmr1 \|= (sConfig->IC1Filter << 4U) \| (sConfig->IC2Filter << 12U);
	2313
	2314	/* Set the TI1 and the TI2 Polarities */
	2315	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
	2316	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
	2317	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4U);
	2318
	2319	/* Write to TIMx SMCR */
	2320	htim->Instance->SMCR = tmpsmcr;
	2321
	2322	/* Write to TIMx CCMR1 */
	2323	htim->Instance->CCMR1 = tmpccmr1;
	2324
	2325	/* Write to TIMx CCER */
	2326	htim->Instance->CCER = tmpccer;
	2327
	2328	/* Initialize the TIM state*/
	2329	htim->State= HAL_TIM_STATE_READY;
	2330
	2331	return HAL_OK;
	2332	}
	2333
	2334
	2335	/**
	2336	* @brief DeInitializes the TIM Encoder interface
	2337	* @param htim TIM Encoder handle
	2338	* @retval HAL status
	2339	*/
	2340	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
	2341	{
	2342	/* Check the parameters */
	2343	assert_param(IS_TIM_INSTANCE(htim->Instance));
	2344
	2345	htim->State = HAL_TIM_STATE_BUSY;
	2346
	2347	/* Disable the TIM Peripheral Clock */
	2348	__HAL_TIM_DISABLE(htim);
	2349
	2350	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
	2351	HAL_TIM_Encoder_MspDeInit(htim);
	2352
	2353	/* Change TIM state */
	2354	htim->State = HAL_TIM_STATE_RESET;
	2355
	2356	/* Release Lock */
	2357	__HAL_UNLOCK(htim);
	2358
	2359	return HAL_OK;
	2360	}
	2361
	2362	/**
	2363	* @brief Initializes the TIM Encoder Interface MSP.
	2364	* @param htim TIM handle
	2365	* @retval None
	2366	*/
	2367	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
	2368	{
	2369	/* Prevent unused argument(s) compilation warning */
	2370	UNUSED(htim);
	2371
	2372	/* NOTE : This function Should not be modified, when the callback is needed,
	2373	the HAL_TIM_Encoder_MspInit could be implemented in the user file
	2374	*/
	2375	}
	2376
	2377	/**
	2378	* @brief DeInitializes TIM Encoder Interface MSP.
	2379	* @param htim TIM handle
	2380	* @retval None
	2381	*/
	2382	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
	2383	{
	2384	/* Prevent unused argument(s) compilation warning */
	2385	UNUSED(htim);
	2386
	2387	/* NOTE : This function Should not be modified, when the callback is needed,
	2388	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
	2389	*/
	2390	}
	2391
	2392	/**
	2393	* @brief Starts the TIM Encoder Interface.
	2394	* @param htim TIM Encoder Interface handle
	2395	* @param Channel TIM Channels to be enabled
	2396	* This parameter can be one of the following values:
	2397	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2398	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2399	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
	2400	* @retval HAL status
	2401	*/
	2402	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
	2403	{
	2404	/* Check the parameters */
	2405	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	2406
	2407	/* Enable the encoder interface channels */
	2408	switch (Channel)
	2409	{
	2410	case TIM_CHANNEL_1:
	2411	{
	2412	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
	2413	break;
	2414	}
	2415	case TIM_CHANNEL_2:
	2416	{
	2417	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
	2418	break;
	2419	}
	2420	default :
	2421	{
	2422	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
	2423	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
	2424	break;
	2425	}
	2426	}
	2427	/* Enable the Peripheral */
	2428	__HAL_TIM_ENABLE(htim);
	2429
	2430	/* Return function status */
	2431	return HAL_OK;
	2432	}
	2433
	2434	/**
	2435	* @brief Stops the TIM Encoder Interface.
	2436	* @param htim TIM Encoder Interface handle
	2437	* @param Channel TIM Channels to be disabled
	2438	* This parameter can be one of the following values:
	2439	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2440	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2441	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
	2442	* @retval HAL status
	2443	*/
	2444	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
	2445	{
	2446	/* Check the parameters */
	2447	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	2448
	2449	/* Disable the Input Capture channels 1 and 2
	2450	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
	2451	switch (Channel)
	2452	{
	2453	case TIM_CHANNEL_1:
	2454	{
	2455	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
	2456	break;
	2457	}
	2458	case TIM_CHANNEL_2:
	2459	{
	2460	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
	2461	break;
	2462	}
	2463	default :
	2464	{
	2465	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
	2466	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
	2467	break;
	2468	}
	2469	}
	2470
	2471	/* Disable the Peripheral */
	2472	__HAL_TIM_DISABLE(htim);
	2473
	2474	/* Return function status */
	2475	return HAL_OK;
	2476	}
	2477
	2478	/**
	2479	* @brief Starts the TIM Encoder Interface in interrupt mode.
	2480	* @param htim TIM Encoder Interface handle
	2481	* @param Channel TIM Channels to be enabled
	2482	* This parameter can be one of the following values:
	2483	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2484	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2485	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
	2486	* @retval HAL status
	2487	*/
	2488	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
	2489	{
	2490	/* Check the parameters */
	2491	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	2492
	2493	/* Enable the encoder interface channels */
	2494	/* Enable the capture compare Interrupts 1 and/or 2 */
	2495	switch (Channel)
	2496	{
	2497	case TIM_CHANNEL_1:
	2498	{
	2499	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
	2500	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
	2501	break;
	2502	}
	2503	case TIM_CHANNEL_2:
	2504	{
	2505	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
	2506	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
	2507	break;
	2508	}
	2509	default :
	2510	{
	2511	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
	2512	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
	2513	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
	2514	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
	2515	break;
	2516	}
	2517	}
	2518
	2519	/* Enable the Peripheral */
	2520	__HAL_TIM_ENABLE(htim);
	2521
	2522	/* Return function status */
	2523	return HAL_OK;
	2524	}
	2525
	2526	/**
	2527	* @brief Stops the TIM Encoder Interface in interrupt mode.
	2528	* @param htim TIM Encoder Interface handle
	2529	* @param Channel TIM Channels to be disabled
	2530	* This parameter can be one of the following values:
	2531	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2532	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2533	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
	2534	* @retval HAL status
	2535	*/
	2536	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
	2537	{
	2538	/* Check the parameters */
	2539	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	2540
	2541	/* Disable the Input Capture channels 1 and 2
	2542	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
	2543	if(Channel == TIM_CHANNEL_1)
	2544	{
	2545	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
	2546
	2547	/* Disable the capture compare Interrupts 1 */
	2548	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
	2549	}
	2550	else if(Channel == TIM_CHANNEL_2)
	2551	{
	2552	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
	2553
	2554	/* Disable the capture compare Interrupts 2 */
	2555	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
	2556	}
	2557	else
	2558	{
	2559	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
	2560	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
	2561
	2562	/* Disable the capture compare Interrupts 1 and 2 */
	2563	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
	2564	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
	2565	}
	2566
	2567	/* Disable the Peripheral */
	2568	__HAL_TIM_DISABLE(htim);
	2569
	2570	/* Change the htim state */
	2571	htim->State = HAL_TIM_STATE_READY;
	2572
	2573	/* Return function status */
	2574	return HAL_OK;
	2575	}
	2576
	2577	/**
	2578	* @brief Starts the TIM Encoder Interface in DMA mode.
	2579	* @param htim TIM Encoder Interface handle
	2580	* @param Channel TIM Channels to be enabled
	2581	* This parameter can be one of the following values:
	2582	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2583	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2584	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
	2585	* @param pData1 The destination Buffer address for IC1.
	2586	* @param pData2 The destination Buffer address for IC2.
	2587	* @param Length The length of data to be transferred from TIM peripheral to memory.
	2588	* @retval HAL status
	2589	*/
	2590	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
	2591	{
	2592	/* Check the parameters */
	2593	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
	2594
	2595	if((htim->State == HAL_TIM_STATE_BUSY))
	2596	{
	2597	return HAL_BUSY;
	2598	}
	2599	else if((htim->State == HAL_TIM_STATE_READY))
	2600	{
	2601	if((((pData1 == 0U) \|\| (pData2 == 0U) )) && (Length > 0U))
	2602	{
	2603	return HAL_ERROR;
	2604	}
	2605	else
	2606	{
	2607	htim->State = HAL_TIM_STATE_BUSY;
	2608	}
	2609	}
	2610
	2611	switch (Channel)
	2612	{
	2613	case TIM_CHANNEL_1:
	2614	{
	2615	/* Set the DMA Period elapsed callback */
	2616	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
	2617
	2618	/* Set the DMA error callback */
	2619	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
	2620
	2621	/* Enable the DMA channel */
	2622	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
	2623
	2624	/* Enable the TIM Input Capture DMA request */
	2625	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
	2626
	2627	/* Enable the Peripheral */
	2628	__HAL_TIM_ENABLE(htim);
	2629
	2630	/* Enable the Capture compare channel */
	2631	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
	2632	}
	2633	break;
	2634
	2635	case TIM_CHANNEL_2:
	2636	{
	2637	/* Set the DMA Period elapsed callback */
	2638	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
	2639
	2640	/* Set the DMA error callback */
	2641	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
	2642	/* Enable the DMA channel */
	2643	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
	2644
	2645	/* Enable the TIM Input Capture DMA request */
	2646	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
	2647
	2648	/* Enable the Peripheral */
	2649	__HAL_TIM_ENABLE(htim);
	2650
	2651	/* Enable the Capture compare channel */
	2652	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
	2653	}
	2654	break;
	2655
	2656	case TIM_CHANNEL_ALL:
	2657	{
	2658	/* Set the DMA Period elapsed callback */
	2659	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
	2660
	2661	/* Set the DMA error callback */
	2662	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
	2663
	2664	/* Enable the DMA channel */
	2665	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
	2666
	2667	/* Set the DMA Period elapsed callback */
	2668	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
	2669
	2670	/* Set the DMA error callback */
	2671	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
	2672
	2673	/* Enable the DMA channel */
	2674	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
	2675
	2676	/* Enable the Peripheral */
	2677	__HAL_TIM_ENABLE(htim);
	2678
	2679	/* Enable the Capture compare channel */
	2680	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
	2681	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
	2682
	2683	/* Enable the TIM Input Capture DMA request */
	2684	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
	2685	/* Enable the TIM Input Capture DMA request */
	2686	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
	2687	}
	2688	break;
	2689
	2690	default:
	2691	break;
	2692	}
	2693	/* Return function status */
	2694	return HAL_OK;
	2695	}
	2696
	2697	/**
	2698	* @brief Stops the TIM Encoder Interface in DMA mode.
	2699	* @param htim TIM Encoder Interface handle
	2700	* @param Channel TIM Channels to be enabled
	2701	* This parameter can be one of the following values:
	2702	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2703	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2704	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
	2705	* @retval HAL status
	2706	*/
	2707	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
	2708	{
	2709	/* Check the parameters */
	2710	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
	2711
	2712	/* Disable the Input Capture channels 1 and 2
	2713	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
	2714	if(Channel == TIM_CHANNEL_1)
	2715	{
	2716	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
	2717
	2718	/* Disable the capture compare DMA Request 1 */
	2719	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
	2720	}
	2721	else if(Channel == TIM_CHANNEL_2)
	2722	{
	2723	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
	2724
	2725	/* Disable the capture compare DMA Request 2 */
	2726	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
	2727	}
	2728	else
	2729	{
	2730	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
	2731	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
	2732
	2733	/* Disable the capture compare DMA Request 1 and 2 */
	2734	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
	2735	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
	2736	}
	2737
	2738	/* Disable the Peripheral */
	2739	__HAL_TIM_DISABLE(htim);
	2740
	2741	/* Change the htim state */
	2742	htim->State = HAL_TIM_STATE_READY;
	2743
	2744	/* Return function status */
	2745	return HAL_OK;
	2746	}
	2747
	2748	/**
	2749	* @}
	2750	*/
	2751	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
	2752	* @brief IRQ handler management
	2753	*
	2754	@verbatim
	2755	==============================================================================
	2756	##### IRQ handler management #####
	2757	==============================================================================
	2758	[..]
	2759	This section provides Timer IRQ handler function.
	2760
	2761	@endverbatim
	2762	* @{
	2763	*/
	2764	/**
	2765	* @brief This function handles TIM interrupts requests.
	2766	* @param htim TIM handle
	2767	* @retval None
	2768	*/
	2769	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
	2770	{
	2771	/* Capture compare 1 event */
	2772	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
	2773	{
	2774	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
	2775	{
	2776	{
	2777	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
	2778	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
	2779
	2780	/* Input capture event */
	2781	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
	2782	{
	2783	HAL_TIM_IC_CaptureCallback(htim);
	2784	}
	2785	/* Output compare event */
	2786	else
	2787	{
	2788	HAL_TIM_OC_DelayElapsedCallback(htim);
	2789	HAL_TIM_PWM_PulseFinishedCallback(htim);
	2790	}
	2791	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
	2792	}
	2793	}
	2794	}
	2795	/* Capture compare 2 event */
	2796	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
	2797	{
	2798	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
	2799	{
	2800	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
	2801	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
	2802	/* Input capture event */
	2803	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
	2804	{
	2805	HAL_TIM_IC_CaptureCallback(htim);
	2806	}
	2807	/* Output compare event */
	2808	else
	2809	{
	2810	HAL_TIM_OC_DelayElapsedCallback(htim);
	2811	HAL_TIM_PWM_PulseFinishedCallback(htim);
	2812	}
	2813	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
	2814	}
	2815	}
	2816	/* Capture compare 3 event */
	2817	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
	2818	{
	2819	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
	2820	{
	2821	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
	2822	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
	2823	/* Input capture event */
	2824	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
	2825	{
	2826	HAL_TIM_IC_CaptureCallback(htim);
	2827	}
	2828	/* Output compare event */
	2829	else
	2830	{
	2831	HAL_TIM_OC_DelayElapsedCallback(htim);
	2832	HAL_TIM_PWM_PulseFinishedCallback(htim);
	2833	}
	2834	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
	2835	}
	2836	}
	2837	/* Capture compare 4 event */
	2838	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
	2839	{
	2840	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
	2841	{
	2842	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
	2843	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
	2844	/* Input capture event */
	2845	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
	2846	{
	2847	HAL_TIM_IC_CaptureCallback(htim);
	2848	}
	2849	/* Output compare event */
	2850	else
	2851	{
	2852	HAL_TIM_OC_DelayElapsedCallback(htim);
	2853	HAL_TIM_PWM_PulseFinishedCallback(htim);
	2854	}
	2855	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
	2856	}
	2857	}
	2858	/* TIM Update event */
	2859	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
	2860	{
	2861	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
	2862	{
	2863	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
	2864	HAL_TIM_PeriodElapsedCallback(htim);
	2865	}
	2866	}
	2867	/* TIM Break input event */
	2868	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
	2869	{
	2870	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
	2871	{
	2872	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
	2873	HAL_TIMEx_BreakCallback(htim);
	2874	}
	2875	}
	2876	/* TIM Trigger detection event */
	2877	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
	2878	{
	2879	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
	2880	{
	2881	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
	2882	HAL_TIM_TriggerCallback(htim);
	2883	}
	2884	}
	2885	/* TIM commutation event */
	2886	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
	2887	{
	2888	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
	2889	{
	2890	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
	2891	HAL_TIMEx_CommutationCallback(htim);
	2892	}
	2893	}
	2894	}
	2895
	2896	/**
	2897	* @}
	2898	*/
	2899
	2900	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
	2901	* @brief Peripheral Control functions
	2902	*
	2903	@verbatim
	2904	==============================================================================
	2905	##### Peripheral Control functions #####
	2906	==============================================================================
	2907	[..]
	2908	This section provides functions allowing to:
	2909	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
	2910	(+) Configure External Clock source.
	2911	(+) Configure Complementary channels, break features and dead time.
	2912	(+) Configure Master and the Slave synchronization.
	2913	(+) Configure the DMA Burst Mode.
	2914
	2915	@endverbatim
	2916	* @{
	2917	*/
	2918
	2919	/**
	2920	* @brief Initializes the TIM Output Compare Channels according to the specified
	2921	* parameters in the TIM_OC_InitTypeDef.
	2922	* @param htim TIM Output Compare handle
	2923	* @param sConfig TIM Output Compare configuration structure
	2924	* @param Channel TIM Channels to be enabled
	2925	* This parameter can be one of the following values:
	2926	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2927	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2928	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	2929	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	2930	* @retval HAL status
	2931	*/
	2932	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
	2933	{
	2934	/* Check the parameters */
	2935	assert_param(IS_TIM_CHANNELS(Channel));
	2936	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
	2937	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
	2938
	2939	/* Check input state */
	2940	__HAL_LOCK(htim);
	2941
	2942	htim->State = HAL_TIM_STATE_BUSY;
	2943
	2944	switch (Channel)
	2945	{
	2946	case TIM_CHANNEL_1:
	2947	{
	2948	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
	2949	/* Configure the TIM Channel 1 in Output Compare */
	2950	TIM_OC1_SetConfig(htim->Instance, sConfig);
	2951	}
	2952	break;
	2953
	2954	case TIM_CHANNEL_2:
	2955	{
	2956	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	2957	/* Configure the TIM Channel 2 in Output Compare */
	2958	TIM_OC2_SetConfig(htim->Instance, sConfig);
	2959	}
	2960	break;
	2961
	2962	case TIM_CHANNEL_3:
	2963	{
	2964	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
	2965	/* Configure the TIM Channel 3 in Output Compare */
	2966	TIM_OC3_SetConfig(htim->Instance, sConfig);
	2967	}
	2968	break;
	2969
	2970	case TIM_CHANNEL_4:
	2971	{
	2972	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
	2973	/* Configure the TIM Channel 4 in Output Compare */
	2974	TIM_OC4_SetConfig(htim->Instance, sConfig);
	2975	}
	2976	break;
	2977
	2978	default:
	2979	break;
	2980	}
	2981	htim->State = HAL_TIM_STATE_READY;
	2982
	2983	__HAL_UNLOCK(htim);
	2984
	2985	return HAL_OK;
	2986	}
	2987
	2988	/**
	2989	* @brief Initializes the TIM Input Capture Channels according to the specified
	2990	* parameters in the TIM_IC_InitTypeDef.
	2991	* @param htim TIM IC handle
	2992	* @param sConfig TIM Input Capture configuration structure
	2993	* @param Channel TIM Channels to be enabled
	2994	* This parameter can be one of the following values:
	2995	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	2996	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	2997	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	2998	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	2999	* @retval HAL status
	3000	*/
	3001	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
	3002	{
	3003	/* Check the parameters */
	3004	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
	3005	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
	3006	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
	3007	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
	3008	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
	3009
	3010	__HAL_LOCK(htim);
	3011
	3012	htim->State = HAL_TIM_STATE_BUSY;
	3013
	3014	if (Channel == TIM_CHANNEL_1)
	3015	{
	3016	/* TI1 Configuration */
	3017	TIM_TI1_SetConfig(htim->Instance,
	3018	sConfig->ICPolarity,
	3019	sConfig->ICSelection,
	3020	sConfig->ICFilter);
	3021
	3022	/* Reset the IC1PSC Bits */
	3023	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
	3024
	3025	/* Set the IC1PSC value */
	3026	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
	3027	}
	3028	else if (Channel == TIM_CHANNEL_2)
	3029	{
	3030	/* TI2 Configuration */
	3031	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	3032
	3033	TIM_TI2_SetConfig(htim->Instance,
	3034	sConfig->ICPolarity,
	3035	sConfig->ICSelection,
	3036	sConfig->ICFilter);
	3037
	3038	/* Reset the IC2PSC Bits */
	3039	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
	3040
	3041	/* Set the IC2PSC value */
	3042	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8U);
	3043	}
	3044	else if (Channel == TIM_CHANNEL_3)
	3045	{
	3046	/* TI3 Configuration */
	3047	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
	3048
	3049	TIM_TI3_SetConfig(htim->Instance,
	3050	sConfig->ICPolarity,
	3051	sConfig->ICSelection,
	3052	sConfig->ICFilter);
	3053
	3054	/* Reset the IC3PSC Bits */
	3055	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
	3056
	3057	/* Set the IC3PSC value */
	3058	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
	3059	}
	3060	else
	3061	{
	3062	/* TI4 Configuration */
	3063	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
	3064
	3065	TIM_TI4_SetConfig(htim->Instance,
	3066	sConfig->ICPolarity,
	3067	sConfig->ICSelection,
	3068	sConfig->ICFilter);
	3069
	3070	/* Reset the IC4PSC Bits */
	3071	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
	3072
	3073	/* Set the IC4PSC value */
	3074	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8U);
	3075	}
	3076
	3077	htim->State = HAL_TIM_STATE_READY;
	3078
	3079	__HAL_UNLOCK(htim);
	3080
	3081	return HAL_OK;
	3082	}
	3083
	3084	/**
	3085	* @brief Initializes the TIM PWM channels according to the specified
	3086	* parameters in the TIM_OC_InitTypeDef.
	3087	* @param htim TIM handle
	3088	* @param sConfig TIM PWM configuration structure
	3089	* @param Channel TIM Channels to be enabled
	3090	* This parameter can be one of the following values:
	3091	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	3092	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	3093	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	3094	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	3095	* @retval HAL status
	3096	*/
	3097	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
	3098	{
	3099	__HAL_LOCK(htim);
	3100
	3101	/* Check the parameters */
	3102	assert_param(IS_TIM_CHANNELS(Channel));
	3103	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
	3104	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
	3105	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
	3106
	3107	htim->State = HAL_TIM_STATE_BUSY;
	3108
	3109	switch (Channel)
	3110	{
	3111	case TIM_CHANNEL_1:
	3112	{
	3113	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
	3114	/* Configure the Channel 1 in PWM mode */
	3115	TIM_OC1_SetConfig(htim->Instance, sConfig);
	3116
	3117	/* Set the Preload enable bit for channel1 */
	3118	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
	3119
	3120	/* Configure the Output Fast mode */
	3121	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
	3122	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
	3123	}
	3124	break;
	3125
	3126	case TIM_CHANNEL_2:
	3127	{
	3128	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	3129	/* Configure the Channel 2 in PWM mode */
	3130	TIM_OC2_SetConfig(htim->Instance, sConfig);
	3131
	3132	/* Set the Preload enable bit for channel2 */
	3133	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
	3134
	3135	/* Configure the Output Fast mode */
	3136	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
	3137	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8U;
	3138	}
	3139	break;
	3140
	3141	case TIM_CHANNEL_3:
	3142	{
	3143	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
	3144	/* Configure the Channel 3 in PWM mode */
	3145	TIM_OC3_SetConfig(htim->Instance, sConfig);
	3146
	3147	/* Set the Preload enable bit for channel3 */
	3148	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
	3149
	3150	/* Configure the Output Fast mode */
	3151	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
	3152	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
	3153	}
	3154	break;
	3155
	3156	case TIM_CHANNEL_4:
	3157	{
	3158	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
	3159	/* Configure the Channel 4 in PWM mode */
	3160	TIM_OC4_SetConfig(htim->Instance, sConfig);
	3161
	3162	/* Set the Preload enable bit for channel4 */
	3163	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
	3164
	3165	/* Configure the Output Fast mode */
	3166	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
	3167	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8U;
	3168	}
	3169	break;
	3170
	3171	default:
	3172	break;
	3173	}
	3174
	3175	htim->State = HAL_TIM_STATE_READY;
	3176
	3177	__HAL_UNLOCK(htim);
	3178
	3179	return HAL_OK;
	3180	}
	3181
	3182	/**
	3183	* @brief Initializes the TIM One Pulse Channels according to the specified
	3184	* parameters in the TIM_OnePulse_InitTypeDef.
	3185	* @param htim TIM One Pulse handle
	3186	* @param sConfig TIM One Pulse configuration structure
	3187	* @param OutputChannel TIM Channels to be enabled
	3188	* This parameter can be one of the following values:
	3189	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	3190	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	3191	* @param InputChannel TIM Channels to be enabled
	3192	* This parameter can be one of the following values:
	3193	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	3194	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	3195	* @retval HAL status
	3196	*/
	3197	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
	3198	{
	3199	TIM_OC_InitTypeDef temp1;
	3200
	3201	/* Check the parameters */
	3202	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
	3203	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
	3204
	3205	if(OutputChannel != InputChannel)
	3206	{
	3207	__HAL_LOCK(htim);
	3208
	3209	htim->State = HAL_TIM_STATE_BUSY;
	3210
	3211	/* Extract the Ouput compare configuration from sConfig structure */
	3212	temp1.OCMode = sConfig->OCMode;
	3213	temp1.Pulse = sConfig->Pulse;
	3214	temp1.OCPolarity = sConfig->OCPolarity;
	3215	temp1.OCNPolarity = sConfig->OCNPolarity;
	3216	temp1.OCIdleState = sConfig->OCIdleState;
	3217	temp1.OCNIdleState = sConfig->OCNIdleState;
	3218
	3219	switch (OutputChannel)
	3220	{
	3221	case TIM_CHANNEL_1:
	3222	{
	3223	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
	3224
	3225	TIM_OC1_SetConfig(htim->Instance, &temp1);
	3226	}
	3227	break;
	3228	case TIM_CHANNEL_2:
	3229	{
	3230	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	3231
	3232	TIM_OC2_SetConfig(htim->Instance, &temp1);
	3233	}
	3234	break;
	3235	default:
	3236	break;
	3237	}
	3238	switch (InputChannel)
	3239	{
	3240	case TIM_CHANNEL_1:
	3241	{
	3242	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
	3243
	3244	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
	3245	sConfig->ICSelection, sConfig->ICFilter);
	3246
	3247	/* Reset the IC1PSC Bits */
	3248	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
	3249
	3250	/* Select the Trigger source */
	3251	htim->Instance->SMCR &= ~TIM_SMCR_TS;
	3252	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
	3253
	3254	/* Select the Slave Mode */
	3255	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
	3256	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
	3257	}
	3258	break;
	3259	case TIM_CHANNEL_2:
	3260	{
	3261	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	3262
	3263	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
	3264	sConfig->ICSelection, sConfig->ICFilter);
	3265
	3266	/* Reset the IC2PSC Bits */
	3267	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
	3268
	3269	/* Select the Trigger source */
	3270	htim->Instance->SMCR &= ~TIM_SMCR_TS;
	3271	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
	3272
	3273	/* Select the Slave Mode */
	3274	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
	3275	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
	3276	}
	3277	break;
	3278
	3279	default:
	3280	break;
	3281	}
	3282
	3283	htim->State = HAL_TIM_STATE_READY;
	3284
	3285	__HAL_UNLOCK(htim);
	3286
	3287	return HAL_OK;
	3288	}
	3289	else
	3290	{
	3291	return HAL_ERROR;
	3292	}
	3293	}
	3294
	3295	/**
	3296	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
	3297	* @param htim TIM handle
	3298	* @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
	3299	* This parameter can be one of the following values:
	3300	* @arg TIM_DMABASE_CR1
	3301	* @arg TIM_DMABASE_CR2
	3302	* @arg TIM_DMABASE_SMCR
	3303	* @arg TIM_DMABASE_DIER
	3304	* @arg TIM_DMABASE_SR
	3305	* @arg TIM_DMABASE_EGR
	3306	* @arg TIM_DMABASE_CCMR1
	3307	* @arg TIM_DMABASE_CCMR2
	3308	* @arg TIM_DMABASE_CCER
	3309	* @arg TIM_DMABASE_CNT
	3310	* @arg TIM_DMABASE_PSC
	3311	* @arg TIM_DMABASE_ARR
	3312	* @arg TIM_DMABASE_RCR
	3313	* @arg TIM_DMABASE_CCR1
	3314	* @arg TIM_DMABASE_CCR2
	3315	* @arg TIM_DMABASE_CCR3
	3316	* @arg TIM_DMABASE_CCR4
	3317	* @arg TIM_DMABASE_BDTR
	3318	* @arg TIM_DMABASE_DCR
	3319	* @param BurstRequestSrc TIM DMA Request sources
	3320	* This parameter can be one of the following values:
	3321	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
	3322	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
	3323	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
	3324	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
	3325	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
	3326	* @arg TIM_DMA_COM: TIM Commutation DMA source
	3327	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
	3328	* @param BurstBuffer The Buffer address.
	3329	* @param BurstLength DMA Burst length. This parameter can be one value
	3330	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
	3331	* @retval HAL status
	3332	*/
	3333	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
	3334	uint32_t *BurstBuffer, uint32_t BurstLength)
	3335	{
	3336	return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
	3337	}
	3338
	3339	/**
	3340	* @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
	3341	* @param htim TIM handle
	3342	* @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
	3343	* This parameter can be one of the following values:
	3344	* @arg TIM_DMABASE_CR1
	3345	* @arg TIM_DMABASE_CR2
	3346	* @arg TIM_DMABASE_SMCR
	3347	* @arg TIM_DMABASE_DIER
	3348	* @arg TIM_DMABASE_SR
	3349	* @arg TIM_DMABASE_EGR
	3350	* @arg TIM_DMABASE_CCMR1
	3351	* @arg TIM_DMABASE_CCMR2
	3352	* @arg TIM_DMABASE_CCER
	3353	* @arg TIM_DMABASE_CNT
	3354	* @arg TIM_DMABASE_PSC
	3355	* @arg TIM_DMABASE_ARR
	3356	* @arg TIM_DMABASE_RCR
	3357	* @arg TIM_DMABASE_CCR1
	3358	* @arg TIM_DMABASE_CCR2
	3359	* @arg TIM_DMABASE_CCR3
	3360	* @arg TIM_DMABASE_CCR4
	3361	* @arg TIM_DMABASE_BDTR
	3362	* @arg TIM_DMABASE_DCR
	3363	* @param BurstRequestSrc TIM DMA Request sources
	3364	* This parameter can be one of the following values:
	3365	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
	3366	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
	3367	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
	3368	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
	3369	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
	3370	* @arg TIM_DMA_COM: TIM Commutation DMA source
	3371	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
	3372	* @param BurstBuffer The Buffer address.
	3373	* @param BurstLength DMA Burst length. This parameter can be one value
	3374	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
	3375	* @param DataLength Data length. This parameter can be one value
	3376	* between 1 and 0xFFFF.
	3377	* @retval HAL status
	3378	*/
	3379	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
	3380	uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
	3381	{
	3382	/* Check the parameters */
	3383	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
	3384	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
	3385	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
	3386	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
	3387	assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
	3388
	3389	if((htim->State == HAL_TIM_STATE_BUSY))
	3390	{
	3391	return HAL_BUSY;
	3392	}
	3393	else if((htim->State == HAL_TIM_STATE_READY))
	3394	{
	3395	if((BurstBuffer == 0U ) && (BurstLength > 0U))
	3396	{
	3397	return HAL_ERROR;
	3398	}
	3399	else
	3400	{
	3401	htim->State = HAL_TIM_STATE_BUSY;
	3402	}
	3403	}
	3404	switch(BurstRequestSrc)
	3405	{
	3406	case TIM_DMA_UPDATE:
	3407	{
	3408	/* Set the DMA Period elapsed callback */
	3409	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
	3410
	3411	/* Set the DMA error callback */
	3412	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
	3413
	3414	/* Enable the DMA channel */
	3415	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
	3416	}
	3417	break;
	3418	case TIM_DMA_CC1:
	3419	{
	3420	/* Set the DMA Period elapsed callback */
	3421	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
	3422
	3423	/* Set the DMA error callback */
	3424	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
	3425
	3426	/* Enable the DMA channel */
	3427	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
	3428	}
	3429	break;
	3430	case TIM_DMA_CC2:
	3431	{
	3432	/* Set the DMA Period elapsed callback */
	3433	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
	3434
	3435	/* Set the DMA error callback */
	3436	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
	3437
	3438	/* Enable the DMA channel */
	3439	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
	3440	}
	3441	break;
	3442	case TIM_DMA_CC3:
	3443	{
	3444	/* Set the DMA Period elapsed callback */
	3445	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
	3446
	3447	/* Set the DMA error callback */
	3448	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
	3449
	3450	/* Enable the DMA channel */
	3451	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
	3452	}
	3453	break;
	3454	case TIM_DMA_CC4:
	3455	{
	3456	/* Set the DMA Period elapsed callback */
	3457	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
	3458
	3459	/* Set the DMA error callback */
	3460	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
	3461
	3462	/* Enable the DMA channel */
	3463	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
	3464	}
	3465	break;
	3466	case TIM_DMA_COM:
	3467	{
	3468	/* Set the DMA Period elapsed callback */
	3469	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
	3470
	3471	/* Set the DMA error callback */
	3472	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
	3473
	3474	/* Enable the DMA channel */
	3475	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
	3476	}
	3477	break;
	3478	case TIM_DMA_TRIGGER:
	3479	{
	3480	/* Set the DMA Period elapsed callback */
	3481	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
	3482
	3483	/* Set the DMA error callback */
	3484	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
	3485
	3486	/* Enable the DMA channel */
	3487	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
	3488	}
	3489	break;
	3490	default:
	3491	break;
	3492	}
	3493	/* configure the DMA Burst Mode */
	3494	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
	3495
	3496	/* Enable the TIM DMA Request */
	3497	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
	3498
	3499	htim->State = HAL_TIM_STATE_READY;
	3500
	3501	/* Return function status */
	3502	return HAL_OK;
	3503	}
	3504
	3505	/**
	3506	* @brief Stops the TIM DMA Burst mode
	3507	* @param htim TIM handle
	3508	* @param BurstRequestSrc TIM DMA Request sources to disable
	3509	* @retval HAL status
	3510	*/
	3511	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
	3512	{
	3513	/* Check the parameters */
	3514	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
	3515
	3516	/* Abort the DMA transfer (at least disable the DMA channel) */
	3517	switch(BurstRequestSrc)
	3518	{
	3519	case TIM_DMA_UPDATE:
	3520	{
	3521	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
	3522	}
	3523	break;
	3524	case TIM_DMA_CC1:
	3525	{
	3526	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
	3527	}
	3528	break;
	3529	case TIM_DMA_CC2:
	3530	{
	3531	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
	3532	}
	3533	break;
	3534	case TIM_DMA_CC3:
	3535	{
	3536	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
	3537	}
	3538	break;
	3539	case TIM_DMA_CC4:
	3540	{
	3541	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
	3542	}
	3543	break;
	3544	case TIM_DMA_COM:
	3545	{
	3546	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
	3547	}
	3548	break;
	3549	case TIM_DMA_TRIGGER:
	3550	{
	3551	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
	3552	}
	3553	break;
	3554	default:
	3555	break;
	3556	}
	3557
	3558	/* Disable the TIM Update DMA request */
	3559	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
	3560
	3561	/* Return function status */
	3562	return HAL_OK;
	3563	}
	3564
	3565	/**
	3566	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
	3567	* @param htim TIM handle
	3568	* @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
	3569	* This parameter can be one of the following values:
	3570	* @arg TIM_DMABASE_CR1
	3571	* @arg TIM_DMABASE_CR2
	3572	* @arg TIM_DMABASE_SMCR
	3573	* @arg TIM_DMABASE_DIER
	3574	* @arg TIM_DMABASE_SR
	3575	* @arg TIM_DMABASE_EGR
	3576	* @arg TIM_DMABASE_CCMR1
	3577	* @arg TIM_DMABASE_CCMR2
	3578	* @arg TIM_DMABASE_CCER
	3579	* @arg TIM_DMABASE_CNT
	3580	* @arg TIM_DMABASE_PSC
	3581	* @arg TIM_DMABASE_ARR
	3582	* @arg TIM_DMABASE_RCR
	3583	* @arg TIM_DMABASE_CCR1
	3584	* @arg TIM_DMABASE_CCR2
	3585	* @arg TIM_DMABASE_CCR3
	3586	* @arg TIM_DMABASE_CCR4
	3587	* @arg TIM_DMABASE_BDTR
	3588	* @arg TIM_DMABASE_DCR
	3589	* @param BurstRequestSrc TIM DMA Request sources
	3590	* This parameter can be one of the following values:
	3591	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
	3592	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
	3593	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
	3594	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
	3595	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
	3596	* @arg TIM_DMA_COM: TIM Commutation DMA source
	3597	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
	3598	* @param BurstBuffer The Buffer address.
	3599	* @param BurstLength DMA Burst length. This parameter can be one value
	3600	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
	3601	* @retval HAL status
	3602	*/
	3603	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
	3604	uint32_t *BurstBuffer, uint32_t BurstLength)
	3605	{
	3606	return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
	3607	}
	3608
	3609	/**
	3610	* @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory
	3611	* @param htim TIM handle
	3612	* @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
	3613	* This parameter can be one of the following values:
	3614	* @arg TIM_DMABASE_CR1
	3615	* @arg TIM_DMABASE_CR2
	3616	* @arg TIM_DMABASE_SMCR
	3617	* @arg TIM_DMABASE_DIER
	3618	* @arg TIM_DMABASE_SR
	3619	* @arg TIM_DMABASE_EGR
	3620	* @arg TIM_DMABASE_CCMR1
	3621	* @arg TIM_DMABASE_CCMR2
	3622	* @arg TIM_DMABASE_CCER
	3623	* @arg TIM_DMABASE_CNT
	3624	* @arg TIM_DMABASE_PSC
	3625	* @arg TIM_DMABASE_ARR
	3626	* @arg TIM_DMABASE_RCR
	3627	* @arg TIM_DMABASE_CCR1
	3628	* @arg TIM_DMABASE_CCR2
	3629	* @arg TIM_DMABASE_CCR3
	3630	* @arg TIM_DMABASE_CCR4
	3631	* @arg TIM_DMABASE_BDTR
	3632	* @arg TIM_DMABASE_DCR
	3633	* @param BurstRequestSrc TIM DMA Request sources
	3634	* This parameter can be one of the following values:
	3635	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
	3636	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
	3637	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
	3638	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
	3639	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
	3640	* @arg TIM_DMA_COM: TIM Commutation DMA source
	3641	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
	3642	* @param BurstBuffer The Buffer address.
	3643	* @param BurstLength DMA Burst length. This parameter can be one value
	3644	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
	3645	* @param DataLength Data length. This parameter can be one value
	3646	* between 1 and 0xFFFF.
	3647	* @retval HAL status
	3648	*/
	3649	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
	3650	uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
	3651	{
	3652	/* Check the parameters */
	3653	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
	3654	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
	3655	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
	3656	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
	3657	assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
	3658
	3659	if((htim->State == HAL_TIM_STATE_BUSY))
	3660	{
	3661	return HAL_BUSY;
	3662	}
	3663	else if((htim->State == HAL_TIM_STATE_READY))
	3664	{
	3665	if((BurstBuffer == 0U ) && (BurstLength > 0U))
	3666	{
	3667	return HAL_ERROR;
	3668	}
	3669	else
	3670	{
	3671	htim->State = HAL_TIM_STATE_BUSY;
	3672	}
	3673	}
	3674	switch(BurstRequestSrc)
	3675	{
	3676	case TIM_DMA_UPDATE:
	3677	{
	3678	/* Set the DMA Period elapsed callback */
	3679	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
	3680
	3681	/* Set the DMA error callback */
	3682	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
	3683
	3684	/* Enable the DMA channel */
	3685	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
	3686	}
	3687	break;
	3688	case TIM_DMA_CC1:
	3689	{
	3690	/* Set the DMA Period elapsed callback */
	3691	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
	3692
	3693	/* Set the DMA error callback */
	3694	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
	3695
	3696	/* Enable the DMA channel */
	3697	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
	3698	}
	3699	break;
	3700	case TIM_DMA_CC2:
	3701	{
	3702	/* Set the DMA Period elapsed callback */
	3703	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
	3704
	3705	/* Set the DMA error callback */
	3706	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
	3707
	3708	/* Enable the DMA channel */
	3709	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
	3710	}
	3711	break;
	3712	case TIM_DMA_CC3:
	3713	{
	3714	/* Set the DMA Period elapsed callback */
	3715	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
	3716
	3717	/* Set the DMA error callback */
	3718	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
	3719
	3720	/* Enable the DMA channel */
	3721	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
	3722	}
	3723	break;
	3724	case TIM_DMA_CC4:
	3725	{
	3726	/* Set the DMA Period elapsed callback */
	3727	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
	3728
	3729	/* Set the DMA error callback */
	3730	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
	3731
	3732	/* Enable the DMA channel */
	3733	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
	3734	}
	3735	break;
	3736	case TIM_DMA_COM:
	3737	{
	3738	/* Set the DMA Period elapsed callback */
	3739	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
	3740
	3741	/* Set the DMA error callback */
	3742	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
	3743
	3744	/* Enable the DMA channel */
	3745	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
	3746	}
	3747	break;
	3748	case TIM_DMA_TRIGGER:
	3749	{
	3750	/* Set the DMA Period elapsed callback */
	3751	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
	3752
	3753	/* Set the DMA error callback */
	3754	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
	3755
	3756	/* Enable the DMA channel */
	3757	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
	3758	}
	3759	break;
	3760	default:
	3761	break;
	3762	}
	3763
	3764	/* configure the DMA Burst Mode */
	3765	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
	3766
	3767	/* Enable the TIM DMA Request */
	3768	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
	3769
	3770	htim->State = HAL_TIM_STATE_READY;
	3771
	3772	/* Return function status */
	3773	return HAL_OK;
	3774	}
	3775
	3776	/**
	3777	* @brief Stop the DMA burst reading
	3778	* @param htim TIM handle
	3779	* @param BurstRequestSrc TIM DMA Request sources to disable.
	3780	* @retval HAL status
	3781	*/
	3782	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
	3783	{
	3784	/* Check the parameters */
	3785	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
	3786
	3787	/* Abort the DMA transfer (at least disable the DMA channel) */
	3788	switch(BurstRequestSrc)
	3789	{
	3790	case TIM_DMA_UPDATE:
	3791	{
	3792	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
	3793	}
	3794	break;
	3795	case TIM_DMA_CC1:
	3796	{
	3797	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
	3798	}
	3799	break;
	3800	case TIM_DMA_CC2:
	3801	{
	3802	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
	3803	}
	3804	break;
	3805	case TIM_DMA_CC3:
	3806	{
	3807	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
	3808	}
	3809	break;
	3810	case TIM_DMA_CC4:
	3811	{
	3812	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
	3813	}
	3814	break;
	3815	case TIM_DMA_COM:
	3816	{
	3817	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
	3818	}
	3819	break;
	3820	case TIM_DMA_TRIGGER:
	3821	{
	3822	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
	3823	}
	3824	break;
	3825	default:
	3826	break;
	3827	}
	3828
	3829	/* Disable the TIM Update DMA request */
	3830	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
	3831
	3832	/* Return function status */
	3833	return HAL_OK;
	3834	}
	3835
	3836	/**
	3837	* @brief Generate a software event
	3838	* @param htim TIM handle
	3839	* @param EventSource specifies the event source.
	3840	* This parameter can be one of the following values:
	3841	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
	3842	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
	3843	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
	3844	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
	3845	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
	3846	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
	3847	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
	3848	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
	3849	* @note TIM6 and TIM7 can only generate an update event.
	3850	* @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
	3851	* @retval HAL status
	3852	*/
	3853
	3854	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
	3855	{
	3856	/* Check the parameters */
	3857	assert_param(IS_TIM_INSTANCE(htim->Instance));
	3858	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
	3859
	3860	/* Process Locked */
	3861	__HAL_LOCK(htim);
	3862
	3863	/* Change the TIM state */
	3864	htim->State = HAL_TIM_STATE_BUSY;
	3865
	3866	/* Set the event sources */
	3867	htim->Instance->EGR = EventSource;
	3868
	3869	/* Change the TIM state */
	3870	htim->State = HAL_TIM_STATE_READY;
	3871
	3872	__HAL_UNLOCK(htim);
	3873
	3874	/* Return function status */
	3875	return HAL_OK;
	3876	}
	3877
	3878	/**
	3879	* @brief Configures the OCRef clear feature
	3880	* @param htim TIM handle
	3881	* @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
	3882	* contains the OCREF clear feature and parameters for the TIM peripheral.
	3883	* @param Channel specifies the TIM Channel
	3884	* This parameter can be one of the following values:
	3885	* @arg TIM_CHANNEL_1: TIM Channel 1
	3886	* @arg TIM_CHANNEL_2: TIM Channel 2
	3887	* @arg TIM_CHANNEL_3: TIM Channel 3
	3888	* @arg TIM_CHANNEL_4: TIM Channel 4
	3889	* @retval HAL status
	3890	*/
	3891	__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
	3892	{
	3893	uint32_t tmpsmcr = 0;
	3894
	3895	/* Check the parameters */
	3896	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
	3897	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
	3898	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
	3899	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
	3900	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
	3901
	3902	/* Process Locked */
	3903	__HAL_LOCK(htim);
	3904
	3905	htim->State = HAL_TIM_STATE_BUSY;
	3906
	3907	switch (sClearInputConfig->ClearInputSource)
	3908	{
	3909	case TIM_CLEARINPUTSOURCE_NONE:
	3910	{
	3911	/* Get the TIMx SMCR register value */
	3912	tmpsmcr = htim->Instance->SMCR;
	3913
	3914	/* Clear the OCREF clear selection bit */
	3915	tmpsmcr &= ~TIM_SMCR_OCCS;
	3916
	3917	/* Clear the ETR Bits */
	3918	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
	3919
	3920	/* Set TIMx_SMCR */
	3921	htim->Instance->SMCR = tmpsmcr;
	3922	}
	3923	break;
	3924
	3925	case TIM_CLEARINPUTSOURCE_ETR:
	3926	{
	3927	TIM_ETR_SetConfig(htim->Instance,
	3928	sClearInputConfig->ClearInputPrescaler,
	3929	sClearInputConfig->ClearInputPolarity,
	3930	sClearInputConfig->ClearInputFilter);
	3931
	3932	/* Set the OCREF clear selection bit */
	3933	htim->Instance->SMCR \|= TIM_SMCR_OCCS;
	3934	}
	3935	break;
	3936	default:
	3937	break;
	3938	}
	3939
	3940	switch (Channel)
	3941	{
	3942	case TIM_CHANNEL_1:
	3943	{
	3944	if(sClearInputConfig->ClearInputState != RESET)
	3945	{
	3946	/* Enable the Ocref clear feature for Channel 1 */
	3947	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
	3948	}
	3949	else
	3950	{
	3951	/* Disable the Ocref clear feature for Channel 1 */
	3952	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
	3953	}
	3954	}
	3955	break;
	3956	case TIM_CHANNEL_2:
	3957	{
	3958	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	3959	if(sClearInputConfig->ClearInputState != RESET)
	3960	{
	3961	/* Enable the Ocref clear feature for Channel 2 */
	3962	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
	3963	}
	3964	else
	3965	{
	3966	/* Disable the Ocref clear feature for Channel 2 */
	3967	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
	3968	}
	3969	}
	3970	break;
	3971	case TIM_CHANNEL_3:
	3972	{
	3973	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
	3974	if(sClearInputConfig->ClearInputState != RESET)
	3975	{
	3976	/* Enable the Ocref clear feature for Channel 3 */
	3977	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
	3978	}
	3979	else
	3980	{
	3981	/* Disable the Ocref clear feature for Channel 3 */
	3982	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
	3983	}
	3984	}
	3985	break;
	3986	case TIM_CHANNEL_4:
	3987	{
	3988	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
	3989	if(sClearInputConfig->ClearInputState != RESET)
	3990	{
	3991	/* Enable the Ocref clear feature for Channel 4 */
	3992	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
	3993	}
	3994	else
	3995	{
	3996	/* Disable the Ocref clear feature for Channel 4 */
	3997	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
	3998	}
	3999	}
	4000	break;
	4001	default:
	4002	break;
	4003	}
	4004
	4005	htim->State = HAL_TIM_STATE_READY;
	4006
	4007	__HAL_UNLOCK(htim);
	4008
	4009	return HAL_OK;
	4010	}
	4011
	4012	/**
	4013	* @brief Configures the clock source to be used
	4014	* @param htim TIM handle
	4015	* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
	4016	* contains the clock source information for the TIM peripheral.
	4017	* @retval HAL status
	4018	*/
	4019	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
	4020	{
	4021	uint32_t tmpsmcr = 0U;
	4022
	4023	/* Process Locked */
	4024	__HAL_LOCK(htim);
	4025
	4026	htim->State = HAL_TIM_STATE_BUSY;
	4027
	4028	/* Check the parameters */
	4029	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
	4030
	4031	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
	4032	tmpsmcr = htim->Instance->SMCR;
	4033	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
	4034	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
	4035	htim->Instance->SMCR = tmpsmcr;
	4036
	4037	switch (sClockSourceConfig->ClockSource)
	4038	{
	4039	case TIM_CLOCKSOURCE_INTERNAL:
	4040	{
	4041	assert_param(IS_TIM_INSTANCE(htim->Instance));
	4042	/* Disable slave mode to clock the prescaler directly with the internal clock */
	4043	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
	4044	}
	4045	break;
	4046
	4047	case TIM_CLOCKSOURCE_ETRMODE1:
	4048	{
	4049	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
	4050	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
	4051
	4052	/* Check ETR input conditioning related parameters */
	4053	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
	4054	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
	4055	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
	4056
	4057	/* Configure the ETR Clock source */
	4058	TIM_ETR_SetConfig(htim->Instance,
	4059	sClockSourceConfig->ClockPrescaler,
	4060	sClockSourceConfig->ClockPolarity,
	4061	sClockSourceConfig->ClockFilter);
	4062	/* Get the TIMx SMCR register value */
	4063	tmpsmcr = htim->Instance->SMCR;
	4064	/* Reset the SMS and TS Bits */
	4065	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
	4066	/* Select the External clock mode1 and the ETRF trigger */
	4067	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
	4068	/* Write to TIMx SMCR */
	4069	htim->Instance->SMCR = tmpsmcr;
	4070	}
	4071	break;
	4072
	4073	case TIM_CLOCKSOURCE_ETRMODE2:
	4074	{
	4075	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
	4076	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
	4077
	4078	/* Check ETR input conditioning related parameters */
	4079	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
	4080	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
	4081	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
	4082
	4083	/* Configure the ETR Clock source */
	4084	TIM_ETR_SetConfig(htim->Instance,
	4085	sClockSourceConfig->ClockPrescaler,
	4086	sClockSourceConfig->ClockPolarity,
	4087	sClockSourceConfig->ClockFilter);
	4088	/* Enable the External clock mode2 */
	4089	htim->Instance->SMCR \|= TIM_SMCR_ECE;
	4090	}
	4091	break;
	4092
	4093	case TIM_CLOCKSOURCE_TI1:
	4094	{
	4095	/* Check whether or not the timer instance supports external clock mode 1 */
	4096	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
	4097
	4098	/* Check TI1 input conditioning related parameters */
	4099	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
	4100	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
	4101
	4102	TIM_TI1_ConfigInputStage(htim->Instance,
	4103	sClockSourceConfig->ClockPolarity,
	4104	sClockSourceConfig->ClockFilter);
	4105	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
	4106	}
	4107	break;
	4108	case TIM_CLOCKSOURCE_TI2:
	4109	{
	4110	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
	4111	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
	4112
	4113	/* Check TI2 input conditioning related parameters */
	4114	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
	4115	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
	4116
	4117	TIM_TI2_ConfigInputStage(htim->Instance,
	4118	sClockSourceConfig->ClockPolarity,
	4119	sClockSourceConfig->ClockFilter);
	4120	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
	4121	}
	4122	break;
	4123	case TIM_CLOCKSOURCE_TI1ED:
	4124	{
	4125	/* Check whether or not the timer instance supports external clock mode 1 */
	4126	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
	4127
	4128	/* Check TI1 input conditioning related parameters */
	4129	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
	4130	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
	4131
	4132	TIM_TI1_ConfigInputStage(htim->Instance,
	4133	sClockSourceConfig->ClockPolarity,
	4134	sClockSourceConfig->ClockFilter);
	4135	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
	4136	}
	4137	break;
	4138	case TIM_CLOCKSOURCE_ITR0:
	4139	{
	4140	/* Check whether or not the timer instance supports external clock mode 1 */
	4141	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
	4142
	4143	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
	4144	}
	4145	break;
	4146	case TIM_CLOCKSOURCE_ITR1:
	4147	{
	4148	/* Check whether or not the timer instance supports external clock mode 1 */
	4149	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
	4150
	4151	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
	4152	}
	4153	break;
	4154	case TIM_CLOCKSOURCE_ITR2:
	4155	{
	4156	/* Check whether or not the timer instance supports external clock mode 1 */
	4157	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
	4158
	4159	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
	4160	}
	4161	break;
	4162	case TIM_CLOCKSOURCE_ITR3:
	4163	{
	4164	/* Check whether or not the timer instance supports external clock mode 1 */
	4165	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
	4166
	4167	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
	4168	}
	4169	break;
	4170
	4171	default:
	4172	break;
	4173	}
	4174	htim->State = HAL_TIM_STATE_READY;
	4175
	4176	__HAL_UNLOCK(htim);
	4177
	4178	return HAL_OK;
	4179	}
	4180
	4181	/**
	4182	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
	4183	* or a XOR combination between CH1_input, CH2_input & CH3_input
	4184	* @param htim TIM handle.
	4185	* @param TI1_Selection Indicate whether or not channel 1 is connected to the
	4186	* output of a XOR gate.
	4187	* This parameter can be one of the following values:
	4188	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
	4189	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
	4190	* pins are connected to the TI1 input (XOR combination)
	4191	* @retval HAL status
	4192	*/
	4193	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
	4194	{
	4195	uint32_t tmpcr2 = 0U;
	4196
	4197	/* Check the parameters */
	4198	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
	4199	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
	4200
	4201	/* Get the TIMx CR2 register value */
	4202	tmpcr2 = htim->Instance->CR2;
	4203
	4204	/* Reset the TI1 selection */
	4205	tmpcr2 &= ~TIM_CR2_TI1S;
	4206
	4207	/* Set the the TI1 selection */
	4208	tmpcr2 \|= TI1_Selection;
	4209
	4210	/* Write to TIMxCR2 */
	4211	htim->Instance->CR2 = tmpcr2;
	4212
	4213	return HAL_OK;
	4214	}
	4215
	4216	/**
	4217	* @brief Configures the TIM in Slave mode
	4218	* @param htim TIM handle.
	4219	* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
	4220	* contains the selected trigger (internal trigger input, filtered
	4221	* timer input or external trigger input) and the ) and the Slave
	4222	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
	4223	* @retval HAL status
	4224	*/
	4225	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
	4226	{
	4227	/* Check the parameters */
	4228	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
	4229	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
	4230	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
	4231
	4232	__HAL_LOCK(htim);
	4233
	4234	htim->State = HAL_TIM_STATE_BUSY;
	4235
	4236	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
	4237
	4238	/* Disable Trigger Interrupt */
	4239	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
	4240
	4241	/* Disable Trigger DMA request */
	4242	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
	4243
	4244	htim->State = HAL_TIM_STATE_READY;
	4245
	4246	__HAL_UNLOCK(htim);
	4247
	4248	return HAL_OK;
	4249	}
	4250
	4251	/**
	4252	* @brief Configures the TIM in Slave mode in interrupt mode
	4253	* @param htim TIM handle.
	4254	* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
	4255	* contains the selected trigger (internal trigger input, filtered
	4256	* timer input or external trigger input) and the ) and the Slave
	4257	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
	4258	* @retval HAL status
	4259	*/
	4260	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
	4261	TIM_SlaveConfigTypeDef * sSlaveConfig)
	4262	{
	4263	/* Check the parameters */
	4264	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
	4265	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
	4266	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
	4267
	4268	__HAL_LOCK(htim);
	4269
	4270	htim->State = HAL_TIM_STATE_BUSY;
	4271
	4272	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
	4273
	4274	/* Enable Trigger Interrupt */
	4275	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
	4276
	4277	/* Disable Trigger DMA request */
	4278	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
	4279
	4280	htim->State = HAL_TIM_STATE_READY;
	4281
	4282	__HAL_UNLOCK(htim);
	4283
	4284	return HAL_OK;
	4285	}
	4286
	4287	/**
	4288	* @brief Read the captured value from Capture Compare unit
	4289	* @param htim TIM handle.
	4290	* @param Channel TIM Channels to be enabled
	4291	* This parameter can be one of the following values:
	4292	* @arg TIM_CHANNEL_1 : TIM Channel 1 selected
	4293	* @arg TIM_CHANNEL_2 : TIM Channel 2 selected
	4294	* @arg TIM_CHANNEL_3 : TIM Channel 3 selected
	4295	* @arg TIM_CHANNEL_4 : TIM Channel 4 selected
	4296	* @retval Captured value
	4297	*/
	4298	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
	4299	{
	4300	uint32_t tmpreg = 0U;
	4301
	4302	__HAL_LOCK(htim);
	4303
	4304	switch (Channel)
	4305	{
	4306	case TIM_CHANNEL_1:
	4307	{
	4308	/* Check the parameters */
	4309	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
	4310
	4311	/* Return the capture 1 value */
	4312	tmpreg = htim->Instance->CCR1;
	4313
	4314	break;
	4315	}
	4316	case TIM_CHANNEL_2:
	4317	{
	4318	/* Check the parameters */
	4319	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	4320
	4321	/* Return the capture 2 value */
	4322	tmpreg = htim->Instance->CCR2;
	4323
	4324	break;
	4325	}
	4326
	4327	case TIM_CHANNEL_3:
	4328	{
	4329	/* Check the parameters */
	4330	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
	4331
	4332	/* Return the capture 3 value */
	4333	tmpreg = htim->Instance->CCR3;
	4334
	4335	break;
	4336	}
	4337
	4338	case TIM_CHANNEL_4:
	4339	{
	4340	/* Check the parameters */
	4341	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
	4342
	4343	/* Return the capture 4 value */
	4344	tmpreg = htim->Instance->CCR4;
	4345
	4346	break;
	4347	}
	4348
	4349	default:
	4350	break;
	4351	}
	4352
	4353	__HAL_UNLOCK(htim);
	4354	return tmpreg;
	4355	}
	4356
	4357	/**
	4358	* @}
	4359	*/
	4360
	4361	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
	4362	* @brief TIM Callbacks functions
	4363	*
	4364	@verbatim
	4365	==============================================================================
	4366	##### TIM Callbacks functions #####
	4367	==============================================================================
	4368	[..]
	4369	This section provides TIM callback functions:
	4370	(+) Timer Period elapsed callback
	4371	(+) Timer Output Compare callback
	4372	(+) Timer Input capture callback
	4373	(+) Timer Trigger callback
	4374	(+) Timer Error callback
	4375
	4376	@endverbatim
	4377	* @{
	4378	*/
	4379
	4380	/**
	4381	* @brief Period elapsed callback in non blocking mode
	4382	* @param htim TIM handle
	4383	* @retval None
	4384	*/
	4385	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
	4386	{
	4387	/* Prevent unused argument(s) compilation warning */
	4388	UNUSED(htim);
	4389
	4390	/* NOTE : This function Should not be modified, when the callback is needed,
	4391	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
	4392	*/
	4393
	4394	}
	4395	/**
	4396	* @brief Output Compare callback in non blocking mode
	4397	* @param htim TIM OC handle
	4398	* @retval None
	4399	*/
	4400	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
	4401	{
	4402	/* Prevent unused argument(s) compilation warning */
	4403	UNUSED(htim);
	4404
	4405	/* NOTE : This function Should not be modified, when the callback is needed,
	4406	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
	4407	*/
	4408	}
	4409	/**
	4410	* @brief Input Capture callback in non blocking mode
	4411	* @param htim TIM IC handle
	4412	* @retval None
	4413	*/
	4414	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
	4415	{
	4416	/* Prevent unused argument(s) compilation warning */
	4417	UNUSED(htim);
	4418
	4419	/* NOTE : This function Should not be modified, when the callback is needed,
	4420	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
	4421	*/
	4422	}
	4423
	4424	/**
	4425	* @brief PWM Pulse finished callback in non blocking mode
	4426	* @param htim TIM handle
	4427	* @retval None
	4428	*/
	4429	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
	4430	{
	4431	/* Prevent unused argument(s) compilation warning */
	4432	UNUSED(htim);
	4433
	4434	/* NOTE : This function Should not be modified, when the callback is needed,
	4435	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
	4436	*/
	4437	}
	4438
	4439	/**
	4440	* @brief Hall Trigger detection callback in non blocking mode
	4441	* @param htim TIM handle
	4442	* @retval None
	4443	*/
	4444	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
	4445	{
	4446	/* Prevent unused argument(s) compilation warning */
	4447	UNUSED(htim);
	4448
	4449	/* NOTE : This function Should not be modified, when the callback is needed,
	4450	the HAL_TIM_TriggerCallback could be implemented in the user file
	4451	*/
	4452	}
	4453
	4454	/**
	4455	* @brief Timer error callback in non blocking mode
	4456	* @param htim TIM handle
	4457	* @retval None
	4458	*/
	4459	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
	4460	{
	4461	/* Prevent unused argument(s) compilation warning */
	4462	UNUSED(htim);
	4463
	4464	/* NOTE : This function Should not be modified, when the callback is needed,
	4465	the HAL_TIM_ErrorCallback could be implemented in the user file
	4466	*/
	4467	}
	4468
	4469	/**
	4470	* @}
	4471	*/
	4472
	4473	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
	4474	* @brief Peripheral State functions
	4475	*
	4476	@verbatim
	4477	==============================================================================
	4478	##### Peripheral State functions #####
	4479	==============================================================================
	4480	[..]
	4481	This subsection permit to get in run-time the status of the peripheral
	4482	and the data flow.
	4483
	4484	@endverbatim
	4485	* @{
	4486	*/
	4487
	4488	/**
	4489	* @brief Return the TIM Base state
	4490	* @param htim TIM Base handle
	4491	* @retval HAL state
	4492	*/
	4493	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
	4494	{
	4495	return htim->State;
	4496	}
	4497
	4498	/**
	4499	* @brief Return the TIM OC state
	4500	* @param htim TIM Ouput Compare handle
	4501	* @retval HAL state
	4502	*/
	4503	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
	4504	{
	4505	return htim->State;
	4506	}
	4507
	4508	/**
	4509	* @brief Return the TIM PWM state
	4510	* @param htim TIM handle
	4511	* @retval HAL state
	4512	*/
	4513	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
	4514	{
	4515	return htim->State;
	4516	}
	4517
	4518	/**
	4519	* @brief Return the TIM Input Capture state
	4520	* @param htim TIM IC handle
	4521	* @retval HAL state
	4522	*/
	4523	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
	4524	{
	4525	return htim->State;
	4526	}
	4527
	4528	/**
	4529	* @brief Return the TIM One Pulse Mode state
	4530	* @param htim TIM OPM handle
	4531	* @retval HAL state
	4532	*/
	4533	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
	4534	{
	4535	return htim->State;
	4536	}
	4537
	4538	/**
	4539	* @brief Return the TIM Encoder Mode state
	4540	* @param htim TIM Encoder handle
	4541	* @retval HAL state
	4542	*/
	4543	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
	4544	{
	4545	return htim->State;
	4546	}
	4547
	4548	/**
	4549	* @}
	4550	*/
	4551
	4552	/**
	4553	* @}
	4554	*/
	4555
	4556	/** @addtogroup TIM_Private_Functions TIM_Private_Functions
	4557	* @{
	4558	*/
	4559
	4560	/**
	4561	* @brief TIM DMA error callback
	4562	* @param hdma pointer to DMA handle.
	4563	* @retval None
	4564	*/
	4565	void TIM_DMAError(DMA_HandleTypeDef *hdma)
	4566	{
	4567	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
	4568
	4569	htim->State= HAL_TIM_STATE_READY;
	4570
	4571	HAL_TIM_ErrorCallback(htim);
	4572	}
	4573
	4574	/**
	4575	* @brief TIM DMA Delay Pulse complete callback.
	4576	* @param hdma pointer to DMA handle.
	4577	* @retval None
	4578	*/
	4579	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
	4580	{
	4581	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
	4582
	4583	htim->State= HAL_TIM_STATE_READY;
	4584
	4585	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
	4586	{
	4587	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
	4588	}
	4589	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
	4590	{
	4591	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
	4592	}
	4593	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
	4594	{
	4595	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
	4596	}
	4597	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
	4598	{
	4599	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
	4600	}
	4601
	4602	HAL_TIM_PWM_PulseFinishedCallback(htim);
	4603
	4604	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
	4605	}
	4606	/**
	4607	* @brief TIM DMA Capture complete callback.
	4608	* @param hdma pointer to DMA handle.
	4609	* @retval None
	4610	*/
	4611	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
	4612	{
	4613	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
	4614
	4615	htim->State= HAL_TIM_STATE_READY;
	4616
	4617	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
	4618	{
	4619	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
	4620	}
	4621	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
	4622	{
	4623	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
	4624	}
	4625	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
	4626	{
	4627	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
	4628	}
	4629	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
	4630	{
	4631	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
	4632	}
	4633
	4634	HAL_TIM_IC_CaptureCallback(htim);
	4635
	4636	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
	4637	}
	4638
	4639	/**
	4640	* @brief TIM DMA Period Elapse complete callback.
	4641	* @param hdma pointer to DMA handle.
	4642	* @retval None
	4643	*/
	4644	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
	4645	{
	4646	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
	4647
	4648	htim->State= HAL_TIM_STATE_READY;
	4649
	4650	HAL_TIM_PeriodElapsedCallback(htim);
	4651	}
	4652
	4653	/**
	4654	* @brief TIM DMA Trigger callback.
	4655	* @param hdma pointer to DMA handle.
	4656	* @retval None
	4657	*/
	4658	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
	4659	{
	4660	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
	4661
	4662	htim->State= HAL_TIM_STATE_READY;
	4663
	4664	HAL_TIM_TriggerCallback(htim);
	4665	}
	4666
	4667	/**
	4668	* @brief Time Base configuration
	4669	* @param TIMx TIM periheral
	4670	* @param Structure TIM Base configuration structure
	4671	* @retval None
	4672	*/
	4673	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
	4674	{
	4675	uint32_t tmpcr1 = 0U;
	4676	tmpcr1 = TIMx->CR1;
	4677
	4678	/* Set TIM Time Base Unit parameters ---------------------------------------*/
	4679	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
	4680	{
	4681	/* Select the Counter Mode */
	4682	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
	4683	tmpcr1 \|= Structure->CounterMode;
	4684	}
	4685
	4686	if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
	4687	{
	4688	/* Set the clock division */
	4689	tmpcr1 &= ~TIM_CR1_CKD;
	4690	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
	4691	}
	4692
	4693	/* Set the auto-reload preload */
	4694	MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
	4695
	4696	TIMx->CR1 = tmpcr1;
	4697
	4698	/* Set the Autoreload value */
	4699	TIMx->ARR = (uint32_t)Structure->Period ;
	4700
	4701	/* Set the Prescaler value */
	4702	TIMx->PSC = (uint32_t)Structure->Prescaler;
	4703
	4704	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
	4705	{
	4706	/* Set the Repetition Counter value */
	4707	TIMx->RCR = Structure->RepetitionCounter;
	4708	}
	4709
	4710	/* Generate an update event to reload the Prescaler
	4711	and the repetition counter(only for TIM1 and TIM8) value immediatly */
	4712	TIMx->EGR = TIM_EGR_UG;
	4713	}
	4714
	4715	/**
	4716	* @brief Time Ouput Compare 1 configuration
	4717	* @param TIMx to select the TIM peripheral
	4718	* @param OC_Config The ouput configuration structure
	4719	* @retval None
	4720	*/
	4721	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
	4722	{
	4723	uint32_t tmpccmrx = 0U;
	4724	uint32_t tmpccer = 0U;
	4725	uint32_t tmpcr2 = 0U;
	4726
	4727	/* Disable the Channel 1: Reset the CC1E Bit */
	4728	TIMx->CCER &= ~TIM_CCER_CC1E;
	4729
	4730	/* Get the TIMx CCER register value */
	4731	tmpccer = TIMx->CCER;
	4732	/* Get the TIMx CR2 register value */
	4733	tmpcr2 = TIMx->CR2;
	4734
	4735	/* Get the TIMx CCMR1 register value */
	4736	tmpccmrx = TIMx->CCMR1;
	4737
	4738	/* Reset the Output Compare Mode Bits */
	4739	tmpccmrx &= ~TIM_CCMR1_OC1M;
	4740	tmpccmrx &= ~TIM_CCMR1_CC1S;
	4741	/* Select the Output Compare Mode */
	4742	tmpccmrx \|= OC_Config->OCMode;
	4743
	4744	/* Reset the Output Polarity level */
	4745	tmpccer &= ~TIM_CCER_CC1P;
	4746	/* Set the Output Compare Polarity */
	4747	tmpccer \|= OC_Config->OCPolarity;
	4748
	4749	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
	4750	{
	4751	/* Check parameters */
	4752	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
	4753
	4754	/* Reset the Output N Polarity level */
	4755	tmpccer &= ~TIM_CCER_CC1NP;
	4756	/* Set the Output N Polarity */
	4757	tmpccer \|= OC_Config->OCNPolarity;
	4758	/* Reset the Output N State */
	4759	tmpccer &= ~TIM_CCER_CC1NE;
	4760	}
	4761
	4762	if(IS_TIM_BREAK_INSTANCE(TIMx))
	4763	{
	4764	/* Check parameters */
	4765	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
	4766	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
	4767
	4768	/* Reset the Output Compare and Output Compare N IDLE State */
	4769	tmpcr2 &= ~TIM_CR2_OIS1;
	4770	tmpcr2 &= ~TIM_CR2_OIS1N;
	4771	/* Set the Output Idle state */
	4772	tmpcr2 \|= OC_Config->OCIdleState;
	4773	/* Set the Output N Idle state */
	4774	tmpcr2 \|= OC_Config->OCNIdleState;
	4775	}
	4776	/* Write to TIMx CR2 */
	4777	TIMx->CR2 = tmpcr2;
	4778
	4779	/* Write to TIMx CCMR1 */
	4780	TIMx->CCMR1 = tmpccmrx;
	4781
	4782	/* Set the Capture Compare Register value */
	4783	TIMx->CCR1 = OC_Config->Pulse;
	4784
	4785	/* Write to TIMx CCER */
	4786	TIMx->CCER = tmpccer;
	4787	}
	4788
	4789	/**
	4790	* @brief Time Ouput Compare 2 configuration
	4791	* @param TIMx to select the TIM peripheral
	4792	* @param OC_Config The ouput configuration structure
	4793	* @retval None
	4794	*/
	4795	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
	4796	{
	4797	uint32_t tmpccmrx = 0U;
	4798	uint32_t tmpccer = 0U;
	4799	uint32_t tmpcr2 = 0U;
	4800
	4801	/* Disable the Channel 2: Reset the CC2E Bit */
	4802	TIMx->CCER &= ~TIM_CCER_CC2E;
	4803
	4804	/* Get the TIMx CCER register value */
	4805	tmpccer = TIMx->CCER;
	4806	/* Get the TIMx CR2 register value */
	4807	tmpcr2 = TIMx->CR2;
	4808
	4809	/* Get the TIMx CCMR1 register value */
	4810	tmpccmrx = TIMx->CCMR1;
	4811
	4812	/* Reset the Output Compare mode and Capture/Compare selection Bits */
	4813	tmpccmrx &= ~TIM_CCMR1_OC2M;
	4814	tmpccmrx &= ~TIM_CCMR1_CC2S;
	4815
	4816	/* Select the Output Compare Mode */
	4817	tmpccmrx \|= (OC_Config->OCMode << 8U);
	4818
	4819	/* Reset the Output Polarity level */
	4820	tmpccer &= ~TIM_CCER_CC2P;
	4821	/* Set the Output Compare Polarity */
	4822	tmpccer \|= (OC_Config->OCPolarity << 4U);
	4823
	4824	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
	4825	{
	4826	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
	4827
	4828	/* Reset the Output N Polarity level */
	4829	tmpccer &= ~TIM_CCER_CC2NP;
	4830	/* Set the Output N Polarity */
	4831	tmpccer \|= (OC_Config->OCNPolarity << 4U);
	4832	/* Reset the Output N State */
	4833	tmpccer &= ~TIM_CCER_CC2NE;
	4834
	4835	}
	4836
	4837	if(IS_TIM_BREAK_INSTANCE(TIMx))
	4838	{
	4839	/* Check parameters */
	4840	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
	4841	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
	4842
	4843	/* Reset the Output Compare and Output Compare N IDLE State */
	4844	tmpcr2 &= ~TIM_CR2_OIS2;
	4845	tmpcr2 &= ~TIM_CR2_OIS2N;
	4846	/* Set the Output Idle state */
	4847	tmpcr2 \|= (OC_Config->OCIdleState << 2U);
	4848	/* Set the Output N Idle state */
	4849	tmpcr2 \|= (OC_Config->OCNIdleState << 2U);
	4850	}
	4851
	4852	/* Write to TIMx CR2 */
	4853	TIMx->CR2 = tmpcr2;
	4854
	4855	/* Write to TIMx CCMR1 */
	4856	TIMx->CCMR1 = tmpccmrx;
	4857
	4858	/* Set the Capture Compare Register value */
	4859	TIMx->CCR2 = OC_Config->Pulse;
	4860
	4861	/* Write to TIMx CCER */
	4862	TIMx->CCER = tmpccer;
	4863	}
	4864
	4865	/**
	4866	* @brief Time Ouput Compare 3 configuration
	4867	* @param TIMx to select the TIM peripheral
	4868	* @param OC_Config The ouput configuration structure
	4869	* @retval None
	4870	*/
	4871	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
	4872	{
	4873	uint32_t tmpccmrx = 0U;
	4874	uint32_t tmpccer = 0U;
	4875	uint32_t tmpcr2 = 0U;
	4876
	4877	/* Disable the Channel 3: Reset the CC2E Bit */
	4878	TIMx->CCER &= ~TIM_CCER_CC3E;
	4879
	4880	/* Get the TIMx CCER register value */
	4881	tmpccer = TIMx->CCER;
	4882	/* Get the TIMx CR2 register value */
	4883	tmpcr2 = TIMx->CR2;
	4884
	4885	/* Get the TIMx CCMR2 register value */
	4886	tmpccmrx = TIMx->CCMR2;
	4887
	4888	/* Reset the Output Compare mode and Capture/Compare selection Bits */
	4889	tmpccmrx &= ~TIM_CCMR2_OC3M;
	4890	tmpccmrx &= ~TIM_CCMR2_CC3S;
	4891	/* Select the Output Compare Mode */
	4892	tmpccmrx \|= OC_Config->OCMode;
	4893
	4894	/* Reset the Output Polarity level */
	4895	tmpccer &= ~TIM_CCER_CC3P;
	4896	/* Set the Output Compare Polarity */
	4897	tmpccer \|= (OC_Config->OCPolarity << 8U);
	4898
	4899	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
	4900	{
	4901	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
	4902
	4903	/* Reset the Output N Polarity level */
	4904	tmpccer &= ~TIM_CCER_CC3NP;
	4905	/* Set the Output N Polarity */
	4906	tmpccer \|= (OC_Config->OCNPolarity << 8U);
	4907	/* Reset the Output N State */
	4908	tmpccer &= ~TIM_CCER_CC3NE;
	4909	}
	4910
	4911	if(IS_TIM_BREAK_INSTANCE(TIMx))
	4912	{
	4913	/* Check parameters */
	4914	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
	4915	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
	4916
	4917	/* Reset the Output Compare and Output Compare N IDLE State */
	4918	tmpcr2 &= ~TIM_CR2_OIS3;
	4919	tmpcr2 &= ~TIM_CR2_OIS3N;
	4920	/* Set the Output Idle state */
	4921	tmpcr2 \|= (OC_Config->OCIdleState << 4U);
	4922	/* Set the Output N Idle state */
	4923	tmpcr2 \|= (OC_Config->OCNIdleState << 4U);
	4924	}
	4925
	4926	/* Write to TIMx CR2 */
	4927	TIMx->CR2 = tmpcr2;
	4928
	4929	/* Write to TIMx CCMR2 */
	4930	TIMx->CCMR2 = tmpccmrx;
	4931
	4932	/* Set the Capture Compare Register value */
	4933	TIMx->CCR3 = OC_Config->Pulse;
	4934
	4935	/* Write to TIMx CCER */
	4936	TIMx->CCER = tmpccer;
	4937	}
	4938
	4939	/**
	4940	* @brief Time Ouput Compare 4 configuration
	4941	* @param TIMx to select the TIM peripheral
	4942	* @param OC_Config The ouput configuration structure
	4943	* @retval None
	4944	*/
	4945	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
	4946	{
	4947	uint32_t tmpccmrx = 0U;
	4948	uint32_t tmpccer = 0U;
	4949	uint32_t tmpcr2 = 0U;
	4950
	4951	/* Disable the Channel 4: Reset the CC4E Bit */
	4952	TIMx->CCER &= ~TIM_CCER_CC4E;
	4953
	4954	/* Get the TIMx CCER register value */
	4955	tmpccer = TIMx->CCER;
	4956	/* Get the TIMx CR2 register value */
	4957	tmpcr2 = TIMx->CR2;
	4958
	4959	/* Get the TIMx CCMR2 register value */
	4960	tmpccmrx = TIMx->CCMR2;
	4961
	4962	/* Reset the Output Compare mode and Capture/Compare selection Bits */
	4963	tmpccmrx &= ~TIM_CCMR2_OC4M;
	4964	tmpccmrx &= ~TIM_CCMR2_CC4S;
	4965
	4966	/* Select the Output Compare Mode */
	4967	tmpccmrx \|= (OC_Config->OCMode << 8U);
	4968
	4969	/* Reset the Output Polarity level */
	4970	tmpccer &= ~TIM_CCER_CC4P;
	4971	/* Set the Output Compare Polarity */
	4972	tmpccer \|= (OC_Config->OCPolarity << 12U);
	4973
	4974	if(IS_TIM_BREAK_INSTANCE(TIMx))
	4975	{
	4976	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
	4977
	4978	/* Reset the Output Compare IDLE State */
	4979	tmpcr2 &= ~TIM_CR2_OIS4;
	4980	/* Set the Output Idle state */
	4981	tmpcr2 \|= (OC_Config->OCIdleState << 6U);
	4982	}
	4983
	4984	/* Write to TIMx CR2 */
	4985	TIMx->CR2 = tmpcr2;
	4986
	4987	/* Write to TIMx CCMR2 */
	4988	TIMx->CCMR2 = tmpccmrx;
	4989
	4990	/* Set the Capture Compare Register value */
	4991	TIMx->CCR4 = OC_Config->Pulse;
	4992
	4993	/* Write to TIMx CCER */
	4994	TIMx->CCER = tmpccer;
	4995	}
	4996
	4997	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
	4998	TIM_SlaveConfigTypeDef * sSlaveConfig)
	4999	{
	5000	uint32_t tmpsmcr = 0U;
	5001	uint32_t tmpccmr1 = 0U;
	5002	uint32_t tmpccer = 0U;
	5003
	5004	/* Get the TIMx SMCR register value */
	5005	tmpsmcr = htim->Instance->SMCR;
	5006
	5007	/* Reset the Trigger Selection Bits */
	5008	tmpsmcr &= ~TIM_SMCR_TS;
	5009	/* Set the Input Trigger source */
	5010	tmpsmcr \|= sSlaveConfig->InputTrigger;
	5011
	5012	/* Reset the slave mode Bits */
	5013	tmpsmcr &= ~TIM_SMCR_SMS;
	5014	/* Set the slave mode */
	5015	tmpsmcr \|= sSlaveConfig->SlaveMode;
	5016
	5017	/* Write to TIMx SMCR */
	5018	htim->Instance->SMCR = tmpsmcr;
	5019
	5020	/* Configure the trigger prescaler, filter, and polarity */
	5021	switch (sSlaveConfig->InputTrigger)
	5022	{
	5023	case TIM_TS_ETRF:
	5024	{
	5025	/* Check the parameters */
	5026	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
	5027	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
	5028	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
	5029	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
	5030	/* Configure the ETR Trigger source */
	5031	TIM_ETR_SetConfig(htim->Instance,
	5032	sSlaveConfig->TriggerPrescaler,
	5033	sSlaveConfig->TriggerPolarity,
	5034	sSlaveConfig->TriggerFilter);
	5035	}
	5036	break;
	5037
	5038	case TIM_TS_TI1F_ED:
	5039	{
	5040	/* Check the parameters */
	5041	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
	5042	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
	5043
	5044	/* Disable the Channel 1: Reset the CC1E Bit */
	5045	tmpccer = htim->Instance->CCER;
	5046	htim->Instance->CCER &= ~TIM_CCER_CC1E;
	5047	tmpccmr1 = htim->Instance->CCMR1;
	5048
	5049	/* Set the filter */
	5050	tmpccmr1 &= ~TIM_CCMR1_IC1F;
	5051	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4U);
	5052
	5053	/* Write to TIMx CCMR1 and CCER registers */
	5054	htim->Instance->CCMR1 = tmpccmr1;
	5055	htim->Instance->CCER = tmpccer;
	5056
	5057	}
	5058	break;
	5059
	5060	case TIM_TS_TI1FP1:
	5061	{
	5062	/* Check the parameters */
	5063	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
	5064	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
	5065	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
	5066
	5067	/* Configure TI1 Filter and Polarity */
	5068	TIM_TI1_ConfigInputStage(htim->Instance,
	5069	sSlaveConfig->TriggerPolarity,
	5070	sSlaveConfig->TriggerFilter);
	5071	}
	5072	break;
	5073
	5074	case TIM_TS_TI2FP2:
	5075	{
	5076	/* Check the parameters */
	5077	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	5078	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
	5079	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
	5080
	5081	/* Configure TI2 Filter and Polarity */
	5082	TIM_TI2_ConfigInputStage(htim->Instance,
	5083	sSlaveConfig->TriggerPolarity,
	5084	sSlaveConfig->TriggerFilter);
	5085	}
	5086	break;
	5087
	5088	case TIM_TS_ITR0:
	5089	{
	5090	/* Check the parameter */
	5091	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	5092	}
	5093	break;
	5094
	5095	case TIM_TS_ITR1:
	5096	{
	5097	/* Check the parameter */
	5098	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	5099	}
	5100	break;
	5101
	5102	case TIM_TS_ITR2:
	5103	{
	5104	/* Check the parameter */
	5105	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	5106	}
	5107	break;
	5108
	5109	case TIM_TS_ITR3:
	5110	{
	5111	/* Check the parameter */
	5112	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
	5113	}
	5114	break;
	5115
	5116	default:
	5117	break;
	5118	}
	5119	}
	5120
	5121	/**
	5122	* @brief Configure the TI1 as Input.
	5123	* @param TIMx to select the TIM peripheral.
	5124	* @param TIM_ICPolarity The Input Polarity.
	5125	* This parameter can be one of the following values:
	5126	* @arg TIM_ICPOLARITY_RISING
	5127	* @arg TIM_ICPOLARITY_FALLING
	5128	* @arg TIM_ICPOLARITY_BOTHEDGE
	5129	* @param TIM_ICSelection specifies the input to be used.
	5130	* This parameter can be one of the following values:
	5131	* @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1.
	5132	* @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2.
	5133	* @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC.
	5134	* @param TIM_ICFilter Specifies the Input Capture Filter.
	5135	* This parameter must be a value between 0x00 and 0x0F.
	5136	* @retval None
	5137	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
	5138	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
	5139	* protected against un-initialized filter and polarity values.
	5140	*/
	5141	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
	5142	uint32_t TIM_ICFilter)
	5143	{
	5144	uint32_t tmpccmr1 = 0U;
	5145	uint32_t tmpccer = 0U;
	5146
	5147	/* Disable the Channel 1: Reset the CC1E Bit */
	5148	TIMx->CCER &= ~TIM_CCER_CC1E;
	5149	tmpccmr1 = TIMx->CCMR1;
	5150	tmpccer = TIMx->CCER;
	5151
	5152	/* Select the Input */
	5153	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
	5154	{
	5155	tmpccmr1 &= ~TIM_CCMR1_CC1S;
	5156	tmpccmr1 \|= TIM_ICSelection;
	5157	}
	5158	else
	5159	{
	5160	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
	5161	}
	5162
	5163	/* Set the filter */
	5164	tmpccmr1 &= ~TIM_CCMR1_IC1F;
	5165	tmpccmr1 \|= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
	5166
	5167	/* Select the Polarity and set the CC1E Bit */
	5168	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
	5169	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
	5170
	5171	/* Write to TIMx CCMR1 and CCER registers */
	5172	TIMx->CCMR1 = tmpccmr1;
	5173	TIMx->CCER = tmpccer;
	5174	}
	5175
	5176	/**
	5177	* @brief Configure the Polarity and Filter for TI1.
	5178	* @param TIMx to select the TIM peripheral.
	5179	* @param TIM_ICPolarity The Input Polarity.
	5180	* This parameter can be one of the following values:
	5181	* @arg TIM_ICPOLARITY_RISING
	5182	* @arg TIM_ICPOLARITY_FALLING
	5183	* @arg TIM_ICPOLARITY_BOTHEDGE
	5184	* @param TIM_ICFilter Specifies the Input Capture Filter.
	5185	* This parameter must be a value between 0x00 and 0x0F.
	5186	* @retval None
	5187	*/
	5188	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
	5189	{
	5190	uint32_t tmpccmr1 = 0U;
	5191	uint32_t tmpccer = 0U;
	5192
	5193	/* Disable the Channel 1: Reset the CC1E Bit */
	5194	tmpccer = TIMx->CCER;
	5195	TIMx->CCER &= ~TIM_CCER_CC1E;
	5196	tmpccmr1 = TIMx->CCMR1;
	5197
	5198	/* Set the filter */
	5199	tmpccmr1 &= ~TIM_CCMR1_IC1F;
	5200	tmpccmr1 \|= (TIM_ICFilter << 4U);
	5201
	5202	/* Select the Polarity and set the CC1E Bit */
	5203	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
	5204	tmpccer \|= TIM_ICPolarity;
	5205
	5206	/* Write to TIMx CCMR1 and CCER registers */
	5207	TIMx->CCMR1 = tmpccmr1;
	5208	TIMx->CCER = tmpccer;
	5209	}
	5210
	5211	/**
	5212	* @brief Configure the TI2 as Input.
	5213	* @param TIMx to select the TIM peripheral
	5214	* @param TIM_ICPolarity The Input Polarity.
	5215	* This parameter can be one of the following values:
	5216	* @arg TIM_ICPOLARITY_RISING
	5217	* @arg TIM_ICPOLARITY_FALLING
	5218	* @arg TIM_ICPOLARITY_BOTHEDGE
	5219	* @param TIM_ICSelection specifies the input to be used.
	5220	* This parameter can be one of the following values:
	5221	* @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2.
	5222	* @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1.
	5223	* @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC.
	5224	* @param TIM_ICFilter Specifies the Input Capture Filter.
	5225	* This parameter must be a value between 0x00 and 0x0F.
	5226	* @retval None
	5227	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
	5228	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
	5229	* protected against un-initialized filter and polarity values.
	5230	*/
	5231	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
	5232	uint32_t TIM_ICFilter)
	5233	{
	5234	uint32_t tmpccmr1 = 0U;
	5235	uint32_t tmpccer = 0U;
	5236
	5237	/* Disable the Channel 2: Reset the CC2E Bit */
	5238	TIMx->CCER &= ~TIM_CCER_CC2E;
	5239	tmpccmr1 = TIMx->CCMR1;
	5240	tmpccer = TIMx->CCER;
	5241
	5242	/* Select the Input */
	5243	tmpccmr1 &= ~TIM_CCMR1_CC2S;
	5244	tmpccmr1 \|= (TIM_ICSelection << 8U);
	5245
	5246	/* Set the filter */
	5247	tmpccmr1 &= ~TIM_CCMR1_IC2F;
	5248	tmpccmr1 \|= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
	5249
	5250	/* Select the Polarity and set the CC2E Bit */
	5251	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
	5252	tmpccer \|= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
	5253
	5254	/* Write to TIMx CCMR1 and CCER registers */
	5255	TIMx->CCMR1 = tmpccmr1 ;
	5256	TIMx->CCER = tmpccer;
	5257	}
	5258
	5259	/**
	5260	* @brief Configure the Polarity and Filter for TI2.
	5261	* @param TIMx to select the TIM peripheral.
	5262	* @param TIM_ICPolarity The Input Polarity.
	5263	* This parameter can be one of the following values:
	5264	* @arg TIM_ICPOLARITY_RISING
	5265	* @arg TIM_ICPOLARITY_FALLING
	5266	* @arg TIM_ICPOLARITY_BOTHEDGE
	5267	* @param TIM_ICFilter Specifies the Input Capture Filter.
	5268	* This parameter must be a value between 0x00 and 0x0F.
	5269	* @retval None
	5270	*/
	5271	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
	5272	{
	5273	uint32_t tmpccmr1 = 0U;
	5274	uint32_t tmpccer = 0U;
	5275
	5276	/* Disable the Channel 2: Reset the CC2E Bit */
	5277	TIMx->CCER &= ~TIM_CCER_CC2E;
	5278	tmpccmr1 = TIMx->CCMR1;
	5279	tmpccer = TIMx->CCER;
	5280
	5281	/* Set the filter */
	5282	tmpccmr1 &= ~TIM_CCMR1_IC2F;
	5283	tmpccmr1 \|= (TIM_ICFilter << 12U);
	5284
	5285	/* Select the Polarity and set the CC2E Bit */
	5286	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
	5287	tmpccer \|= (TIM_ICPolarity << 4U);
	5288
	5289	/* Write to TIMx CCMR1 and CCER registers */
	5290	TIMx->CCMR1 = tmpccmr1 ;
	5291	TIMx->CCER = tmpccer;
	5292	}
	5293
	5294	/**
	5295	* @brief Configure the TI3 as Input.
	5296	* @param TIMx to select the TIM peripheral
	5297	* @param TIM_ICPolarity The Input Polarity.
	5298	* This parameter can be one of the following values:
	5299	* @arg TIM_ICPOLARITY_RISING
	5300	* @arg TIM_ICPOLARITY_FALLING
	5301	* @arg TIM_ICPOLARITY_BOTHEDGE
	5302	* @param TIM_ICSelection specifies the input to be used.
	5303	* This parameter can be one of the following values:
	5304	* @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3.
	5305	* @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4.
	5306	* @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC.
	5307	* @param TIM_ICFilter Specifies the Input Capture Filter.
	5308	* This parameter must be a value between 0x00 and 0x0F.
	5309	* @retval None
	5310	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
	5311	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
	5312	* protected against un-initialized filter and polarity values.
	5313	*/
	5314	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
	5315	uint32_t TIM_ICFilter)
	5316	{
	5317	uint32_t tmpccmr2 = 0U;
	5318	uint32_t tmpccer = 0U;
	5319
	5320	/* Disable the Channel 3: Reset the CC3E Bit */
	5321	TIMx->CCER &= ~TIM_CCER_CC3E;
	5322	tmpccmr2 = TIMx->CCMR2;
	5323	tmpccer = TIMx->CCER;
	5324
	5325	/* Select the Input */
	5326	tmpccmr2 &= ~TIM_CCMR2_CC3S;
	5327	tmpccmr2 \|= TIM_ICSelection;
	5328
	5329	/* Set the filter */
	5330	tmpccmr2 &= ~TIM_CCMR2_IC3F;
	5331	tmpccmr2 \|= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
	5332
	5333	/* Select the Polarity and set the CC3E Bit */
	5334	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
	5335	tmpccer \|= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
	5336
	5337	/* Write to TIMx CCMR2 and CCER registers */
	5338	TIMx->CCMR2 = tmpccmr2;
	5339	TIMx->CCER = tmpccer;
	5340	}
	5341
	5342	/**
	5343	* @brief Configure the TI4 as Input.
	5344	* @param TIMx to select the TIM peripheral
	5345	* @param TIM_ICPolarity The Input Polarity.
	5346	* This parameter can be one of the following values:
	5347	* @arg TIM_ICPOLARITY_RISING
	5348	* @arg TIM_ICPOLARITY_FALLING
	5349	* @arg TIM_ICPOLARITY_BOTHEDGE
	5350	* @param TIM_ICSelection specifies the input to be used.
	5351	* This parameter can be one of the following values:
	5352	* @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4.
	5353	* @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3.
	5354	* @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC.
	5355	* @param TIM_ICFilter Specifies the Input Capture Filter.
	5356	* This parameter must be a value between 0x00 and 0x0F.
	5357	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
	5358	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
	5359	* protected against un-initialized filter and polarity values.
	5360	* @retval None
	5361	*/
	5362	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
	5363	uint32_t TIM_ICFilter)
	5364	{
	5365	uint32_t tmpccmr2 = 0U;
	5366	uint32_t tmpccer = 0U;
	5367
	5368	/* Disable the Channel 4: Reset the CC4E Bit */
	5369	TIMx->CCER &= ~TIM_CCER_CC4E;
	5370	tmpccmr2 = TIMx->CCMR2;
	5371	tmpccer = TIMx->CCER;
	5372
	5373	/* Select the Input */
	5374	tmpccmr2 &= ~TIM_CCMR2_CC4S;
	5375	tmpccmr2 \|= (TIM_ICSelection << 8U);
	5376
	5377	/* Set the filter */
	5378	tmpccmr2 &= ~TIM_CCMR2_IC4F;
	5379	tmpccmr2 \|= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
	5380
	5381	/* Select the Polarity and set the CC4E Bit */
	5382	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
	5383	tmpccer \|= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
	5384
	5385	/* Write to TIMx CCMR2 and CCER registers */
	5386	TIMx->CCMR2 = tmpccmr2;
	5387	TIMx->CCER = tmpccer ;
	5388	}
	5389
	5390	/**
	5391	* @brief Selects the Input Trigger source
	5392	* @param TIMx to select the TIM peripheral
	5393	* @param InputTriggerSource The Input Trigger source.
	5394	* This parameter can be one of the following values:
	5395	* @arg TIM_TS_ITR0 : Internal Trigger 0
	5396	* @arg TIM_TS_ITR1 : Internal Trigger 1
	5397	* @arg TIM_TS_ITR2 : Internal Trigger 2
	5398	* @arg TIM_TS_ITR3 : Internal Trigger 3
	5399	* @arg TIM_TS_TI1F_ED : TI1 Edge Detector
	5400	* @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
	5401	* @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
	5402	* @arg TIM_TS_ETRF : External Trigger input
	5403	* @retval None
	5404	*/
	5405	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
	5406	{
	5407	uint32_t tmpsmcr = 0U;
	5408
	5409	/* Get the TIMx SMCR register value */
	5410	tmpsmcr = TIMx->SMCR;
	5411	/* Reset the TS Bits */
	5412	tmpsmcr &= ~TIM_SMCR_TS;
	5413	/* Set the Input Trigger source and the slave mode*/
	5414	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
	5415	/* Write to TIMx SMCR */
	5416	TIMx->SMCR = tmpsmcr;
	5417	}
	5418	/**
	5419	* @brief Configures the TIMx External Trigger (ETR).
	5420	* @param TIMx to select the TIM peripheral
	5421	* @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
	5422	* This parameter can be one of the following values:
	5423	* @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
	5424	* @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
	5425	* @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
	5426	* @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
	5427	* @param TIM_ExtTRGPolarity The external Trigger Polarity.
	5428	* This parameter can be one of the following values:
	5429	* @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
	5430	* @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
	5431	* @param ExtTRGFilter External Trigger Filter.
	5432	* This parameter must be a value between 0x00 and 0x0F
	5433	* @retval None
	5434	*/
	5435	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
	5436	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
	5437	{
	5438	uint32_t tmpsmcr = 0U;
	5439
	5440	tmpsmcr = TIMx->SMCR;
	5441
	5442	/* Reset the ETR Bits */
	5443	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
	5444
	5445	/* Set the Prescaler, the Filter value and the Polarity */
	5446	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8U)));
	5447
	5448	/* Write to TIMx SMCR */
	5449	TIMx->SMCR = tmpsmcr;
	5450	}
	5451
	5452	/**
	5453	* @brief Enables or disables the TIM Capture Compare Channel x.
	5454	* @param TIMx to select the TIM peripheral
	5455	* @param Channel specifies the TIM Channel
	5456	* This parameter can be one of the following values:
	5457	* @arg TIM_CHANNEL_1 : TIM Channel 1
	5458	* @arg TIM_CHANNEL_2 : TIM Channel 2
	5459	* @arg TIM_CHANNEL_3 : TIM Channel 3
	5460	* @arg TIM_CHANNEL_4 : TIM Channel 4
	5461	* @param ChannelState specifies the TIM Channel CCxE bit new state.
	5462	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
	5463	* @retval None
	5464	*/
	5465	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
	5466	{
	5467	uint32_t tmp = 0U;
	5468
	5469	/* Check the parameters */
	5470	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
	5471	assert_param(IS_TIM_CHANNELS(Channel));
	5472
	5473	tmp = TIM_CCER_CC1E << Channel;
	5474
	5475	/* Reset the CCxE Bit */
	5476	TIMx->CCER &= ~tmp;
	5477
	5478	/* Set or reset the CCxE Bit */
	5479	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
	5480	}
	5481
	5482
	5483	/**
	5484	* @}
	5485	*/
	5486
	5487	#endif /* HAL_TIM_MODULE_ENABLED */
	5488	/**
	5489	* @}
	5490	*/
	5491
	5492	/**
	5493	* @}
	5494	*/
	5495	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/