| 提交 | 用户 | age | ||
| bfc108 | 1 | /** |
| Q | 2 | ****************************************************************************** |
| 3 | * @file stm32f0xx_hal_cec.h | |
| 4 | * @author MCD Application Team | |
| 5 | * @brief Header file of CEC HAL module. | |
| 6 | ****************************************************************************** | |
| 7 | * @attention | |
| 8 | * | |
| 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> | |
| 10 | * | |
| 11 | * Redistribution and use in source and binary forms, with or without modification, | |
| 12 | * are permitted provided that the following conditions are met: | |
| 13 | * 1. Redistributions of source code must retain the above copyright notice, | |
| 14 | * this list of conditions and the following disclaimer. | |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, | |
| 16 | * this list of conditions and the following disclaimer in the documentation | |
| 17 | * and/or other materials provided with the distribution. | |
| 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
| 19 | * may be used to endorse or promote products derived from this software | |
| 20 | * without specific prior written permission. | |
| 21 | * | |
| 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
| 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
| 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
| 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
| 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
| 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 32 | * | |
| 33 | ****************************************************************************** | |
| 34 | */ | |
| 35 | ||
| 36 | /* Define to prevent recursive inclusion -------------------------------------*/ | |
| 37 | #ifndef __STM32F0xx_HAL_CEC_H | |
| 38 | #define __STM32F0xx_HAL_CEC_H | |
| 39 | ||
| 40 | #ifdef __cplusplus | |
| 41 | extern "C" { | |
| 42 | #endif | |
| 43 | ||
| 44 | #if defined(STM32F042x6) || defined(STM32F048xx) ||\ | |
| 45 | defined(STM32F051x8) || defined(STM32F058xx) ||\ | |
| 46 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\ | |
| 47 | defined(STM32F091xC) || defined(STM32F098xx) | |
| 48 | /* Includes ------------------------------------------------------------------*/ | |
| 49 | #include "stm32f0xx_hal_def.h" | |
| 50 | ||
| 51 | /** @addtogroup STM32F0xx_HAL_Driver | |
| 52 | * @{ | |
| 53 | */ | |
| 54 | ||
| 55 | /** @addtogroup CEC | |
| 56 | * @{ | |
| 57 | */ | |
| 58 | ||
| 59 | /* Exported types ------------------------------------------------------------*/ | |
| 60 | /** @defgroup CEC_Exported_Types CEC Exported Types | |
| 61 | * @{ | |
| 62 | */ | |
| 63 | ||
| 64 | /** | |
| 65 | * @brief CEC Init Structure definition | |
| 66 | */ | |
| 67 | typedef struct | |
| 68 | { | |
| 69 | uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. | |
| 70 | It can be one of @ref CEC_Signal_Free_Time | |
| 71 | and belongs to the set {0,...,7} where | |
| 72 | 0x0 is the default configuration | |
| 73 | else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ | |
| 74 | ||
| 75 | uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, | |
| 76 | it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE | |
| 77 | or CEC_EXTENDED_TOLERANCE */ | |
| 78 | ||
| 79 | uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. | |
| 80 | CEC_NO_RX_STOP_ON_BRE: reception is not stopped. | |
| 81 | CEC_RX_STOP_ON_BRE: reception is stopped. */ | |
| 82 | ||
| 83 | uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the | |
| 84 | CEC line upon Bit Rising Error detection. | |
| 85 | CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. | |
| 86 | CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ | |
| 87 | ||
| 88 | uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the | |
| 89 | CEC line upon Long Bit Period Error detection. | |
| 90 | CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. | |
| 91 | CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ | |
| 92 | ||
| 93 | uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line | |
| 94 | upon an error detected on a broadcast message. | |
| 95 | ||
| 96 | It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values: | |
| 97 | ||
| 98 | 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. | |
| 99 | a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE | |
| 100 | and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. | |
| 101 | b) LBPE detection: error-bit generation on the CEC line | |
| 102 | if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. | |
| 103 | ||
| 104 | 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. | |
| 105 | no error-bit generation in case neither a) nor b) are satisfied. Additionally, | |
| 106 | there is no error-bit generation in case of Short Bit Period Error detection in | |
| 107 | a broadcast message while LSTN bit is set. */ | |
| 108 | ||
| 109 | uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts. | |
| 110 | CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. | |
| 111 | CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */ | |
| 112 | ||
| 113 | uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values: | |
| 114 | ||
| 115 | CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its | |
| 116 | own address (OAR). Messages addressed to different destination are ignored. | |
| 117 | Broadcast messages are always received. | |
| 118 | ||
| 119 | CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own | |
| 120 | address (OAR) with positive acknowledge. Messages addressed to different destination | |
| 121 | are received, but without interfering with the CEC bus: no acknowledge sent. */ | |
| 122 | ||
| 123 | uint16_t OwnAddress; /*!< Own addresses configuration | |
| 124 | This parameter can be a value of @ref CEC_OWN_ADDRESS */ | |
| 125 | ||
| 126 | uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */ | |
| 127 | ||
| 128 | ||
| 129 | }CEC_InitTypeDef; | |
| 130 | ||
| 131 | /** | |
| 132 | * @brief HAL CEC State structures definition | |
| 133 | * @note HAL CEC State value is a combination of 2 different substates: gState and RxState. | |
| 134 | * - gState contains CEC state information related to global Handle management | |
| 135 | * and also information related to Tx operations. | |
| 136 | * gState value coding follow below described bitmap : | |
| 137 | * b7 (not used) | |
| 138 | * x : Should be set to 0 | |
| 139 | * b6 Error information | |
| 140 | * 0 : No Error | |
| 141 | * 1 : Error | |
| 142 | * b5 IP initilisation status | |
| 143 | * 0 : Reset (IP not initialized) | |
| 144 | * 1 : Init done (IP initialized. HAL CEC Init function already called) | |
| 145 | * b4-b3 (not used) | |
| 146 | * xx : Should be set to 00 | |
| 147 | * b2 Intrinsic process state | |
| 148 | * 0 : Ready | |
| 149 | * 1 : Busy (IP busy with some configuration or internal operations) | |
| 150 | * b1 (not used) | |
| 151 | * x : Should be set to 0 | |
| 152 | * b0 Tx state | |
| 153 | * 0 : Ready (no Tx operation ongoing) | |
| 154 | * 1 : Busy (Tx operation ongoing) | |
| 155 | * - RxState contains information related to Rx operations. | |
| 156 | * RxState value coding follow below described bitmap : | |
| 157 | * b7-b6 (not used) | |
| 158 | * xx : Should be set to 00 | |
| 159 | * b5 IP initilisation status | |
| 160 | * 0 : Reset (IP not initialized) | |
| 161 | * 1 : Init done (IP initialized) | |
| 162 | * b4-b2 (not used) | |
| 163 | * xxx : Should be set to 000 | |
| 164 | * b1 Rx state | |
| 165 | * 0 : Ready (no Rx operation ongoing) | |
| 166 | * 1 : Busy (Rx operation ongoing) | |
| 167 | * b0 (not used) | |
| 168 | * x : Should be set to 0. | |
| 169 | */ | |
| 170 | typedef enum | |
| 171 | { | |
| 172 | HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized | |
| 173 | Value is allowed for gState and RxState */ | |
| 174 | HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use | |
| 175 | Value is allowed for gState and RxState */ | |
| 176 | HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing | |
| 177 | Value is allowed for gState only */ | |
| 178 | HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing | |
| 179 | Value is allowed for RxState only */ | |
| 180 | HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing | |
| 181 | Value is allowed for gState only */ | |
| 182 | HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing | |
| 183 | Value is allowed for gState only */ | |
| 184 | HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */ | |
| 185 | }HAL_CEC_StateTypeDef; | |
| 186 | ||
| 187 | /** | |
| 188 | * @brief CEC handle Structure definition | |
| 189 | */ | |
| 190 | typedef struct | |
| 191 | { | |
| 192 | CEC_TypeDef *Instance; /*!< CEC registers base address */ | |
| 193 | ||
| 194 | CEC_InitTypeDef Init; /*!< CEC communication parameters */ | |
| 195 | ||
| 196 | uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ | |
| 197 | ||
| 198 | uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ | |
| 199 | ||
| 200 | uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ | |
| 201 | ||
| 202 | HAL_LockTypeDef Lock; /*!< Locking object */ | |
| 203 | ||
| 204 | HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management | |
| 205 | and also related to Tx operations. | |
| 206 | This parameter can be a value of @ref HAL_CEC_StateTypeDef */ | |
| 207 | ||
| 208 | HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. | |
| 209 | This parameter can be a value of @ref HAL_CEC_StateTypeDef */ | |
| 210 | ||
| 211 | uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register | |
| 212 | in case error is reported */ | |
| 213 | }CEC_HandleTypeDef; | |
| 214 | /** | |
| 215 | * @} | |
| 216 | */ | |
| 217 | ||
| 218 | /* Exported constants --------------------------------------------------------*/ | |
| 219 | /** @defgroup CEC_Exported_Constants CEC Exported Constants | |
| 220 | * @{ | |
| 221 | */ | |
| 222 | ||
| 223 | /** @defgroup CEC_Error_Code CEC Error Code | |
| 224 | * @{ | |
| 225 | */ | |
| 226 | #define HAL_CEC_ERROR_NONE (0x00000000U) /*!< no error */ | |
| 227 | #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */ | |
| 228 | #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */ | |
| 229 | #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */ | |
| 230 | #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */ | |
| 231 | #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */ | |
| 232 | #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */ | |
| 233 | #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */ | |
| 234 | #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */ | |
| 235 | #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */ | |
| 236 | /** | |
| 237 | * @} | |
| 238 | */ | |
| 239 | ||
| 240 | /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter | |
| 241 | * @{ | |
| 242 | */ | |
| 243 | #define CEC_DEFAULT_SFT (0x00000000U) | |
| 244 | #define CEC_0_5_BITPERIOD_SFT (0x00000001U) | |
| 245 | #define CEC_1_5_BITPERIOD_SFT (0x00000002U) | |
| 246 | #define CEC_2_5_BITPERIOD_SFT (0x00000003U) | |
| 247 | #define CEC_3_5_BITPERIOD_SFT (0x00000004U) | |
| 248 | #define CEC_4_5_BITPERIOD_SFT (0x00000005U) | |
| 249 | #define CEC_5_5_BITPERIOD_SFT (0x00000006U) | |
| 250 | #define CEC_6_5_BITPERIOD_SFT (0x00000007U) | |
| 251 | /** | |
| 252 | * @} | |
| 253 | */ | |
| 254 | ||
| 255 | /** @defgroup CEC_Tolerance CEC Receiver Tolerance | |
| 256 | * @{ | |
| 257 | */ | |
| 258 | #define CEC_STANDARD_TOLERANCE (0x00000000U) | |
| 259 | #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) | |
| 260 | /** | |
| 261 | * @} | |
| 262 | */ | |
| 263 | ||
| 264 | /** @defgroup CEC_BRERxStop CEC Reception Stop on Error | |
| 265 | * @{ | |
| 266 | */ | |
| 267 | #define CEC_NO_RX_STOP_ON_BRE (0x00000000U) | |
| 268 | #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) | |
| 269 | /** | |
| 270 | * @} | |
| 271 | */ | |
| 272 | ||
| 273 | /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported | |
| 274 | * @{ | |
| 275 | */ | |
| 276 | #define CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U) | |
| 277 | #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) | |
| 278 | /** | |
| 279 | * @} | |
| 280 | */ | |
| 281 | ||
| 282 | /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported | |
| 283 | * @{ | |
| 284 | */ | |
| 285 | #define CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U) | |
| 286 | #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) | |
| 287 | /** | |
| 288 | * @} | |
| 289 | */ | |
| 290 | ||
| 291 | /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message | |
| 292 | * @{ | |
| 293 | */ | |
| 294 | #define CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U) | |
| 295 | #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) | |
| 296 | /** | |
| 297 | * @} | |
| 298 | */ | |
| 299 | ||
| 300 | /** @defgroup CEC_SFT_Option CEC Signal Free Time start option | |
| 301 | * @{ | |
| 302 | */ | |
| 303 | #define CEC_SFT_START_ON_TXSOM (0x00000000U) | |
| 304 | #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) | |
| 305 | /** | |
| 306 | * @} | |
| 307 | */ | |
| 308 | ||
| 309 | /** @defgroup CEC_Listening_Mode CEC Listening mode option | |
| 310 | * @{ | |
| 311 | */ | |
| 312 | #define CEC_REDUCED_LISTENING_MODE (0x00000000U) | |
| 313 | #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) | |
| 314 | /** | |
| 315 | * @} | |
| 316 | */ | |
| 317 | ||
| 318 | /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register | |
| 319 | * @{ | |
| 320 | */ | |
| 321 | #define CEC_CFGR_OAR_LSB_POS (16U) | |
| 322 | /** | |
| 323 | * @} | |
| 324 | */ | |
| 325 | ||
| 326 | /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header | |
| 327 | * @{ | |
| 328 | */ | |
| 329 | #define CEC_INITIATOR_LSB_POS (4U) | |
| 330 | /** | |
| 331 | * @} | |
| 332 | */ | |
| 333 | ||
| 334 | /** @defgroup CEC_OWN_ADDRESS CEC Own Address | |
| 335 | * @{ | |
| 336 | */ | |
| 337 | #define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ | |
| 338 | #define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ | |
| 339 | #define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ | |
| 340 | #define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ | |
| 341 | #define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ | |
| 342 | #define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ | |
| 343 | #define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ | |
| 344 | #define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ | |
| 345 | #define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ | |
| 346 | #define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ | |
| 347 | #define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */ | |
| 348 | #define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */ | |
| 349 | #define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */ | |
| 350 | #define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */ | |
| 351 | #define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */ | |
| 352 | #define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */ | |
| 353 | /** | |
| 354 | * @} | |
| 355 | */ | |
| 356 | ||
| 357 | /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition | |
| 358 | * @{ | |
| 359 | */ | |
| 360 | #define CEC_IT_TXACKE CEC_IER_TXACKEIE | |
| 361 | #define CEC_IT_TXERR CEC_IER_TXERRIE | |
| 362 | #define CEC_IT_TXUDR CEC_IER_TXUDRIE | |
| 363 | #define CEC_IT_TXEND CEC_IER_TXENDIE | |
| 364 | #define CEC_IT_TXBR CEC_IER_TXBRIE | |
| 365 | #define CEC_IT_ARBLST CEC_IER_ARBLSTIE | |
| 366 | #define CEC_IT_RXACKE CEC_IER_RXACKEIE | |
| 367 | #define CEC_IT_LBPE CEC_IER_LBPEIE | |
| 368 | #define CEC_IT_SBPE CEC_IER_SBPEIE | |
| 369 | #define CEC_IT_BRE CEC_IER_BREIE | |
| 370 | #define CEC_IT_RXOVR CEC_IER_RXOVRIE | |
| 371 | #define CEC_IT_RXEND CEC_IER_RXENDIE | |
| 372 | #define CEC_IT_RXBR CEC_IER_RXBRIE | |
| 373 | /** | |
| 374 | * @} | |
| 375 | */ | |
| 376 | ||
| 377 | /** @defgroup CEC_Flags_Definitions CEC Flags definition | |
| 378 | * @{ | |
| 379 | */ | |
| 380 | #define CEC_FLAG_TXACKE CEC_ISR_TXACKE | |
| 381 | #define CEC_FLAG_TXERR CEC_ISR_TXERR | |
| 382 | #define CEC_FLAG_TXUDR CEC_ISR_TXUDR | |
| 383 | #define CEC_FLAG_TXEND CEC_ISR_TXEND | |
| 384 | #define CEC_FLAG_TXBR CEC_ISR_TXBR | |
| 385 | #define CEC_FLAG_ARBLST CEC_ISR_ARBLST | |
| 386 | #define CEC_FLAG_RXACKE CEC_ISR_RXACKE | |
| 387 | #define CEC_FLAG_LBPE CEC_ISR_LBPE | |
| 388 | #define CEC_FLAG_SBPE CEC_ISR_SBPE | |
| 389 | #define CEC_FLAG_BRE CEC_ISR_BRE | |
| 390 | #define CEC_FLAG_RXOVR CEC_ISR_RXOVR | |
| 391 | #define CEC_FLAG_RXEND CEC_ISR_RXEND | |
| 392 | #define CEC_FLAG_RXBR CEC_ISR_RXBR | |
| 393 | /** | |
| 394 | * @} | |
| 395 | */ | |
| 396 | ||
| 397 | /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags | |
| 398 | * @{ | |
| 399 | */ | |
| 400 | #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ | |
| 401 | CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) | |
| 402 | /** | |
| 403 | * @} | |
| 404 | */ | |
| 405 | ||
| 406 | /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag | |
| 407 | * @{ | |
| 408 | */ | |
| 409 | #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) | |
| 410 | /** | |
| 411 | * @} | |
| 412 | */ | |
| 413 | ||
| 414 | /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag | |
| 415 | * @{ | |
| 416 | */ | |
| 417 | #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) | |
| 418 | /** | |
| 419 | * @} | |
| 420 | */ | |
| 421 | ||
| 422 | /** | |
| 423 | * @} | |
| 424 | */ | |
| 425 | ||
| 426 | /* Exported macros -----------------------------------------------------------*/ | |
| 427 | /** @defgroup CEC_Exported_Macros CEC Exported Macros | |
| 428 | * @{ | |
| 429 | */ | |
| 430 | ||
| 431 | /** @brief Reset CEC handle gstate & RxState | |
| 432 | * @param __HANDLE__ CEC handle. | |
| 433 | * @retval None | |
| 434 | */ | |
| 435 | #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ | |
| 436 | (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ | |
| 437 | (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ | |
| 438 | } while(0) | |
| 439 | ||
| 440 | /** @brief Checks whether or not the specified CEC interrupt flag is set. | |
| 441 | * @param __HANDLE__ specifies the CEC Handle. | |
| 442 | * @param __FLAG__ specifies the flag to check. | |
| 443 | * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error | |
| 444 | * @arg CEC_FLAG_TXERR: Tx Error. | |
| 445 | * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. | |
| 446 | * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). | |
| 447 | * @arg CEC_FLAG_TXBR: Tx-Byte Request. | |
| 448 | * @arg CEC_FLAG_ARBLST: Arbitration Lost | |
| 449 | * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge | |
| 450 | * @arg CEC_FLAG_LBPE: Rx Long period Error | |
| 451 | * @arg CEC_FLAG_SBPE: Rx Short period Error | |
| 452 | * @arg CEC_FLAG_BRE: Rx Bit Rising Error | |
| 453 | * @arg CEC_FLAG_RXOVR: Rx Overrun. | |
| 454 | * @arg CEC_FLAG_RXEND: End Of Reception. | |
| 455 | * @arg CEC_FLAG_RXBR: Rx-Byte Received. | |
| 456 | * @retval ITStatus | |
| 457 | */ | |
| 458 | #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) | |
| 459 | ||
| 460 | /** @brief Clears the interrupt or status flag when raised (write at 1) | |
| 461 | * @param __HANDLE__ specifies the CEC Handle. | |
| 462 | * @param __FLAG__ specifies the interrupt/status flag to clear. | |
| 463 | * This parameter can be one of the following values: | |
| 464 | * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error | |
| 465 | * @arg CEC_FLAG_TXERR: Tx Error. | |
| 466 | * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. | |
| 467 | * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). | |
| 468 | * @arg CEC_FLAG_TXBR: Tx-Byte Request. | |
| 469 | * @arg CEC_FLAG_ARBLST: Arbitration Lost | |
| 470 | * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge | |
| 471 | * @arg CEC_FLAG_LBPE: Rx Long period Error | |
| 472 | * @arg CEC_FLAG_SBPE: Rx Short period Error | |
| 473 | * @arg CEC_FLAG_BRE: Rx Bit Rising Error | |
| 474 | * @arg CEC_FLAG_RXOVR: Rx Overrun. | |
| 475 | * @arg CEC_FLAG_RXEND: End Of Reception. | |
| 476 | * @arg CEC_FLAG_RXBR: Rx-Byte Received. | |
| 477 | * @retval none | |
| 478 | */ | |
| 479 | #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) | |
| 480 | ||
| 481 | /** @brief Enables the specified CEC interrupt. | |
| 482 | * @param __HANDLE__ specifies the CEC Handle. | |
| 483 | * @param __INTERRUPT__ specifies the CEC interrupt to enable. | |
| 484 | * This parameter can be one of the following values: | |
| 485 | * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable | |
| 486 | * @arg CEC_IT_TXERR: Tx Error IT Enable | |
| 487 | * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable | |
| 488 | * @arg CEC_IT_TXEND: End of transmission IT Enable | |
| 489 | * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable | |
| 490 | * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable | |
| 491 | * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable | |
| 492 | * @arg CEC_IT_LBPE: Rx Long period Error IT Enable | |
| 493 | * @arg CEC_IT_SBPE: Rx Short period Error IT Enable | |
| 494 | * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable | |
| 495 | * @arg CEC_IT_RXOVR: Rx Overrun IT Enable | |
| 496 | * @arg CEC_IT_RXEND: End Of Reception IT Enable | |
| 497 | * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable | |
| 498 | * @retval none | |
| 499 | */ | |
| 500 | #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) | |
| 501 | ||
| 502 | /** @brief Disables the specified CEC interrupt. | |
| 503 | * @param __HANDLE__ specifies the CEC Handle. | |
| 504 | * @param __INTERRUPT__ specifies the CEC interrupt to disable. | |
| 505 | * This parameter can be one of the following values: | |
| 506 | * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable | |
| 507 | * @arg CEC_IT_TXERR: Tx Error IT Enable | |
| 508 | * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable | |
| 509 | * @arg CEC_IT_TXEND: End of transmission IT Enable | |
| 510 | * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable | |
| 511 | * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable | |
| 512 | * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable | |
| 513 | * @arg CEC_IT_LBPE: Rx Long period Error IT Enable | |
| 514 | * @arg CEC_IT_SBPE: Rx Short period Error IT Enable | |
| 515 | * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable | |
| 516 | * @arg CEC_IT_RXOVR: Rx Overrun IT Enable | |
| 517 | * @arg CEC_IT_RXEND: End Of Reception IT Enable | |
| 518 | * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable | |
| 519 | * @retval none | |
| 520 | */ | |
| 521 | #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) | |
| 522 | ||
| 523 | /** @brief Checks whether or not the specified CEC interrupt is enabled. | |
| 524 | * @param __HANDLE__ specifies the CEC Handle. | |
| 525 | * @param __INTERRUPT__ specifies the CEC interrupt to check. | |
| 526 | * This parameter can be one of the following values: | |
| 527 | * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable | |
| 528 | * @arg CEC_IT_TXERR: Tx Error IT Enable | |
| 529 | * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable | |
| 530 | * @arg CEC_IT_TXEND: End of transmission IT Enable | |
| 531 | * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable | |
| 532 | * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable | |
| 533 | * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable | |
| 534 | * @arg CEC_IT_LBPE: Rx Long period Error IT Enable | |
| 535 | * @arg CEC_IT_SBPE: Rx Short period Error IT Enable | |
| 536 | * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable | |
| 537 | * @arg CEC_IT_RXOVR: Rx Overrun IT Enable | |
| 538 | * @arg CEC_IT_RXEND: End Of Reception IT Enable | |
| 539 | * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable | |
| 540 | * @retval FlagStatus | |
| 541 | */ | |
| 542 | #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) | |
| 543 | ||
| 544 | /** @brief Enables the CEC device | |
| 545 | * @param __HANDLE__ specifies the CEC Handle. | |
| 546 | * @retval none | |
| 547 | */ | |
| 548 | #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) | |
| 549 | ||
| 550 | /** @brief Disables the CEC device | |
| 551 | * @param __HANDLE__ specifies the CEC Handle. | |
| 552 | * @retval none | |
| 553 | */ | |
| 554 | #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) | |
| 555 | ||
| 556 | /** @brief Set Transmission Start flag | |
| 557 | * @param __HANDLE__ specifies the CEC Handle. | |
| 558 | * @retval none | |
| 559 | */ | |
| 560 | #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) | |
| 561 | ||
| 562 | /** @brief Set Transmission End flag | |
| 563 | * @param __HANDLE__ specifies the CEC Handle. | |
| 564 | * @retval none | |
| 565 | * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. | |
| 566 | */ | |
| 567 | #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) | |
| 568 | ||
| 569 | /** @brief Get Transmission Start flag | |
| 570 | * @param __HANDLE__ specifies the CEC Handle. | |
| 571 | * @retval FlagStatus | |
| 572 | */ | |
| 573 | #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) | |
| 574 | ||
| 575 | /** @brief Get Transmission End flag | |
| 576 | * @param __HANDLE__ specifies the CEC Handle. | |
| 577 | * @retval FlagStatus | |
| 578 | */ | |
| 579 | #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) | |
| 580 | ||
| 581 | /** @brief Clear OAR register | |
| 582 | * @param __HANDLE__ specifies the CEC Handle. | |
| 583 | * @retval none | |
| 584 | */ | |
| 585 | #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) | |
| 586 | ||
| 587 | /** @brief Set OAR register (without resetting previously set address in case of multi-address mode) | |
| 588 | * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand | |
| 589 | * @param __HANDLE__ specifies the CEC Handle. | |
| 590 | * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) | |
| 591 | * @retval none | |
| 592 | */ | |
| 593 | #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) | |
| 594 | ||
| 595 | /** | |
| 596 | * @} | |
| 597 | */ | |
| 598 | ||
| 599 | /* Exported functions --------------------------------------------------------*/ | |
| 600 | /** @addtogroup CEC_Exported_Functions | |
| 601 | * @{ | |
| 602 | */ | |
| 603 | ||
| 604 | /** @addtogroup CEC_Exported_Functions_Group1 | |
| 605 | * @{ | |
| 606 | */ | |
| 607 | /* Initialization and de-initialization functions ****************************/ | |
| 608 | HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); | |
| 609 | HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); | |
| 610 | HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress); | |
| 611 | void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); | |
| 612 | void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); | |
| 613 | /** | |
| 614 | * @} | |
| 615 | */ | |
| 616 | ||
| 617 | /** @addtogroup CEC_Exported_Functions_Group2 | |
| 618 | * @{ | |
| 619 | */ | |
| 620 | /* I/O operation functions ***************************************************/ | |
| 621 | HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); | |
| 622 | uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec); | |
| 623 | void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer); | |
| 624 | void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); | |
| 625 | void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); | |
| 626 | void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); | |
| 627 | void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); | |
| 628 | /** | |
| 629 | * @} | |
| 630 | */ | |
| 631 | ||
| 632 | /** @addtogroup CEC_Exported_Functions_Group3 | |
| 633 | * @{ | |
| 634 | */ | |
| 635 | /* Peripheral State functions ************************************************/ | |
| 636 | HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); | |
| 637 | uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); | |
| 638 | /** | |
| 639 | * @} | |
| 640 | */ | |
| 641 | ||
| 642 | /** | |
| 643 | * @} | |
| 644 | */ | |
| 645 | ||
| 646 | /* Private types -------------------------------------------------------------*/ | |
| 647 | /** @defgroup CEC_Private_Types CEC Private Types | |
| 648 | * @{ | |
| 649 | */ | |
| 650 | ||
| 651 | /** | |
| 652 | * @} | |
| 653 | */ | |
| 654 | ||
| 655 | /* Private variables ---------------------------------------------------------*/ | |
| 656 | /** @defgroup CEC_Private_Variables CEC Private Variables | |
| 657 | * @{ | |
| 658 | */ | |
| 659 | ||
| 660 | /** | |
| 661 | * @} | |
| 662 | */ | |
| 663 | ||
| 664 | /* Private constants ---------------------------------------------------------*/ | |
| 665 | /** @defgroup CEC_Private_Constants CEC Private Constants | |
| 666 | * @{ | |
| 667 | */ | |
| 668 | ||
| 669 | /** | |
| 670 | * @} | |
| 671 | */ | |
| 672 | ||
| 673 | /* Private macros ------------------------------------------------------------*/ | |
| 674 | /** @defgroup CEC_Private_Macros CEC Private Macros | |
| 675 | * @{ | |
| 676 | */ | |
| 677 | ||
| 678 | #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT) | |
| 679 | ||
| 680 | #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \ | |
| 681 | ((__RXTOL__) == CEC_EXTENDED_TOLERANCE)) | |
| 682 | ||
| 683 | #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \ | |
| 684 | ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) | |
| 685 | ||
| 686 | #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ | |
| 687 | ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION)) | |
| 688 | ||
| 689 | #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ | |
| 690 | ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) | |
| 691 | ||
| 692 | #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ | |
| 693 | ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) | |
| 694 | ||
| 695 | #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ | |
| 696 | ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) | |
| 697 | ||
| 698 | #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \ | |
| 699 | ((__MODE__) == CEC_FULL_LISTENING_MODE)) | |
| 700 | ||
| 701 | /** @brief Check CEC message size. | |
| 702 | * The message size is the payload size: without counting the header, | |
| 703 | * it varies from 0 byte (ping operation, one header only, no payload) to | |
| 704 | * 15 bytes (1 opcode and up to 14 operands following the header). | |
| 705 | * @param __SIZE__ CEC message size. | |
| 706 | * @retval Test result (TRUE or FALSE). | |
| 707 | */ | |
| 708 | #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) | |
| 709 | ||
| 710 | /** @brief Check CEC device Own Address Register (OAR) setting. | |
| 711 | * OAR address is written in a 15-bit field within CEC_CFGR register. | |
| 712 | * @param __ADDRESS__ CEC own address. | |
| 713 | * @retval Test result (TRUE or FALSE). | |
| 714 | */ | |
| 715 | #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) | |
| 716 | ||
| 717 | /** @brief Check CEC initiator or destination logical address setting. | |
| 718 | * Initiator and destination addresses are coded over 4 bits. | |
| 719 | * @param __ADDRESS__ CEC initiator or logical address. | |
| 720 | * @retval Test result (TRUE or FALSE). | |
| 721 | */ | |
| 722 | #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU) | |
| 723 | /** | |
| 724 | * @} | |
| 725 | */ | |
| 726 | /* Private functions ---------------------------------------------------------*/ | |
| 727 | /** @defgroup CEC_Private_Functions CEC Private Functions | |
| 728 | * @{ | |
| 729 | */ | |
| 730 | ||
| 731 | /** | |
| 732 | * @} | |
| 733 | */ | |
| 734 | ||
| 735 | /** | |
| 736 | * @} | |
| 737 | */ | |
| 738 | ||
| 739 | /** | |
| 740 | * @} | |
| 741 | */ | |
| 742 | ||
| 743 | #endif /* defined(STM32F042x6) || defined(STM32F048xx) || */ | |
| 744 | /* defined(STM32F051x8) || defined(STM32F058xx) || */ | |
| 745 | /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */ | |
| 746 | /* defined(STM32F091xC) || defined(STM32F098xx) */ | |
| 747 | #ifdef __cplusplus | |
| 748 | } | |
| 749 | #endif | |
| 750 | ||
| 751 | #endif /* __STM32F0xx_HAL_CEC_H */ | |
| 752 | ||
| 753 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ | |
