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483170	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_ll_i2c.h
	4	* @author MCD Application Team
	5	* @brief Header file of I2C LL module.
	6	******************************************************************************
	7	* @attention
	8	*
	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	10	*
	11	* Redistribution and use in source and binary forms, with or without modification,
	12	* are permitted provided that the following conditions are met:
	13	* 1. Redistributions of source code must retain the above copyright notice,
	14	* this list of conditions and the following disclaimer.
	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	19	* may be used to endorse or promote products derived from this software
	20	* without specific prior written permission.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	******************************************************************************
	34	*/
	35
	36	/* Define to prevent recursive inclusion -------------------------------------*/
	37	#ifndef __STM32F0xx_LL_I2C_H
	38	#define __STM32F0xx_LL_I2C_H
	39
	40	#ifdef __cplusplus
	41	extern "C" {
	42	#endif
	43
	44	/* Includes ------------------------------------------------------------------*/
	45	#include "stm32f0xx.h"
	46
	47	/** @addtogroup STM32F0xx_LL_Driver
	48	* @{
	49	*/
	50
	51	#if defined (I2C1) \|\| defined (I2C2)
	52
	53	/** @defgroup I2C_LL I2C
	54	* @{
	55	*/
	56
	57	/* Private types -------------------------------------------------------------*/
	58	/* Private variables ---------------------------------------------------------*/
	59
	60	/* Private constants ---------------------------------------------------------*/
	61	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
	62	* @{
	63	*/
	64	/**
	65	* @}
	66	*/
	67
	68	/* Private macros ------------------------------------------------------------*/
	69	#if defined(USE_FULL_LL_DRIVER)
	70	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
	71	* @{
	72	*/
	73	/**
	74	* @}
	75	*/
	76	#endif /USE_FULL_LL_DRIVER/
	77
	78	/* Exported types ------------------------------------------------------------*/
	79	#if defined(USE_FULL_LL_DRIVER)
	80	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
	81	* @{
	82	*/
	83	typedef struct
	84	{
	85	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
	86	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
	87
	88	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
	89
	90	uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
	91	This parameter must be set by referring to the STM32CubeMX Tool and
	92	the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
	93
	94	This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
	95
	96	uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
	97	This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
	98
	99	This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
	100
	101	uint32_t DigitalFilter; /*!< Configures the digital noise filter.
	102	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
	103
	104	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
	105
	106	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
	107	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
	108
	109	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
	110
	111	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
	112	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
	113
	114	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
	115
	116	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
	117	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
	118
	119	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
	120	} LL_I2C_InitTypeDef;
	121	/**
	122	* @}
	123	*/
	124	#endif /USE_FULL_LL_DRIVER/
	125
	126	/* Exported constants --------------------------------------------------------*/
	127	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
	128	* @{
	129	*/
	130
	131	/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
	132	* @brief Flags defines which can be used with LL_I2C_WriteReg function
	133	* @{
	134	*/
	135	#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /!< Address Matched flag /
	136	#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /!< Not Acknowledge flag /
	137	#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /!< Stop detection flag /
	138	#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /!< Bus error flag /
	139	#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /!< Arbitration Lost flag /
	140	#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /!< Overrun/Underrun flag /
	141	#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /!< PEC error flag /
	142	#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /!< Timeout detection flag /
	143	#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /!< Alert flag /
	144	/**
	145	* @}
	146	*/
	147
	148	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
	149	* @brief Flags defines which can be used with LL_I2C_ReadReg function
	150	* @{
	151	*/
	152	#define LL_I2C_ISR_TXE I2C_ISR_TXE /!< Transmit data register empty /
	153	#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /!< Transmit interrupt status /
	154	#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /!< Receive data register not empty /
	155	#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /!< Address matched (slave mode) /
	156	#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /!< Not Acknowledge received flag /
	157	#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /!< Stop detection flag /
	158	#define LL_I2C_ISR_TC I2C_ISR_TC /!< Transfer Complete (master mode) /
	159	#define LL_I2C_ISR_TCR I2C_ISR_TCR /!< Transfer Complete Reload /
	160	#define LL_I2C_ISR_BERR I2C_ISR_BERR /!< Bus error /
	161	#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /!< Arbitration lost /
	162	#define LL_I2C_ISR_OVR I2C_ISR_OVR /!< Overrun/Underrun (slave mode) /
	163	#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
	164	#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
	165	#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /!< SMBus alert (SMBus mode) /
	166	#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /!< Bus busy /
	167	/**
	168	* @}
	169	*/
	170
	171	/** @defgroup I2C_LL_EC_IT IT Defines
	172	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
	173	* @{
	174	*/
	175	#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /!< TX Interrupt enable /
	176	#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /!< RX Interrupt enable /
	177	#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /!< Address match Interrupt enable (slave only) /
	178	#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /!< Not acknowledge received Interrupt enable /
	179	#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /!< STOP detection Interrupt enable /
	180	#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /!< Transfer Complete interrupt enable /
	181	#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /!< Error interrupts enable /
	182	/**
	183	* @}
	184	*/
	185
	186	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
	187	* @{
	188	*/
	189	#define LL_I2C_MODE_I2C 0x00000000U /!< I2C Master or Slave mode /
	190	#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /!< SMBus Host address acknowledge /
	191	#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /!< SMBus Device default mode (Default address not acknowledge) /
	192	#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /!< SMBus Device Default address acknowledge /
	193	/**
	194	* @}
	195	*/
	196
	197	/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
	198	* @{
	199	*/
	200	#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /!< Analog filter is enabled. /
	201	#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /!< Analog filter is disabled. /
	202	/**
	203	* @}
	204	*/
	205
	206	/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
	207	* @{
	208	*/
	209	#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /!< Master operates in 7-bit addressing mode. /
	210	#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /!< Master operates in 10-bit addressing mode./
	211	/**
	212	* @}
	213	*/
	214
	215	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
	216	* @{
	217	*/
	218	#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /!< Own address 1 is a 7-bit address. /
	219	#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /!< Own address 1 is a 10-bit address./
	220	/**
	221	* @}
	222	*/
	223
	224	/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
	225	* @{
	226	*/
	227	#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /!< Own Address2 No mask. /
	228	#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /!< Only Address2 bits[7:2] are compared. /
	229	#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /!< Only Address2 bits[7:3] are compared. /
	230	#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /!< Only Address2 bits[7:4] are compared. /
	231	#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /!< Only Address2 bits[7:5] are compared. /
	232	#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /!< Only Address2 bits[7:6] are compared. /
	233	#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /!< Only Address2 bits[7] are compared. /
	234	#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /!< No comparison is done. All Address2 are acknowledged./
	235	/**
	236	* @}
	237	*/
	238
	239	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
	240	* @{
	241	*/
	242	#define LL_I2C_ACK 0x00000000U /!< ACK is sent after current received byte. /
	243	#define LL_I2C_NACK I2C_CR2_NACK /!< NACK is sent after current received byte./
	244	/**
	245	* @}
	246	*/
	247
	248	/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
	249	* @{
	250	*/
	251	#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /!< Slave Address in 7-bit. /
	252	#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /!< Slave Address in 10-bit./
	253	/**
	254	* @}
	255	*/
	256
	257	/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
	258	* @{
	259	*/
	260	#define LL_I2C_REQUEST_WRITE 0x00000000U /!< Master request a write transfer. /
	261	#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /!< Master request a read transfer. /
	262	/**
	263	* @}
	264	*/
	265
	266	/** @defgroup I2C_LL_EC_MODE Transfer End Mode
	267	* @{
	268	*/
	269	#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /!< Enable I2C Reload mode. /
	270	#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /!< Enable I2C Automatic end mode with no HW PEC comparison. /
	271	#define LL_I2C_MODE_SOFTEND 0x00000000U /!< Enable I2C Software end mode with no HW PEC comparison. /
	272	#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
	273	#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
	274	#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /!< Enable SMBUS Software end mode with HW PEC comparison. /
	275	#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
	276	#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Software end mode with HW PEC comparison. /
	277	/**
	278	* @}
	279	*/
	280
	281	/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
	282	* @{
	283	*/
	284	#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /!< Don't Generate Stop and Start condition. /
	285	#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /!< Generate Stop condition (Size should be set to 0). /
	286	#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Start for read request. /
	287	#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /!< Generate Start for write request. /
	288	#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Restart for read request, slave 7Bit address. /
	289	#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /!< Generate Restart for write request, slave 7Bit address. /
	290	#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN \| I2C_CR2_HEAD10R) /!< Generate Restart for read request, slave 10Bit address. /
	291	#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /!< Generate Restart for write request, slave 10Bit address./
	292	/**
	293	* @}
	294	*/
	295
	296	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
	297	* @{
	298	*/
	299	#define LL_I2C_DIRECTION_WRITE 0x00000000U /!< Write transfer request by master, slave enters receiver mode. /
	300	#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /!< Read transfer request by master, slave enters transmitter mode./
	301	/**
	302	* @}
	303	*/
	304
	305	/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
	306	* @{
	307	*/
	308	#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /!< Get address of data register used for transmission /
	309	#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /!< Get address of data register used for reception /
	310	/**
	311	* @}
	312	*/
	313
	314	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
	315	* @{
	316	*/
	317	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /!< TimeoutA is used to detect SCL low level timeout. /
	318	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /!< TimeoutA is used to detect both SCL and SDA high level timeout./
	319	/**
	320	* @}
	321	*/
	322
	323	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
	324	* @{
	325	*/
	326	#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /!< TimeoutA enable bit /
	327	#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /!< TimeoutB (extended clock) enable bit /
	328	#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN) /!< TimeoutA and TimeoutB (extended clock) enable bits /
	329	/**
	330	* @}
	331	*/
	332
	333	/**
	334	* @}
	335	*/
	336
	337	/* Exported macro ------------------------------------------------------------*/
	338	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
	339	* @{
	340	*/
	341
	342	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
	343	* @{
	344	*/
	345
	346	/**
	347	* @brief Write a value in I2C register
	348	* @param __INSTANCE__ I2C Instance
	349	* @param __REG__ Register to be written
	350	* @param __VALUE__ Value to be written in the register
	351	* @retval None
	352	*/
	353	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
	354
	355	/**
	356	* @brief Read a value in I2C register
	357	* @param __INSTANCE__ I2C Instance
	358	* @param __REG__ Register to be read
	359	* @retval Register value
	360	*/
	361	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
	362	/**
	363	* @}
	364	*/
	365
	366	/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
	367	* @{
	368	*/
	369	/**
	370	* @brief Configure the SDA setup, hold time and the SCL high, low period.
	371	* @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
	372	* @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
	373	* @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
	374	* @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
	375	* @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
	376	* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
	377	*/
	378	#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
	379	((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) \| \
	380	(((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) \| \
	381	(((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) \| \
	382	(((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) \| \
	383	(((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
	384	/**
	385	* @}
	386	*/
	387
	388	/**
	389	* @}
	390	*/
	391
	392	/* Exported functions --------------------------------------------------------*/
	393	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
	394	* @{
	395	*/
	396
	397	/** @defgroup I2C_LL_EF_Configuration Configuration
	398	* @{
	399	*/
	400
	401	/**
	402	* @brief Enable I2C peripheral (PE = 1).
	403	* @rmtoll CR1 PE LL_I2C_Enable
	404	* @param I2Cx I2C Instance.
	405	* @retval None
	406	*/
	407	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
	408	{
	409	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
	410	}
	411
	412	/**
	413	* @brief Disable I2C peripheral (PE = 0).
	414	* @note When PE = 0, the I2C SCL and SDA lines are released.
	415	* Internal state machines and status bits are put back to their reset value.
	416	* When cleared, PE must be kept low for at least 3 APB clock cycles.
	417	* @rmtoll CR1 PE LL_I2C_Disable
	418	* @param I2Cx I2C Instance.
	419	* @retval None
	420	*/
	421	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
	422	{
	423	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
	424	}
	425
	426	/**
	427	* @brief Check if the I2C peripheral is enabled or disabled.
	428	* @rmtoll CR1 PE LL_I2C_IsEnabled
	429	* @param I2Cx I2C Instance.
	430	* @retval State of bit (1 or 0).
	431	*/
	432	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
	433	{
	434	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
	435	}
	436
	437	/**
	438	* @brief Configure Noise Filters (Analog and Digital).
	439	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
	440	* The filters can only be programmed when the I2C is disabled (PE = 0).
	441	* @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
	442	* CR1 DNF LL_I2C_ConfigFilters
	443	* @param I2Cx I2C Instance.
	444	* @param AnalogFilter This parameter can be one of the following values:
	445	* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
	446	* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
	447	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
	448	* This parameter is used to configure the digital noise filter on SDA and SCL input.
	449	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
	450	* @retval None
	451	*/
	452	__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
	453	{
	454	MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF \| I2C_CR1_DNF, AnalogFilter \| (DigitalFilter << I2C_CR1_DNF_Pos));
	455	}
	456
	457	/**
	458	* @brief Configure Digital Noise Filter.
	459	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
	460	* This filter can only be programmed when the I2C is disabled (PE = 0).
	461	* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
	462	* @param I2Cx I2C Instance.
	463	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
	464	* This parameter is used to configure the digital noise filter on SDA and SCL input.
	465	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
	466	* @retval None
	467	*/
	468	__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
	469	{
	470	MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
	471	}
	472
	473	/**
	474	* @brief Get the current Digital Noise Filter configuration.
	475	* @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
	476	* @param I2Cx I2C Instance.
	477	* @retval Value between Min_Data=0x0 and Max_Data=0xF
	478	*/
	479	__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
	480	{
	481	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
	482	}
	483
	484	/**
	485	* @brief Enable Analog Noise Filter.
	486	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
	487	* @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
	488	* @param I2Cx I2C Instance.
	489	* @retval None
	490	*/
	491	__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
	492	{
	493	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
	494	}
	495
	496	/**
	497	* @brief Disable Analog Noise Filter.
	498	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
	499	* @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
	500	* @param I2Cx I2C Instance.
	501	* @retval None
	502	*/
	503	__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
	504	{
	505	SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
	506	}
	507
	508	/**
	509	* @brief Check if Analog Noise Filter is enabled or disabled.
	510	* @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
	511	* @param I2Cx I2C Instance.
	512	* @retval State of bit (1 or 0).
	513	*/
	514	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
	515	{
	516	return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
	517	}
	518
	519	/**
	520	* @brief Enable DMA transmission requests.
	521	* @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
	522	* @param I2Cx I2C Instance.
	523	* @retval None
	524	*/
	525	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
	526	{
	527	SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
	528	}
	529
	530	/**
	531	* @brief Disable DMA transmission requests.
	532	* @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
	533	* @param I2Cx I2C Instance.
	534	* @retval None
	535	*/
	536	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
	537	{
	538	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
	539	}
	540
	541	/**
	542	* @brief Check if DMA transmission requests are enabled or disabled.
	543	* @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
	544	* @param I2Cx I2C Instance.
	545	* @retval State of bit (1 or 0).
	546	*/
	547	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
	548	{
	549	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
	550	}
	551
	552	/**
	553	* @brief Enable DMA reception requests.
	554	* @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
	555	* @param I2Cx I2C Instance.
	556	* @retval None
	557	*/
	558	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
	559	{
	560	SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
	561	}
	562
	563	/**
	564	* @brief Disable DMA reception requests.
	565	* @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
	566	* @param I2Cx I2C Instance.
	567	* @retval None
	568	*/
	569	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
	570	{
	571	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
	572	}
	573
	574	/**
	575	* @brief Check if DMA reception requests are enabled or disabled.
	576	* @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
	577	* @param I2Cx I2C Instance.
	578	* @retval State of bit (1 or 0).
	579	*/
	580	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
	581	{
	582	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
	583	}
	584
	585	/**
	586	* @brief Get the data register address used for DMA transfer
	587	* @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
	588	* RXDR RXDATA LL_I2C_DMA_GetRegAddr
	589	* @param I2Cx I2C Instance
	590	* @param Direction This parameter can be one of the following values:
	591	* @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
	592	* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
	593	* @retval Address of data register
	594	*/
	595	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
	596	{
	597	register uint32_t data_reg_addr = 0U;
	598
	599	if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
	600	{
	601	/* return address of TXDR register */
	602	data_reg_addr = (uint32_t) & (I2Cx->TXDR);
	603	}
	604	else
	605	{
	606	/* return address of RXDR register */
	607	data_reg_addr = (uint32_t) & (I2Cx->RXDR);
	608	}
	609
	610	return data_reg_addr;
	611	}
	612
	613	/**
	614	* @brief Enable Clock stretching.
	615	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
	616	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
	617	* @param I2Cx I2C Instance.
	618	* @retval None
	619	*/
	620	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
	621	{
	622	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
	623	}
	624
	625	/**
	626	* @brief Disable Clock stretching.
	627	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
	628	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
	629	* @param I2Cx I2C Instance.
	630	* @retval None
	631	*/
	632	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
	633	{
	634	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
	635	}
	636
	637	/**
	638	* @brief Check if Clock stretching is enabled or disabled.
	639	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
	640	* @param I2Cx I2C Instance.
	641	* @retval State of bit (1 or 0).
	642	*/
	643	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
	644	{
	645	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
	646	}
	647
	648	/**
	649	* @brief Enable hardware byte control in slave mode.
	650	* @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
	651	* @param I2Cx I2C Instance.
	652	* @retval None
	653	*/
	654	__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
	655	{
	656	SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
	657	}
	658
	659	/**
	660	* @brief Disable hardware byte control in slave mode.
	661	* @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
	662	* @param I2Cx I2C Instance.
	663	* @retval None
	664	*/
	665	__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
	666	{
	667	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
	668	}
	669
	670	/**
	671	* @brief Check if hardware byte control in slave mode is enabled or disabled.
	672	* @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
	673	* @param I2Cx I2C Instance.
	674	* @retval State of bit (1 or 0).
	675	*/
	676	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
	677	{
	678	return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
	679	}
	680
	681	#if defined(I2C_CR1_WUPEN)
	682	/**
	683	* @brief Enable Wakeup from STOP.
	684	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
	685	* WakeUpFromStop feature is supported by the I2Cx Instance.
	686	* @note This bit can only be programmed when Digital Filter is disabled.
	687	* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
	688	* @param I2Cx I2C Instance.
	689	* @retval None
	690	*/
	691	__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
	692	{
	693	SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
	694	}
	695
	696	/**
	697	* @brief Disable Wakeup from STOP.
	698	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
	699	* WakeUpFromStop feature is supported by the I2Cx Instance.
	700	* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
	701	* @param I2Cx I2C Instance.
	702	* @retval None
	703	*/
	704	__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
	705	{
	706	CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
	707	}
	708
	709	/**
	710	* @brief Check if Wakeup from STOP is enabled or disabled.
	711	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
	712	* WakeUpFromStop feature is supported by the I2Cx Instance.
	713	* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
	714	* @param I2Cx I2C Instance.
	715	* @retval State of bit (1 or 0).
	716	*/
	717	__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
	718	{
	719	return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
	720	}
	721	#endif
	722
	723	/**
	724	* @brief Enable General Call.
	725	* @note When enabled the Address 0x00 is ACKed.
	726	* @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
	727	* @param I2Cx I2C Instance.
	728	* @retval None
	729	*/
	730	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
	731	{
	732	SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
	733	}
	734
	735	/**
	736	* @brief Disable General Call.
	737	* @note When disabled the Address 0x00 is NACKed.
	738	* @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
	739	* @param I2Cx I2C Instance.
	740	* @retval None
	741	*/
	742	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
	743	{
	744	CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
	745	}
	746
	747	/**
	748	* @brief Check if General Call is enabled or disabled.
	749	* @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
	750	* @param I2Cx I2C Instance.
	751	* @retval State of bit (1 or 0).
	752	*/
	753	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
	754	{
	755	return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
	756	}
	757
	758	/**
	759	* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
	760	* @note Changing this bit is not allowed, when the START bit is set.
	761	* @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
	762	* @param I2Cx I2C Instance.
	763	* @param AddressingMode This parameter can be one of the following values:
	764	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
	765	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
	766	* @retval None
	767	*/
	768	__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
	769	{
	770	MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
	771	}
	772
	773	/**
	774	* @brief Get the Master addressing mode.
	775	* @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
	776	* @param I2Cx I2C Instance.
	777	* @retval Returned value can be one of the following values:
	778	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
	779	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
	780	*/
	781	__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
	782	{
	783	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
	784	}
	785
	786	/**
	787	* @brief Set the Own Address1.
	788	* @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
	789	* OAR1 OA1MODE LL_I2C_SetOwnAddress1
	790	* @param I2Cx I2C Instance.
	791	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
	792	* @param OwnAddrSize This parameter can be one of the following values:
	793	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
	794	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
	795	* @retval None
	796	*/
	797	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
	798	{
	799	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 \| I2C_OAR1_OA1MODE, OwnAddress1 \| OwnAddrSize);
	800	}
	801
	802	/**
	803	* @brief Enable acknowledge on Own Address1 match address.
	804	* @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
	805	* @param I2Cx I2C Instance.
	806	* @retval None
	807	*/
	808	__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
	809	{
	810	SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
	811	}
	812
	813	/**
	814	* @brief Disable acknowledge on Own Address1 match address.
	815	* @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
	816	* @param I2Cx I2C Instance.
	817	* @retval None
	818	*/
	819	__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
	820	{
	821	CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
	822	}
	823
	824	/**
	825	* @brief Check if Own Address1 acknowledge is enabled or disabled.
	826	* @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
	827	* @param I2Cx I2C Instance.
	828	* @retval State of bit (1 or 0).
	829	*/
	830	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
	831	{
	832	return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
	833	}
	834
	835	/**
	836	* @brief Set the 7bits Own Address2.
	837	* @note This action has no effect if own address2 is enabled.
	838	* @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
	839	* OAR2 OA2MSK LL_I2C_SetOwnAddress2
	840	* @param I2Cx I2C Instance.
	841	* @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
	842	* @param OwnAddrMask This parameter can be one of the following values:
	843	* @arg @ref LL_I2C_OWNADDRESS2_NOMASK
	844	* @arg @ref LL_I2C_OWNADDRESS2_MASK01
	845	* @arg @ref LL_I2C_OWNADDRESS2_MASK02
	846	* @arg @ref LL_I2C_OWNADDRESS2_MASK03
	847	* @arg @ref LL_I2C_OWNADDRESS2_MASK04
	848	* @arg @ref LL_I2C_OWNADDRESS2_MASK05
	849	* @arg @ref LL_I2C_OWNADDRESS2_MASK06
	850	* @arg @ref LL_I2C_OWNADDRESS2_MASK07
	851	* @retval None
	852	*/
	853	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
	854	{
	855	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 \| I2C_OAR2_OA2MSK, OwnAddress2 \| OwnAddrMask);
	856	}
	857
	858	/**
	859	* @brief Enable acknowledge on Own Address2 match address.
	860	* @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
	861	* @param I2Cx I2C Instance.
	862	* @retval None
	863	*/
	864	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
	865	{
	866	SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
	867	}
	868
	869	/**
	870	* @brief Disable acknowledge on Own Address2 match address.
	871	* @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
	872	* @param I2Cx I2C Instance.
	873	* @retval None
	874	*/
	875	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
	876	{
	877	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
	878	}
	879
	880	/**
	881	* @brief Check if Own Address1 acknowledge is enabled or disabled.
	882	* @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
	883	* @param I2Cx I2C Instance.
	884	* @retval State of bit (1 or 0).
	885	*/
	886	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
	887	{
	888	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
	889	}
	890
	891	/**
	892	* @brief Configure the SDA setup, hold time and the SCL high, low period.
	893	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
	894	* @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
	895	* @param I2Cx I2C Instance.
	896	* @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
	897	* @note This parameter is computed with the STM32CubeMX Tool.
	898	* @retval None
	899	*/
	900	__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
	901	{
	902	WRITE_REG(I2Cx->TIMINGR, Timing);
	903	}
	904
	905	/**
	906	* @brief Get the Timing Prescaler setting.
	907	* @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
	908	* @param I2Cx I2C Instance.
	909	* @retval Value between Min_Data=0x0 and Max_Data=0xF
	910	*/
	911	__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
	912	{
	913	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
	914	}
	915
	916	/**
	917	* @brief Get the SCL low period setting.
	918	* @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
	919	* @param I2Cx I2C Instance.
	920	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
	921	*/
	922	__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
	923	{
	924	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
	925	}
	926
	927	/**
	928	* @brief Get the SCL high period setting.
	929	* @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
	930	* @param I2Cx I2C Instance.
	931	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
	932	*/
	933	__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
	934	{
	935	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
	936	}
	937
	938	/**
	939	* @brief Get the SDA hold time.
	940	* @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
	941	* @param I2Cx I2C Instance.
	942	* @retval Value between Min_Data=0x0 and Max_Data=0xF
	943	*/
	944	__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
	945	{
	946	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
	947	}
	948
	949	/**
	950	* @brief Get the SDA setup time.
	951	* @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
	952	* @param I2Cx I2C Instance.
	953	* @retval Value between Min_Data=0x0 and Max_Data=0xF
	954	*/
	955	__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
	956	{
	957	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
	958	}
	959
	960	/**
	961	* @brief Configure peripheral mode.
	962	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	963	* SMBus feature is supported by the I2Cx Instance.
	964	* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
	965	* CR1 SMBDEN LL_I2C_SetMode
	966	* @param I2Cx I2C Instance.
	967	* @param PeripheralMode This parameter can be one of the following values:
	968	* @arg @ref LL_I2C_MODE_I2C
	969	* @arg @ref LL_I2C_MODE_SMBUS_HOST
	970	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
	971	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
	972	* @retval None
	973	*/
	974	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
	975	{
	976	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN, PeripheralMode);
	977	}
	978
	979	/**
	980	* @brief Get peripheral mode.
	981	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	982	* SMBus feature is supported by the I2Cx Instance.
	983	* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
	984	* CR1 SMBDEN LL_I2C_GetMode
	985	* @param I2Cx I2C Instance.
	986	* @retval Returned value can be one of the following values:
	987	* @arg @ref LL_I2C_MODE_I2C
	988	* @arg @ref LL_I2C_MODE_SMBUS_HOST
	989	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
	990	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
	991	*/
	992	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
	993	{
	994	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN));
	995	}
	996
	997	/**
	998	* @brief Enable SMBus alert (Host or Device mode)
	999	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1000	* SMBus feature is supported by the I2Cx Instance.
	1001	* @note SMBus Device mode:
	1002	* - SMBus Alert pin is drived low and
	1003	* Alert Response Address Header acknowledge is enabled.
	1004	* SMBus Host mode:
	1005	* - SMBus Alert pin management is supported.
	1006	* @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
	1007	* @param I2Cx I2C Instance.
	1008	* @retval None
	1009	*/
	1010	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
	1011	{
	1012	SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
	1013	}
	1014
	1015	/**
	1016	* @brief Disable SMBus alert (Host or Device mode)
	1017	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1018	* SMBus feature is supported by the I2Cx Instance.
	1019	* @note SMBus Device mode:
	1020	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
	1021	* Alert Response Address Header acknowledge is disabled.
	1022	* SMBus Host mode:
	1023	* - SMBus Alert pin management is not supported.
	1024	* @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
	1025	* @param I2Cx I2C Instance.
	1026	* @retval None
	1027	*/
	1028	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
	1029	{
	1030	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
	1031	}
	1032
	1033	/**
	1034	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
	1035	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1036	* SMBus feature is supported by the I2Cx Instance.
	1037	* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
	1038	* @param I2Cx I2C Instance.
	1039	* @retval State of bit (1 or 0).
	1040	*/
	1041	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
	1042	{
	1043	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
	1044	}
	1045
	1046	/**
	1047	* @brief Enable SMBus Packet Error Calculation (PEC).
	1048	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1049	* SMBus feature is supported by the I2Cx Instance.
	1050	* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
	1051	* @param I2Cx I2C Instance.
	1052	* @retval None
	1053	*/
	1054	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
	1055	{
	1056	SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
	1057	}
	1058
	1059	/**
	1060	* @brief Disable SMBus Packet Error Calculation (PEC).
	1061	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1062	* SMBus feature is supported by the I2Cx Instance.
	1063	* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
	1064	* @param I2Cx I2C Instance.
	1065	* @retval None
	1066	*/
	1067	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
	1068	{
	1069	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
	1070	}
	1071
	1072	/**
	1073	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
	1074	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1075	* SMBus feature is supported by the I2Cx Instance.
	1076	* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
	1077	* @param I2Cx I2C Instance.
	1078	* @retval State of bit (1 or 0).
	1079	*/
	1080	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
	1081	{
	1082	return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
	1083	}
	1084
	1085	/**
	1086	* @brief Configure the SMBus Clock Timeout.
	1087	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1088	* SMBus feature is supported by the I2Cx Instance.
	1089	* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
	1090	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
	1091	* TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
	1092	* TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
	1093	* @param I2Cx I2C Instance.
	1094	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
	1095	* @param TimeoutAMode This parameter can be one of the following values:
	1096	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
	1097	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
	1098	* @param TimeoutB
	1099	* @retval None
	1100	*/
	1101	__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
	1102	uint32_t TimeoutB)
	1103	{
	1104	MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA \| I2C_TIMEOUTR_TIDLE \| I2C_TIMEOUTR_TIMEOUTB,
	1105	TimeoutA \| TimeoutAMode \| (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
	1106	}
	1107
	1108	/**
	1109	* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
	1110	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1111	* SMBus feature is supported by the I2Cx Instance.
	1112	* @note These bits can only be programmed when TimeoutA is disabled.
	1113	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
	1114	* @param I2Cx I2C Instance.
	1115	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
	1116	* @retval None
	1117	*/
	1118	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
	1119	{
	1120	WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
	1121	}
	1122
	1123	/**
	1124	* @brief Get the SMBus Clock TimeoutA setting.
	1125	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1126	* SMBus feature is supported by the I2Cx Instance.
	1127	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
	1128	* @param I2Cx I2C Instance.
	1129	* @retval Value between Min_Data=0 and Max_Data=0xFFF
	1130	*/
	1131	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
	1132	{
	1133	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
	1134	}
	1135
	1136	/**
	1137	* @brief Set the SMBus Clock TimeoutA mode.
	1138	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1139	* SMBus feature is supported by the I2Cx Instance.
	1140	* @note This bit can only be programmed when TimeoutA is disabled.
	1141	* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
	1142	* @param I2Cx I2C Instance.
	1143	* @param TimeoutAMode This parameter can be one of the following values:
	1144	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
	1145	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
	1146	* @retval None
	1147	*/
	1148	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
	1149	{
	1150	WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
	1151	}
	1152
	1153	/**
	1154	* @brief Get the SMBus Clock TimeoutA mode.
	1155	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1156	* SMBus feature is supported by the I2Cx Instance.
	1157	* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
	1158	* @param I2Cx I2C Instance.
	1159	* @retval Returned value can be one of the following values:
	1160	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
	1161	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
	1162	*/
	1163	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
	1164	{
	1165	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
	1166	}
	1167
	1168	/**
	1169	* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
	1170	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1171	* SMBus feature is supported by the I2Cx Instance.
	1172	* @note These bits can only be programmed when TimeoutB is disabled.
	1173	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
	1174	* @param I2Cx I2C Instance.
	1175	* @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
	1176	* @retval None
	1177	*/
	1178	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
	1179	{
	1180	WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
	1181	}
	1182
	1183	/**
	1184	* @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
	1185	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1186	* SMBus feature is supported by the I2Cx Instance.
	1187	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
	1188	* @param I2Cx I2C Instance.
	1189	* @retval Value between Min_Data=0 and Max_Data=0xFFF
	1190	*/
	1191	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
	1192	{
	1193	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
	1194	}
	1195
	1196	/**
	1197	* @brief Enable the SMBus Clock Timeout.
	1198	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1199	* SMBus feature is supported by the I2Cx Instance.
	1200	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
	1201	* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
	1202	* @param I2Cx I2C Instance.
	1203	* @param ClockTimeout This parameter can be one of the following values:
	1204	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
	1205	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
	1206	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
	1207	* @retval None
	1208	*/
	1209	__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
	1210	{
	1211	SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
	1212	}
	1213
	1214	/**
	1215	* @brief Disable the SMBus Clock Timeout.
	1216	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1217	* SMBus feature is supported by the I2Cx Instance.
	1218	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
	1219	* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
	1220	* @param I2Cx I2C Instance.
	1221	* @param ClockTimeout This parameter can be one of the following values:
	1222	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
	1223	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
	1224	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
	1225	* @retval None
	1226	*/
	1227	__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
	1228	{
	1229	CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
	1230	}
	1231
	1232	/**
	1233	* @brief Check if the SMBus Clock Timeout is enabled or disabled.
	1234	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1235	* SMBus feature is supported by the I2Cx Instance.
	1236	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
	1237	* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
	1238	* @param I2Cx I2C Instance.
	1239	* @param ClockTimeout This parameter can be one of the following values:
	1240	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
	1241	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
	1242	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
	1243	* @retval State of bit (1 or 0).
	1244	*/
	1245	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
	1246	{
	1247	return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
	1248	}
	1249
	1250	/**
	1251	* @}
	1252	*/
	1253
	1254	/** @defgroup I2C_LL_EF_IT_Management IT_Management
	1255	* @{
	1256	*/
	1257
	1258	/**
	1259	* @brief Enable TXIS interrupt.
	1260	* @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
	1261	* @param I2Cx I2C Instance.
	1262	* @retval None
	1263	*/
	1264	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
	1265	{
	1266	SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
	1267	}
	1268
	1269	/**
	1270	* @brief Disable TXIS interrupt.
	1271	* @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
	1272	* @param I2Cx I2C Instance.
	1273	* @retval None
	1274	*/
	1275	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
	1276	{
	1277	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
	1278	}
	1279
	1280	/**
	1281	* @brief Check if the TXIS Interrupt is enabled or disabled.
	1282	* @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
	1283	* @param I2Cx I2C Instance.
	1284	* @retval State of bit (1 or 0).
	1285	*/
	1286	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
	1287	{
	1288	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
	1289	}
	1290
	1291	/**
	1292	* @brief Enable RXNE interrupt.
	1293	* @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
	1294	* @param I2Cx I2C Instance.
	1295	* @retval None
	1296	*/
	1297	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
	1298	{
	1299	SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
	1300	}
	1301
	1302	/**
	1303	* @brief Disable RXNE interrupt.
	1304	* @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
	1305	* @param I2Cx I2C Instance.
	1306	* @retval None
	1307	*/
	1308	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
	1309	{
	1310	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
	1311	}
	1312
	1313	/**
	1314	* @brief Check if the RXNE Interrupt is enabled or disabled.
	1315	* @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
	1316	* @param I2Cx I2C Instance.
	1317	* @retval State of bit (1 or 0).
	1318	*/
	1319	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
	1320	{
	1321	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
	1322	}
	1323
	1324	/**
	1325	* @brief Enable Address match interrupt (slave mode only).
	1326	* @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
	1327	* @param I2Cx I2C Instance.
	1328	* @retval None
	1329	*/
	1330	__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
	1331	{
	1332	SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
	1333	}
	1334
	1335	/**
	1336	* @brief Disable Address match interrupt (slave mode only).
	1337	* @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
	1338	* @param I2Cx I2C Instance.
	1339	* @retval None
	1340	*/
	1341	__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
	1342	{
	1343	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
	1344	}
	1345
	1346	/**
	1347	* @brief Check if Address match interrupt is enabled or disabled.
	1348	* @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
	1349	* @param I2Cx I2C Instance.
	1350	* @retval State of bit (1 or 0).
	1351	*/
	1352	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
	1353	{
	1354	return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
	1355	}
	1356
	1357	/**
	1358	* @brief Enable Not acknowledge received interrupt.
	1359	* @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
	1360	* @param I2Cx I2C Instance.
	1361	* @retval None
	1362	*/
	1363	__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
	1364	{
	1365	SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
	1366	}
	1367
	1368	/**
	1369	* @brief Disable Not acknowledge received interrupt.
	1370	* @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
	1371	* @param I2Cx I2C Instance.
	1372	* @retval None
	1373	*/
	1374	__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
	1375	{
	1376	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
	1377	}
	1378
	1379	/**
	1380	* @brief Check if Not acknowledge received interrupt is enabled or disabled.
	1381	* @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
	1382	* @param I2Cx I2C Instance.
	1383	* @retval State of bit (1 or 0).
	1384	*/
	1385	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
	1386	{
	1387	return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
	1388	}
	1389
	1390	/**
	1391	* @brief Enable STOP detection interrupt.
	1392	* @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
	1393	* @param I2Cx I2C Instance.
	1394	* @retval None
	1395	*/
	1396	__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
	1397	{
	1398	SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
	1399	}
	1400
	1401	/**
	1402	* @brief Disable STOP detection interrupt.
	1403	* @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
	1404	* @param I2Cx I2C Instance.
	1405	* @retval None
	1406	*/
	1407	__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
	1408	{
	1409	CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
	1410	}
	1411
	1412	/**
	1413	* @brief Check if STOP detection interrupt is enabled or disabled.
	1414	* @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
	1415	* @param I2Cx I2C Instance.
	1416	* @retval State of bit (1 or 0).
	1417	*/
	1418	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
	1419	{
	1420	return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
	1421	}
	1422
	1423	/**
	1424	* @brief Enable Transfer Complete interrupt.
	1425	* @note Any of these events will generate interrupt :
	1426	* Transfer Complete (TC)
	1427	* Transfer Complete Reload (TCR)
	1428	* @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
	1429	* @param I2Cx I2C Instance.
	1430	* @retval None
	1431	*/
	1432	__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
	1433	{
	1434	SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
	1435	}
	1436
	1437	/**
	1438	* @brief Disable Transfer Complete interrupt.
	1439	* @note Any of these events will generate interrupt :
	1440	* Transfer Complete (TC)
	1441	* Transfer Complete Reload (TCR)
	1442	* @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
	1443	* @param I2Cx I2C Instance.
	1444	* @retval None
	1445	*/
	1446	__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
	1447	{
	1448	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
	1449	}
	1450
	1451	/**
	1452	* @brief Check if Transfer Complete interrupt is enabled or disabled.
	1453	* @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
	1454	* @param I2Cx I2C Instance.
	1455	* @retval State of bit (1 or 0).
	1456	*/
	1457	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
	1458	{
	1459	return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
	1460	}
	1461
	1462	/**
	1463	* @brief Enable Error interrupts.
	1464	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1465	* SMBus feature is supported by the I2Cx Instance.
	1466	* @note Any of these errors will generate interrupt :
	1467	* Arbitration Loss (ARLO)
	1468	* Bus Error detection (BERR)
	1469	* Overrun/Underrun (OVR)
	1470	* SMBus Timeout detection (TIMEOUT)
	1471	* SMBus PEC error detection (PECERR)
	1472	* SMBus Alert pin event detection (ALERT)
	1473	* @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
	1474	* @param I2Cx I2C Instance.
	1475	* @retval None
	1476	*/
	1477	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
	1478	{
	1479	SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
	1480	}
	1481
	1482	/**
	1483	* @brief Disable Error interrupts.
	1484	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1485	* SMBus feature is supported by the I2Cx Instance.
	1486	* @note Any of these errors will generate interrupt :
	1487	* Arbitration Loss (ARLO)
	1488	* Bus Error detection (BERR)
	1489	* Overrun/Underrun (OVR)
	1490	* SMBus Timeout detection (TIMEOUT)
	1491	* SMBus PEC error detection (PECERR)
	1492	* SMBus Alert pin event detection (ALERT)
	1493	* @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
	1494	* @param I2Cx I2C Instance.
	1495	* @retval None
	1496	*/
	1497	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
	1498	{
	1499	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
	1500	}
	1501
	1502	/**
	1503	* @brief Check if Error interrupts are enabled or disabled.
	1504	* @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
	1505	* @param I2Cx I2C Instance.
	1506	* @retval State of bit (1 or 0).
	1507	*/
	1508	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
	1509	{
	1510	return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
	1511	}
	1512
	1513	/**
	1514	* @}
	1515	*/
	1516
	1517	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
	1518	* @{
	1519	*/
	1520
	1521	/**
	1522	* @brief Indicate the status of Transmit data register empty flag.
	1523	* @note RESET: When next data is written in Transmit data register.
	1524	* SET: When Transmit data register is empty.
	1525	* @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
	1526	* @param I2Cx I2C Instance.
	1527	* @retval State of bit (1 or 0).
	1528	*/
	1529	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
	1530	{
	1531	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
	1532	}
	1533
	1534	/**
	1535	* @brief Indicate the status of Transmit interrupt flag.
	1536	* @note RESET: When next data is written in Transmit data register.
	1537	* SET: When Transmit data register is empty.
	1538	* @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
	1539	* @param I2Cx I2C Instance.
	1540	* @retval State of bit (1 or 0).
	1541	*/
	1542	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
	1543	{
	1544	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
	1545	}
	1546
	1547	/**
	1548	* @brief Indicate the status of Receive data register not empty flag.
	1549	* @note RESET: When Receive data register is read.
	1550	* SET: When the received data is copied in Receive data register.
	1551	* @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
	1552	* @param I2Cx I2C Instance.
	1553	* @retval State of bit (1 or 0).
	1554	*/
	1555	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
	1556	{
	1557	return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
	1558	}
	1559
	1560	/**
	1561	* @brief Indicate the status of Address matched flag (slave mode).
	1562	* @note RESET: Clear default value.
	1563	* SET: When the received slave address matched with one of the enabled slave address.
	1564	* @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
	1565	* @param I2Cx I2C Instance.
	1566	* @retval State of bit (1 or 0).
	1567	*/
	1568	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
	1569	{
	1570	return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
	1571	}
	1572
	1573	/**
	1574	* @brief Indicate the status of Not Acknowledge received flag.
	1575	* @note RESET: Clear default value.
	1576	* SET: When a NACK is received after a byte transmission.
	1577	* @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
	1578	* @param I2Cx I2C Instance.
	1579	* @retval State of bit (1 or 0).
	1580	*/
	1581	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
	1582	{
	1583	return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
	1584	}
	1585
	1586	/**
	1587	* @brief Indicate the status of Stop detection flag.
	1588	* @note RESET: Clear default value.
	1589	* SET: When a Stop condition is detected.
	1590	* @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
	1591	* @param I2Cx I2C Instance.
	1592	* @retval State of bit (1 or 0).
	1593	*/
	1594	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
	1595	{
	1596	return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
	1597	}
	1598
	1599	/**
	1600	* @brief Indicate the status of Transfer complete flag (master mode).
	1601	* @note RESET: Clear default value.
	1602	* SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
	1603	* @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
	1604	* @param I2Cx I2C Instance.
	1605	* @retval State of bit (1 or 0).
	1606	*/
	1607	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
	1608	{
	1609	return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
	1610	}
	1611
	1612	/**
	1613	* @brief Indicate the status of Transfer complete flag (master mode).
	1614	* @note RESET: Clear default value.
	1615	* SET: When RELOAD=1 and NBYTES date have been transferred.
	1616	* @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
	1617	* @param I2Cx I2C Instance.
	1618	* @retval State of bit (1 or 0).
	1619	*/
	1620	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
	1621	{
	1622	return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
	1623	}
	1624
	1625	/**
	1626	* @brief Indicate the status of Bus error flag.
	1627	* @note RESET: Clear default value.
	1628	* SET: When a misplaced Start or Stop condition is detected.
	1629	* @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
	1630	* @param I2Cx I2C Instance.
	1631	* @retval State of bit (1 or 0).
	1632	*/
	1633	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
	1634	{
	1635	return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
	1636	}
	1637
	1638	/**
	1639	* @brief Indicate the status of Arbitration lost flag.
	1640	* @note RESET: Clear default value.
	1641	* SET: When arbitration lost.
	1642	* @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
	1643	* @param I2Cx I2C Instance.
	1644	* @retval State of bit (1 or 0).
	1645	*/
	1646	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
	1647	{
	1648	return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
	1649	}
	1650
	1651	/**
	1652	* @brief Indicate the status of Overrun/Underrun flag (slave mode).
	1653	* @note RESET: Clear default value.
	1654	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
	1655	* @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
	1656	* @param I2Cx I2C Instance.
	1657	* @retval State of bit (1 or 0).
	1658	*/
	1659	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
	1660	{
	1661	return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
	1662	}
	1663
	1664	/**
	1665	* @brief Indicate the status of SMBus PEC error flag in reception.
	1666	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1667	* SMBus feature is supported by the I2Cx Instance.
	1668	* @note RESET: Clear default value.
	1669	* SET: When the received PEC does not match with the PEC register content.
	1670	* @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
	1671	* @param I2Cx I2C Instance.
	1672	* @retval State of bit (1 or 0).
	1673	*/
	1674	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
	1675	{
	1676	return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
	1677	}
	1678
	1679	/**
	1680	* @brief Indicate the status of SMBus Timeout detection flag.
	1681	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1682	* SMBus feature is supported by the I2Cx Instance.
	1683	* @note RESET: Clear default value.
	1684	* SET: When a timeout or extended clock timeout occurs.
	1685	* @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
	1686	* @param I2Cx I2C Instance.
	1687	* @retval State of bit (1 or 0).
	1688	*/
	1689	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
	1690	{
	1691	return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
	1692	}
	1693
	1694	/**
	1695	* @brief Indicate the status of SMBus alert flag.
	1696	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1697	* SMBus feature is supported by the I2Cx Instance.
	1698	* @note RESET: Clear default value.
	1699	* SET: When SMBus host configuration, SMBus alert enabled and
	1700	* a falling edge event occurs on SMBA pin.
	1701	* @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
	1702	* @param I2Cx I2C Instance.
	1703	* @retval State of bit (1 or 0).
	1704	*/
	1705	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
	1706	{
	1707	return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
	1708	}
	1709
	1710	/**
	1711	* @brief Indicate the status of Bus Busy flag.
	1712	* @note RESET: Clear default value.
	1713	* SET: When a Start condition is detected.
	1714	* @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
	1715	* @param I2Cx I2C Instance.
	1716	* @retval State of bit (1 or 0).
	1717	*/
	1718	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
	1719	{
	1720	return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
	1721	}
	1722
	1723	/**
	1724	* @brief Clear Address Matched flag.
	1725	* @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
	1726	* @param I2Cx I2C Instance.
	1727	* @retval None
	1728	*/
	1729	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
	1730	{
	1731	SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
	1732	}
	1733
	1734	/**
	1735	* @brief Clear Not Acknowledge flag.
	1736	* @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
	1737	* @param I2Cx I2C Instance.
	1738	* @retval None
	1739	*/
	1740	__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
	1741	{
	1742	SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
	1743	}
	1744
	1745	/**
	1746	* @brief Clear Stop detection flag.
	1747	* @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
	1748	* @param I2Cx I2C Instance.
	1749	* @retval None
	1750	*/
	1751	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
	1752	{
	1753	SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
	1754	}
	1755
	1756	/**
	1757	* @brief Clear Transmit data register empty flag (TXE).
	1758	* @note This bit can be clear by software in order to flush the transmit data register (TXDR).
	1759	* @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
	1760	* @param I2Cx I2C Instance.
	1761	* @retval None
	1762	*/
	1763	__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
	1764	{
	1765	WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
	1766	}
	1767
	1768	/**
	1769	* @brief Clear Bus error flag.
	1770	* @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
	1771	* @param I2Cx I2C Instance.
	1772	* @retval None
	1773	*/
	1774	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
	1775	{
	1776	SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
	1777	}
	1778
	1779	/**
	1780	* @brief Clear Arbitration lost flag.
	1781	* @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
	1782	* @param I2Cx I2C Instance.
	1783	* @retval None
	1784	*/
	1785	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
	1786	{
	1787	SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
	1788	}
	1789
	1790	/**
	1791	* @brief Clear Overrun/Underrun flag.
	1792	* @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
	1793	* @param I2Cx I2C Instance.
	1794	* @retval None
	1795	*/
	1796	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
	1797	{
	1798	SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
	1799	}
	1800
	1801	/**
	1802	* @brief Clear SMBus PEC error flag.
	1803	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1804	* SMBus feature is supported by the I2Cx Instance.
	1805	* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
	1806	* @param I2Cx I2C Instance.
	1807	* @retval None
	1808	*/
	1809	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
	1810	{
	1811	SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
	1812	}
	1813
	1814	/**
	1815	* @brief Clear SMBus Timeout detection flag.
	1816	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1817	* SMBus feature is supported by the I2Cx Instance.
	1818	* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
	1819	* @param I2Cx I2C Instance.
	1820	* @retval None
	1821	*/
	1822	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
	1823	{
	1824	SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
	1825	}
	1826
	1827	/**
	1828	* @brief Clear SMBus Alert flag.
	1829	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	1830	* SMBus feature is supported by the I2Cx Instance.
	1831	* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
	1832	* @param I2Cx I2C Instance.
	1833	* @retval None
	1834	*/
	1835	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
	1836	{
	1837	SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
	1838	}
	1839
	1840	/**
	1841	* @}
	1842	*/
	1843
	1844	/** @defgroup I2C_LL_EF_Data_Management Data_Management
	1845	* @{
	1846	*/
	1847
	1848	/**
	1849	* @brief Enable automatic STOP condition generation (master mode).
	1850	* @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
	1851	* This bit has no effect in slave mode or when RELOAD bit is set.
	1852	* @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
	1853	* @param I2Cx I2C Instance.
	1854	* @retval None
	1855	*/
	1856	__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
	1857	{
	1858	SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
	1859	}
	1860
	1861	/**
	1862	* @brief Disable automatic STOP condition generation (master mode).
	1863	* @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
	1864	* @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
	1865	* @param I2Cx I2C Instance.
	1866	* @retval None
	1867	*/
	1868	__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
	1869	{
	1870	CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
	1871	}
	1872
	1873	/**
	1874	* @brief Check if automatic STOP condition is enabled or disabled.
	1875	* @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
	1876	* @param I2Cx I2C Instance.
	1877	* @retval State of bit (1 or 0).
	1878	*/
	1879	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
	1880	{
	1881	return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
	1882	}
	1883
	1884	/**
	1885	* @brief Enable reload mode (master mode).
	1886	* @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
	1887	* @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
	1888	* @param I2Cx I2C Instance.
	1889	* @retval None
	1890	*/
	1891	__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
	1892	{
	1893	SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
	1894	}
	1895
	1896	/**
	1897	* @brief Disable reload mode (master mode).
	1898	* @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
	1899	* @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
	1900	* @param I2Cx I2C Instance.
	1901	* @retval None
	1902	*/
	1903	__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
	1904	{
	1905	CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
	1906	}
	1907
	1908	/**
	1909	* @brief Check if reload mode is enabled or disabled.
	1910	* @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
	1911	* @param I2Cx I2C Instance.
	1912	* @retval State of bit (1 or 0).
	1913	*/
	1914	__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
	1915	{
	1916	return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
	1917	}
	1918
	1919	/**
	1920	* @brief Configure the number of bytes for transfer.
	1921	* @note Changing these bits when START bit is set is not allowed.
	1922	* @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
	1923	* @param I2Cx I2C Instance.
	1924	* @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
	1925	* @retval None
	1926	*/
	1927	__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
	1928	{
	1929	MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
	1930	}
	1931
	1932	/**
	1933	* @brief Get the number of bytes configured for transfer.
	1934	* @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
	1935	* @param I2Cx I2C Instance.
	1936	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
	1937	*/
	1938	__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
	1939	{
	1940	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
	1941	}
	1942
	1943	/**
	1944	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
	1945	* @note Usage in Slave mode only.
	1946	* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
	1947	* @param I2Cx I2C Instance.
	1948	* @param TypeAcknowledge This parameter can be one of the following values:
	1949	* @arg @ref LL_I2C_ACK
	1950	* @arg @ref LL_I2C_NACK
	1951	* @retval None
	1952	*/
	1953	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
	1954	{
	1955	MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
	1956	}
	1957
	1958	/**
	1959	* @brief Generate a START or RESTART condition
	1960	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
	1961	* This action has no effect when RELOAD is set.
	1962	* @rmtoll CR2 START LL_I2C_GenerateStartCondition
	1963	* @param I2Cx I2C Instance.
	1964	* @retval None
	1965	*/
	1966	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
	1967	{
	1968	SET_BIT(I2Cx->CR2, I2C_CR2_START);
	1969	}
	1970
	1971	/**
	1972	* @brief Generate a STOP condition after the current byte transfer (master mode).
	1973	* @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
	1974	* @param I2Cx I2C Instance.
	1975	* @retval None
	1976	*/
	1977	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
	1978	{
	1979	SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
	1980	}
	1981
	1982	/**
	1983	* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
	1984	* @note The master sends the complete 10bit slave address read sequence :
	1985	* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
	1986	* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
	1987	* @param I2Cx I2C Instance.
	1988	* @retval None
	1989	*/
	1990	__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
	1991	{
	1992	CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
	1993	}
	1994
	1995	/**
	1996	* @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
	1997	* @note The master only sends the first 7 bits of 10bit address in Read direction.
	1998	* @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
	1999	* @param I2Cx I2C Instance.
	2000	* @retval None
	2001	*/
	2002	__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
	2003	{
	2004	SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
	2005	}
	2006
	2007	/**
	2008	* @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
	2009	* @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
	2010	* @param I2Cx I2C Instance.
	2011	* @retval State of bit (1 or 0).
	2012	*/
	2013	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
	2014	{
	2015	return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
	2016	}
	2017
	2018	/**
	2019	* @brief Configure the transfer direction (master mode).
	2020	* @note Changing these bits when START bit is set is not allowed.
	2021	* @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
	2022	* @param I2Cx I2C Instance.
	2023	* @param TransferRequest This parameter can be one of the following values:
	2024	* @arg @ref LL_I2C_REQUEST_WRITE
	2025	* @arg @ref LL_I2C_REQUEST_READ
	2026	* @retval None
	2027	*/
	2028	__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
	2029	{
	2030	MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
	2031	}
	2032
	2033	/**
	2034	* @brief Get the transfer direction requested (master mode).
	2035	* @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
	2036	* @param I2Cx I2C Instance.
	2037	* @retval Returned value can be one of the following values:
	2038	* @arg @ref LL_I2C_REQUEST_WRITE
	2039	* @arg @ref LL_I2C_REQUEST_READ
	2040	*/
	2041	__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
	2042	{
	2043	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
	2044	}
	2045
	2046	/**
	2047	* @brief Configure the slave address for transfer (master mode).
	2048	* @note Changing these bits when START bit is set is not allowed.
	2049	* @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
	2050	* @param I2Cx I2C Instance.
	2051	* @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
	2052	* @retval None
	2053	*/
	2054	__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
	2055	{
	2056	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
	2057	}
	2058
	2059	/**
	2060	* @brief Get the slave address programmed for transfer.
	2061	* @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
	2062	* @param I2Cx I2C Instance.
	2063	* @retval Value between Min_Data=0x0 and Max_Data=0x3F
	2064	*/
	2065	__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
	2066	{
	2067	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
	2068	}
	2069
	2070	/**
	2071	* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
	2072	* @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
	2073	* CR2 ADD10 LL_I2C_HandleTransfer\n
	2074	* CR2 RD_WRN LL_I2C_HandleTransfer\n
	2075	* CR2 START LL_I2C_HandleTransfer\n
	2076	* CR2 STOP LL_I2C_HandleTransfer\n
	2077	* CR2 RELOAD LL_I2C_HandleTransfer\n
	2078	* CR2 NBYTES LL_I2C_HandleTransfer\n
	2079	* CR2 AUTOEND LL_I2C_HandleTransfer\n
	2080	* CR2 HEAD10R LL_I2C_HandleTransfer
	2081	* @param I2Cx I2C Instance.
	2082	* @param SlaveAddr Specifies the slave address to be programmed.
	2083	* @param SlaveAddrSize This parameter can be one of the following values:
	2084	* @arg @ref LL_I2C_ADDRSLAVE_7BIT
	2085	* @arg @ref LL_I2C_ADDRSLAVE_10BIT
	2086	* @param TransferSize Specifies the number of bytes to be programmed.
	2087	* This parameter must be a value between Min_Data=0 and Max_Data=255.
	2088	* @param EndMode This parameter can be one of the following values:
	2089	* @arg @ref LL_I2C_MODE_RELOAD
	2090	* @arg @ref LL_I2C_MODE_AUTOEND
	2091	* @arg @ref LL_I2C_MODE_SOFTEND
	2092	* @arg @ref LL_I2C_MODE_SMBUS_RELOAD
	2093	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
	2094	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
	2095	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
	2096	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
	2097	* @param Request This parameter can be one of the following values:
	2098	* @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
	2099	* @arg @ref LL_I2C_GENERATE_STOP
	2100	* @arg @ref LL_I2C_GENERATE_START_READ
	2101	* @arg @ref LL_I2C_GENERATE_START_WRITE
	2102	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
	2103	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
	2104	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
	2105	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
	2106	* @retval None
	2107	*/
	2108	__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
	2109	uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
	2110	{
	2111	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD \| I2C_CR2_ADD10 \| I2C_CR2_RD_WRN \| I2C_CR2_START \| I2C_CR2_STOP \| I2C_CR2_RELOAD \|
	2112	I2C_CR2_NBYTES \| I2C_CR2_AUTOEND \| I2C_CR2_HEAD10R,
	2113	SlaveAddr \| SlaveAddrSize \| TransferSize << I2C_CR2_NBYTES_Pos \| EndMode \| Request);
	2114	}
	2115
	2116	/**
	2117	* @brief Indicate the value of transfer direction (slave mode).
	2118	* @note RESET: Write transfer, Slave enters in receiver mode.
	2119	* SET: Read transfer, Slave enters in transmitter mode.
	2120	* @rmtoll ISR DIR LL_I2C_GetTransferDirection
	2121	* @param I2Cx I2C Instance.
	2122	* @retval Returned value can be one of the following values:
	2123	* @arg @ref LL_I2C_DIRECTION_WRITE
	2124	* @arg @ref LL_I2C_DIRECTION_READ
	2125	*/
	2126	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
	2127	{
	2128	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
	2129	}
	2130
	2131	/**
	2132	* @brief Return the slave matched address.
	2133	* @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
	2134	* @param I2Cx I2C Instance.
	2135	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
	2136	*/
	2137	__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
	2138	{
	2139	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
	2140	}
	2141
	2142	/**
	2143	* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
	2144	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	2145	* SMBus feature is supported by the I2Cx Instance.
	2146	* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
	2147	* This bit has no effect when RELOAD bit is set.
	2148	* This bit has no effect in device mode when SBC bit is not set.
	2149	* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
	2150	* @param I2Cx I2C Instance.
	2151	* @retval None
	2152	*/
	2153	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
	2154	{
	2155	SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
	2156	}
	2157
	2158	/**
	2159	* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
	2160	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	2161	* SMBus feature is supported by the I2Cx Instance.
	2162	* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
	2163	* @param I2Cx I2C Instance.
	2164	* @retval State of bit (1 or 0).
	2165	*/
	2166	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
	2167	{
	2168	return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
	2169	}
	2170
	2171	/**
	2172	* @brief Get the SMBus Packet Error byte calculated.
	2173	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
	2174	* SMBus feature is supported by the I2Cx Instance.
	2175	* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
	2176	* @param I2Cx I2C Instance.
	2177	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
	2178	*/
	2179	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
	2180	{
	2181	return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
	2182	}
	2183
	2184	/**
	2185	* @brief Read Receive Data register.
	2186	* @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
	2187	* @param I2Cx I2C Instance.
	2188	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
	2189	*/
	2190	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
	2191	{
	2192	return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
	2193	}
	2194
	2195	/**
	2196	* @brief Write in Transmit Data Register .
	2197	* @rmtoll TXDR TXDATA LL_I2C_TransmitData8
	2198	* @param I2Cx I2C Instance.
	2199	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
	2200	* @retval None
	2201	*/
	2202	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
	2203	{
	2204	WRITE_REG(I2Cx->TXDR, Data);
	2205	}
	2206
	2207	/**
	2208	* @}
	2209	*/
	2210
	2211	#if defined(USE_FULL_LL_DRIVER)
	2212	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
	2213	* @{
	2214	*/
	2215
	2216	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
	2217	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
	2218	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
	2219
	2220
	2221	/**
	2222	* @}
	2223	*/
	2224	#endif /* USE_FULL_LL_DRIVER */
	2225
	2226	/**
	2227	* @}
	2228	*/
	2229
	2230	/**
	2231	* @}
	2232	*/
	2233
	2234	#endif /* I2C1 \|\| I2C2 */
	2235
	2236	/**
	2237	* @}
	2238	*/
	2239
	2240	#ifdef __cplusplus
	2241	}
	2242	#endif
	2243
	2244	#endif /* __STM32F0xx_LL_I2C_H */
	2245
	2246	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/