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483170	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_ll_dma.h
	4	* @author MCD Application Team
	5	* @brief Header file of DMA LL module.
	6	******************************************************************************
	7	* @attention
	8	*
	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	10	*
	11	* Redistribution and use in source and binary forms, with or without modification,
	12	* are permitted provided that the following conditions are met:
	13	* 1. Redistributions of source code must retain the above copyright notice,
	14	* this list of conditions and the following disclaimer.
	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	19	* may be used to endorse or promote products derived from this software
	20	* without specific prior written permission.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	******************************************************************************
	34	*/
	35
	36	/* Define to prevent recursive inclusion -------------------------------------*/
	37	#ifndef __STM32F0xx_LL_DMA_H
	38	#define __STM32F0xx_LL_DMA_H
	39
	40	#ifdef __cplusplus
	41	extern "C" {
	42	#endif
	43
	44	/* Includes ------------------------------------------------------------------*/
	45	#include "stm32f0xx.h"
	46
	47	/** @addtogroup STM32F0xx_LL_Driver
	48	* @{
	49	*/
	50
	51	#if defined (DMA1) \|\| defined (DMA2)
	52
	53	/** @defgroup DMA_LL DMA
	54	* @{
	55	*/
	56
	57	/* Private types -------------------------------------------------------------*/
	58	/* Private variables ---------------------------------------------------------*/
	59	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
	60	* @{
	61	*/
	62	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
	63	static const uint8_t CHANNEL_OFFSET_TAB[] =
	64	{
	65	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
	66	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
	67	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
	68	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
	69	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
	70	#if defined(DMA1_Channel6)
	71	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
	72	#endif /DMA1_Channel6/
	73	#if defined(DMA1_Channel7)
	74	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
	75	#endif /DMA1_Channel7/
	76	};
	77	/**
	78	* @}
	79	*/
	80
	81	/* Private constants ---------------------------------------------------------*/
	82	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
	83	* @{
	84	*/
	85	/* Define used to get CSELR register offset */
	86	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
	87
	88	/* Defines used for the bit position in the register and perform offsets */
	89	#define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U)
	90	/**
	91	* @}
	92	*/
	93
	94	/* Private macros ------------------------------------------------------------*/
	95	#if defined(USE_FULL_LL_DRIVER)
	96	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
	97	* @{
	98	*/
	99	/**
	100	* @}
	101	*/
	102	#endif /USE_FULL_LL_DRIVER/
	103
	104	/* Exported types ------------------------------------------------------------*/
	105	#if defined(USE_FULL_LL_DRIVER)
	106	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
	107	* @{
	108	*/
	109	typedef struct
	110	{
	111	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
	112	or as Source base address in case of memory to memory transfer direction.
	113
	114	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
	115
	116	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
	117	or as Destination base address in case of memory to memory transfer direction.
	118
	119	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
	120
	121	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
	122	from memory to memory or from peripheral to memory.
	123	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
	124
	125	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
	126
	127	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
	128	This parameter can be a value of @ref DMA_LL_EC_MODE
	129	@note: The circular buffer mode cannot be used if the memory to memory
	130	data transfer direction is configured on the selected Channel
	131
	132	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
	133
	134	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
	135	is incremented or not.
	136	This parameter can be a value of @ref DMA_LL_EC_PERIPH
	137
	138	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
	139
	140	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
	141	is incremented or not.
	142	This parameter can be a value of @ref DMA_LL_EC_MEMORY
	143
	144	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
	145
	146	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
	147	in case of memory to memory transfer direction.
	148	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
	149
	150	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
	151
	152	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
	153	in case of memory to memory transfer direction.
	154	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
	155
	156	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
	157
	158	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
	159	The data unit is equal to the source buffer configuration set in PeripheralSize
	160	or MemorySize parameters depending in the transfer direction.
	161	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
	162
	163	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
	164	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
	165
	166	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
	167	This parameter can be a value of @ref DMA_LL_EC_REQUEST
	168
	169	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
	170	#endif
	171
	172	uint32_t Priority; /*!< Specifies the channel priority level.
	173	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
	174
	175	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
	176
	177	} LL_DMA_InitTypeDef;
	178	/**
	179	* @}
	180	*/
	181	#endif /USE_FULL_LL_DRIVER/
	182
	183	/* Exported constants --------------------------------------------------------*/
	184	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
	185	* @{
	186	*/
	187	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
	188	* @brief Flags defines which can be used with LL_DMA_WriteReg function
	189	* @{
	190	*/
	191	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
	192	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
	193	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
	194	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
	195	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
	196	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
	197	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
	198	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
	199	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
	200	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
	201	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
	202	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
	203	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
	204	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
	205	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
	206	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
	207	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
	208	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
	209	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
	210	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
	211	#if defined(DMA1_Channel6)
	212	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
	213	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
	214	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
	215	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
	216	#endif
	217	#if defined(DMA1_Channel7)
	218	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
	219	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
	220	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
	221	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
	222	#endif
	223	/**
	224	* @}
	225	*/
	226
	227	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
	228	* @brief Flags defines which can be used with LL_DMA_ReadReg function
	229	* @{
	230	*/
	231	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
	232	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
	233	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
	234	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
	235	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
	236	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
	237	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
	238	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
	239	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
	240	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
	241	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
	242	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
	243	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
	244	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
	245	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
	246	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
	247	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
	248	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
	249	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
	250	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
	251	#if defined(DMA1_Channel6)
	252	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
	253	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
	254	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
	255	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
	256	#endif
	257	#if defined(DMA1_Channel7)
	258	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
	259	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
	260	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
	261	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
	262	#endif
	263	/**
	264	* @}
	265	*/
	266
	267	/** @defgroup DMA_LL_EC_IT IT Defines
	268	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
	269	* @{
	270	*/
	271	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
	272	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
	273	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
	274	/**
	275	* @}
	276	*/
	277
	278	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
	279	* @{
	280	*/
	281	#define LL_DMA_CHANNEL_1 0x00000001U /!< DMA Channel 1 /
	282	#define LL_DMA_CHANNEL_2 0x00000002U /!< DMA Channel 2 /
	283	#define LL_DMA_CHANNEL_3 0x00000003U /!< DMA Channel 3 /
	284	#define LL_DMA_CHANNEL_4 0x00000004U /!< DMA Channel 4 /
	285	#define LL_DMA_CHANNEL_5 0x00000005U /!< DMA Channel 5 /
	286	#if defined(DMA1_Channel6)
	287	#define LL_DMA_CHANNEL_6 0x00000006U /!< DMA Channel 6 /
	288	#endif
	289	#if defined(DMA1_Channel7)
	290	#define LL_DMA_CHANNEL_7 0x00000007U /!< DMA Channel 7 /
	291	#endif
	292	#if defined(USE_FULL_LL_DRIVER)
	293	#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
	294	#endif /USE_FULL_LL_DRIVER/
	295	/**
	296	* @}
	297	*/
	298
	299	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
	300	* @{
	301	*/
	302	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
	303	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
	304	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
	305	/**
	306	* @}
	307	*/
	308
	309	/** @defgroup DMA_LL_EC_MODE Transfer mode
	310	* @{
	311	*/
	312	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
	313	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
	314	/**
	315	* @}
	316	*/
	317
	318	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
	319	* @{
	320	*/
	321	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
	322	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
	323	/**
	324	* @}
	325	*/
	326
	327	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
	328	* @{
	329	*/
	330	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
	331	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
	332	/**
	333	* @}
	334	*/
	335
	336	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
	337	* @{
	338	*/
	339	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
	340	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
	341	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
	342	/**
	343	* @}
	344	*/
	345
	346	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
	347	* @{
	348	*/
	349	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
	350	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
	351	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
	352	/**
	353	* @}
	354	*/
	355
	356	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
	357	* @{
	358	*/
	359	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
	360	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
	361	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
	362	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
	363	/**
	364	* @}
	365	*/
	366
	367	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
	368	/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
	369	* @{
	370	*/
	371	#define LL_DMA_REQUEST_0 0x00000000U /!< DMA peripheral request 0 /
	372	#define LL_DMA_REQUEST_1 0x00000001U /!< DMA peripheral request 1 /
	373	#define LL_DMA_REQUEST_2 0x00000002U /!< DMA peripheral request 2 /
	374	#define LL_DMA_REQUEST_3 0x00000003U /!< DMA peripheral request 3 /
	375	#define LL_DMA_REQUEST_4 0x00000004U /!< DMA peripheral request 4 /
	376	#define LL_DMA_REQUEST_5 0x00000005U /!< DMA peripheral request 5 /
	377	#define LL_DMA_REQUEST_6 0x00000006U /!< DMA peripheral request 6 /
	378	#define LL_DMA_REQUEST_7 0x00000007U /!< DMA peripheral request 7 /
	379	#define LL_DMA_REQUEST_8 0x00000008U /!< DMA peripheral request 8 /
	380	#define LL_DMA_REQUEST_9 0x00000009U /!< DMA peripheral request 9 /
	381	#define LL_DMA_REQUEST_10 0x0000000AU /!< DMA peripheral request 10 /
	382	#define LL_DMA_REQUEST_11 0x0000000BU /!< DMA peripheral request 11 /
	383	#define LL_DMA_REQUEST_12 0x0000000CU /!< DMA peripheral request 12 /
	384	#define LL_DMA_REQUEST_13 0x0000000DU /!< DMA peripheral request 13 /
	385	#define LL_DMA_REQUEST_14 0x0000000EU /!< DMA peripheral request 14 /
	386	#define LL_DMA_REQUEST_15 0x0000000FU /!< DMA peripheral request 15 /
	387	/**
	388	* @}
	389	*/
	390	#endif
	391
	392	/**
	393	* @}
	394	*/
	395
	396	/* Exported macro ------------------------------------------------------------*/
	397	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
	398	* @{
	399	*/
	400
	401	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
	402	* @{
	403	*/
	404	/**
	405	* @brief Write a value in DMA register
	406	* @param __INSTANCE__ DMA Instance
	407	* @param __REG__ Register to be written
	408	* @param __VALUE__ Value to be written in the register
	409	* @retval None
	410	*/
	411	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
	412
	413	/**
	414	* @brief Read a value in DMA register
	415	* @param __INSTANCE__ DMA Instance
	416	* @param __REG__ Register to be read
	417	* @retval Register value
	418	*/
	419	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
	420	/**
	421	* @}
	422	*/
	423
	424	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
	425	* @{
	426	*/
	427	/**
	428	* @brief Convert DMAx_Channely into DMAx
	429	* @param __CHANNEL_INSTANCE__ DMAx_Channely
	430	* @retval DMAx
	431	*/
	432	#if defined(DMA2)
	433	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
	434	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
	435	#else
	436	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
	437	#endif
	438
	439	/**
	440	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
	441	* @param __CHANNEL_INSTANCE__ DMAx_Channely
	442	* @retval LL_DMA_CHANNEL_y
	443	*/
	444	#if defined (DMA2)
	445	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
	446	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
	447	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
	448	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
	449	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
	450	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
	451	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
	452	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
	453	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
	454	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
	455	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
	456	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
	457	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
	458	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
	459	LL_DMA_CHANNEL_7)
	460	#else
	461	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
	462	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
	463	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
	464	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
	465	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
	466	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
	467	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
	468	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
	469	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
	470	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
	471	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
	472	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
	473	LL_DMA_CHANNEL_7)
	474	#endif
	475	#else
	476	#if defined (DMA1_Channel6) && defined (DMA1_Channel7)
	477	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
	478	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
	479	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
	480	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
	481	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
	482	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
	483	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
	484	LL_DMA_CHANNEL_7)
	485	#elif defined (DMA1_Channel6)
	486	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
	487	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
	488	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
	489	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
	490	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
	491	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
	492	LL_DMA_CHANNEL_6)
	493	#else
	494	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
	495	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
	496	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
	497	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
	498	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
	499	LL_DMA_CHANNEL_5)
	500	#endif /* DMA1_Channel6 && DMA1_Channel7 */
	501	#endif
	502
	503	/**
	504	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
	505	* @param __DMA_INSTANCE__ DMAx
	506	* @param __CHANNEL__ LL_DMA_CHANNEL_y
	507	* @retval DMAx_Channely
	508	*/
	509	#if defined (DMA2)
	510	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
	511	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
	512	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
	513	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
	514	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
	515	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
	516	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
	517	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
	518	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
	519	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
	520	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
	521	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
	522	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
	523	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
	524	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
	525	DMA2_Channel7)
	526	#else
	527	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
	528	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
	529	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
	530	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
	531	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
	532	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
	533	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
	534	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
	535	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
	536	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
	537	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
	538	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
	539	DMA1_Channel7)
	540	#endif
	541	#else
	542	#if defined (DMA1_Channel6) && defined (DMA1_Channel7)
	543	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
	544	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
	545	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
	546	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
	547	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
	548	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
	549	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
	550	DMA1_Channel7)
	551	#elif defined (DMA1_Channel6)
	552	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
	553	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
	554	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
	555	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
	556	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
	557	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
	558	DMA1_Channel6)
	559	#else
	560	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
	561	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
	562	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
	563	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
	564	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
	565	DMA1_Channel5)
	566	#endif /* DMA1_Channel6 && DMA1_Channel7 */
	567	#endif
	568
	569	/**
	570	* @}
	571	*/
	572
	573	/**
	574	* @}
	575	*/
	576
	577	/* Exported functions --------------------------------------------------------*/
	578	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
	579	* @{
	580	*/
	581
	582	/** @defgroup DMA_LL_EF_Configuration Configuration
	583	* @{
	584	*/
	585	/**
	586	* @brief Enable DMA channel.
	587	* @rmtoll CCR EN LL_DMA_EnableChannel
	588	* @param DMAx DMAx Instance
	589	* @param Channel This parameter can be one of the following values:
	590	* @arg @ref LL_DMA_CHANNEL_1
	591	* @arg @ref LL_DMA_CHANNEL_2
	592	* @arg @ref LL_DMA_CHANNEL_3
	593	* @arg @ref LL_DMA_CHANNEL_4
	594	* @arg @ref LL_DMA_CHANNEL_5
	595	* @arg @ref LL_DMA_CHANNEL_6
	596	* @arg @ref LL_DMA_CHANNEL_7
	597	* @retval None
	598	*/
	599	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
	600	{
	601	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
	602	}
	603
	604	/**
	605	* @brief Disable DMA channel.
	606	* @rmtoll CCR EN LL_DMA_DisableChannel
	607	* @param DMAx DMAx Instance
	608	* @param Channel This parameter can be one of the following values:
	609	* @arg @ref LL_DMA_CHANNEL_1
	610	* @arg @ref LL_DMA_CHANNEL_2
	611	* @arg @ref LL_DMA_CHANNEL_3
	612	* @arg @ref LL_DMA_CHANNEL_4
	613	* @arg @ref LL_DMA_CHANNEL_5
	614	* @arg @ref LL_DMA_CHANNEL_6
	615	* @arg @ref LL_DMA_CHANNEL_7
	616	* @retval None
	617	*/
	618	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
	619	{
	620	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
	621	}
	622
	623	/**
	624	* @brief Check if DMA channel is enabled or disabled.
	625	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
	626	* @param DMAx DMAx Instance
	627	* @param Channel This parameter can be one of the following values:
	628	* @arg @ref LL_DMA_CHANNEL_1
	629	* @arg @ref LL_DMA_CHANNEL_2
	630	* @arg @ref LL_DMA_CHANNEL_3
	631	* @arg @ref LL_DMA_CHANNEL_4
	632	* @arg @ref LL_DMA_CHANNEL_5
	633	* @arg @ref LL_DMA_CHANNEL_6
	634	* @arg @ref LL_DMA_CHANNEL_7
	635	* @retval State of bit (1 or 0).
	636	*/
	637	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
	638	{
	639	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	640	DMA_CCR_EN) == (DMA_CCR_EN));
	641	}
	642
	643	/**
	644	* @brief Configure all parameters link to DMA transfer.
	645	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
	646	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
	647	* CCR CIRC LL_DMA_ConfigTransfer\n
	648	* CCR PINC LL_DMA_ConfigTransfer\n
	649	* CCR MINC LL_DMA_ConfigTransfer\n
	650	* CCR PSIZE LL_DMA_ConfigTransfer\n
	651	* CCR MSIZE LL_DMA_ConfigTransfer\n
	652	* CCR PL LL_DMA_ConfigTransfer
	653	* @param DMAx DMAx Instance
	654	* @param Channel This parameter can be one of the following values:
	655	* @arg @ref LL_DMA_CHANNEL_1
	656	* @arg @ref LL_DMA_CHANNEL_2
	657	* @arg @ref LL_DMA_CHANNEL_3
	658	* @arg @ref LL_DMA_CHANNEL_4
	659	* @arg @ref LL_DMA_CHANNEL_5
	660	* @arg @ref LL_DMA_CHANNEL_6
	661	* @arg @ref LL_DMA_CHANNEL_7
	662	* @param Configuration This parameter must be a combination of all the following values:
	663	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
	664	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
	665	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
	666	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
	667	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
	668	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
	669	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
	670	* @retval None
	671	*/
	672	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
	673	{
	674	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	675	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
	676	Configuration);
	677	}
	678
	679	/**
	680	* @brief Set Data transfer direction (read from peripheral or from memory).
	681	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
	682	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
	683	* @param DMAx DMAx Instance
	684	* @param Channel This parameter can be one of the following values:
	685	* @arg @ref LL_DMA_CHANNEL_1
	686	* @arg @ref LL_DMA_CHANNEL_2
	687	* @arg @ref LL_DMA_CHANNEL_3
	688	* @arg @ref LL_DMA_CHANNEL_4
	689	* @arg @ref LL_DMA_CHANNEL_5
	690	* @arg @ref LL_DMA_CHANNEL_6
	691	* @arg @ref LL_DMA_CHANNEL_7
	692	* @param Direction This parameter can be one of the following values:
	693	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
	694	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
	695	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
	696	* @retval None
	697	*/
	698	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
	699	{
	700	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	701	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
	702	}
	703
	704	/**
	705	* @brief Get Data transfer direction (read from peripheral or from memory).
	706	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
	707	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
	708	* @param DMAx DMAx Instance
	709	* @param Channel This parameter can be one of the following values:
	710	* @arg @ref LL_DMA_CHANNEL_1
	711	* @arg @ref LL_DMA_CHANNEL_2
	712	* @arg @ref LL_DMA_CHANNEL_3
	713	* @arg @ref LL_DMA_CHANNEL_4
	714	* @arg @ref LL_DMA_CHANNEL_5
	715	* @arg @ref LL_DMA_CHANNEL_6
	716	* @arg @ref LL_DMA_CHANNEL_7
	717	* @retval Returned value can be one of the following values:
	718	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
	719	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
	720	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
	721	*/
	722	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
	723	{
	724	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	725	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
	726	}
	727
	728	/**
	729	* @brief Set DMA mode circular or normal.
	730	* @note The circular buffer mode cannot be used if the memory-to-memory
	731	* data transfer is configured on the selected Channel.
	732	* @rmtoll CCR CIRC LL_DMA_SetMode
	733	* @param DMAx DMAx Instance
	734	* @param Channel This parameter can be one of the following values:
	735	* @arg @ref LL_DMA_CHANNEL_1
	736	* @arg @ref LL_DMA_CHANNEL_2
	737	* @arg @ref LL_DMA_CHANNEL_3
	738	* @arg @ref LL_DMA_CHANNEL_4
	739	* @arg @ref LL_DMA_CHANNEL_5
	740	* @arg @ref LL_DMA_CHANNEL_6
	741	* @arg @ref LL_DMA_CHANNEL_7
	742	* @param Mode This parameter can be one of the following values:
	743	* @arg @ref LL_DMA_MODE_NORMAL
	744	* @arg @ref LL_DMA_MODE_CIRCULAR
	745	* @retval None
	746	*/
	747	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
	748	{
	749	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
	750	Mode);
	751	}
	752
	753	/**
	754	* @brief Get DMA mode circular or normal.
	755	* @rmtoll CCR CIRC LL_DMA_GetMode
	756	* @param DMAx DMAx Instance
	757	* @param Channel This parameter can be one of the following values:
	758	* @arg @ref LL_DMA_CHANNEL_1
	759	* @arg @ref LL_DMA_CHANNEL_2
	760	* @arg @ref LL_DMA_CHANNEL_3
	761	* @arg @ref LL_DMA_CHANNEL_4
	762	* @arg @ref LL_DMA_CHANNEL_5
	763	* @arg @ref LL_DMA_CHANNEL_6
	764	* @arg @ref LL_DMA_CHANNEL_7
	765	* @retval Returned value can be one of the following values:
	766	* @arg @ref LL_DMA_MODE_NORMAL
	767	* @arg @ref LL_DMA_MODE_CIRCULAR
	768	*/
	769	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
	770	{
	771	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	772	DMA_CCR_CIRC));
	773	}
	774
	775	/**
	776	* @brief Set Peripheral increment mode.
	777	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
	778	* @param DMAx DMAx Instance
	779	* @param Channel This parameter can be one of the following values:
	780	* @arg @ref LL_DMA_CHANNEL_1
	781	* @arg @ref LL_DMA_CHANNEL_2
	782	* @arg @ref LL_DMA_CHANNEL_3
	783	* @arg @ref LL_DMA_CHANNEL_4
	784	* @arg @ref LL_DMA_CHANNEL_5
	785	* @arg @ref LL_DMA_CHANNEL_6
	786	* @arg @ref LL_DMA_CHANNEL_7
	787	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
	788	* @arg @ref LL_DMA_PERIPH_INCREMENT
	789	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
	790	* @retval None
	791	*/
	792	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
	793	{
	794	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
	795	PeriphOrM2MSrcIncMode);
	796	}
	797
	798	/**
	799	* @brief Get Peripheral increment mode.
	800	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
	801	* @param DMAx DMAx Instance
	802	* @param Channel This parameter can be one of the following values:
	803	* @arg @ref LL_DMA_CHANNEL_1
	804	* @arg @ref LL_DMA_CHANNEL_2
	805	* @arg @ref LL_DMA_CHANNEL_3
	806	* @arg @ref LL_DMA_CHANNEL_4
	807	* @arg @ref LL_DMA_CHANNEL_5
	808	* @arg @ref LL_DMA_CHANNEL_6
	809	* @arg @ref LL_DMA_CHANNEL_7
	810	* @retval Returned value can be one of the following values:
	811	* @arg @ref LL_DMA_PERIPH_INCREMENT
	812	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
	813	*/
	814	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
	815	{
	816	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	817	DMA_CCR_PINC));
	818	}
	819
	820	/**
	821	* @brief Set Memory increment mode.
	822	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
	823	* @param DMAx DMAx Instance
	824	* @param Channel This parameter can be one of the following values:
	825	* @arg @ref LL_DMA_CHANNEL_1
	826	* @arg @ref LL_DMA_CHANNEL_2
	827	* @arg @ref LL_DMA_CHANNEL_3
	828	* @arg @ref LL_DMA_CHANNEL_4
	829	* @arg @ref LL_DMA_CHANNEL_5
	830	* @arg @ref LL_DMA_CHANNEL_6
	831	* @arg @ref LL_DMA_CHANNEL_7
	832	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
	833	* @arg @ref LL_DMA_MEMORY_INCREMENT
	834	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
	835	* @retval None
	836	*/
	837	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
	838	{
	839	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
	840	MemoryOrM2MDstIncMode);
	841	}
	842
	843	/**
	844	* @brief Get Memory increment mode.
	845	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
	846	* @param DMAx DMAx Instance
	847	* @param Channel This parameter can be one of the following values:
	848	* @arg @ref LL_DMA_CHANNEL_1
	849	* @arg @ref LL_DMA_CHANNEL_2
	850	* @arg @ref LL_DMA_CHANNEL_3
	851	* @arg @ref LL_DMA_CHANNEL_4
	852	* @arg @ref LL_DMA_CHANNEL_5
	853	* @arg @ref LL_DMA_CHANNEL_6
	854	* @arg @ref LL_DMA_CHANNEL_7
	855	* @retval Returned value can be one of the following values:
	856	* @arg @ref LL_DMA_MEMORY_INCREMENT
	857	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
	858	*/
	859	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
	860	{
	861	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	862	DMA_CCR_MINC));
	863	}
	864
	865	/**
	866	* @brief Set Peripheral size.
	867	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
	868	* @param DMAx DMAx Instance
	869	* @param Channel This parameter can be one of the following values:
	870	* @arg @ref LL_DMA_CHANNEL_1
	871	* @arg @ref LL_DMA_CHANNEL_2
	872	* @arg @ref LL_DMA_CHANNEL_3
	873	* @arg @ref LL_DMA_CHANNEL_4
	874	* @arg @ref LL_DMA_CHANNEL_5
	875	* @arg @ref LL_DMA_CHANNEL_6
	876	* @arg @ref LL_DMA_CHANNEL_7
	877	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
	878	* @arg @ref LL_DMA_PDATAALIGN_BYTE
	879	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
	880	* @arg @ref LL_DMA_PDATAALIGN_WORD
	881	* @retval None
	882	*/
	883	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
	884	{
	885	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
	886	PeriphOrM2MSrcDataSize);
	887	}
	888
	889	/**
	890	* @brief Get Peripheral size.
	891	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
	892	* @param DMAx DMAx Instance
	893	* @param Channel This parameter can be one of the following values:
	894	* @arg @ref LL_DMA_CHANNEL_1
	895	* @arg @ref LL_DMA_CHANNEL_2
	896	* @arg @ref LL_DMA_CHANNEL_3
	897	* @arg @ref LL_DMA_CHANNEL_4
	898	* @arg @ref LL_DMA_CHANNEL_5
	899	* @arg @ref LL_DMA_CHANNEL_6
	900	* @arg @ref LL_DMA_CHANNEL_7
	901	* @retval Returned value can be one of the following values:
	902	* @arg @ref LL_DMA_PDATAALIGN_BYTE
	903	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
	904	* @arg @ref LL_DMA_PDATAALIGN_WORD
	905	*/
	906	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
	907	{
	908	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	909	DMA_CCR_PSIZE));
	910	}
	911
	912	/**
	913	* @brief Set Memory size.
	914	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
	915	* @param DMAx DMAx Instance
	916	* @param Channel This parameter can be one of the following values:
	917	* @arg @ref LL_DMA_CHANNEL_1
	918	* @arg @ref LL_DMA_CHANNEL_2
	919	* @arg @ref LL_DMA_CHANNEL_3
	920	* @arg @ref LL_DMA_CHANNEL_4
	921	* @arg @ref LL_DMA_CHANNEL_5
	922	* @arg @ref LL_DMA_CHANNEL_6
	923	* @arg @ref LL_DMA_CHANNEL_7
	924	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
	925	* @arg @ref LL_DMA_MDATAALIGN_BYTE
	926	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
	927	* @arg @ref LL_DMA_MDATAALIGN_WORD
	928	* @retval None
	929	*/
	930	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
	931	{
	932	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
	933	MemoryOrM2MDstDataSize);
	934	}
	935
	936	/**
	937	* @brief Get Memory size.
	938	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
	939	* @param DMAx DMAx Instance
	940	* @param Channel This parameter can be one of the following values:
	941	* @arg @ref LL_DMA_CHANNEL_1
	942	* @arg @ref LL_DMA_CHANNEL_2
	943	* @arg @ref LL_DMA_CHANNEL_3
	944	* @arg @ref LL_DMA_CHANNEL_4
	945	* @arg @ref LL_DMA_CHANNEL_5
	946	* @arg @ref LL_DMA_CHANNEL_6
	947	* @arg @ref LL_DMA_CHANNEL_7
	948	* @retval Returned value can be one of the following values:
	949	* @arg @ref LL_DMA_MDATAALIGN_BYTE
	950	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
	951	* @arg @ref LL_DMA_MDATAALIGN_WORD
	952	*/
	953	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
	954	{
	955	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	956	DMA_CCR_MSIZE));
	957	}
	958
	959	/**
	960	* @brief Set Channel priority level.
	961	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
	962	* @param DMAx DMAx Instance
	963	* @param Channel This parameter can be one of the following values:
	964	* @arg @ref LL_DMA_CHANNEL_1
	965	* @arg @ref LL_DMA_CHANNEL_2
	966	* @arg @ref LL_DMA_CHANNEL_3
	967	* @arg @ref LL_DMA_CHANNEL_4
	968	* @arg @ref LL_DMA_CHANNEL_5
	969	* @arg @ref LL_DMA_CHANNEL_6
	970	* @arg @ref LL_DMA_CHANNEL_7
	971	* @param Priority This parameter can be one of the following values:
	972	* @arg @ref LL_DMA_PRIORITY_LOW
	973	* @arg @ref LL_DMA_PRIORITY_MEDIUM
	974	* @arg @ref LL_DMA_PRIORITY_HIGH
	975	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
	976	* @retval None
	977	*/
	978	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
	979	{
	980	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
	981	Priority);
	982	}
	983
	984	/**
	985	* @brief Get Channel priority level.
	986	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
	987	* @param DMAx DMAx Instance
	988	* @param Channel This parameter can be one of the following values:
	989	* @arg @ref LL_DMA_CHANNEL_1
	990	* @arg @ref LL_DMA_CHANNEL_2
	991	* @arg @ref LL_DMA_CHANNEL_3
	992	* @arg @ref LL_DMA_CHANNEL_4
	993	* @arg @ref LL_DMA_CHANNEL_5
	994	* @arg @ref LL_DMA_CHANNEL_6
	995	* @arg @ref LL_DMA_CHANNEL_7
	996	* @retval Returned value can be one of the following values:
	997	* @arg @ref LL_DMA_PRIORITY_LOW
	998	* @arg @ref LL_DMA_PRIORITY_MEDIUM
	999	* @arg @ref LL_DMA_PRIORITY_HIGH
	1000	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
	1001	*/
	1002	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
	1003	{
	1004	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	1005	DMA_CCR_PL));
	1006	}
	1007
	1008	/**
	1009	* @brief Set Number of data to transfer.
	1010	* @note This action has no effect if
	1011	* channel is enabled.
	1012	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
	1013	* @param DMAx DMAx Instance
	1014	* @param Channel This parameter can be one of the following values:
	1015	* @arg @ref LL_DMA_CHANNEL_1
	1016	* @arg @ref LL_DMA_CHANNEL_2
	1017	* @arg @ref LL_DMA_CHANNEL_3
	1018	* @arg @ref LL_DMA_CHANNEL_4
	1019	* @arg @ref LL_DMA_CHANNEL_5
	1020	* @arg @ref LL_DMA_CHANNEL_6
	1021	* @arg @ref LL_DMA_CHANNEL_7
	1022	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
	1023	* @retval None
	1024	*/
	1025	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
	1026	{
	1027	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
	1028	DMA_CNDTR_NDT, NbData);
	1029	}
	1030
	1031	/**
	1032	* @brief Get Number of data to transfer.
	1033	* @note Once the channel is enabled, the return value indicate the
	1034	* remaining bytes to be transmitted.
	1035	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
	1036	* @param DMAx DMAx Instance
	1037	* @param Channel This parameter can be one of the following values:
	1038	* @arg @ref LL_DMA_CHANNEL_1
	1039	* @arg @ref LL_DMA_CHANNEL_2
	1040	* @arg @ref LL_DMA_CHANNEL_3
	1041	* @arg @ref LL_DMA_CHANNEL_4
	1042	* @arg @ref LL_DMA_CHANNEL_5
	1043	* @arg @ref LL_DMA_CHANNEL_6
	1044	* @arg @ref LL_DMA_CHANNEL_7
	1045	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
	1046	*/
	1047	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
	1048	{
	1049	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
	1050	DMA_CNDTR_NDT));
	1051	}
	1052
	1053	/**
	1054	* @brief Configure the Source and Destination addresses.
	1055	* @note This API must not be called when the DMA channel is enabled.
	1056	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
	1057	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
	1058	* CMAR MA LL_DMA_ConfigAddresses
	1059	* @param DMAx DMAx Instance
	1060	* @param Channel This parameter can be one of the following values:
	1061	* @arg @ref LL_DMA_CHANNEL_1
	1062	* @arg @ref LL_DMA_CHANNEL_2
	1063	* @arg @ref LL_DMA_CHANNEL_3
	1064	* @arg @ref LL_DMA_CHANNEL_4
	1065	* @arg @ref LL_DMA_CHANNEL_5
	1066	* @arg @ref LL_DMA_CHANNEL_6
	1067	* @arg @ref LL_DMA_CHANNEL_7
	1068	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
	1069	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
	1070	* @param Direction This parameter can be one of the following values:
	1071	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
	1072	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
	1073	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
	1074	* @retval None
	1075	*/
	1076	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
	1077	uint32_t DstAddress, uint32_t Direction)
	1078	{
	1079	/* Direction Memory to Periph */
	1080	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
	1081	{
	1082	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
	1083	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
	1084	}
	1085	/* Direction Periph to Memory and Memory to Memory */
	1086	else
	1087	{
	1088	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
	1089	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
	1090	}
	1091	}
	1092
	1093	/**
	1094	* @brief Set the Memory address.
	1095	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
	1096	* @note This API must not be called when the DMA channel is enabled.
	1097	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
	1098	* @param DMAx DMAx Instance
	1099	* @param Channel This parameter can be one of the following values:
	1100	* @arg @ref LL_DMA_CHANNEL_1
	1101	* @arg @ref LL_DMA_CHANNEL_2
	1102	* @arg @ref LL_DMA_CHANNEL_3
	1103	* @arg @ref LL_DMA_CHANNEL_4
	1104	* @arg @ref LL_DMA_CHANNEL_5
	1105	* @arg @ref LL_DMA_CHANNEL_6
	1106	* @arg @ref LL_DMA_CHANNEL_7
	1107	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
	1108	* @retval None
	1109	*/
	1110	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
	1111	{
	1112	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
	1113	}
	1114
	1115	/**
	1116	* @brief Set the Peripheral address.
	1117	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
	1118	* @note This API must not be called when the DMA channel is enabled.
	1119	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
	1120	* @param DMAx DMAx Instance
	1121	* @param Channel This parameter can be one of the following values:
	1122	* @arg @ref LL_DMA_CHANNEL_1
	1123	* @arg @ref LL_DMA_CHANNEL_2
	1124	* @arg @ref LL_DMA_CHANNEL_3
	1125	* @arg @ref LL_DMA_CHANNEL_4
	1126	* @arg @ref LL_DMA_CHANNEL_5
	1127	* @arg @ref LL_DMA_CHANNEL_6
	1128	* @arg @ref LL_DMA_CHANNEL_7
	1129	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
	1130	* @retval None
	1131	*/
	1132	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
	1133	{
	1134	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
	1135	}
	1136
	1137	/**
	1138	* @brief Get Memory address.
	1139	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
	1140	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
	1141	* @param DMAx DMAx Instance
	1142	* @param Channel This parameter can be one of the following values:
	1143	* @arg @ref LL_DMA_CHANNEL_1
	1144	* @arg @ref LL_DMA_CHANNEL_2
	1145	* @arg @ref LL_DMA_CHANNEL_3
	1146	* @arg @ref LL_DMA_CHANNEL_4
	1147	* @arg @ref LL_DMA_CHANNEL_5
	1148	* @arg @ref LL_DMA_CHANNEL_6
	1149	* @arg @ref LL_DMA_CHANNEL_7
	1150	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
	1151	*/
	1152	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
	1153	{
	1154	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
	1155	}
	1156
	1157	/**
	1158	* @brief Get Peripheral address.
	1159	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
	1160	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
	1161	* @param DMAx DMAx Instance
	1162	* @param Channel This parameter can be one of the following values:
	1163	* @arg @ref LL_DMA_CHANNEL_1
	1164	* @arg @ref LL_DMA_CHANNEL_2
	1165	* @arg @ref LL_DMA_CHANNEL_3
	1166	* @arg @ref LL_DMA_CHANNEL_4
	1167	* @arg @ref LL_DMA_CHANNEL_5
	1168	* @arg @ref LL_DMA_CHANNEL_6
	1169	* @arg @ref LL_DMA_CHANNEL_7
	1170	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
	1171	*/
	1172	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
	1173	{
	1174	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
	1175	}
	1176
	1177	/**
	1178	* @brief Set the Memory to Memory Source address.
	1179	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
	1180	* @note This API must not be called when the DMA channel is enabled.
	1181	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
	1182	* @param DMAx DMAx Instance
	1183	* @param Channel This parameter can be one of the following values:
	1184	* @arg @ref LL_DMA_CHANNEL_1
	1185	* @arg @ref LL_DMA_CHANNEL_2
	1186	* @arg @ref LL_DMA_CHANNEL_3
	1187	* @arg @ref LL_DMA_CHANNEL_4
	1188	* @arg @ref LL_DMA_CHANNEL_5
	1189	* @arg @ref LL_DMA_CHANNEL_6
	1190	* @arg @ref LL_DMA_CHANNEL_7
	1191	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
	1192	* @retval None
	1193	*/
	1194	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
	1195	{
	1196	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
	1197	}
	1198
	1199	/**
	1200	* @brief Set the Memory to Memory Destination address.
	1201	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
	1202	* @note This API must not be called when the DMA channel is enabled.
	1203	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
	1204	* @param DMAx DMAx Instance
	1205	* @param Channel This parameter can be one of the following values:
	1206	* @arg @ref LL_DMA_CHANNEL_1
	1207	* @arg @ref LL_DMA_CHANNEL_2
	1208	* @arg @ref LL_DMA_CHANNEL_3
	1209	* @arg @ref LL_DMA_CHANNEL_4
	1210	* @arg @ref LL_DMA_CHANNEL_5
	1211	* @arg @ref LL_DMA_CHANNEL_6
	1212	* @arg @ref LL_DMA_CHANNEL_7
	1213	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
	1214	* @retval None
	1215	*/
	1216	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
	1217	{
	1218	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
	1219	}
	1220
	1221	/**
	1222	* @brief Get the Memory to Memory Source address.
	1223	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
	1224	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
	1225	* @param DMAx DMAx Instance
	1226	* @param Channel This parameter can be one of the following values:
	1227	* @arg @ref LL_DMA_CHANNEL_1
	1228	* @arg @ref LL_DMA_CHANNEL_2
	1229	* @arg @ref LL_DMA_CHANNEL_3
	1230	* @arg @ref LL_DMA_CHANNEL_4
	1231	* @arg @ref LL_DMA_CHANNEL_5
	1232	* @arg @ref LL_DMA_CHANNEL_6
	1233	* @arg @ref LL_DMA_CHANNEL_7
	1234	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
	1235	*/
	1236	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
	1237	{
	1238	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
	1239	}
	1240
	1241	/**
	1242	* @brief Get the Memory to Memory Destination address.
	1243	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
	1244	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
	1245	* @param DMAx DMAx Instance
	1246	* @param Channel This parameter can be one of the following values:
	1247	* @arg @ref LL_DMA_CHANNEL_1
	1248	* @arg @ref LL_DMA_CHANNEL_2
	1249	* @arg @ref LL_DMA_CHANNEL_3
	1250	* @arg @ref LL_DMA_CHANNEL_4
	1251	* @arg @ref LL_DMA_CHANNEL_5
	1252	* @arg @ref LL_DMA_CHANNEL_6
	1253	* @arg @ref LL_DMA_CHANNEL_7
	1254	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
	1255	*/
	1256	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
	1257	{
	1258	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
	1259	}
	1260
	1261	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
	1262	/**
	1263	* @brief Set DMA request for DMA instance on Channel x.
	1264	* @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
	1265	* @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
	1266	* CSELR C2S LL_DMA_SetPeriphRequest\n
	1267	* CSELR C3S LL_DMA_SetPeriphRequest\n
	1268	* CSELR C4S LL_DMA_SetPeriphRequest\n
	1269	* CSELR C5S LL_DMA_SetPeriphRequest\n
	1270	* CSELR C6S LL_DMA_SetPeriphRequest\n
	1271	* CSELR C7S LL_DMA_SetPeriphRequest
	1272	* @param DMAx DMAx Instance
	1273	* @param Channel This parameter can be one of the following values:
	1274	* @arg @ref LL_DMA_CHANNEL_1
	1275	* @arg @ref LL_DMA_CHANNEL_2
	1276	* @arg @ref LL_DMA_CHANNEL_3
	1277	* @arg @ref LL_DMA_CHANNEL_4
	1278	* @arg @ref LL_DMA_CHANNEL_5
	1279	* @arg @ref LL_DMA_CHANNEL_6
	1280	* @arg @ref LL_DMA_CHANNEL_7
	1281	* @param PeriphRequest This parameter can be one of the following values:
	1282	* @arg @ref LL_DMA_REQUEST_0
	1283	* @arg @ref LL_DMA_REQUEST_1
	1284	* @arg @ref LL_DMA_REQUEST_2
	1285	* @arg @ref LL_DMA_REQUEST_3
	1286	* @arg @ref LL_DMA_REQUEST_4
	1287	* @arg @ref LL_DMA_REQUEST_5
	1288	* @arg @ref LL_DMA_REQUEST_6
	1289	* @arg @ref LL_DMA_REQUEST_7
	1290	* @arg @ref LL_DMA_REQUEST_8
	1291	* @arg @ref LL_DMA_REQUEST_9
	1292	* @arg @ref LL_DMA_REQUEST_10
	1293	* @arg @ref LL_DMA_REQUEST_11
	1294	* @arg @ref LL_DMA_REQUEST_12
	1295	* @arg @ref LL_DMA_REQUEST_13
	1296	* @arg @ref LL_DMA_REQUEST_14
	1297	* @arg @ref LL_DMA_REQUEST_15
	1298	* @retval None
	1299	*/
	1300	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
	1301	{
	1302	MODIFY_REG(DMAx->CSELR,
	1303	DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
	1304	}
	1305
	1306	/**
	1307	* @brief Get DMA request for DMA instance on Channel x.
	1308	* @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
	1309	* CSELR C2S LL_DMA_GetPeriphRequest\n
	1310	* CSELR C3S LL_DMA_GetPeriphRequest\n
	1311	* CSELR C4S LL_DMA_GetPeriphRequest\n
	1312	* CSELR C5S LL_DMA_GetPeriphRequest\n
	1313	* CSELR C6S LL_DMA_GetPeriphRequest\n
	1314	* CSELR C7S LL_DMA_GetPeriphRequest
	1315	* @param DMAx DMAx Instance
	1316	* @param Channel This parameter can be one of the following values:
	1317	* @arg @ref LL_DMA_CHANNEL_1
	1318	* @arg @ref LL_DMA_CHANNEL_2
	1319	* @arg @ref LL_DMA_CHANNEL_3
	1320	* @arg @ref LL_DMA_CHANNEL_4
	1321	* @arg @ref LL_DMA_CHANNEL_5
	1322	* @arg @ref LL_DMA_CHANNEL_6
	1323	* @arg @ref LL_DMA_CHANNEL_7
	1324	* @retval Returned value can be one of the following values:
	1325	* @arg @ref LL_DMA_REQUEST_0
	1326	* @arg @ref LL_DMA_REQUEST_1
	1327	* @arg @ref LL_DMA_REQUEST_2
	1328	* @arg @ref LL_DMA_REQUEST_3
	1329	* @arg @ref LL_DMA_REQUEST_4
	1330	* @arg @ref LL_DMA_REQUEST_5
	1331	* @arg @ref LL_DMA_REQUEST_6
	1332	* @arg @ref LL_DMA_REQUEST_7
	1333	* @arg @ref LL_DMA_REQUEST_8
	1334	* @arg @ref LL_DMA_REQUEST_9
	1335	* @arg @ref LL_DMA_REQUEST_10
	1336	* @arg @ref LL_DMA_REQUEST_11
	1337	* @arg @ref LL_DMA_REQUEST_12
	1338	* @arg @ref LL_DMA_REQUEST_13
	1339	* @arg @ref LL_DMA_REQUEST_14
	1340	* @arg @ref LL_DMA_REQUEST_15
	1341	*/
	1342	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
	1343	{
	1344	return (READ_BIT(DMAx->CSELR,
	1345	DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
	1346	}
	1347	#endif
	1348
	1349	/**
	1350	* @}
	1351	*/
	1352
	1353	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
	1354	* @{
	1355	*/
	1356
	1357	/**
	1358	* @brief Get Channel 1 global interrupt flag.
	1359	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
	1360	* @param DMAx DMAx Instance
	1361	* @retval State of bit (1 or 0).
	1362	*/
	1363	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
	1364	{
	1365	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
	1366	}
	1367
	1368	/**
	1369	* @brief Get Channel 2 global interrupt flag.
	1370	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
	1371	* @param DMAx DMAx Instance
	1372	* @retval State of bit (1 or 0).
	1373	*/
	1374	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
	1375	{
	1376	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
	1377	}
	1378
	1379	/**
	1380	* @brief Get Channel 3 global interrupt flag.
	1381	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
	1382	* @param DMAx DMAx Instance
	1383	* @retval State of bit (1 or 0).
	1384	*/
	1385	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
	1386	{
	1387	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
	1388	}
	1389
	1390	/**
	1391	* @brief Get Channel 4 global interrupt flag.
	1392	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
	1393	* @param DMAx DMAx Instance
	1394	* @retval State of bit (1 or 0).
	1395	*/
	1396	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
	1397	{
	1398	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
	1399	}
	1400
	1401	/**
	1402	* @brief Get Channel 5 global interrupt flag.
	1403	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
	1404	* @param DMAx DMAx Instance
	1405	* @retval State of bit (1 or 0).
	1406	*/
	1407	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
	1408	{
	1409	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
	1410	}
	1411
	1412	#if defined(DMA1_Channel6)
	1413	/**
	1414	* @brief Get Channel 6 global interrupt flag.
	1415	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
	1416	* @param DMAx DMAx Instance
	1417	* @retval State of bit (1 or 0).
	1418	*/
	1419	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
	1420	{
	1421	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
	1422	}
	1423	#endif
	1424
	1425	#if defined(DMA1_Channel7)
	1426	/**
	1427	* @brief Get Channel 7 global interrupt flag.
	1428	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
	1429	* @param DMAx DMAx Instance
	1430	* @retval State of bit (1 or 0).
	1431	*/
	1432	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
	1433	{
	1434	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
	1435	}
	1436	#endif
	1437
	1438	/**
	1439	* @brief Get Channel 1 transfer complete flag.
	1440	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
	1441	* @param DMAx DMAx Instance
	1442	* @retval State of bit (1 or 0).
	1443	*/
	1444	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
	1445	{
	1446	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
	1447	}
	1448
	1449	/**
	1450	* @brief Get Channel 2 transfer complete flag.
	1451	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
	1452	* @param DMAx DMAx Instance
	1453	* @retval State of bit (1 or 0).
	1454	*/
	1455	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
	1456	{
	1457	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
	1458	}
	1459
	1460	/**
	1461	* @brief Get Channel 3 transfer complete flag.
	1462	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
	1463	* @param DMAx DMAx Instance
	1464	* @retval State of bit (1 or 0).
	1465	*/
	1466	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
	1467	{
	1468	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
	1469	}
	1470
	1471	/**
	1472	* @brief Get Channel 4 transfer complete flag.
	1473	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
	1474	* @param DMAx DMAx Instance
	1475	* @retval State of bit (1 or 0).
	1476	*/
	1477	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
	1478	{
	1479	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
	1480	}
	1481
	1482	/**
	1483	* @brief Get Channel 5 transfer complete flag.
	1484	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
	1485	* @param DMAx DMAx Instance
	1486	* @retval State of bit (1 or 0).
	1487	*/
	1488	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
	1489	{
	1490	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
	1491	}
	1492
	1493	#if defined(DMA1_Channel6)
	1494	/**
	1495	* @brief Get Channel 6 transfer complete flag.
	1496	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
	1497	* @param DMAx DMAx Instance
	1498	* @retval State of bit (1 or 0).
	1499	*/
	1500	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
	1501	{
	1502	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
	1503	}
	1504	#endif
	1505
	1506	#if defined(DMA1_Channel7)
	1507	/**
	1508	* @brief Get Channel 7 transfer complete flag.
	1509	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
	1510	* @param DMAx DMAx Instance
	1511	* @retval State of bit (1 or 0).
	1512	*/
	1513	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
	1514	{
	1515	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
	1516	}
	1517	#endif
	1518
	1519	/**
	1520	* @brief Get Channel 1 half transfer flag.
	1521	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
	1522	* @param DMAx DMAx Instance
	1523	* @retval State of bit (1 or 0).
	1524	*/
	1525	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
	1526	{
	1527	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
	1528	}
	1529
	1530	/**
	1531	* @brief Get Channel 2 half transfer flag.
	1532	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
	1533	* @param DMAx DMAx Instance
	1534	* @retval State of bit (1 or 0).
	1535	*/
	1536	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
	1537	{
	1538	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
	1539	}
	1540
	1541	/**
	1542	* @brief Get Channel 3 half transfer flag.
	1543	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
	1544	* @param DMAx DMAx Instance
	1545	* @retval State of bit (1 or 0).
	1546	*/
	1547	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
	1548	{
	1549	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
	1550	}
	1551
	1552	/**
	1553	* @brief Get Channel 4 half transfer flag.
	1554	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
	1555	* @param DMAx DMAx Instance
	1556	* @retval State of bit (1 or 0).
	1557	*/
	1558	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
	1559	{
	1560	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
	1561	}
	1562
	1563	/**
	1564	* @brief Get Channel 5 half transfer flag.
	1565	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
	1566	* @param DMAx DMAx Instance
	1567	* @retval State of bit (1 or 0).
	1568	*/
	1569	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
	1570	{
	1571	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
	1572	}
	1573
	1574	#if defined(DMA1_Channel6)
	1575	/**
	1576	* @brief Get Channel 6 half transfer flag.
	1577	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
	1578	* @param DMAx DMAx Instance
	1579	* @retval State of bit (1 or 0).
	1580	*/
	1581	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
	1582	{
	1583	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
	1584	}
	1585	#endif
	1586
	1587	#if defined(DMA1_Channel7)
	1588	/**
	1589	* @brief Get Channel 7 half transfer flag.
	1590	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
	1591	* @param DMAx DMAx Instance
	1592	* @retval State of bit (1 or 0).
	1593	*/
	1594	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
	1595	{
	1596	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
	1597	}
	1598	#endif
	1599
	1600	/**
	1601	* @brief Get Channel 1 transfer error flag.
	1602	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
	1603	* @param DMAx DMAx Instance
	1604	* @retval State of bit (1 or 0).
	1605	*/
	1606	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
	1607	{
	1608	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
	1609	}
	1610
	1611	/**
	1612	* @brief Get Channel 2 transfer error flag.
	1613	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
	1614	* @param DMAx DMAx Instance
	1615	* @retval State of bit (1 or 0).
	1616	*/
	1617	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
	1618	{
	1619	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
	1620	}
	1621
	1622	/**
	1623	* @brief Get Channel 3 transfer error flag.
	1624	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
	1625	* @param DMAx DMAx Instance
	1626	* @retval State of bit (1 or 0).
	1627	*/
	1628	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
	1629	{
	1630	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
	1631	}
	1632
	1633	/**
	1634	* @brief Get Channel 4 transfer error flag.
	1635	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
	1636	* @param DMAx DMAx Instance
	1637	* @retval State of bit (1 or 0).
	1638	*/
	1639	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
	1640	{
	1641	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
	1642	}
	1643
	1644	/**
	1645	* @brief Get Channel 5 transfer error flag.
	1646	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
	1647	* @param DMAx DMAx Instance
	1648	* @retval State of bit (1 or 0).
	1649	*/
	1650	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
	1651	{
	1652	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
	1653	}
	1654
	1655	#if defined(DMA1_Channel6)
	1656	/**
	1657	* @brief Get Channel 6 transfer error flag.
	1658	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
	1659	* @param DMAx DMAx Instance
	1660	* @retval State of bit (1 or 0).
	1661	*/
	1662	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
	1663	{
	1664	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
	1665	}
	1666	#endif
	1667
	1668	#if defined(DMA1_Channel7)
	1669	/**
	1670	* @brief Get Channel 7 transfer error flag.
	1671	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
	1672	* @param DMAx DMAx Instance
	1673	* @retval State of bit (1 or 0).
	1674	*/
	1675	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
	1676	{
	1677	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
	1678	}
	1679	#endif
	1680
	1681	/**
	1682	* @brief Clear Channel 1 global interrupt flag.
	1683	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
	1684	* @param DMAx DMAx Instance
	1685	* @retval None
	1686	*/
	1687	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
	1688	{
	1689	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
	1690	}
	1691
	1692	/**
	1693	* @brief Clear Channel 2 global interrupt flag.
	1694	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
	1695	* @param DMAx DMAx Instance
	1696	* @retval None
	1697	*/
	1698	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
	1699	{
	1700	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
	1701	}
	1702
	1703	/**
	1704	* @brief Clear Channel 3 global interrupt flag.
	1705	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
	1706	* @param DMAx DMAx Instance
	1707	* @retval None
	1708	*/
	1709	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
	1710	{
	1711	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
	1712	}
	1713
	1714	/**
	1715	* @brief Clear Channel 4 global interrupt flag.
	1716	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
	1717	* @param DMAx DMAx Instance
	1718	* @retval None
	1719	*/
	1720	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
	1721	{
	1722	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
	1723	}
	1724
	1725	/**
	1726	* @brief Clear Channel 5 global interrupt flag.
	1727	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
	1728	* @param DMAx DMAx Instance
	1729	* @retval None
	1730	*/
	1731	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
	1732	{
	1733	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
	1734	}
	1735
	1736	#if defined(DMA1_Channel6)
	1737	/**
	1738	* @brief Clear Channel 6 global interrupt flag.
	1739	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
	1740	* @param DMAx DMAx Instance
	1741	* @retval None
	1742	*/
	1743	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
	1744	{
	1745	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
	1746	}
	1747	#endif
	1748
	1749	#if defined(DMA1_Channel7)
	1750	/**
	1751	* @brief Clear Channel 7 global interrupt flag.
	1752	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
	1753	* @param DMAx DMAx Instance
	1754	* @retval None
	1755	*/
	1756	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
	1757	{
	1758	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
	1759	}
	1760	#endif
	1761
	1762	/**
	1763	* @brief Clear Channel 1 transfer complete flag.
	1764	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
	1765	* @param DMAx DMAx Instance
	1766	* @retval None
	1767	*/
	1768	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
	1769	{
	1770	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
	1771	}
	1772
	1773	/**
	1774	* @brief Clear Channel 2 transfer complete flag.
	1775	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
	1776	* @param DMAx DMAx Instance
	1777	* @retval None
	1778	*/
	1779	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
	1780	{
	1781	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
	1782	}
	1783
	1784	/**
	1785	* @brief Clear Channel 3 transfer complete flag.
	1786	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
	1787	* @param DMAx DMAx Instance
	1788	* @retval None
	1789	*/
	1790	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
	1791	{
	1792	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
	1793	}
	1794
	1795	/**
	1796	* @brief Clear Channel 4 transfer complete flag.
	1797	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
	1798	* @param DMAx DMAx Instance
	1799	* @retval None
	1800	*/
	1801	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
	1802	{
	1803	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
	1804	}
	1805
	1806	/**
	1807	* @brief Clear Channel 5 transfer complete flag.
	1808	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
	1809	* @param DMAx DMAx Instance
	1810	* @retval None
	1811	*/
	1812	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
	1813	{
	1814	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
	1815	}
	1816
	1817	#if defined(DMA1_Channel6)
	1818	/**
	1819	* @brief Clear Channel 6 transfer complete flag.
	1820	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
	1821	* @param DMAx DMAx Instance
	1822	* @retval None
	1823	*/
	1824	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
	1825	{
	1826	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
	1827	}
	1828	#endif
	1829
	1830	#if defined(DMA1_Channel7)
	1831	/**
	1832	* @brief Clear Channel 7 transfer complete flag.
	1833	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
	1834	* @param DMAx DMAx Instance
	1835	* @retval None
	1836	*/
	1837	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
	1838	{
	1839	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
	1840	}
	1841	#endif
	1842
	1843	/**
	1844	* @brief Clear Channel 1 half transfer flag.
	1845	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
	1846	* @param DMAx DMAx Instance
	1847	* @retval None
	1848	*/
	1849	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
	1850	{
	1851	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
	1852	}
	1853
	1854	/**
	1855	* @brief Clear Channel 2 half transfer flag.
	1856	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
	1857	* @param DMAx DMAx Instance
	1858	* @retval None
	1859	*/
	1860	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
	1861	{
	1862	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
	1863	}
	1864
	1865	/**
	1866	* @brief Clear Channel 3 half transfer flag.
	1867	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
	1868	* @param DMAx DMAx Instance
	1869	* @retval None
	1870	*/
	1871	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
	1872	{
	1873	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
	1874	}
	1875
	1876	/**
	1877	* @brief Clear Channel 4 half transfer flag.
	1878	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
	1879	* @param DMAx DMAx Instance
	1880	* @retval None
	1881	*/
	1882	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
	1883	{
	1884	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
	1885	}
	1886
	1887	/**
	1888	* @brief Clear Channel 5 half transfer flag.
	1889	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
	1890	* @param DMAx DMAx Instance
	1891	* @retval None
	1892	*/
	1893	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
	1894	{
	1895	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
	1896	}
	1897
	1898	#if defined(DMA1_Channel6)
	1899	/**
	1900	* @brief Clear Channel 6 half transfer flag.
	1901	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
	1902	* @param DMAx DMAx Instance
	1903	* @retval None
	1904	*/
	1905	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
	1906	{
	1907	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
	1908	}
	1909	#endif
	1910
	1911	#if defined(DMA1_Channel7)
	1912	/**
	1913	* @brief Clear Channel 7 half transfer flag.
	1914	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
	1915	* @param DMAx DMAx Instance
	1916	* @retval None
	1917	*/
	1918	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
	1919	{
	1920	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
	1921	}
	1922	#endif
	1923
	1924	/**
	1925	* @brief Clear Channel 1 transfer error flag.
	1926	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
	1927	* @param DMAx DMAx Instance
	1928	* @retval None
	1929	*/
	1930	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
	1931	{
	1932	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
	1933	}
	1934
	1935	/**
	1936	* @brief Clear Channel 2 transfer error flag.
	1937	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
	1938	* @param DMAx DMAx Instance
	1939	* @retval None
	1940	*/
	1941	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
	1942	{
	1943	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
	1944	}
	1945
	1946	/**
	1947	* @brief Clear Channel 3 transfer error flag.
	1948	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
	1949	* @param DMAx DMAx Instance
	1950	* @retval None
	1951	*/
	1952	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
	1953	{
	1954	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
	1955	}
	1956
	1957	/**
	1958	* @brief Clear Channel 4 transfer error flag.
	1959	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
	1960	* @param DMAx DMAx Instance
	1961	* @retval None
	1962	*/
	1963	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
	1964	{
	1965	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
	1966	}
	1967
	1968	/**
	1969	* @brief Clear Channel 5 transfer error flag.
	1970	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
	1971	* @param DMAx DMAx Instance
	1972	* @retval None
	1973	*/
	1974	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
	1975	{
	1976	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
	1977	}
	1978
	1979	#if defined(DMA1_Channel6)
	1980	/**
	1981	* @brief Clear Channel 6 transfer error flag.
	1982	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
	1983	* @param DMAx DMAx Instance
	1984	* @retval None
	1985	*/
	1986	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
	1987	{
	1988	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
	1989	}
	1990	#endif
	1991
	1992	#if defined(DMA1_Channel7)
	1993	/**
	1994	* @brief Clear Channel 7 transfer error flag.
	1995	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
	1996	* @param DMAx DMAx Instance
	1997	* @retval None
	1998	*/
	1999	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
	2000	{
	2001	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
	2002	}
	2003	#endif
	2004
	2005	/**
	2006	* @}
	2007	*/
	2008
	2009	/** @defgroup DMA_LL_EF_IT_Management IT_Management
	2010	* @{
	2011	*/
	2012	/**
	2013	* @brief Enable Transfer complete interrupt.
	2014	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
	2015	* @param DMAx DMAx Instance
	2016	* @param Channel This parameter can be one of the following values:
	2017	* @arg @ref LL_DMA_CHANNEL_1
	2018	* @arg @ref LL_DMA_CHANNEL_2
	2019	* @arg @ref LL_DMA_CHANNEL_3
	2020	* @arg @ref LL_DMA_CHANNEL_4
	2021	* @arg @ref LL_DMA_CHANNEL_5
	2022	* @arg @ref LL_DMA_CHANNEL_6
	2023	* @arg @ref LL_DMA_CHANNEL_7
	2024	* @retval None
	2025	*/
	2026	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
	2027	{
	2028	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
	2029	}
	2030
	2031	/**
	2032	* @brief Enable Half transfer interrupt.
	2033	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
	2034	* @param DMAx DMAx Instance
	2035	* @param Channel This parameter can be one of the following values:
	2036	* @arg @ref LL_DMA_CHANNEL_1
	2037	* @arg @ref LL_DMA_CHANNEL_2
	2038	* @arg @ref LL_DMA_CHANNEL_3
	2039	* @arg @ref LL_DMA_CHANNEL_4
	2040	* @arg @ref LL_DMA_CHANNEL_5
	2041	* @arg @ref LL_DMA_CHANNEL_6
	2042	* @arg @ref LL_DMA_CHANNEL_7
	2043	* @retval None
	2044	*/
	2045	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
	2046	{
	2047	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
	2048	}
	2049
	2050	/**
	2051	* @brief Enable Transfer error interrupt.
	2052	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
	2053	* @param DMAx DMAx Instance
	2054	* @param Channel This parameter can be one of the following values:
	2055	* @arg @ref LL_DMA_CHANNEL_1
	2056	* @arg @ref LL_DMA_CHANNEL_2
	2057	* @arg @ref LL_DMA_CHANNEL_3
	2058	* @arg @ref LL_DMA_CHANNEL_4
	2059	* @arg @ref LL_DMA_CHANNEL_5
	2060	* @arg @ref LL_DMA_CHANNEL_6
	2061	* @arg @ref LL_DMA_CHANNEL_7
	2062	* @retval None
	2063	*/
	2064	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
	2065	{
	2066	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
	2067	}
	2068
	2069	/**
	2070	* @brief Disable Transfer complete interrupt.
	2071	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
	2072	* @param DMAx DMAx Instance
	2073	* @param Channel This parameter can be one of the following values:
	2074	* @arg @ref LL_DMA_CHANNEL_1
	2075	* @arg @ref LL_DMA_CHANNEL_2
	2076	* @arg @ref LL_DMA_CHANNEL_3
	2077	* @arg @ref LL_DMA_CHANNEL_4
	2078	* @arg @ref LL_DMA_CHANNEL_5
	2079	* @arg @ref LL_DMA_CHANNEL_6
	2080	* @arg @ref LL_DMA_CHANNEL_7
	2081	* @retval None
	2082	*/
	2083	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
	2084	{
	2085	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
	2086	}
	2087
	2088	/**
	2089	* @brief Disable Half transfer interrupt.
	2090	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
	2091	* @param DMAx DMAx Instance
	2092	* @param Channel This parameter can be one of the following values:
	2093	* @arg @ref LL_DMA_CHANNEL_1
	2094	* @arg @ref LL_DMA_CHANNEL_2
	2095	* @arg @ref LL_DMA_CHANNEL_3
	2096	* @arg @ref LL_DMA_CHANNEL_4
	2097	* @arg @ref LL_DMA_CHANNEL_5
	2098	* @arg @ref LL_DMA_CHANNEL_6
	2099	* @arg @ref LL_DMA_CHANNEL_7
	2100	* @retval None
	2101	*/
	2102	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
	2103	{
	2104	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
	2105	}
	2106
	2107	/**
	2108	* @brief Disable Transfer error interrupt.
	2109	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
	2110	* @param DMAx DMAx Instance
	2111	* @param Channel This parameter can be one of the following values:
	2112	* @arg @ref LL_DMA_CHANNEL_1
	2113	* @arg @ref LL_DMA_CHANNEL_2
	2114	* @arg @ref LL_DMA_CHANNEL_3
	2115	* @arg @ref LL_DMA_CHANNEL_4
	2116	* @arg @ref LL_DMA_CHANNEL_5
	2117	* @arg @ref LL_DMA_CHANNEL_6
	2118	* @arg @ref LL_DMA_CHANNEL_7
	2119	* @retval None
	2120	*/
	2121	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
	2122	{
	2123	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
	2124	}
	2125
	2126	/**
	2127	* @brief Check if Transfer complete Interrupt is enabled.
	2128	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
	2129	* @param DMAx DMAx Instance
	2130	* @param Channel This parameter can be one of the following values:
	2131	* @arg @ref LL_DMA_CHANNEL_1
	2132	* @arg @ref LL_DMA_CHANNEL_2
	2133	* @arg @ref LL_DMA_CHANNEL_3
	2134	* @arg @ref LL_DMA_CHANNEL_4
	2135	* @arg @ref LL_DMA_CHANNEL_5
	2136	* @arg @ref LL_DMA_CHANNEL_6
	2137	* @arg @ref LL_DMA_CHANNEL_7
	2138	* @retval State of bit (1 or 0).
	2139	*/
	2140	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
	2141	{
	2142	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	2143	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
	2144	}
	2145
	2146	/**
	2147	* @brief Check if Half transfer Interrupt is enabled.
	2148	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
	2149	* @param DMAx DMAx Instance
	2150	* @param Channel This parameter can be one of the following values:
	2151	* @arg @ref LL_DMA_CHANNEL_1
	2152	* @arg @ref LL_DMA_CHANNEL_2
	2153	* @arg @ref LL_DMA_CHANNEL_3
	2154	* @arg @ref LL_DMA_CHANNEL_4
	2155	* @arg @ref LL_DMA_CHANNEL_5
	2156	* @arg @ref LL_DMA_CHANNEL_6
	2157	* @arg @ref LL_DMA_CHANNEL_7
	2158	* @retval State of bit (1 or 0).
	2159	*/
	2160	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
	2161	{
	2162	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	2163	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
	2164	}
	2165
	2166	/**
	2167	* @brief Check if Transfer error Interrupt is enabled.
	2168	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
	2169	* @param DMAx DMAx Instance
	2170	* @param Channel This parameter can be one of the following values:
	2171	* @arg @ref LL_DMA_CHANNEL_1
	2172	* @arg @ref LL_DMA_CHANNEL_2
	2173	* @arg @ref LL_DMA_CHANNEL_3
	2174	* @arg @ref LL_DMA_CHANNEL_4
	2175	* @arg @ref LL_DMA_CHANNEL_5
	2176	* @arg @ref LL_DMA_CHANNEL_6
	2177	* @arg @ref LL_DMA_CHANNEL_7
	2178	* @retval State of bit (1 or 0).
	2179	*/
	2180	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
	2181	{
	2182	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
	2183	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
	2184	}
	2185
	2186	/**
	2187	* @}
	2188	*/
	2189
	2190	#if defined(USE_FULL_LL_DRIVER)
	2191	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
	2192	* @{
	2193	*/
	2194
	2195	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
	2196	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
	2197	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
	2198
	2199	/**
	2200	* @}
	2201	*/
	2202	#endif /* USE_FULL_LL_DRIVER */
	2203
	2204	/**
	2205	* @}
	2206	*/
	2207
	2208	/**
	2209	* @}
	2210	*/
	2211
	2212	#endif /* DMA1 \|\| DMA2 */
	2213
	2214	/**
	2215	* @}
	2216	*/
	2217
	2218	#ifdef __cplusplus
	2219	}
	2220	#endif
	2221
	2222	#endif /* __STM32F0xx_LL_DMA_H */
	2223
	2224	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/