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483170	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_ll_adc.h
	4	* @author MCD Application Team
	5	* @brief Header file of ADC LL module.
	6	******************************************************************************
	7	* @attention
	8	*
	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	10	*
	11	* Redistribution and use in source and binary forms, with or without modification,
	12	* are permitted provided that the following conditions are met:
	13	* 1. Redistributions of source code must retain the above copyright notice,
	14	* this list of conditions and the following disclaimer.
	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	19	* may be used to endorse or promote products derived from this software
	20	* without specific prior written permission.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	******************************************************************************
	34	*/
	35
	36	/* Define to prevent recursive inclusion -------------------------------------*/
	37	#ifndef __STM32F0xx_LL_ADC_H
	38	#define __STM32F0xx_LL_ADC_H
	39
	40	#ifdef __cplusplus
	41	extern "C" {
	42	#endif
	43
	44	/* Includes ------------------------------------------------------------------*/
	45	#include "stm32f0xx.h"
	46
	47	/** @addtogroup STM32F0xx_LL_Driver
	48	* @{
	49	*/
	50
	51	#if defined (ADC1)
	52
	53	/** @defgroup ADC_LL ADC
	54	* @{
	55	*/
	56
	57	/* Private types -------------------------------------------------------------*/
	58	/* Private variables ---------------------------------------------------------*/
	59
	60	/* Private constants ---------------------------------------------------------*/
	61	/** @defgroup ADC_LL_Private_Constants ADC Private Constants
	62	* @{
	63	*/
	64
	65	/* Internal mask for ADC group regular trigger: */
	66	/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
	67	/* - regular trigger source */
	68	/* - regular trigger edge */
	69	#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
	70
	71	/* Mask containing trigger source masks for each of possible */
	72	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
	73	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
	74	#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0U)) \| \
	75	((ADC_CFGR1_EXTSEL) << (4U * 1U)) \| \
	76	((ADC_CFGR1_EXTSEL) << (4U * 2U)) \| \
	77	((ADC_CFGR1_EXTSEL) << (4U * 3U)) )
	78
	79	/* Mask containing trigger edge masks for each of possible */
	80	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
	81	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
	82	#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0U)) \| \
	83	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) \| \
	84	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) \| \
	85	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
	86
	87	/* Definition of ADC group regular trigger bits information. */
	88	#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */
	89	#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */
	90
	91
	92
	93	/* Internal mask for ADC channel: */
	94	/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
	95	/* - channel identifier defined by number */
	96	/* - channel identifier defined by bitfield */
	97	/* - channel differentiation between external channels (connected to */
	98	/* GPIO pins) and internal channels (connected to internal paths) */
	99	#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWDCH)
	100	#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
	101	#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
	102	#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_BITFIELD_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
	103	/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
	104	#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
	105
	106	/* Channel differentiation between external and internal channels */
	107	#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */
	108	#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
	109
	110	/* Definition of channels ID number information to be inserted into */
	111	/* channels literals definition. */
	112	#define ADC_CHANNEL_0_NUMBER (0x00000000U)
	113	#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR1_AWDCH_0)
	114	#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR1_AWDCH_1 )
	115	#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
	116	#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR1_AWDCH_2 )
	117	#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_0)
	118	#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 )
	119	#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
	120	#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR1_AWDCH_3 )
	121	#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_0)
	122	#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_1 )
	123	#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
	124	#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 )
	125	#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_0)
	126	#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 )
	127	#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
	128	#define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWDCH_4 )
	129	#define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWDCH_4 \| ADC_CFGR1_AWDCH_0)
	130	#define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWDCH_4 \| ADC_CFGR1_AWDCH_1 )
	131
	132	/* Definition of channels ID bitfield information to be inserted into */
	133	/* channels literals definition. */
	134	#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
	135	#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
	136	#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
	137	#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
	138	#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
	139	#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
	140	#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
	141	#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
	142	#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
	143	#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
	144	#define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
	145	#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
	146	#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
	147	#define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
	148	#define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
	149	#define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
	150	#define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
	151	#define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
	152	#define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
	153
	154	/* Internal mask for ADC analog watchdog: */
	155	/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
	156	/* (concatenation of multiple bits used in different analog watchdogs, */
	157	/* (feature of several watchdogs not available on all STM32 families)). */
	158	/* - analog watchdog 1: monitored channel defined by number, */
	159	/* selection of ADC group (ADC group regular). */
	160
	161	/* Internal register offset for ADC analog watchdog channel configuration */
	162	#define ADC_AWD_CR1_REGOFFSET (0x00000000U)
	163
	164	#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
	165
	166	#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL)
	167	#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
	168
	169	/* Internal register offset for ADC analog watchdog threshold configuration */
	170	#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
	171	#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET)
	172
	173
	174	/* ADC registers bits positions */
	175	#define ADC_CFGR1_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */
	176	#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */
	177	#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
	178	#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */
	179	#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */
	180	#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */
	181	#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */
	182	#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */
	183	#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */
	184	#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */
	185	#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */
	186	#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */
	187	#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */
	188	#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */
	189	#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */
	190	#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */
	191	#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */
	192	#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */
	193	#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */
	194	#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */
	195	#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */
	196	#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */
	197
	198
	199	/* ADC registers bits groups */
	200	#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL \| ADC_CR_ADSTP \| ADC_CR_ADSTART \| ADC_CR_ADDIS \| ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
	201
	202
	203	/* ADC internal channels related definitions */
	204	/* Internal voltage reference VrefInt */
	205	#define VREFINT_CAL_ADDR ((uint16_t) (0x1FFFF7BAU)) / Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
	206	#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
	207	/* Temperature sensor */
	208	#define TEMPSENSOR_CAL1_ADDR ((uint16_t) (0x1FFFF7B8U)) / Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
	209	#define TEMPSENSOR_CAL2_ADDR ((uint16_t) (0x1FFFF7C2U)) / Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
	210	#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
	211	#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
	212	#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
	213
	214
	215	/**
	216	* @}
	217	*/
	218
	219
	220	/* Exported types ------------------------------------------------------------*/
	221	#if defined(USE_FULL_LL_DRIVER)
	222	/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
	223	* @{
	224	*/
	225
	226	/**
	227	* @brief Structure definition of some features of ADC instance.
	228	* @note These parameters have an impact on ADC scope: ADC instance.
	229	* Refer to corresponding unitary functions into
	230	* @ref ADC_LL_EF_Configuration_ADC_Instance .
	231	* @note The setting of these parameters by function @ref LL_ADC_Init()
	232	* is conditioned to ADC state:
	233	* ADC instance must be disabled.
	234	* This condition is applied to all ADC features, for efficiency
	235	* and compatibility over all STM32 families. However, the different
	236	* features can be set under different ADC state conditions
	237	* (setting possible with ADC enabled without conversion on going,
	238	* ADC enabled with conversion on going, ...)
	239	* Each feature can be updated afterwards with a unitary function
	240	* and potentially with ADC in a different state than disabled,
	241	* refer to description of each function for setting
	242	* conditioned to ADC state.
	243	*/
	244	typedef struct
	245	{
	246	uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
	247	This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
	248	@note On this STM32 serie, this parameter has some clock ratio constraints:
	249	ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
	250	(APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
	251
	252
	253	This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
	254	For more details, refer to description of this function. */
	255
	256	uint32_t Resolution; /*!< Set ADC resolution.
	257	This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
	258
	259	This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
	260
	261	uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
	262	This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
	263
	264	This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
	265
	266	uint32_t LowPowerMode; /*!< Set ADC low power mode.
	267	This parameter can be a value of @ref ADC_LL_EC_LP_MODE
	268
	269	This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
	270
	271	} LL_ADC_InitTypeDef;
	272
	273	/**
	274	* @brief Structure definition of some features of ADC group regular.
	275	* @note These parameters have an impact on ADC scope: ADC group regular.
	276	* Refer to corresponding unitary functions into
	277	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
	278	* (functions with prefix "REG").
	279	* @note The setting of these parameters by function @ref LL_ADC_REG_Init()
	280	* is conditioned to ADC state:
	281	* ADC instance must be disabled.
	282	* This condition is applied to all ADC features, for efficiency
	283	* and compatibility over all STM32 families. However, the different
	284	* features can be set under different ADC state conditions
	285	* (setting possible with ADC enabled without conversion on going,
	286	* ADC enabled with conversion on going, ...)
	287	* Each feature can be updated afterwards with a unitary function
	288	* and potentially with ADC in a different state than disabled,
	289	* refer to description of each function for setting
	290	* conditioned to ADC state.
	291	*/
	292	typedef struct
	293	{
	294	uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
	295	This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
	296	@note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
	297	(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
	298	In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
	299
	300	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
	301
	302	uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
	303	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
	304	@note This parameter has an effect only if group regular sequencer is enabled
	305	(several ADC channels enabled in group regular sequencer).
	306
	307	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
	308
	309	uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
	310	This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
	311	Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
	312
	313	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
	314
	315	uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
	316	This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
	317
	318	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
	319
	320	uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
	321	data preserved or overwritten.
	322	This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
	323
	324	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
	325
	326	} LL_ADC_REG_InitTypeDef;
	327
	328	/**
	329	* @}
	330	*/
	331	#endif /* USE_FULL_LL_DRIVER */
	332
	333	/* Exported constants --------------------------------------------------------*/
	334	/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
	335	* @{
	336	*/
	337
	338	/** @defgroup ADC_LL_EC_FLAG ADC flags
	339	* @brief Flags defines which can be used with LL_ADC_ReadReg function
	340	* @{
	341	*/
	342	#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /!< ADC flag ADC instance ready /
	343	#define LL_ADC_FLAG_EOC ADC_ISR_EOC /!< ADC flag ADC group regular end of unitary conversion /
	344	#define LL_ADC_FLAG_EOS ADC_ISR_EOS /!< ADC flag ADC group regular end of sequence conversions /
	345	#define LL_ADC_FLAG_OVR ADC_ISR_OVR /!< ADC flag ADC group regular overrun /
	346	#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC flag ADC group regular end of sampling phase /
	347	#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD /!< ADC flag ADC analog watchdog 1 /
	348	/**
	349	* @}
	350	*/
	351
	352	/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
	353	* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
	354	* @{
	355	*/
	356	#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /!< ADC interruption ADC instance ready /
	357	#define LL_ADC_IT_EOC ADC_IER_EOCIE /!< ADC interruption ADC group regular end of unitary conversion /
	358	#define LL_ADC_IT_EOS ADC_IER_EOSIE /!< ADC interruption ADC group regular end of sequence conversions /
	359	#define LL_ADC_IT_OVR ADC_IER_OVRIE /!< ADC interruption ADC group regular overrun /
	360	#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /!< ADC interruption ADC group regular end of sampling phase /
	361	#define LL_ADC_IT_AWD1 ADC_IER_AWDIE /!< ADC interruption ADC analog watchdog 1 /
	362	/**
	363	* @}
	364	*/
	365
	366	/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
	367	* @{
	368	*/
	369	/* List of ADC registers intended to be used (most commonly) with */
	370	/* DMA transfer. */
	371	/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
	372	#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
	373	/**
	374	* @}
	375	*/
	376
	377	/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
	378	* @{
	379	*/
	380	/* Note: Other measurement paths to internal channels may be available */
	381	/* (connections to other peripherals). */
	382	/* If they are not listed below, they do not require any specific */
	383	/* path enable. In this case, Access to measurement path is done */
	384	/* only by selecting the corresponding ADC internal channel. */
	385	#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/!< ADC measurement pathes all disabled /
	386	#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /!< ADC measurement path to internal channel VrefInt /
	387	#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /!< ADC measurement path to internal channel temperature sensor /
	388	#if defined(ADC_CCR_VBATEN)
	389	#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /!< ADC measurement path to internal channel Vbat /
	390	#endif
	391	/**
	392	* @}
	393	*/
	394
	395	/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
	396	* @{
	397	*/
	398	#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /!< ADC synchronous clock derived from AHB clock divided by 4 /
	399	#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /!< ADC synchronous clock derived from AHB clock divided by 2 /
	400	#define LL_ADC_CLOCK_ASYNC (0x00000000U) /!< ADC asynchronous clock. On this STM32 serie, asynchronous clock has no prescaler. /
	401	/**
	402	* @}
	403	*/
	404
	405	/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
	406	* @{
	407	*/
	408	#define LL_ADC_RESOLUTION_12B (0x00000000U) /!< ADC resolution 12 bits /
	409	#define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /!< ADC resolution 10 bits /
	410	#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /!< ADC resolution 8 bits /
	411	#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 \| ADC_CFGR1_RES_0) /!< ADC resolution 6 bits /
	412	/**
	413	* @}
	414	*/
	415
	416	/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
	417	* @{
	418	*/
	419	#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)/
	420	#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)/
	421	/**
	422	* @}
	423	*/
	424
	425	/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
	426	* @{
	427	*/
	428	#define LL_ADC_LP_MODE_NONE (0x00000000U) /!< No ADC low power mode activated /
	429	#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). /
	430	#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). Note: On STM32F0, if enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) during auto wait phase. /
	431	#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT \| ADC_CFGR1_AUTOFF) /!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). /
	432	/**
	433	* @}
	434	*/
	435
	436	/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
	437	* @{
	438	*/
	439	#define LL_ADC_GROUP_REGULAR (0x00000001U) /!< ADC group regular (available on all STM32 devices) /
	440	/**
	441	* @}
	442	*/
	443
	444	/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
	445	* @{
	446	*/
	447	#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \| ADC_CHANNEL_0_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 /
	448	#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \| ADC_CHANNEL_1_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 /
	449	#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \| ADC_CHANNEL_2_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 /
	450	#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \| ADC_CHANNEL_3_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 /
	451	#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \| ADC_CHANNEL_4_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 /
	452	#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \| ADC_CHANNEL_5_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 /
	453	#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \| ADC_CHANNEL_6_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 /
	454	#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \| ADC_CHANNEL_7_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 /
	455	#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \| ADC_CHANNEL_8_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 /
	456	#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \| ADC_CHANNEL_9_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 /
	457	#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \| ADC_CHANNEL_10_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 /
	458	#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \| ADC_CHANNEL_11_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 /
	459	#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \| ADC_CHANNEL_12_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 /
	460	#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \| ADC_CHANNEL_13_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 /
	461	#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \| ADC_CHANNEL_14_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 /
	462	#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \| ADC_CHANNEL_15_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 /
	463	#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \| ADC_CHANNEL_16_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 /
	464	#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \| ADC_CHANNEL_17_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 /
	465	#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to VrefInt: Internal voltage reference. /
	466	#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Temperature sensor. /
	467	#if defined(ADC_CCR_VBATEN)
	468	#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \| ADC_CHANNEL_18_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 /
	469	#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda. /
	470	#endif
	471	/**
	472	* @}
	473	*/
	474
	475	/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
	476	* @{
	477	*/
	478	#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /!< ADC group regular conversion trigger internal: SW start. /
	479	#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). /
	480	#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
	481	#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
	482	#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 \| ADC_CFGR1_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). /
	483	#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). /
	484	/**
	485	* @}
	486	*/
	487
	488	/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
	489	* @{
	490	*/
	491	#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /!< ADC group regular conversion trigger polarity set to rising edge /
	492	#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /!< ADC group regular conversion trigger polarity set to falling edge /
	493	#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 \| ADC_CFGR1_EXTEN_0) /!< ADC group regular conversion trigger polarity set to both rising and falling edges /
	494	/**
	495	* @}
	496	*/
	497
	498	/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
	499	* @{
	500	*/
	501	#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /!< ADC conversions are performed in single mode: one conversion per trigger /
	502	#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically /
	503	/**
	504	* @}
	505	*/
	506
	507	/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
	508	* @{
	509	*/
	510	#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /!< ADC conversions are not transferred by DMA /
	511	#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. /
	512	#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG \| ADC_CFGR1_DMAEN) /!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. /
	513	/**
	514	* @}
	515	*/
	516
	517	/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
	518	* @{
	519	*/
	520	#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U)/!< ADC group regular behavior in case of overrun: data preserved /
	521	#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /!< ADC group regular behavior in case of overrun: data overwritten /
	522	/**
	523	* @}
	524	*/
	525
	526	/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
	527	* @{
	528	*/
	529	#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000U)/!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. /
	530	#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) /
	531	/**
	532	* @}
	533	*/
	534
	535	/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
	536	* @{
	537	*/
	538	#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /!< ADC group regular sequencer discontinuous mode disable /
	539	#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank /
	540	/**
	541	* @}
	542	*/
	543
	544	/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
	545	* @{
	546	*/
	547	#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000U) /!< Sampling time 1.5 ADC clock cycle /
	548	#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP_0) /!< Sampling time 7.5 ADC clock cycles /
	549	#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR_SMP_1) /!< Sampling time 13.5 ADC clock cycles /
	550	#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR_SMP_1 \| ADC_SMPR_SMP_0) /!< Sampling time 28.5 ADC clock cycles /
	551	#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR_SMP_2) /!< Sampling time 41.5 ADC clock cycles /
	552	#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR_SMP_2 \| ADC_SMPR_SMP_0) /!< Sampling time 55.5 ADC clock cycles /
	553	#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR_SMP_2 \| ADC_SMPR_SMP_1) /!< Sampling time 71.5 ADC clock cycles /
	554	#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR_SMP_2 \| ADC_SMPR_SMP_1 \| ADC_SMPR_SMP_0) /!< Sampling time 239.5 ADC clock cycles /
	555	/**
	556	* @}
	557	*/
	558
	559	/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
	560	* @{
	561	*/
	562	#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /!< ADC analog watchdog number 1 /
	563	/**
	564	* @}
	565	*/
	566
	567	/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
	568	* @{
	569	*/
	570	#define LL_ADC_AWD_DISABLE (0x00000000U) /!< ADC analog watchdog monitoring disabled /
	571	#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by group regular only /
	572	#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only /
	573	#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only /
	574	#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only /
	575	#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only /
	576	#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only /
	577	#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only /
	578	#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only /
	579	#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only /
	580	#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only /
	581	#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only /
	582	#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only /
	583	#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only /
	584	#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only /
	585	#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only /
	586	#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only /
	587	#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only /
	588	#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only /
	589	#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only /
	590	#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only /
	591	#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only /
	592	#if defined(ADC_CCR_VBATEN)
	593	#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only /
	594	#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only /
	595	#endif
	596	/**
	597	* @}
	598	*/
	599
	600	/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
	601	* @{
	602	*/
	603	#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR_HT ) /!< ADC analog watchdog threshold high /
	604	#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR_LT) /!< ADC analog watchdog threshold low /
	605	#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR_HT \| ADC_TR_LT) /!< ADC analog watchdog both thresholds high and low concatenated into the same data /
	606	/**
	607	* @}
	608	*/
	609
	610
	611	/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
	612	* @note Only ADC IP HW delays are defined in ADC LL driver driver,
	613	* not timeout values.
	614	* For details on delays values, refer to descriptions in source code
	615	* above each literal definition.
	616	* @{
	617	*/
	618
	619	/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
	620	/* not timeout values. */
	621	/* Timeout values for ADC operations are dependent to device clock */
	622	/* configuration (system clock versus ADC clock), */
	623	/* and therefore must be defined in user application. */
	624	/* Indications for estimation of ADC timeout delays, for this */
	625	/* STM32 serie: */
	626	/* - ADC calibration time: maximum delay is 83/fADC. */
	627	/* (refer to device datasheet, parameter "tCAL") */
	628	/* - ADC enable time: maximum delay is 1 conversion cycle. */
	629	/* (refer to device datasheet, parameter "tSTAB") */
	630	/* - ADC disable time: maximum delay should be a few ADC clock cycles */
	631	/* - ADC stop conversion time: maximum delay should be a few ADC clock */
	632	/* cycles */
	633	/* - ADC conversion time: duration depending on ADC clock and ADC */
	634	/* configuration. */
	635	/* (refer to device reference manual, section "Timing") */
	636
	637
	638	/* Delay for internal voltage reference stabilization time. */
	639	/* Delay set to maximum value (refer to device datasheet, */
	640	/* parameter "tSTART"). */
	641	/* Unit: us */
	642	#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /!< Delay for internal voltage reference stabilization time /
	643
	644	/* Delay for temperature sensor stabilization time. */
	645	/* Literal set to maximum value (refer to device datasheet, */
	646	/* parameter "tSTART"). */
	647	/* Unit: us */
	648	#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /!< Delay for temperature sensor stabilization time /
	649
	650	/* Delay required between ADC end of calibration and ADC enable. */
	651	/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
	652	/* are required between ADC end of calibration and ADC enable. */
	653	/* Wait time can be computed in user application by waiting for the */
	654	/* equivalent number of CPU cycles, by taking into account */
	655	/* ratio of CPU clock versus ADC clock prescalers. */
	656	/* Unit: ADC clock cycles. */
	657	#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2U) /!< Delay required between ADC end of calibration and ADC enable /
	658
	659	/**
	660	* @}
	661	*/
	662
	663	/**
	664	* @}
	665	*/
	666
	667
	668	/* Exported macro ------------------------------------------------------------*/
	669	/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
	670	* @{
	671	*/
	672
	673	/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
	674	* @{
	675	*/
	676
	677	/**
	678	* @brief Write a value in ADC register
	679	* @param __INSTANCE__ ADC Instance
	680	* @param __REG__ Register to be written
	681	* @param __VALUE__ Value to be written in the register
	682	* @retval None
	683	*/
	684	#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
	685
	686	/**
	687	* @brief Read a value in ADC register
	688	* @param __INSTANCE__ ADC Instance
	689	* @param __REG__ Register to be read
	690	* @retval Register value
	691	*/
	692	#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
	693	/**
	694	* @}
	695	*/
	696
	697	/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
	698	* @{
	699	*/
	700
	701	/**
	702	* @brief Helper macro to get ADC channel number in decimal format
	703	* from literals LL_ADC_CHANNEL_x.
	704	* @note Example:
	705	* __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
	706	* will return decimal number "4".
	707	* @note The input can be a value from functions where a channel
	708	* number is returned, either defined with number
	709	* or with bitfield (only one bit must be set).
	710	* @param __CHANNEL__ This parameter can be one of the following values:
	711	* @arg @ref LL_ADC_CHANNEL_0
	712	* @arg @ref LL_ADC_CHANNEL_1
	713	* @arg @ref LL_ADC_CHANNEL_2
	714	* @arg @ref LL_ADC_CHANNEL_3
	715	* @arg @ref LL_ADC_CHANNEL_4
	716	* @arg @ref LL_ADC_CHANNEL_5
	717	* @arg @ref LL_ADC_CHANNEL_6
	718	* @arg @ref LL_ADC_CHANNEL_7
	719	* @arg @ref LL_ADC_CHANNEL_8
	720	* @arg @ref LL_ADC_CHANNEL_9
	721	* @arg @ref LL_ADC_CHANNEL_10
	722	* @arg @ref LL_ADC_CHANNEL_11
	723	* @arg @ref LL_ADC_CHANNEL_12
	724	* @arg @ref LL_ADC_CHANNEL_13
	725	* @arg @ref LL_ADC_CHANNEL_14
	726	* @arg @ref LL_ADC_CHANNEL_15
	727	* @arg @ref LL_ADC_CHANNEL_16
	728	* @arg @ref LL_ADC_CHANNEL_17
	729	* @arg @ref LL_ADC_CHANNEL_18 (1)
	730	* @arg @ref LL_ADC_CHANNEL_VREFINT
	731	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
	732	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
	733	*
	734	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	735	* @retval Value between Min_Data=0 and Max_Data=18
	736	*/
	737	#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
	738	((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
	739	? ( \
	740	((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
	741	) \
	742	: \
	743	( \
	744	(((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) : \
	745	( \
	746	(((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) : \
	747	( \
	748	(((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) : \
	749	( \
	750	(((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) : \
	751	( \
	752	(((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) : \
	753	( \
	754	(((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) : \
	755	( \
	756	(((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) : \
	757	( \
	758	(((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) : \
	759	( \
	760	(((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) : \
	761	( \
	762	(((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) : \
	763	( \
	764	(((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) : \
	765	( \
	766	(((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) : \
	767	( \
	768	(((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) : \
	769	( \
	770	(((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13U) : \
	771	( \
	772	(((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? (14U) : \
	773	( \
	774	(((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? (15U) : \
	775	( \
	776	(((__CHANNEL__) & ADC_CHSELR_CHSEL16) == ADC_CHSELR_CHSEL16) ? (16U) : \
	777	( \
	778	(((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) ? (17U) : \
	779	( \
	780	(((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL18) ? (18U) : \
	781	(0U) \
	782	) \
	783	) \
	784	) \
	785	) \
	786	) \
	787	) \
	788	) \
	789	) \
	790	) \
	791	) \
	792	) \
	793	) \
	794	) \
	795	) \
	796	) \
	797	) \
	798	) \
	799	) \
	800	) \
	801	)
	802
	803	/**
	804	* @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
	805	* from number in decimal format.
	806	* @note Example:
	807	* __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
	808	* will return a data equivalent to "LL_ADC_CHANNEL_4".
	809	* @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
	810	* @retval Returned value can be one of the following values:
	811	* @arg @ref LL_ADC_CHANNEL_0
	812	* @arg @ref LL_ADC_CHANNEL_1
	813	* @arg @ref LL_ADC_CHANNEL_2
	814	* @arg @ref LL_ADC_CHANNEL_3
	815	* @arg @ref LL_ADC_CHANNEL_4
	816	* @arg @ref LL_ADC_CHANNEL_5
	817	* @arg @ref LL_ADC_CHANNEL_6
	818	* @arg @ref LL_ADC_CHANNEL_7
	819	* @arg @ref LL_ADC_CHANNEL_8
	820	* @arg @ref LL_ADC_CHANNEL_9
	821	* @arg @ref LL_ADC_CHANNEL_10
	822	* @arg @ref LL_ADC_CHANNEL_11
	823	* @arg @ref LL_ADC_CHANNEL_12
	824	* @arg @ref LL_ADC_CHANNEL_13
	825	* @arg @ref LL_ADC_CHANNEL_14
	826	* @arg @ref LL_ADC_CHANNEL_15
	827	* @arg @ref LL_ADC_CHANNEL_16
	828	* @arg @ref LL_ADC_CHANNEL_17
	829	* @arg @ref LL_ADC_CHANNEL_18 (1)
	830	* @arg @ref LL_ADC_CHANNEL_VREFINT (2)
	831	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
	832	* @arg @ref LL_ADC_CHANNEL_VBAT (1)(2)
	833	*
	834	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.\n
	835	* (2) For ADC channel read back from ADC register,
	836	* comparison with internal channel parameter to be done
	837	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
	838	*/
	839	#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
	840	( \
	841	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
	842	(ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \
	843	)
	844
	845	/**
	846	* @brief Helper macro to determine whether the selected channel
	847	* corresponds to literal definitions of driver.
	848	* @note The different literal definitions of ADC channels are:
	849	* - ADC internal channel:
	850	* LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
	851	* - ADC external channel (channel connected to a GPIO pin):
	852	* LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
	853	* @note The channel parameter must be a value defined from literal
	854	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
	855	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
	856	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
	857	* must not be a value from functions where a channel number is
	858	* returned from ADC registers,
	859	* because internal and external channels share the same channel
	860	* number in ADC registers. The differentiation is made only with
	861	* parameters definitions of driver.
	862	* @param __CHANNEL__ This parameter can be one of the following values:
	863	* @arg @ref LL_ADC_CHANNEL_0
	864	* @arg @ref LL_ADC_CHANNEL_1
	865	* @arg @ref LL_ADC_CHANNEL_2
	866	* @arg @ref LL_ADC_CHANNEL_3
	867	* @arg @ref LL_ADC_CHANNEL_4
	868	* @arg @ref LL_ADC_CHANNEL_5
	869	* @arg @ref LL_ADC_CHANNEL_6
	870	* @arg @ref LL_ADC_CHANNEL_7
	871	* @arg @ref LL_ADC_CHANNEL_8
	872	* @arg @ref LL_ADC_CHANNEL_9
	873	* @arg @ref LL_ADC_CHANNEL_10
	874	* @arg @ref LL_ADC_CHANNEL_11
	875	* @arg @ref LL_ADC_CHANNEL_12
	876	* @arg @ref LL_ADC_CHANNEL_13
	877	* @arg @ref LL_ADC_CHANNEL_14
	878	* @arg @ref LL_ADC_CHANNEL_15
	879	* @arg @ref LL_ADC_CHANNEL_16
	880	* @arg @ref LL_ADC_CHANNEL_17
	881	* @arg @ref LL_ADC_CHANNEL_18 (1)
	882	* @arg @ref LL_ADC_CHANNEL_VREFINT
	883	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
	884	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
	885	*
	886	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	887	* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
	888	* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
	889	*/
	890	#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
	891	(((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
	892
	893	/**
	894	* @brief Helper macro to convert a channel defined from parameter
	895	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
	896	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
	897	* to its equivalent parameter definition of a ADC external channel
	898	* (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
	899	* @note The channel parameter can be, additionally to a value
	900	* defined from parameter definition of a ADC internal channel
	901	* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
	902	* a value defined from parameter definition of
	903	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
	904	* or a value from functions where a channel number is returned
	905	* from ADC registers.
	906	* @param __CHANNEL__ This parameter can be one of the following values:
	907	* @arg @ref LL_ADC_CHANNEL_0
	908	* @arg @ref LL_ADC_CHANNEL_1
	909	* @arg @ref LL_ADC_CHANNEL_2
	910	* @arg @ref LL_ADC_CHANNEL_3
	911	* @arg @ref LL_ADC_CHANNEL_4
	912	* @arg @ref LL_ADC_CHANNEL_5
	913	* @arg @ref LL_ADC_CHANNEL_6
	914	* @arg @ref LL_ADC_CHANNEL_7
	915	* @arg @ref LL_ADC_CHANNEL_8
	916	* @arg @ref LL_ADC_CHANNEL_9
	917	* @arg @ref LL_ADC_CHANNEL_10
	918	* @arg @ref LL_ADC_CHANNEL_11
	919	* @arg @ref LL_ADC_CHANNEL_12
	920	* @arg @ref LL_ADC_CHANNEL_13
	921	* @arg @ref LL_ADC_CHANNEL_14
	922	* @arg @ref LL_ADC_CHANNEL_15
	923	* @arg @ref LL_ADC_CHANNEL_16
	924	* @arg @ref LL_ADC_CHANNEL_17
	925	* @arg @ref LL_ADC_CHANNEL_18 (1)
	926	* @arg @ref LL_ADC_CHANNEL_VREFINT
	927	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
	928	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
	929	*
	930	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	931	* @retval Returned value can be one of the following values:
	932	* @arg @ref LL_ADC_CHANNEL_0
	933	* @arg @ref LL_ADC_CHANNEL_1
	934	* @arg @ref LL_ADC_CHANNEL_2
	935	* @arg @ref LL_ADC_CHANNEL_3
	936	* @arg @ref LL_ADC_CHANNEL_4
	937	* @arg @ref LL_ADC_CHANNEL_5
	938	* @arg @ref LL_ADC_CHANNEL_6
	939	* @arg @ref LL_ADC_CHANNEL_7
	940	* @arg @ref LL_ADC_CHANNEL_8
	941	* @arg @ref LL_ADC_CHANNEL_9
	942	* @arg @ref LL_ADC_CHANNEL_10
	943	* @arg @ref LL_ADC_CHANNEL_11
	944	* @arg @ref LL_ADC_CHANNEL_12
	945	* @arg @ref LL_ADC_CHANNEL_13
	946	* @arg @ref LL_ADC_CHANNEL_14
	947	* @arg @ref LL_ADC_CHANNEL_15
	948	* @arg @ref LL_ADC_CHANNEL_16
	949	* @arg @ref LL_ADC_CHANNEL_17
	950	* @arg @ref LL_ADC_CHANNEL_18
	951	*/
	952	#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
	953	((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
	954
	955	/**
	956	* @brief Helper macro to determine whether the internal channel
	957	* selected is available on the ADC instance selected.
	958	* @note The channel parameter must be a value defined from parameter
	959	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
	960	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
	961	* must not be a value defined from parameter definition of
	962	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
	963	* or a value from functions where a channel number is
	964	* returned from ADC registers,
	965	* because internal and external channels share the same channel
	966	* number in ADC registers. The differentiation is made only with
	967	* parameters definitions of driver.
	968	* @param __ADC_INSTANCE__ ADC instance
	969	* @param __CHANNEL__ This parameter can be one of the following values:
	970	* @arg @ref LL_ADC_CHANNEL_VREFINT
	971	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
	972	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
	973	*
	974	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	975	* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
	976	* Value "1" if the internal channel selected is available on the ADC instance selected.
	977	*/
	978	#if defined(ADC_CCR_VBATEN)
	979	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
	980	( \
	981	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
	982	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
	983	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
	984	)
	985	#else
	986	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
	987	( \
	988	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
	989	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
	990	)
	991	#endif
	992
	993	/**
	994	* @brief Helper macro to define ADC analog watchdog parameter:
	995	* define a single channel to monitor with analog watchdog
	996	* from sequencer channel and groups definition.
	997	* @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
	998	* Example:
	999	* LL_ADC_SetAnalogWDMonitChannels(
	1000	* ADC1, LL_ADC_AWD1,
	1001	* __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
	1002	* @param __CHANNEL__ This parameter can be one of the following values:
	1003	* @arg @ref LL_ADC_CHANNEL_0
	1004	* @arg @ref LL_ADC_CHANNEL_1
	1005	* @arg @ref LL_ADC_CHANNEL_2
	1006	* @arg @ref LL_ADC_CHANNEL_3
	1007	* @arg @ref LL_ADC_CHANNEL_4
	1008	* @arg @ref LL_ADC_CHANNEL_5
	1009	* @arg @ref LL_ADC_CHANNEL_6
	1010	* @arg @ref LL_ADC_CHANNEL_7
	1011	* @arg @ref LL_ADC_CHANNEL_8
	1012	* @arg @ref LL_ADC_CHANNEL_9
	1013	* @arg @ref LL_ADC_CHANNEL_10
	1014	* @arg @ref LL_ADC_CHANNEL_11
	1015	* @arg @ref LL_ADC_CHANNEL_12
	1016	* @arg @ref LL_ADC_CHANNEL_13
	1017	* @arg @ref LL_ADC_CHANNEL_14
	1018	* @arg @ref LL_ADC_CHANNEL_15
	1019	* @arg @ref LL_ADC_CHANNEL_16
	1020	* @arg @ref LL_ADC_CHANNEL_17
	1021	* @arg @ref LL_ADC_CHANNEL_18 (1)
	1022	* @arg @ref LL_ADC_CHANNEL_VREFINT (2)
	1023	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
	1024	* @arg @ref LL_ADC_CHANNEL_VBAT (1)(2)
	1025	*
	1026	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.\n
	1027	* (2) For ADC channel read back from ADC register,
	1028	* comparison with internal channel parameter to be done
	1029	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
	1030	* @param __GROUP__ This parameter can be one of the following values:
	1031	* @arg @ref LL_ADC_GROUP_REGULAR
	1032	* @retval Returned value can be one of the following values:
	1033	* @arg @ref LL_ADC_AWD_DISABLE
	1034	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
	1035	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
	1036	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
	1037	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
	1038	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
	1039	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
	1040	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
	1041	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
	1042	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
	1043	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
	1044	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
	1045	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
	1046	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
	1047	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
	1048	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
	1049	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
	1050	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
	1051	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
	1052	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
	1053	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
	1054	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG
	1055	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
	1056	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
	1057	*
	1058	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	1059	*/
	1060	#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
	1061	(((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL)
	1062
	1063	/**
	1064	* @brief Helper macro to set the value of ADC analog watchdog threshold high
	1065	* or low in function of ADC resolution, when ADC resolution is
	1066	* different of 12 bits.
	1067	* @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
	1068	* or @ref LL_ADC_SetAnalogWDThresholds().
	1069	* Example, with a ADC resolution of 8 bits, to set the value of
	1070	* analog watchdog threshold high (on 8 bits):
	1071	* LL_ADC_SetAnalogWDThresholds
	1072	* (< ADCx param >,
	1073	* __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
	1074	* );
	1075	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
	1076	* @arg @ref LL_ADC_RESOLUTION_12B
	1077	* @arg @ref LL_ADC_RESOLUTION_10B
	1078	* @arg @ref LL_ADC_RESOLUTION_8B
	1079	* @arg @ref LL_ADC_RESOLUTION_6B
	1080	* @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
	1081	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
	1082	*/
	1083	#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
	1084	((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
	1085
	1086	/**
	1087	* @brief Helper macro to get the value of ADC analog watchdog threshold high
	1088	* or low in function of ADC resolution, when ADC resolution is
	1089	* different of 12 bits.
	1090	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
	1091	* Example, with a ADC resolution of 8 bits, to get the value of
	1092	* analog watchdog threshold high (on 8 bits):
	1093	* < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
	1094	* (LL_ADC_RESOLUTION_8B,
	1095	* LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
	1096	* );
	1097	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
	1098	* @arg @ref LL_ADC_RESOLUTION_12B
	1099	* @arg @ref LL_ADC_RESOLUTION_10B
	1100	* @arg @ref LL_ADC_RESOLUTION_8B
	1101	* @arg @ref LL_ADC_RESOLUTION_6B
	1102	* @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
	1103	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
	1104	*/
	1105	#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
	1106	((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
	1107
	1108	/**
	1109	* @brief Helper macro to get the ADC analog watchdog threshold high
	1110	* or low from raw value containing both thresholds concatenated.
	1111	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
	1112	* Example, to get analog watchdog threshold high from the register raw value:
	1113	* __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
	1114	* @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
	1115	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
	1116	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
	1117	* @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
	1118	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
	1119	*/
	1120	#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
	1121	(((__AWD_THRESHOLD_TYPE__) == LL_ADC_AWD_THRESHOLD_LOW) \
	1122	? ( \
	1123	(__AWD_THRESHOLDS__) & LL_ADC_AWD_THRESHOLD_LOW \
	1124	) \
	1125	: \
	1126	( \
	1127	((__AWD_THRESHOLDS__) >> ADC_TR_HT_BITOFFSET_POS) & LL_ADC_AWD_THRESHOLD_LOW \
	1128	) \
	1129	)
	1130
	1131	/**
	1132	* @brief Helper macro to select the ADC common instance
	1133	* to which is belonging the selected ADC instance.
	1134	* @note ADC common register instance can be used for:
	1135	* - Set parameters common to several ADC instances
	1136	* - Multimode (for devices with several ADC instances)
	1137	* Refer to functions having argument "ADCxy_COMMON" as parameter.
	1138	* @param __ADCx__ ADC instance
	1139	* @retval ADC common register instance
	1140	*/
	1141	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
	1142	(ADC1_COMMON)
	1143
	1144	/**
	1145	* @brief Helper macro to check if all ADC instances sharing the same
	1146	* ADC common instance are disabled.
	1147	* @note This check is required by functions with setting conditioned to
	1148	* ADC state:
	1149	* All ADC instances of the ADC common group must be disabled.
	1150	* Refer to functions having argument "ADCxy_COMMON" as parameter.
	1151	* @note On devices with only 1 ADC common instance, parameter of this macro
	1152	* is useless and can be ignored (parameter kept for compatibility
	1153	* with devices featuring several ADC common instances).
	1154	* @param __ADCXY_COMMON__ ADC common instance
	1155	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
	1156	* @retval Value "0" if all ADC instances sharing the same ADC common instance
	1157	* are disabled.
	1158	* Value "1" if at least one ADC instance sharing the same ADC common instance
	1159	* is enabled.
	1160	*/
	1161	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
	1162	LL_ADC_IsEnabled(ADC1)
	1163
	1164	/**
	1165	* @brief Helper macro to define the ADC conversion data full-scale digital
	1166	* value corresponding to the selected ADC resolution.
	1167	* @note ADC conversion data full-scale corresponds to voltage range
	1168	* determined by analog voltage references Vref+ and Vref-
	1169	* (refer to reference manual).
	1170	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
	1171	* @arg @ref LL_ADC_RESOLUTION_12B
	1172	* @arg @ref LL_ADC_RESOLUTION_10B
	1173	* @arg @ref LL_ADC_RESOLUTION_8B
	1174	* @arg @ref LL_ADC_RESOLUTION_6B
	1175	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
	1176	*/
	1177	#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
	1178	(0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))
	1179
	1180	/**
	1181	* @brief Helper macro to convert the ADC conversion data from
	1182	* a resolution to another resolution.
	1183	* @param __DATA__ ADC conversion data to be converted
	1184	* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
	1185	* This parameter can be one of the following values:
	1186	* @arg @ref LL_ADC_RESOLUTION_12B
	1187	* @arg @ref LL_ADC_RESOLUTION_10B
	1188	* @arg @ref LL_ADC_RESOLUTION_8B
	1189	* @arg @ref LL_ADC_RESOLUTION_6B
	1190	* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
	1191	* This parameter can be one of the following values:
	1192	* @arg @ref LL_ADC_RESOLUTION_12B
	1193	* @arg @ref LL_ADC_RESOLUTION_10B
	1194	* @arg @ref LL_ADC_RESOLUTION_8B
	1195	* @arg @ref LL_ADC_RESOLUTION_6B
	1196	* @retval ADC conversion data to the requested resolution
	1197	*/
	1198	#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
	1199	(((__DATA__) \
	1200	<< ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) \
	1201	>> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)) \
	1202	)
	1203
	1204	/**
	1205	* @brief Helper macro to calculate the voltage (unit: mVolt)
	1206	* corresponding to a ADC conversion data (unit: digital value).
	1207	* @note Analog reference voltage (Vref+) must be either known from
	1208	* user board environment or can be calculated using ADC measurement
	1209	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
	1210	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
	1211	* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
	1212	* (unit: digital value).
	1213	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
	1214	* @arg @ref LL_ADC_RESOLUTION_12B
	1215	* @arg @ref LL_ADC_RESOLUTION_10B
	1216	* @arg @ref LL_ADC_RESOLUTION_8B
	1217	* @arg @ref LL_ADC_RESOLUTION_6B
	1218	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
	1219	*/
	1220	#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
	1221	__ADC_DATA__,\
	1222	__ADC_RESOLUTION__) \
	1223	((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
	1224	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
	1225	)
	1226
	1227	/**
	1228	* @brief Helper macro to calculate analog reference voltage (Vref+)
	1229	* (unit: mVolt) from ADC conversion data of internal voltage
	1230	* reference VrefInt.
	1231	* @note Computation is using VrefInt calibration value
	1232	* stored in system memory for each device during production.
	1233	* @note This voltage depends on user board environment: voltage level
	1234	* connected to pin Vref+.
	1235	* On devices with small package, the pin Vref+ is not present
	1236	* and internally bonded to pin Vdda.
	1237	* @note On this STM32 serie, calibration data of internal voltage reference
	1238	* VrefInt corresponds to a resolution of 12 bits,
	1239	* this is the recommended ADC resolution to convert voltage of
	1240	* internal voltage reference VrefInt.
	1241	* Otherwise, this macro performs the processing to scale
	1242	* ADC conversion data to 12 bits.
	1243	* @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
	1244	* of internal voltage reference VrefInt (unit: digital value).
	1245	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
	1246	* @arg @ref LL_ADC_RESOLUTION_12B
	1247	* @arg @ref LL_ADC_RESOLUTION_10B
	1248	* @arg @ref LL_ADC_RESOLUTION_8B
	1249	* @arg @ref LL_ADC_RESOLUTION_6B
	1250	* @retval Analog reference voltage (unit: mV)
	1251	*/
	1252	#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
	1253	__ADC_RESOLUTION__) \
	1254	(((uint32_t)(VREFINT_CAL_ADDR) VREFINT_CAL_VREF) \
	1255	/ __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
	1256	(__ADC_RESOLUTION__), \
	1257	LL_ADC_RESOLUTION_12B) \
	1258	)
	1259
	1260	/**
	1261	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
	1262	* from ADC conversion data of internal temperature sensor.
	1263	* @note Computation is using temperature sensor calibration values
	1264	* stored in system memory for each device during production.
	1265	* @note Calculation formula:
	1266	* Temperature = ((TS_ADC_DATA - TS_CAL1)
	1267	* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
	1268	* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
	1269	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
	1270	* Avg_Slope = (TS_CAL2 - TS_CAL1)
	1271	* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
	1272	* TS_CAL1 = equivalent TS_ADC_DATA at temperature
	1273	* TEMP_DEGC_CAL1 (calibrated in factory)
	1274	* TS_CAL2 = equivalent TS_ADC_DATA at temperature
	1275	* TEMP_DEGC_CAL2 (calibrated in factory)
	1276	* Caution: Calculation relevancy under reserve that calibration
	1277	* parameters are correct (address and data).
	1278	* To calculate temperature using temperature sensor
	1279	* datasheet typical values (generic values less, therefore
	1280	* less accurate than calibrated values),
	1281	* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
	1282	* @note As calculation input, the analog reference voltage (Vref+) must be
	1283	* defined as it impacts the ADC LSB equivalent voltage.
	1284	* @note Analog reference voltage (Vref+) must be either known from
	1285	* user board environment or can be calculated using ADC measurement
	1286	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
	1287	* @note On this STM32 serie, calibration data of temperature sensor
	1288	* corresponds to a resolution of 12 bits,
	1289	* this is the recommended ADC resolution to convert voltage of
	1290	* temperature sensor.
	1291	* Otherwise, this macro performs the processing to scale
	1292	* ADC conversion data to 12 bits.
	1293	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
	1294	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
	1295	* temperature sensor (unit: digital value).
	1296	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
	1297	* sensor voltage has been measured.
	1298	* This parameter can be one of the following values:
	1299	* @arg @ref LL_ADC_RESOLUTION_12B
	1300	* @arg @ref LL_ADC_RESOLUTION_10B
	1301	* @arg @ref LL_ADC_RESOLUTION_8B
	1302	* @arg @ref LL_ADC_RESOLUTION_6B
	1303	* @retval Temperature (unit: degree Celsius)
	1304	*/
	1305	#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
	1306	__TEMPSENSOR_ADC_DATA__,\
	1307	__ADC_RESOLUTION__) \
	1308	(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
	1309	(__ADC_RESOLUTION__), \
	1310	LL_ADC_RESOLUTION_12B) \
	1311	* (__VREFANALOG_VOLTAGE__)) \
	1312	/ TEMPSENSOR_CAL_VREFANALOG) \
	1313	- (int32_t) *TEMPSENSOR_CAL1_ADDR) \
	1314	) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
	1315	) / (int32_t)((int32_t)TEMPSENSOR_CAL2_ADDR - (int32_t)TEMPSENSOR_CAL1_ADDR) \
	1316	) + TEMPSENSOR_CAL1_TEMP \
	1317	)
	1318
	1319	/**
	1320	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
	1321	* from ADC conversion data of internal temperature sensor.
	1322	* @note Computation is using temperature sensor typical values
	1323	* (refer to device datasheet).
	1324	* @note Calculation formula:
	1325	* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
	1326	* / Avg_Slope + CALx_TEMP
	1327	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
	1328	* (unit: digital value)
	1329	* Avg_Slope = temperature sensor slope
	1330	* (unit: uV/Degree Celsius)
	1331	* TS_TYP_CALx_VOLT = temperature sensor digital value at
	1332	* temperature CALx_TEMP (unit: mV)
	1333	* Caution: Calculation relevancy under reserve the temperature sensor
	1334	* of the current device has characteristics in line with
	1335	* datasheet typical values.
	1336	* If temperature sensor calibration values are available on
	1337	* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
	1338	* temperature calculation will be more accurate using
	1339	* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
	1340	* @note As calculation input, the analog reference voltage (Vref+) must be
	1341	* defined as it impacts the ADC LSB equivalent voltage.
	1342	* @note Analog reference voltage (Vref+) must be either known from
	1343	* user board environment or can be calculated using ADC measurement
	1344	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
	1345	* @note ADC measurement data must correspond to a resolution of 12bits
	1346	* (full scale digital value 4095). If not the case, the data must be
	1347	* preliminarily rescaled to an equivalent resolution of 12 bits.
	1348	* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
	1349	* On STM32F0, refer to device datasheet parameter "Avg_Slope".
	1350	* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
	1351	* On STM32F0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
	1352	* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
	1353	* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
	1354	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
	1355	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
	1356	* This parameter can be one of the following values:
	1357	* @arg @ref LL_ADC_RESOLUTION_12B
	1358	* @arg @ref LL_ADC_RESOLUTION_10B
	1359	* @arg @ref LL_ADC_RESOLUTION_8B
	1360	* @arg @ref LL_ADC_RESOLUTION_6B
	1361	* @retval Temperature (unit: degree Celsius)
	1362	*/
	1363	#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
	1364	__TEMPSENSOR_TYP_CALX_V__,\
	1365	__TEMPSENSOR_CALX_TEMP__,\
	1366	__VREFANALOG_VOLTAGE__,\
	1367	__TEMPSENSOR_ADC_DATA__,\
	1368	__ADC_RESOLUTION__) \
	1369	((( ( \
	1370	(int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
	1371	* 1000) \
	1372	- \
	1373	(int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
	1374	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
	1375	* 1000) \
	1376	) \
	1377	) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
	1378	) + (__TEMPSENSOR_CALX_TEMP__) \
	1379	)
	1380
	1381	/**
	1382	* @}
	1383	*/
	1384
	1385	/**
	1386	* @}
	1387	*/
	1388
	1389
	1390	/* Exported functions --------------------------------------------------------*/
	1391	/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
	1392	* @{
	1393	*/
	1394
	1395	/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
	1396	* @{
	1397	*/
	1398	/* Note: LL ADC functions to set DMA transfer are located into sections of */
	1399	/* configuration of ADC instance, groups and multimode (if available): */
	1400	/* @ref LL_ADC_REG_SetDMATransfer(), ... */
	1401
	1402	/**
	1403	* @brief Function to help to configure DMA transfer from ADC: retrieve the
	1404	* ADC register address from ADC instance and a list of ADC registers
	1405	* intended to be used (most commonly) with DMA transfer.
	1406	* @note These ADC registers are data registers:
	1407	* when ADC conversion data is available in ADC data registers,
	1408	* ADC generates a DMA transfer request.
	1409	* @note This macro is intended to be used with LL DMA driver, refer to
	1410	* function "LL_DMA_ConfigAddresses()".
	1411	* Example:
	1412	* LL_DMA_ConfigAddresses(DMA1,
	1413	* LL_DMA_CHANNEL_1,
	1414	* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
	1415	* (uint32_t)&< array or variable >,
	1416	* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
	1417	* @note For devices with several ADC: in multimode, some devices
	1418	* use a different data register outside of ADC instance scope
	1419	* (common data register). This macro manages this register difference,
	1420	* only ADC instance has to be set as parameter.
	1421	* @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
	1422	* @param ADCx ADC instance
	1423	* @param Register This parameter can be one of the following values:
	1424	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
	1425	* @retval ADC register address
	1426	*/
	1427	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
	1428	{
	1429	/* Retrieve address of register DR */
	1430	return (uint32_t)&(ADCx->DR);
	1431	}
	1432
	1433	/**
	1434	* @}
	1435	*/
	1436
	1437	/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
	1438	* @{
	1439	*/
	1440
	1441	/**
	1442	* @brief Set parameter common to several ADC: measurement path to internal
	1443	* channels (VrefInt, temperature sensor, ...).
	1444	* @note One or several values can be selected.
	1445	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
	1446	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
	1447	* @note Stabilization time of measurement path to internal channel:
	1448	* After enabling internal paths, before starting ADC conversion,
	1449	* a delay is required for internal voltage reference and
	1450	* temperature sensor stabilization time.
	1451	* Refer to device datasheet.
	1452	* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
	1453	* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
	1454	* @note ADC internal channel sampling time constraint:
	1455	* For ADC conversion of internal channels,
	1456	* a sampling time minimum value is required.
	1457	* Refer to device datasheet.
	1458	* @note On this STM32 serie, setting of this feature is conditioned to
	1459	* ADC state:
	1460	* All ADC instances of the ADC common group must be disabled.
	1461	* This check can be done with function @ref LL_ADC_IsEnabled() for each
	1462	* ADC instance or by using helper macro helper macro
	1463	* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
	1464	* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
	1465	* CCR TSEN LL_ADC_SetCommonPathInternalCh\n
	1466	* CCR VBATEN LL_ADC_SetCommonPathInternalCh
	1467	* @param ADCxy_COMMON ADC common instance
	1468	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
	1469	* @param PathInternal This parameter can be a combination of the following values:
	1470	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
	1471	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
	1472	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
	1473	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT (1)
	1474	*
	1475	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	1476	* @retval None
	1477	*/
	1478	__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
	1479	{
	1480	#if defined(ADC_CCR_VBATEN)
	1481	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN \| ADC_CCR_VBATEN, PathInternal);
	1482	#else
	1483	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN, PathInternal);
	1484	#endif
	1485	}
	1486
	1487	/**
	1488	* @brief Get parameter common to several ADC: measurement path to internal
	1489	* channels (VrefInt, temperature sensor, ...).
	1490	* @note One or several values can be selected.
	1491	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
	1492	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
	1493	* @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
	1494	* CCR TSEN LL_ADC_GetCommonPathInternalCh\n
	1495	* CCR VBATEN LL_ADC_GetCommonPathInternalCh
	1496	* @param ADCxy_COMMON ADC common instance
	1497	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
	1498	* @retval Returned value can be a combination of the following values:
	1499	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
	1500	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
	1501	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
	1502	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT (1)
	1503	*
	1504	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	1505	*/
	1506	__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
	1507	{
	1508	#if defined(ADC_CCR_VBATEN)
	1509	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN \| ADC_CCR_VBATEN));
	1510	#else
	1511	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN));
	1512	#endif
	1513	}
	1514
	1515	/**
	1516	* @}
	1517	*/
	1518
	1519	/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
	1520	* @{
	1521	*/
	1522
	1523	/**
	1524	* @brief Set ADC instance clock source and prescaler.
	1525	* @note On this STM32 serie, setting of this feature is conditioned to
	1526	* ADC state:
	1527	* ADC must be disabled.
	1528	* @rmtoll CFGR2 CKMODE LL_ADC_SetClock
	1529	* @param ADCx ADC instance
	1530	* @param ClockSource This parameter can be one of the following values:
	1531	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
	1532	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
	1533	* @arg @ref LL_ADC_CLOCK_ASYNC (1)
	1534	*
	1535	* (1) On this STM32 serie, synchronous clock has no prescaler.
	1536	* @retval None
	1537	*/
	1538	__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
	1539	{
	1540	MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
	1541	}
	1542
	1543	/**
	1544	* @brief Get ADC instance clock source and prescaler.
	1545	* @rmtoll CFGR2 CKMODE LL_ADC_GetClock
	1546	* @param ADCx ADC instance
	1547	* @retval Returned value can be one of the following values:
	1548	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
	1549	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
	1550	* @arg @ref LL_ADC_CLOCK_ASYNC (1)
	1551	*
	1552	* (1) On this STM32 serie, synchronous clock has no prescaler.
	1553	*/
	1554	__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
	1555	{
	1556	return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
	1557	}
	1558
	1559	/**
	1560	* @brief Set ADC resolution.
	1561	* Refer to reference manual for alignments formats
	1562	* dependencies to ADC resolutions.
	1563	* @note On this STM32 serie, setting of this feature is conditioned to
	1564	* ADC state:
	1565	* ADC must be disabled or enabled without conversion on going
	1566	* on group regular.
	1567	* @rmtoll CFGR1 RES LL_ADC_SetResolution
	1568	* @param ADCx ADC instance
	1569	* @param Resolution This parameter can be one of the following values:
	1570	* @arg @ref LL_ADC_RESOLUTION_12B
	1571	* @arg @ref LL_ADC_RESOLUTION_10B
	1572	* @arg @ref LL_ADC_RESOLUTION_8B
	1573	* @arg @ref LL_ADC_RESOLUTION_6B
	1574	* @retval None
	1575	*/
	1576	__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
	1577	{
	1578	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
	1579	}
	1580
	1581	/**
	1582	* @brief Get ADC resolution.
	1583	* Refer to reference manual for alignments formats
	1584	* dependencies to ADC resolutions.
	1585	* @rmtoll CFGR1 RES LL_ADC_GetResolution
	1586	* @param ADCx ADC instance
	1587	* @retval Returned value can be one of the following values:
	1588	* @arg @ref LL_ADC_RESOLUTION_12B
	1589	* @arg @ref LL_ADC_RESOLUTION_10B
	1590	* @arg @ref LL_ADC_RESOLUTION_8B
	1591	* @arg @ref LL_ADC_RESOLUTION_6B
	1592	*/
	1593	__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
	1594	{
	1595	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
	1596	}
	1597
	1598	/**
	1599	* @brief Set ADC conversion data alignment.
	1600	* @note Refer to reference manual for alignments formats
	1601	* dependencies to ADC resolutions.
	1602	* @note On this STM32 serie, setting of this feature is conditioned to
	1603	* ADC state:
	1604	* ADC must be disabled or enabled without conversion on going
	1605	* on group regular.
	1606	* @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
	1607	* @param ADCx ADC instance
	1608	* @param DataAlignment This parameter can be one of the following values:
	1609	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
	1610	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
	1611	* @retval None
	1612	*/
	1613	__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
	1614	{
	1615	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
	1616	}
	1617
	1618	/**
	1619	* @brief Get ADC conversion data alignment.
	1620	* @note Refer to reference manual for alignments formats
	1621	* dependencies to ADC resolutions.
	1622	* @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
	1623	* @param ADCx ADC instance
	1624	* @retval Returned value can be one of the following values:
	1625	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
	1626	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
	1627	*/
	1628	__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
	1629	{
	1630	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
	1631	}
	1632
	1633	/**
	1634	* @brief Set ADC low power mode.
	1635	* @note Description of ADC low power modes:
	1636	* - ADC low power mode "auto wait": Dynamic low power mode,
	1637	* ADC conversions occurrences are limited to the minimum necessary
	1638	* in order to reduce power consumption.
	1639	* New ADC conversion starts only when the previous
	1640	* unitary conversion data (for ADC group regular)
	1641	* has been retrieved by user software.
	1642	* In the meantime, ADC remains idle: does not performs any
	1643	* other conversion.
	1644	* This mode allows to automatically adapt the ADC conversions
	1645	* triggers to the speed of the software that reads the data.
	1646	* Moreover, this avoids risk of overrun for low frequency
	1647	* applications.
	1648	* How to use this low power mode:
	1649	* - Do not use with interruption or DMA since these modes
	1650	* have to clear immediately the EOC flag to free the
	1651	* IRQ vector sequencer.
	1652	* - Do use with polling: 1. Start conversion,
	1653	* 2. Later on, when conversion data is needed: poll for end of
	1654	* conversion to ensure that conversion is completed and
	1655	* retrieve ADC conversion data. This will trig another
	1656	* ADC conversion start.
	1657	* - ADC low power mode "auto power-off" (feature available on
	1658	* this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
	1659	* the ADC automatically powers-off after a conversion and
	1660	* automatically wakes up when a new conversion is triggered
	1661	* (with startup time between trigger and start of sampling).
	1662	* This feature can be combined with low power mode "auto wait".
	1663	* @note With ADC low power mode "auto wait", the ADC conversion data read
	1664	* is corresponding to previous ADC conversion start, independently
	1665	* of delay during which ADC was idle.
	1666	* Therefore, the ADC conversion data may be outdated: does not
	1667	* correspond to the current voltage level on the selected
	1668	* ADC channel.
	1669	* @note On this STM32 serie, setting of this feature is conditioned to
	1670	* ADC state:
	1671	* ADC must be disabled or enabled without conversion on going
	1672	* on group regular.
	1673	* @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n
	1674	* CFGR1 AUTOFF LL_ADC_SetLowPowerMode
	1675	* @param ADCx ADC instance
	1676	* @param LowPowerMode This parameter can be one of the following values:
	1677	* @arg @ref LL_ADC_LP_MODE_NONE
	1678	* @arg @ref LL_ADC_LP_AUTOWAIT
	1679	* @arg @ref LL_ADC_LP_AUTOPOWEROFF
	1680	* @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
	1681	* @retval None
	1682	*/
	1683	__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
	1684	{
	1685	MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT \| ADC_CFGR1_AUTOFF), LowPowerMode);
	1686	}
	1687
	1688	/**
	1689	* @brief Get ADC low power mode:
	1690	* @note Description of ADC low power modes:
	1691	* - ADC low power mode "auto wait": Dynamic low power mode,
	1692	* ADC conversions occurrences are limited to the minimum necessary
	1693	* in order to reduce power consumption.
	1694	* New ADC conversion starts only when the previous
	1695	* unitary conversion data (for ADC group regular)
	1696	* has been retrieved by user software.
	1697	* In the meantime, ADC remains idle: does not performs any
	1698	* other conversion.
	1699	* This mode allows to automatically adapt the ADC conversions
	1700	* triggers to the speed of the software that reads the data.
	1701	* Moreover, this avoids risk of overrun for low frequency
	1702	* applications.
	1703	* How to use this low power mode:
	1704	* - Do not use with interruption or DMA since these modes
	1705	* have to clear immediately the EOC flag to free the
	1706	* IRQ vector sequencer.
	1707	* - Do use with polling: 1. Start conversion,
	1708	* 2. Later on, when conversion data is needed: poll for end of
	1709	* conversion to ensure that conversion is completed and
	1710	* retrieve ADC conversion data. This will trig another
	1711	* ADC conversion start.
	1712	* - ADC low power mode "auto power-off" (feature available on
	1713	* this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
	1714	* the ADC automatically powers-off after a conversion and
	1715	* automatically wakes up when a new conversion is triggered
	1716	* (with startup time between trigger and start of sampling).
	1717	* This feature can be combined with low power mode "auto wait".
	1718	* @note With ADC low power mode "auto wait", the ADC conversion data read
	1719	* is corresponding to previous ADC conversion start, independently
	1720	* of delay during which ADC was idle.
	1721	* Therefore, the ADC conversion data may be outdated: does not
	1722	* correspond to the current voltage level on the selected
	1723	* ADC channel.
	1724	* @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n
	1725	* CFGR1 AUTOFF LL_ADC_GetLowPowerMode
	1726	* @param ADCx ADC instance
	1727	* @retval Returned value can be one of the following values:
	1728	* @arg @ref LL_ADC_LP_MODE_NONE
	1729	* @arg @ref LL_ADC_LP_AUTOWAIT
	1730	* @arg @ref LL_ADC_LP_AUTOPOWEROFF
	1731	* @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
	1732	*/
	1733	__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
	1734	{
	1735	return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT \| ADC_CFGR1_AUTOFF)));
	1736	}
	1737
	1738	/**
	1739	* @brief Set sampling time common to a group of channels.
	1740	* @note Unit: ADC clock cycles.
	1741	* @note On this STM32 serie, sampling time scope is on ADC instance:
	1742	* Sampling time common to all channels.
	1743	* (on some other STM32 families, sampling time is channel wise)
	1744	* @note In case of internal channel (VrefInt, TempSensor, ...) to be
	1745	* converted:
	1746	* sampling time constraints must be respected (sampling time can be
	1747	* adjusted in function of ADC clock frequency and sampling time
	1748	* setting).
	1749	* Refer to device datasheet for timings values (parameters TS_vrefint,
	1750	* TS_temp, ...).
	1751	* @note Conversion time is the addition of sampling time and processing time.
	1752	* On this STM32 serie, ADC processing time is:
	1753	* - 12.5 ADC clock cycles at ADC resolution 12 bits
	1754	* - 10.5 ADC clock cycles at ADC resolution 10 bits
	1755	* - 8.5 ADC clock cycles at ADC resolution 8 bits
	1756	* - 6.5 ADC clock cycles at ADC resolution 6 bits
	1757	* @note In case of ADC conversion of internal channel (VrefInt,
	1758	* temperature sensor, ...), a sampling time minimum value
	1759	* is required.
	1760	* Refer to device datasheet.
	1761	* @note On this STM32 serie, setting of this feature is conditioned to
	1762	* ADC state:
	1763	* ADC must be disabled or enabled without conversion on going
	1764	* on group regular.
	1765	* @rmtoll SMPR SMP LL_ADC_SetSamplingTimeCommonChannels
	1766	* @param ADCx ADC instance
	1767	* @param SamplingTime This parameter can be one of the following values:
	1768	* @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
	1769	* @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
	1770	* @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
	1771	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
	1772	* @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
	1773	* @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
	1774	* @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
	1775	* @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
	1776	* @retval None
	1777	*/
	1778	__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTime)
	1779	{
	1780	MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime);
	1781	}
	1782
	1783	/**
	1784	* @brief Get sampling time common to a group of channels.
	1785	* @note Unit: ADC clock cycles.
	1786	* @note On this STM32 serie, sampling time scope is on ADC instance:
	1787	* Sampling time common to all channels.
	1788	* (on some other STM32 families, sampling time is channel wise)
	1789	* @note Conversion time is the addition of sampling time and processing time.
	1790	* Refer to reference manual for ADC processing time of
	1791	* this STM32 serie.
	1792	* @rmtoll SMPR SMP LL_ADC_GetSamplingTimeCommonChannels
	1793	* @param ADCx ADC instance
	1794	* @retval Returned value can be one of the following values:
	1795	* @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
	1796	* @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
	1797	* @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
	1798	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
	1799	* @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
	1800	* @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
	1801	* @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
	1802	* @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
	1803	*/
	1804	__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx)
	1805	{
	1806	return (uint32_t)(READ_BIT(ADCx->SMPR, ADC_SMPR_SMP));
	1807	}
	1808
	1809	/**
	1810	* @}
	1811	*/
	1812
	1813	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
	1814	* @{
	1815	*/
	1816
	1817	/**
	1818	* @brief Set ADC group regular conversion trigger source:
	1819	* internal (SW start) or from external IP (timer event,
	1820	* external interrupt line).
	1821	* @note On this STM32 serie, setting trigger source to external trigger
	1822	* also set trigger polarity to rising edge
	1823	* (default setting for compatibility with some ADC on other
	1824	* STM32 families having this setting set by HW default value).
	1825	* In case of need to modify trigger edge, use
	1826	* function @ref LL_ADC_REG_SetTriggerEdge().
	1827	* @note Availability of parameters of trigger sources from timer
	1828	* depends on timers availability on the selected device.
	1829	* @note On this STM32 serie, setting of this feature is conditioned to
	1830	* ADC state:
	1831	* ADC must be disabled or enabled without conversion on going
	1832	* on group regular.
	1833	* @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
	1834	* CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
	1835	* @param ADCx ADC instance
	1836	* @param TriggerSource This parameter can be one of the following values:
	1837	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
	1838	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
	1839	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
	1840	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
	1841	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
	1842	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
	1843	*
	1844	* (1) On STM32F0, parameter not available on all devices
	1845	* @retval None
	1846	*/
	1847	__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
	1848	{
	1849	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN \| ADC_CFGR1_EXTSEL, TriggerSource);
	1850	}
	1851
	1852	/**
	1853	* @brief Get ADC group regular conversion trigger source:
	1854	* internal (SW start) or from external IP (timer event,
	1855	* external interrupt line).
	1856	* @note To determine whether group regular trigger source is
	1857	* internal (SW start) or external, without detail
	1858	* of which peripheral is selected as external trigger,
	1859	* (equivalent to
	1860	* "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
	1861	* use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
	1862	* @note Availability of parameters of trigger sources from timer
	1863	* depends on timers availability on the selected device.
	1864	* @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
	1865	* CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
	1866	* @param ADCx ADC instance
	1867	* @retval Returned value can be one of the following values:
	1868	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
	1869	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
	1870	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
	1871	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
	1872	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
	1873	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
	1874	*
	1875	* (1) On STM32F0, parameter not available on all devices
	1876	*/
	1877	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
	1878	{
	1879	register uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL \| ADC_CFGR1_EXTEN);
	1880
	1881	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
	1882	/* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
	1883	register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
	1884
	1885	/* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
	1886	/* to match with triggers literals definition. */
	1887	return ((TriggerSource
	1888	& (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
	1889	\| ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
	1890	);
	1891	}
	1892
	1893	/**
	1894	* @brief Get ADC group regular conversion trigger source internal (SW start)
	1895	or external.
	1896	* @note In case of group regular trigger source set to external trigger,
	1897	* to determine which peripheral is selected as external trigger,
	1898	* use function @ref LL_ADC_REG_GetTriggerSource().
	1899	* @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
	1900	* @param ADCx ADC instance
	1901	* @retval Value "0" if trigger source external trigger
	1902	* Value "1" if trigger source SW start.
	1903	*/
	1904	__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
	1905	{
	1906	return (READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN));
	1907	}
	1908
	1909	/**
	1910	* @brief Set ADC group regular conversion trigger polarity.
	1911	* @note Applicable only for trigger source set to external trigger.
	1912	* @note On this STM32 serie, setting of this feature is conditioned to
	1913	* ADC state:
	1914	* ADC must be disabled or enabled without conversion on going
	1915	* on group regular.
	1916	* @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
	1917	* @param ADCx ADC instance
	1918	* @param ExternalTriggerEdge This parameter can be one of the following values:
	1919	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
	1920	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
	1921	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
	1922	* @retval None
	1923	*/
	1924	__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
	1925	{
	1926	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
	1927	}
	1928
	1929	/**
	1930	* @brief Get ADC group regular conversion trigger polarity.
	1931	* @note Applicable only for trigger source set to external trigger.
	1932	* @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
	1933	* @param ADCx ADC instance
	1934	* @retval Returned value can be one of the following values:
	1935	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
	1936	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
	1937	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
	1938	*/
	1939	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
	1940	{
	1941	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
	1942	}
	1943
	1944
	1945	/**
	1946	* @brief Set ADC group regular sequencer scan direction.
	1947	* @note On some other STM32 families, this setting is not available and
	1948	* the default scan direction is forward.
	1949	* @note On this STM32 serie, setting of this feature is conditioned to
	1950	* ADC state:
	1951	* ADC must be disabled or enabled without conversion on going
	1952	* on group regular.
	1953	* @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
	1954	* @param ADCx ADC instance
	1955	* @param ScanDirection This parameter can be one of the following values:
	1956	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
	1957	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
	1958	* @retval None
	1959	*/
	1960	__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
	1961	{
	1962	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
	1963	}
	1964
	1965	/**
	1966	* @brief Get ADC group regular sequencer scan direction.
	1967	* @note On some other STM32 families, this setting is not available and
	1968	* the default scan direction is forward.
	1969	* @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
	1970	* @param ADCx ADC instance
	1971	* @retval Returned value can be one of the following values:
	1972	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
	1973	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
	1974	*/
	1975	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
	1976	{
	1977	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
	1978	}
	1979
	1980	/**
	1981	* @brief Set ADC group regular sequencer discontinuous mode:
	1982	* sequence subdivided and scan conversions interrupted every selected
	1983	* number of ranks.
	1984	* @note It is not possible to enable both ADC group regular
	1985	* continuous mode and sequencer discontinuous mode.
	1986	* @note On this STM32 serie, setting of this feature is conditioned to
	1987	* ADC state:
	1988	* ADC must be disabled or enabled without conversion on going
	1989	* on group regular.
	1990	* @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
	1991	* @param ADCx ADC instance
	1992	* @param SeqDiscont This parameter can be one of the following values:
	1993	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
	1994	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
	1995	* @retval None
	1996	*/
	1997	__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
	1998	{
	1999	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
	2000	}
	2001
	2002	/**
	2003	* @brief Get ADC group regular sequencer discontinuous mode:
	2004	* sequence subdivided and scan conversions interrupted every selected
	2005	* number of ranks.
	2006	* @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
	2007	* @param ADCx ADC instance
	2008	* @retval Returned value can be one of the following values:
	2009	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
	2010	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
	2011	*/
	2012	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
	2013	{
	2014	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
	2015	}
	2016
	2017	/**
	2018	* @brief Set ADC group regular sequence: channel on rank corresponding to
	2019	* channel number.
	2020	* @note This function performs:
	2021	* - Channels ordering into each rank of scan sequence:
	2022	* rank of each channel is fixed by channel HW number
	2023	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
	2024	* - Set channels selected by overwriting the current sequencer
	2025	* configuration.
	2026	* @note On this STM32 serie, ADC group regular sequencer is
	2027	* not fully configurable: sequencer length and each rank
	2028	* affectation to a channel are fixed by channel HW number.
	2029	* @note Depending on devices and packages, some channels may not be available.
	2030	* Refer to device datasheet for channels availability.
	2031	* @note On this STM32 serie, to measure internal channels (VrefInt,
	2032	* TempSensor, ...), measurement paths to internal channels must be
	2033	* enabled separately.
	2034	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
	2035	* @note On this STM32 serie, setting of this feature is conditioned to
	2036	* ADC state:
	2037	* ADC must be disabled or enabled without conversion on going
	2038	* on group regular.
	2039	* @note One or several values can be selected.
	2040	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
	2041	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
	2042	* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
	2043	* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
	2044	* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
	2045	* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
	2046	* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
	2047	* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
	2048	* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
	2049	* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
	2050	* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
	2051	* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
	2052	* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
	2053	* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
	2054	* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
	2055	* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
	2056	* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
	2057	* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
	2058	* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
	2059	* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
	2060	* @param ADCx ADC instance
	2061	* @param Channel This parameter can be a combination of the following values:
	2062	* @arg @ref LL_ADC_CHANNEL_0
	2063	* @arg @ref LL_ADC_CHANNEL_1
	2064	* @arg @ref LL_ADC_CHANNEL_2
	2065	* @arg @ref LL_ADC_CHANNEL_3
	2066	* @arg @ref LL_ADC_CHANNEL_4
	2067	* @arg @ref LL_ADC_CHANNEL_5
	2068	* @arg @ref LL_ADC_CHANNEL_6
	2069	* @arg @ref LL_ADC_CHANNEL_7
	2070	* @arg @ref LL_ADC_CHANNEL_8
	2071	* @arg @ref LL_ADC_CHANNEL_9
	2072	* @arg @ref LL_ADC_CHANNEL_10
	2073	* @arg @ref LL_ADC_CHANNEL_11
	2074	* @arg @ref LL_ADC_CHANNEL_12
	2075	* @arg @ref LL_ADC_CHANNEL_13
	2076	* @arg @ref LL_ADC_CHANNEL_14
	2077	* @arg @ref LL_ADC_CHANNEL_15
	2078	* @arg @ref LL_ADC_CHANNEL_16
	2079	* @arg @ref LL_ADC_CHANNEL_17
	2080	* @arg @ref LL_ADC_CHANNEL_18 (1)
	2081	* @arg @ref LL_ADC_CHANNEL_VREFINT
	2082	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
	2083	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
	2084	*
	2085	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	2086	* @retval None
	2087	*/
	2088	__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
	2089	{
	2090	/* Parameter "Channel" is used with masks because containing */
	2091	/* other bits reserved for other purpose. */
	2092	WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
	2093	}
	2094
	2095	/**
	2096	* @brief Add channel to ADC group regular sequence: channel on rank corresponding to
	2097	* channel number.
	2098	* @note This function performs:
	2099	* - Channels ordering into each rank of scan sequence:
	2100	* rank of each channel is fixed by channel HW number
	2101	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
	2102	* - Set channels selected by adding them to the current sequencer
	2103	* configuration.
	2104	* @note On this STM32 serie, ADC group regular sequencer is
	2105	* not fully configurable: sequencer length and each rank
	2106	* affectation to a channel are fixed by channel HW number.
	2107	* @note Depending on devices and packages, some channels may not be available.
	2108	* Refer to device datasheet for channels availability.
	2109	* @note On this STM32 serie, to measure internal channels (VrefInt,
	2110	* TempSensor, ...), measurement paths to internal channels must be
	2111	* enabled separately.
	2112	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
	2113	* @note On this STM32 serie, setting of this feature is conditioned to
	2114	* ADC state:
	2115	* ADC must be disabled or enabled without conversion on going
	2116	* on group regular.
	2117	* @note One or several values can be selected.
	2118	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
	2119	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
	2120	* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
	2121	* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
	2122	* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
	2123	* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
	2124	* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
	2125	* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
	2126	* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
	2127	* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
	2128	* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
	2129	* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
	2130	* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
	2131	* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
	2132	* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
	2133	* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
	2134	* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
	2135	* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
	2136	* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
	2137	* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
	2138	* @param ADCx ADC instance
	2139	* @param Channel This parameter can be a combination of the following values:
	2140	* @arg @ref LL_ADC_CHANNEL_0
	2141	* @arg @ref LL_ADC_CHANNEL_1
	2142	* @arg @ref LL_ADC_CHANNEL_2
	2143	* @arg @ref LL_ADC_CHANNEL_3
	2144	* @arg @ref LL_ADC_CHANNEL_4
	2145	* @arg @ref LL_ADC_CHANNEL_5
	2146	* @arg @ref LL_ADC_CHANNEL_6
	2147	* @arg @ref LL_ADC_CHANNEL_7
	2148	* @arg @ref LL_ADC_CHANNEL_8
	2149	* @arg @ref LL_ADC_CHANNEL_9
	2150	* @arg @ref LL_ADC_CHANNEL_10
	2151	* @arg @ref LL_ADC_CHANNEL_11
	2152	* @arg @ref LL_ADC_CHANNEL_12
	2153	* @arg @ref LL_ADC_CHANNEL_13
	2154	* @arg @ref LL_ADC_CHANNEL_14
	2155	* @arg @ref LL_ADC_CHANNEL_15
	2156	* @arg @ref LL_ADC_CHANNEL_16
	2157	* @arg @ref LL_ADC_CHANNEL_17
	2158	* @arg @ref LL_ADC_CHANNEL_18 (1)
	2159	* @arg @ref LL_ADC_CHANNEL_VREFINT
	2160	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
	2161	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
	2162	*
	2163	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	2164	* @retval None
	2165	*/
	2166	__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
	2167	{
	2168	/* Parameter "Channel" is used with masks because containing */
	2169	/* other bits reserved for other purpose. */
	2170	SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
	2171	}
	2172
	2173	/**
	2174	* @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
	2175	* channel number.
	2176	* @note This function performs:
	2177	* - Channels ordering into each rank of scan sequence:
	2178	* rank of each channel is fixed by channel HW number
	2179	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
	2180	* - Set channels selected by removing them to the current sequencer
	2181	* configuration.
	2182	* @note On this STM32 serie, ADC group regular sequencer is
	2183	* not fully configurable: sequencer length and each rank
	2184	* affectation to a channel are fixed by channel HW number.
	2185	* @note Depending on devices and packages, some channels may not be available.
	2186	* Refer to device datasheet for channels availability.
	2187	* @note On this STM32 serie, to measure internal channels (VrefInt,
	2188	* TempSensor, ...), measurement paths to internal channels must be
	2189	* enabled separately.
	2190	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
	2191	* @note On this STM32 serie, setting of this feature is conditioned to
	2192	* ADC state:
	2193	* ADC must be disabled or enabled without conversion on going
	2194	* on group regular.
	2195	* @note One or several values can be selected.
	2196	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
	2197	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
	2198	* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
	2199	* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
	2200	* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
	2201	* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
	2202	* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
	2203	* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
	2204	* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
	2205	* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
	2206	* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
	2207	* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
	2208	* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
	2209	* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
	2210	* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
	2211	* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
	2212	* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
	2213	* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
	2214	* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
	2215	* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
	2216	* @param ADCx ADC instance
	2217	* @param Channel This parameter can be a combination of the following values:
	2218	* @arg @ref LL_ADC_CHANNEL_0
	2219	* @arg @ref LL_ADC_CHANNEL_1
	2220	* @arg @ref LL_ADC_CHANNEL_2
	2221	* @arg @ref LL_ADC_CHANNEL_3
	2222	* @arg @ref LL_ADC_CHANNEL_4
	2223	* @arg @ref LL_ADC_CHANNEL_5
	2224	* @arg @ref LL_ADC_CHANNEL_6
	2225	* @arg @ref LL_ADC_CHANNEL_7
	2226	* @arg @ref LL_ADC_CHANNEL_8
	2227	* @arg @ref LL_ADC_CHANNEL_9
	2228	* @arg @ref LL_ADC_CHANNEL_10
	2229	* @arg @ref LL_ADC_CHANNEL_11
	2230	* @arg @ref LL_ADC_CHANNEL_12
	2231	* @arg @ref LL_ADC_CHANNEL_13
	2232	* @arg @ref LL_ADC_CHANNEL_14
	2233	* @arg @ref LL_ADC_CHANNEL_15
	2234	* @arg @ref LL_ADC_CHANNEL_16
	2235	* @arg @ref LL_ADC_CHANNEL_17
	2236	* @arg @ref LL_ADC_CHANNEL_18 (1)
	2237	* @arg @ref LL_ADC_CHANNEL_VREFINT
	2238	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
	2239	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
	2240	*
	2241	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	2242	* @retval None
	2243	*/
	2244	__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
	2245	{
	2246	/* Parameter "Channel" is used with masks because containing */
	2247	/* other bits reserved for other purpose. */
	2248	CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
	2249	}
	2250
	2251	/**
	2252	* @brief Get ADC group regular sequence: channel on rank corresponding to
	2253	* channel number.
	2254	* @note This function performs:
	2255	* - Channels order reading into each rank of scan sequence:
	2256	* rank of each channel is fixed by channel HW number
	2257	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
	2258	* @note On this STM32 serie, ADC group regular sequencer is
	2259	* not fully configurable: sequencer length and each rank
	2260	* affectation to a channel are fixed by channel HW number.
	2261	* @note Depending on devices and packages, some channels may not be available.
	2262	* Refer to device datasheet for channels availability.
	2263	* @note On this STM32 serie, to measure internal channels (VrefInt,
	2264	* TempSensor, ...), measurement paths to internal channels must be
	2265	* enabled separately.
	2266	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
	2267	* @note On this STM32 serie, setting of this feature is conditioned to
	2268	* ADC state:
	2269	* ADC must be disabled or enabled without conversion on going
	2270	* on group regular.
	2271	* @note One or several values can be retrieved.
	2272	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
	2273	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
	2274	* CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
	2275	* CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
	2276	* CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
	2277	* CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
	2278	* CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
	2279	* CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
	2280	* CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
	2281	* CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
	2282	* CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
	2283	* CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
	2284	* CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
	2285	* CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
	2286	* CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
	2287	* CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
	2288	* CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
	2289	* CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
	2290	* CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
	2291	* CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
	2292	* @param ADCx ADC instance
	2293	* @retval Returned value can be a combination of the following values:
	2294	* @arg @ref LL_ADC_CHANNEL_0
	2295	* @arg @ref LL_ADC_CHANNEL_1
	2296	* @arg @ref LL_ADC_CHANNEL_2
	2297	* @arg @ref LL_ADC_CHANNEL_3
	2298	* @arg @ref LL_ADC_CHANNEL_4
	2299	* @arg @ref LL_ADC_CHANNEL_5
	2300	* @arg @ref LL_ADC_CHANNEL_6
	2301	* @arg @ref LL_ADC_CHANNEL_7
	2302	* @arg @ref LL_ADC_CHANNEL_8
	2303	* @arg @ref LL_ADC_CHANNEL_9
	2304	* @arg @ref LL_ADC_CHANNEL_10
	2305	* @arg @ref LL_ADC_CHANNEL_11
	2306	* @arg @ref LL_ADC_CHANNEL_12
	2307	* @arg @ref LL_ADC_CHANNEL_13
	2308	* @arg @ref LL_ADC_CHANNEL_14
	2309	* @arg @ref LL_ADC_CHANNEL_15
	2310	* @arg @ref LL_ADC_CHANNEL_16
	2311	* @arg @ref LL_ADC_CHANNEL_17
	2312	* @arg @ref LL_ADC_CHANNEL_18 (1)
	2313	* @arg @ref LL_ADC_CHANNEL_VREFINT
	2314	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
	2315	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
	2316	*
	2317	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	2318	*/
	2319	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
	2320	{
	2321	register uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
	2322
	2323	return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
	2324	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
	2325	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
	2326	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
	2327	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
	2328	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
	2329	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
	2330	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
	2331	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
	2332	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
	2333	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
	2334	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
	2335	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
	2336	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
	2337	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
	2338	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
	2339	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
	2340	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
	2341	#if defined(ADC_CCR_VBATEN)
	2342	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
	2343	#endif
	2344	);
	2345	}
	2346	/**
	2347	* @brief Set ADC continuous conversion mode on ADC group regular.
	2348	* @note Description of ADC continuous conversion mode:
	2349	* - single mode: one conversion per trigger
	2350	* - continuous mode: after the first trigger, following
	2351	* conversions launched successively automatically.
	2352	* @note It is not possible to enable both ADC group regular
	2353	* continuous mode and sequencer discontinuous mode.
	2354	* @note On this STM32 serie, setting of this feature is conditioned to
	2355	* ADC state:
	2356	* ADC must be disabled or enabled without conversion on going
	2357	* on group regular.
	2358	* @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
	2359	* @param ADCx ADC instance
	2360	* @param Continuous This parameter can be one of the following values:
	2361	* @arg @ref LL_ADC_REG_CONV_SINGLE
	2362	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
	2363	* @retval None
	2364	*/
	2365	__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
	2366	{
	2367	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
	2368	}
	2369
	2370	/**
	2371	* @brief Get ADC continuous conversion mode on ADC group regular.
	2372	* @note Description of ADC continuous conversion mode:
	2373	* - single mode: one conversion per trigger
	2374	* - continuous mode: after the first trigger, following
	2375	* conversions launched successively automatically.
	2376	* @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
	2377	* @param ADCx ADC instance
	2378	* @retval Returned value can be one of the following values:
	2379	* @arg @ref LL_ADC_REG_CONV_SINGLE
	2380	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
	2381	*/
	2382	__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
	2383	{
	2384	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
	2385	}
	2386
	2387	/**
	2388	* @brief Set ADC group regular conversion data transfer: no transfer or
	2389	* transfer by DMA, and DMA requests mode.
	2390	* @note If transfer by DMA selected, specifies the DMA requests
	2391	* mode:
	2392	* - Limited mode (One shot mode): DMA transfer requests are stopped
	2393	* when number of DMA data transfers (number of
	2394	* ADC conversions) is reached.
	2395	* This ADC mode is intended to be used with DMA mode non-circular.
	2396	* - Unlimited mode: DMA transfer requests are unlimited,
	2397	* whatever number of DMA data transfers (number of
	2398	* ADC conversions).
	2399	* This ADC mode is intended to be used with DMA mode circular.
	2400	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
	2401	* mode non-circular:
	2402	* when DMA transfers size will be reached, DMA will stop transfers of
	2403	* ADC conversions data ADC will raise an overrun error
	2404	* (overrun flag and interruption if enabled).
	2405	* @note To configure DMA source address (peripheral address),
	2406	* use function @ref LL_ADC_DMA_GetRegAddr().
	2407	* @note On this STM32 serie, setting of this feature is conditioned to
	2408	* ADC state:
	2409	* ADC must be disabled or enabled without conversion on going
	2410	* on group regular.
	2411	* @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
	2412	* CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
	2413	* @param ADCx ADC instance
	2414	* @param DMATransfer This parameter can be one of the following values:
	2415	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
	2416	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
	2417	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
	2418	* @retval None
	2419	*/
	2420	__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
	2421	{
	2422	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN \| ADC_CFGR1_DMACFG, DMATransfer);
	2423	}
	2424
	2425	/**
	2426	* @brief Get ADC group regular conversion data transfer: no transfer or
	2427	* transfer by DMA, and DMA requests mode.
	2428	* @note If transfer by DMA selected, specifies the DMA requests
	2429	* mode:
	2430	* - Limited mode (One shot mode): DMA transfer requests are stopped
	2431	* when number of DMA data transfers (number of
	2432	* ADC conversions) is reached.
	2433	* This ADC mode is intended to be used with DMA mode non-circular.
	2434	* - Unlimited mode: DMA transfer requests are unlimited,
	2435	* whatever number of DMA data transfers (number of
	2436	* ADC conversions).
	2437	* This ADC mode is intended to be used with DMA mode circular.
	2438	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
	2439	* mode non-circular:
	2440	* when DMA transfers size will be reached, DMA will stop transfers of
	2441	* ADC conversions data ADC will raise an overrun error
	2442	* (overrun flag and interruption if enabled).
	2443	* @note To configure DMA source address (peripheral address),
	2444	* use function @ref LL_ADC_DMA_GetRegAddr().
	2445	* @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
	2446	* CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
	2447	* @param ADCx ADC instance
	2448	* @retval Returned value can be one of the following values:
	2449	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
	2450	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
	2451	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
	2452	*/
	2453	__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
	2454	{
	2455	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN \| ADC_CFGR1_DMACFG));
	2456	}
	2457
	2458	/**
	2459	* @brief Set ADC group regular behavior in case of overrun:
	2460	* data preserved or overwritten.
	2461	* @note Compatibility with devices without feature overrun:
	2462	* other devices without this feature have a behavior
	2463	* equivalent to data overwritten.
	2464	* The default setting of overrun is data preserved.
	2465	* Therefore, for compatibility with all devices, parameter
	2466	* overrun should be set to data overwritten.
	2467	* @note On this STM32 serie, setting of this feature is conditioned to
	2468	* ADC state:
	2469	* ADC must be disabled or enabled without conversion on going
	2470	* on group regular.
	2471	* @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
	2472	* @param ADCx ADC instance
	2473	* @param Overrun This parameter can be one of the following values:
	2474	* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
	2475	* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
	2476	* @retval None
	2477	*/
	2478	__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
	2479	{
	2480	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
	2481	}
	2482
	2483	/**
	2484	* @brief Get ADC group regular behavior in case of overrun:
	2485	* data preserved or overwritten.
	2486	* @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
	2487	* @param ADCx ADC instance
	2488	* @retval Returned value can be one of the following values:
	2489	* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
	2490	* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
	2491	*/
	2492	__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
	2493	{
	2494	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
	2495	}
	2496
	2497	/**
	2498	* @}
	2499	*/
	2500
	2501
	2502	/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
	2503	* @{
	2504	*/
	2505
	2506	/**
	2507	* @brief Set ADC analog watchdog monitored channels:
	2508	* a single channel or all channels,
	2509	* on ADC group regular.
	2510	* @note Once monitored channels are selected, analog watchdog
	2511	* is enabled.
	2512	* @note In case of need to define a single channel to monitor
	2513	* with analog watchdog from sequencer channel definition,
	2514	* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
	2515	* @note On this STM32 serie, there is only 1 kind of analog watchdog
	2516	* instance:
	2517	* - AWD standard (instance AWD1):
	2518	* - channels monitored: can monitor 1 channel or all channels.
	2519	* - groups monitored: ADC group regular.
	2520	* - resolution: resolution is not limited (corresponds to
	2521	* ADC resolution configured).
	2522	* @note On this STM32 serie, setting of this feature is conditioned to
	2523	* ADC state:
	2524	* ADC must be disabled or enabled without conversion on going
	2525	* on group regular.
	2526	* @rmtoll CFGR1 AWDCH LL_ADC_SetAnalogWDMonitChannels\n
	2527	* CFGR1 AWDSGL LL_ADC_SetAnalogWDMonitChannels\n
	2528	* CFGR1 AWDEN LL_ADC_SetAnalogWDMonitChannels
	2529	* @param ADCx ADC instance
	2530	* @param AWDChannelGroup This parameter can be one of the following values:
	2531	* @arg @ref LL_ADC_AWD_DISABLE
	2532	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
	2533	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
	2534	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
	2535	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
	2536	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
	2537	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
	2538	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
	2539	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
	2540	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
	2541	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
	2542	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
	2543	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
	2544	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
	2545	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
	2546	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
	2547	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
	2548	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
	2549	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
	2550	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
	2551	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
	2552	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG
	2553	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
	2554	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
	2555	*
	2556	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
	2557	* @retval None
	2558	*/
	2559	__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
	2560	{
	2561	MODIFY_REG(ADCx->CFGR1,
	2562	(ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_AWDEN),
	2563	(AWDChannelGroup & ADC_AWD_CR_ALL_CHANNEL_MASK));
	2564	}
	2565
	2566	/**
	2567	* @brief Get ADC analog watchdog monitored channel.
	2568	* @note Usage of the returned channel number:
	2569	* - To reinject this channel into another function LL_ADC_xxx:
	2570	* the returned channel number is only partly formatted on definition
	2571	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
	2572	* with parts of literals LL_ADC_CHANNEL_x or using
	2573	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
	2574	* Then the selected literal LL_ADC_CHANNEL_x can be used
	2575	* as parameter for another function.
	2576	* - To get the channel number in decimal format:
	2577	* process the returned value with the helper macro
	2578	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
	2579	* Applicable only when the analog watchdog is set to monitor
	2580	* one channel.
	2581	* @note On this STM32 serie, there is only 1 kind of analog watchdog
	2582	* instance:
	2583	* - AWD standard (instance AWD1):
	2584	* - channels monitored: can monitor 1 channel or all channels.
	2585	* - groups monitored: ADC group regular.
	2586	* - resolution: resolution is not limited (corresponds to
	2587	* ADC resolution configured).
	2588	* @note On this STM32 serie, setting of this feature is conditioned to
	2589	* ADC state:
	2590	* ADC must be disabled or enabled without conversion on going
	2591	* on group regular.
	2592	* @rmtoll CFGR1 AWDCH LL_ADC_GetAnalogWDMonitChannels\n
	2593	* CFGR1 AWDSGL LL_ADC_GetAnalogWDMonitChannels\n
	2594	* CFGR1 AWDEN LL_ADC_GetAnalogWDMonitChannels
	2595	* @param ADCx ADC instance
	2596	* @retval Returned value can be one of the following values:
	2597	* @arg @ref LL_ADC_AWD_DISABLE
	2598	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
	2599	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
	2600	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
	2601	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
	2602	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
	2603	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
	2604	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
	2605	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
	2606	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
	2607	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
	2608	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
	2609	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
	2610	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
	2611	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
	2612	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
	2613	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
	2614	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
	2615	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
	2616	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
	2617	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG
	2618	*/
	2619	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
	2620	{
	2621	register uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_AWDEN));
	2622
	2623	/* Note: Set variable according to channel definition including channel ID */
	2624	/* with bitfield. */
	2625	register uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS);
	2626	register uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
	2627
	2628	return (AWDChannelGroup \| (AWDChannelBitField * AWDChannelSingle));
	2629	}
	2630
	2631	/**
	2632	* @brief Set ADC analog watchdog thresholds value of both thresholds
	2633	* high and low.
	2634	* @note If value of only one threshold high or low must be set,
	2635	* use function @ref LL_ADC_SetAnalogWDThresholds().
	2636	* @note In case of ADC resolution different of 12 bits,
	2637	* analog watchdog thresholds data require a specific shift.
	2638	* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
	2639	* @note On this STM32 serie, there is only 1 kind of analog watchdog
	2640	* instance:
	2641	* - AWD standard (instance AWD1):
	2642	* - channels monitored: can monitor 1 channel or all channels.
	2643	* - groups monitored: ADC group regular.
	2644	* - resolution: resolution is not limited (corresponds to
	2645	* ADC resolution configured).
	2646	* @note On this STM32 serie, setting of this feature is conditioned to
	2647	* ADC state:
	2648	* ADC must be disabled or enabled without conversion on going
	2649	* on group regular.
	2650	* @rmtoll TR HT LL_ADC_ConfigAnalogWDThresholds\n
	2651	* TR LT LL_ADC_ConfigAnalogWDThresholds
	2652	* @param ADCx ADC instance
	2653	* @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
	2654	* @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
	2655	* @retval None
	2656	*/
	2657	__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
	2658	{
	2659	MODIFY_REG(ADCx->TR,
	2660	ADC_TR_HT \| ADC_TR_LT,
	2661	(AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) \| AWDThresholdLowValue);
	2662	}
	2663
	2664	/**
	2665	* @brief Set ADC analog watchdog threshold value of threshold
	2666	* high or low.
	2667	* @note If values of both thresholds high or low must be set,
	2668	* use function @ref LL_ADC_ConfigAnalogWDThresholds().
	2669	* @note In case of ADC resolution different of 12 bits,
	2670	* analog watchdog thresholds data require a specific shift.
	2671	* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
	2672	* @note On this STM32 serie, there is only 1 kind of analog watchdog
	2673	* instance:
	2674	* - AWD standard (instance AWD1):
	2675	* - channels monitored: can monitor 1 channel or all channels.
	2676	* - groups monitored: ADC group regular.
	2677	* - resolution: resolution is not limited (corresponds to
	2678	* ADC resolution configured).
	2679	* @note On this STM32 serie, setting of this feature is conditioned to
	2680	* ADC state:
	2681	* ADC must be disabled or enabled without conversion on going
	2682	* on group regular.
	2683	* @rmtoll TR HT LL_ADC_SetAnalogWDThresholds\n
	2684	* TR LT LL_ADC_SetAnalogWDThresholds
	2685	* @param ADCx ADC instance
	2686	* @param AWDThresholdsHighLow This parameter can be one of the following values:
	2687	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
	2688	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
	2689	* @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
	2690	* @retval None
	2691	*/
	2692	__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
	2693	{
	2694	/* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
	2695	/* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
	2696	/* high is selected, then data is shifted to LSB. Else(threshold low), */
	2697	/* data is not shifted. */
	2698	MODIFY_REG(ADCx->TR,
	2699	AWDThresholdsHighLow,
	2700	AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & 0x00000010U));
	2701	}
	2702
	2703	/**
	2704	* @brief Get ADC analog watchdog threshold value of threshold high,
	2705	* threshold low or raw data with ADC thresholds high and low
	2706	* concatenated.
	2707	* @note If raw data with ADC thresholds high and low is retrieved,
	2708	* the data of each threshold high or low can be isolated
	2709	* using helper macro:
	2710	* @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
	2711	* @note In case of ADC resolution different of 12 bits,
	2712	* analog watchdog thresholds data require a specific shift.
	2713	* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
	2714	* @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
	2715	* TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
	2716	* TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
	2717	* TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
	2718	* TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
	2719	* TR3 LT3 LL_ADC_GetAnalogWDThresholds
	2720	* @param ADCx ADC instance
	2721	* @param AWDThresholdsHighLow This parameter can be one of the following values:
	2722	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
	2723	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
	2724	* @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
	2725	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
	2726	*/
	2727	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
	2728	{
	2729	/* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
	2730	/* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
	2731	/* high is selected, then data is shifted to LSB. Else(threshold low or */
	2732	/* both thresholds), data is not shifted. */
	2733	return (uint32_t)(READ_BIT(ADCx->TR,
	2734	(AWDThresholdsHighLow \| ADC_TR_LT))
	2735	>> ((~AWDThresholdsHighLow) & 0x00000010U)
	2736	);
	2737	}
	2738
	2739	/**
	2740	* @}
	2741	*/
	2742
	2743	/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
	2744	* @{
	2745	*/
	2746
	2747	/**
	2748	* @brief Enable the selected ADC instance.
	2749	* @note On this STM32 serie, after ADC enable, a delay for
	2750	* ADC internal analog stabilization is required before performing a
	2751	* ADC conversion start.
	2752	* Refer to device datasheet, parameter tSTAB.
	2753	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
	2754	* is enabled and when conversion clock is active.
	2755	* (not only core clock: this ADC has a dual clock domain)
	2756	* @note On this STM32 serie, setting of this feature is conditioned to
	2757	* ADC state:
	2758	* ADC must be ADC disabled and ADC internal voltage regulator enabled.
	2759	* @rmtoll CR ADEN LL_ADC_Enable
	2760	* @param ADCx ADC instance
	2761	* @retval None
	2762	*/
	2763	__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
	2764	{
	2765	/* Note: Write register with some additional bits forced to state reset */
	2766	/* instead of modifying only the selected bit for this function, */
	2767	/* to not interfere with bits with HW property "rs". */
	2768	MODIFY_REG(ADCx->CR,
	2769	ADC_CR_BITS_PROPERTY_RS,
	2770	ADC_CR_ADEN);
	2771	}
	2772
	2773	/**
	2774	* @brief Disable the selected ADC instance.
	2775	* @note On this STM32 serie, setting of this feature is conditioned to
	2776	* ADC state:
	2777	* ADC must be not disabled. Must be enabled without conversion on going
	2778	* on group regular.
	2779	* @rmtoll CR ADDIS LL_ADC_Disable
	2780	* @param ADCx ADC instance
	2781	* @retval None
	2782	*/
	2783	__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
	2784	{
	2785	/* Note: Write register with some additional bits forced to state reset */
	2786	/* instead of modifying only the selected bit for this function, */
	2787	/* to not interfere with bits with HW property "rs". */
	2788	MODIFY_REG(ADCx->CR,
	2789	ADC_CR_BITS_PROPERTY_RS,
	2790	ADC_CR_ADDIS);
	2791	}
	2792
	2793	/**
	2794	* @brief Get the selected ADC instance enable state.
	2795	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
	2796	* is enabled and when conversion clock is active.
	2797	* (not only core clock: this ADC has a dual clock domain)
	2798	* @rmtoll CR ADEN LL_ADC_IsEnabled
	2799	* @param ADCx ADC instance
	2800	* @retval 0: ADC is disabled, 1: ADC is enabled.
	2801	*/
	2802	__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
	2803	{
	2804	return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
	2805	}
	2806
	2807	/**
	2808	* @brief Get the selected ADC instance disable state.
	2809	* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
	2810	* @param ADCx ADC instance
	2811	* @retval 0: no ADC disable command on going.
	2812	*/
	2813	__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
	2814	{
	2815	return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
	2816	}
	2817
	2818	/**
	2819	* @brief Start ADC calibration in the mode single-ended
	2820	* or differential (for devices with differential mode available).
	2821	* @note On this STM32 serie, a minimum number of ADC clock cycles
	2822	* are required between ADC end of calibration and ADC enable.
	2823	* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
	2824	* @note In case of usage of ADC with DMA transfer:
	2825	* On this STM32 serie, ADC DMA transfer request should be disabled
	2826	* during calibration:
	2827	* Calibration factor is available in data register
	2828	* and also transfered by DMA.
	2829	* To not insert ADC calibration factor among ADC conversion data
	2830	* in array variable, DMA transfer must be disabled during
	2831	* calibration.
	2832	* (DMA transfer setting backup and disable before calibration,
	2833	* DMA transfer setting restore after calibration.
	2834	* Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
	2835	* @ref LL_ADC_REG_SetDMATransfer() ).
	2836	* @note On this STM32 serie, setting of this feature is conditioned to
	2837	* ADC state:
	2838	* ADC must be ADC disabled.
	2839	* @rmtoll CR ADCAL LL_ADC_StartCalibration
	2840	* @param ADCx ADC instance
	2841	* @retval None
	2842	*/
	2843	__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
	2844	{
	2845	/* Note: Write register with some additional bits forced to state reset */
	2846	/* instead of modifying only the selected bit for this function, */
	2847	/* to not interfere with bits with HW property "rs". */
	2848	MODIFY_REG(ADCx->CR,
	2849	ADC_CR_BITS_PROPERTY_RS,
	2850	ADC_CR_ADCAL);
	2851	}
	2852
	2853	/**
	2854	* @brief Get ADC calibration state.
	2855	* @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
	2856	* @param ADCx ADC instance
	2857	* @retval 0: calibration complete, 1: calibration in progress.
	2858	*/
	2859	__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
	2860	{
	2861	return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
	2862	}
	2863
	2864	/**
	2865	* @}
	2866	*/
	2867
	2868	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
	2869	* @{
	2870	*/
	2871
	2872	/**
	2873	* @brief Start ADC group regular conversion.
	2874	* @note On this STM32 serie, this function is relevant for both
	2875	* internal trigger (SW start) and external trigger:
	2876	* - If ADC trigger has been set to software start, ADC conversion
	2877	* starts immediately.
	2878	* - If ADC trigger has been set to external trigger, ADC conversion
	2879	* will start at next trigger event (on the selected trigger edge)
	2880	* following the ADC start conversion command.
	2881	* @note On this STM32 serie, setting of this feature is conditioned to
	2882	* ADC state:
	2883	* ADC must be enabled without conversion on going on group regular,
	2884	* without conversion stop command on going on group regular,
	2885	* without ADC disable command on going.
	2886	* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
	2887	* @param ADCx ADC instance
	2888	* @retval None
	2889	*/
	2890	__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
	2891	{
	2892	/* Note: Write register with some additional bits forced to state reset */
	2893	/* instead of modifying only the selected bit for this function, */
	2894	/* to not interfere with bits with HW property "rs". */
	2895	MODIFY_REG(ADCx->CR,
	2896	ADC_CR_BITS_PROPERTY_RS,
	2897	ADC_CR_ADSTART);
	2898	}
	2899
	2900	/**
	2901	* @brief Stop ADC group regular conversion.
	2902	* @note On this STM32 serie, setting of this feature is conditioned to
	2903	* ADC state:
	2904	* ADC must be enabled with conversion on going on group regular,
	2905	* without ADC disable command on going.
	2906	* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
	2907	* @param ADCx ADC instance
	2908	* @retval None
	2909	*/
	2910	__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
	2911	{
	2912	/* Note: Write register with some additional bits forced to state reset */
	2913	/* instead of modifying only the selected bit for this function, */
	2914	/* to not interfere with bits with HW property "rs". */
	2915	MODIFY_REG(ADCx->CR,
	2916	ADC_CR_BITS_PROPERTY_RS,
	2917	ADC_CR_ADSTP);
	2918	}
	2919
	2920	/**
	2921	* @brief Get ADC group regular conversion state.
	2922	* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
	2923	* @param ADCx ADC instance
	2924	* @retval 0: no conversion is on going on ADC group regular.
	2925	*/
	2926	__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
	2927	{
	2928	return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
	2929	}
	2930
	2931	/**
	2932	* @brief Get ADC group regular command of conversion stop state
	2933	* @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
	2934	* @param ADCx ADC instance
	2935	* @retval 0: no command of conversion stop is on going on ADC group regular.
	2936	*/
	2937	__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
	2938	{
	2939	return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
	2940	}
	2941
	2942	/**
	2943	* @brief Get ADC group regular conversion data, range fit for
	2944	* all ADC configurations: all ADC resolutions and
	2945	* all oversampling increased data width (for devices
	2946	* with feature oversampling).
	2947	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
	2948	* @param ADCx ADC instance
	2949	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
	2950	*/
	2951	__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
	2952	{
	2953	return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
	2954	}
	2955
	2956	/**
	2957	* @brief Get ADC group regular conversion data, range fit for
	2958	* ADC resolution 12 bits.
	2959	* @note For devices with feature oversampling: Oversampling
	2960	* can increase data width, function for extended range
	2961	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
	2962	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
	2963	* @param ADCx ADC instance
	2964	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
	2965	*/
	2966	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
	2967	{
	2968	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
	2969	}
	2970
	2971	/**
	2972	* @brief Get ADC group regular conversion data, range fit for
	2973	* ADC resolution 10 bits.
	2974	* @note For devices with feature oversampling: Oversampling
	2975	* can increase data width, function for extended range
	2976	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
	2977	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
	2978	* @param ADCx ADC instance
	2979	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
	2980	*/
	2981	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
	2982	{
	2983	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
	2984	}
	2985
	2986	/**
	2987	* @brief Get ADC group regular conversion data, range fit for
	2988	* ADC resolution 8 bits.
	2989	* @note For devices with feature oversampling: Oversampling
	2990	* can increase data width, function for extended range
	2991	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
	2992	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
	2993	* @param ADCx ADC instance
	2994	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
	2995	*/
	2996	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
	2997	{
	2998	return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
	2999	}
	3000
	3001	/**
	3002	* @brief Get ADC group regular conversion data, range fit for
	3003	* ADC resolution 6 bits.
	3004	* @note For devices with feature oversampling: Oversampling
	3005	* can increase data width, function for extended range
	3006	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
	3007	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
	3008	* @param ADCx ADC instance
	3009	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
	3010	*/
	3011	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
	3012	{
	3013	return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
	3014	}
	3015
	3016	/**
	3017	* @}
	3018	*/
	3019
	3020	/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
	3021	* @{
	3022	*/
	3023
	3024	/**
	3025	* @brief Get flag ADC ready.
	3026	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
	3027	* is enabled and when conversion clock is active.
	3028	* (not only core clock: this ADC has a dual clock domain)
	3029	* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
	3030	* @param ADCx ADC instance
	3031	* @retval State of bit (1 or 0).
	3032	*/
	3033	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
	3034	{
	3035	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
	3036	}
	3037
	3038	/**
	3039	* @brief Get flag ADC group regular end of unitary conversion.
	3040	* @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
	3041	* @param ADCx ADC instance
	3042	* @retval State of bit (1 or 0).
	3043	*/
	3044	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
	3045	{
	3046	return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
	3047	}
	3048
	3049	/**
	3050	* @brief Get flag ADC group regular end of sequence conversions.
	3051	* @rmtoll ISR EOSEQ LL_ADC_IsActiveFlag_EOS
	3052	* @param ADCx ADC instance
	3053	* @retval State of bit (1 or 0).
	3054	*/
	3055	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
	3056	{
	3057	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
	3058	}
	3059
	3060	/**
	3061	* @brief Get flag ADC group regular overrun.
	3062	* @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
	3063	* @param ADCx ADC instance
	3064	* @retval State of bit (1 or 0).
	3065	*/
	3066	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
	3067	{
	3068	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
	3069	}
	3070
	3071	/**
	3072	* @brief Get flag ADC group regular end of sampling phase.
	3073	* @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
	3074	* @param ADCx ADC instance
	3075	* @retval State of bit (1 or 0).
	3076	*/
	3077	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
	3078	{
	3079	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
	3080	}
	3081
	3082	/**
	3083	* @brief Get flag ADC analog watchdog 1 flag
	3084	* @rmtoll ISR AWD LL_ADC_IsActiveFlag_AWD1
	3085	* @param ADCx ADC instance
	3086	* @retval State of bit (1 or 0).
	3087	*/
	3088	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
	3089	{
	3090	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
	3091	}
	3092
	3093	/**
	3094	* @brief Clear flag ADC ready.
	3095	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
	3096	* is enabled and when conversion clock is active.
	3097	* (not only core clock: this ADC has a dual clock domain)
	3098	* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
	3099	* @param ADCx ADC instance
	3100	* @retval None
	3101	*/
	3102	__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
	3103	{
	3104	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
	3105	}
	3106
	3107	/**
	3108	* @brief Clear flag ADC group regular end of unitary conversion.
	3109	* @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
	3110	* @param ADCx ADC instance
	3111	* @retval None
	3112	*/
	3113	__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
	3114	{
	3115	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
	3116	}
	3117
	3118	/**
	3119	* @brief Clear flag ADC group regular end of sequence conversions.
	3120	* @rmtoll ISR EOSEQ LL_ADC_ClearFlag_EOS
	3121	* @param ADCx ADC instance
	3122	* @retval None
	3123	*/
	3124	__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
	3125	{
	3126	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
	3127	}
	3128
	3129	/**
	3130	* @brief Clear flag ADC group regular overrun.
	3131	* @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
	3132	* @param ADCx ADC instance
	3133	* @retval None
	3134	*/
	3135	__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
	3136	{
	3137	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
	3138	}
	3139
	3140	/**
	3141	* @brief Clear flag ADC group regular end of sampling phase.
	3142	* @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
	3143	* @param ADCx ADC instance
	3144	* @retval None
	3145	*/
	3146	__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
	3147	{
	3148	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
	3149	}
	3150
	3151	/**
	3152	* @brief Clear flag ADC analog watchdog 1.
	3153	* @rmtoll ISR AWD LL_ADC_ClearFlag_AWD1
	3154	* @param ADCx ADC instance
	3155	* @retval None
	3156	*/
	3157	__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
	3158	{
	3159	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
	3160	}
	3161
	3162	/**
	3163	* @}
	3164	*/
	3165
	3166	/** @defgroup ADC_LL_EF_IT_Management ADC IT management
	3167	* @{
	3168	*/
	3169
	3170	/**
	3171	* @brief Enable ADC ready.
	3172	* @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
	3173	* @param ADCx ADC instance
	3174	* @retval None
	3175	*/
	3176	__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
	3177	{
	3178	SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
	3179	}
	3180
	3181	/**
	3182	* @brief Enable interruption ADC group regular end of unitary conversion.
	3183	* @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
	3184	* @param ADCx ADC instance
	3185	* @retval None
	3186	*/
	3187	__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
	3188	{
	3189	SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
	3190	}
	3191
	3192	/**
	3193	* @brief Enable interruption ADC group regular end of sequence conversions.
	3194	* @rmtoll IER EOSEQIE LL_ADC_EnableIT_EOS
	3195	* @param ADCx ADC instance
	3196	* @retval None
	3197	*/
	3198	__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
	3199	{
	3200	SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
	3201	}
	3202
	3203	/**
	3204	* @brief Enable ADC group regular interruption overrun.
	3205	* @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
	3206	* @param ADCx ADC instance
	3207	* @retval None
	3208	*/
	3209	__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
	3210	{
	3211	SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
	3212	}
	3213
	3214	/**
	3215	* @brief Enable interruption ADC group regular end of sampling.
	3216	* @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
	3217	* @param ADCx ADC instance
	3218	* @retval None
	3219	*/
	3220	__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
	3221	{
	3222	SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
	3223	}
	3224
	3225	/**
	3226	* @brief Enable interruption ADC analog watchdog 1.
	3227	* @rmtoll IER AWDIE LL_ADC_EnableIT_AWD1
	3228	* @param ADCx ADC instance
	3229	* @retval None
	3230	*/
	3231	__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
	3232	{
	3233	SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
	3234	}
	3235
	3236	/**
	3237	* @brief Disable interruption ADC ready.
	3238	* @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
	3239	* @param ADCx ADC instance
	3240	* @retval None
	3241	*/
	3242	__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
	3243	{
	3244	CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
	3245	}
	3246
	3247	/**
	3248	* @brief Disable interruption ADC group regular end of unitary conversion.
	3249	* @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
	3250	* @param ADCx ADC instance
	3251	* @retval None
	3252	*/
	3253	__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
	3254	{
	3255	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
	3256	}
	3257
	3258	/**
	3259	* @brief Disable interruption ADC group regular end of sequence conversions.
	3260	* @rmtoll IER EOSEQIE LL_ADC_DisableIT_EOS
	3261	* @param ADCx ADC instance
	3262	* @retval None
	3263	*/
	3264	__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
	3265	{
	3266	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
	3267	}
	3268
	3269	/**
	3270	* @brief Disable interruption ADC group regular overrun.
	3271	* @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
	3272	* @param ADCx ADC instance
	3273	* @retval None
	3274	*/
	3275	__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
	3276	{
	3277	CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
	3278	}
	3279
	3280	/**
	3281	* @brief Disable interruption ADC group regular end of sampling.
	3282	* @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
	3283	* @param ADCx ADC instance
	3284	* @retval None
	3285	*/
	3286	__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
	3287	{
	3288	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
	3289	}
	3290
	3291	/**
	3292	* @brief Disable interruption ADC analog watchdog 1.
	3293	* @rmtoll IER AWDIE LL_ADC_DisableIT_AWD1
	3294	* @param ADCx ADC instance
	3295	* @retval None
	3296	*/
	3297	__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
	3298	{
	3299	CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
	3300	}
	3301
	3302	/**
	3303	* @brief Get state of interruption ADC ready
	3304	* (0: interrupt disabled, 1: interrupt enabled).
	3305	* @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
	3306	* @param ADCx ADC instance
	3307	* @retval State of bit (1 or 0).
	3308	*/
	3309	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
	3310	{
	3311	return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
	3312	}
	3313
	3314	/**
	3315	* @brief Get state of interruption ADC group regular end of unitary conversion
	3316	* (0: interrupt disabled, 1: interrupt enabled).
	3317	* @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
	3318	* @param ADCx ADC instance
	3319	* @retval State of bit (1 or 0).
	3320	*/
	3321	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
	3322	{
	3323	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
	3324	}
	3325
	3326	/**
	3327	* @brief Get state of interruption ADC group regular end of sequence conversions
	3328	* (0: interrupt disabled, 1: interrupt enabled).
	3329	* @rmtoll IER EOSEQIE LL_ADC_IsEnabledIT_EOS
	3330	* @param ADCx ADC instance
	3331	* @retval State of bit (1 or 0).
	3332	*/
	3333	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
	3334	{
	3335	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
	3336	}
	3337
	3338	/**
	3339	* @brief Get state of interruption ADC group regular overrun
	3340	* (0: interrupt disabled, 1: interrupt enabled).
	3341	* @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
	3342	* @param ADCx ADC instance
	3343	* @retval State of bit (1 or 0).
	3344	*/
	3345	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
	3346	{
	3347	return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
	3348	}
	3349
	3350	/**
	3351	* @brief Get state of interruption ADC group regular end of sampling
	3352	* (0: interrupt disabled, 1: interrupt enabled).
	3353	* @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
	3354	* @param ADCx ADC instance
	3355	* @retval State of bit (1 or 0).
	3356	*/
	3357	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
	3358	{
	3359	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
	3360	}
	3361
	3362	/**
	3363	* @brief Get state of interruption ADC analog watchdog 1
	3364	* (0: interrupt disabled, 1: interrupt enabled).
	3365	* @rmtoll IER AWDIE LL_ADC_IsEnabledIT_AWD1
	3366	* @param ADCx ADC instance
	3367	* @retval State of bit (1 or 0).
	3368	*/
	3369	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
	3370	{
	3371	return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
	3372	}
	3373
	3374	/**
	3375	* @}
	3376	*/
	3377
	3378	#if defined(USE_FULL_LL_DRIVER)
	3379	/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
	3380	* @{
	3381	*/
	3382
	3383	/* Initialization of some features of ADC common parameters and multimode */
	3384	/* Note: On this STM32 serie, there is no ADC common initialization */
	3385	/* function. */
	3386	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
	3387
	3388	/* De-initialization of ADC instance */
	3389	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
	3390
	3391	/* Initialization of some features of ADC instance */
	3392	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct);
	3393	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
	3394
	3395	/* Initialization of some features of ADC instance and ADC group regular */
	3396	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct);
	3397	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
	3398
	3399	/**
	3400	* @}
	3401	*/
	3402	#endif /* USE_FULL_LL_DRIVER */
	3403
	3404	/**
	3405	* @}
	3406	*/
	3407
	3408	/**
	3409	* @}
	3410	*/
	3411
	3412	#endif /* ADC1 */
	3413
	3414	/**
	3415	* @}
	3416	*/
	3417
	3418	#ifdef __cplusplus
	3419	}
	3420	#endif
	3421
	3422	#endif /* __STM32F0xx_LL_ADC_H */
	3423
	3424	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/