| 提交 | 用户 | age | ||
| 9aed5d | 1 | //***************************************************************************** |
| Q | 2 | // |
| 3 | //! \file w5500.h | |
| 4 | //! \brief W5500 HAL Header File. | |
| 5 | //! \version 1.0.0 | |
| 6 | //! \date 2013/10/21 | |
| 7 | //! \par Revision history | |
| 8 | //! <2013/10/21> 1st Release | |
| 9 | //! \author MidnightCow | |
| 10 | //! \copyright | |
| 11 | //! | |
| 12 | //! Copyright (c) 2013, WIZnet Co., LTD. | |
| 13 | //! All rights reserved. | |
| 14 | //! | |
| 15 | //! Redistribution and use in source and binary forms, with or without | |
| 16 | //! modification, are permitted provided that the following conditions | |
| 17 | //! are met: | |
| 18 | //! | |
| 19 | //! * Redistributions of source code must retain the above copyright | |
| 20 | //! notice, this list of conditions and the following disclaimer. | |
| 21 | //! * Redistributions in binary form must reproduce the above copyright | |
| 22 | //! notice, this list of conditions and the following disclaimer in the | |
| 23 | //! documentation and/or other materials provided with the distribution. | |
| 24 | //! * Neither the name of the <ORGANIZATION> nor the names of its | |
| 25 | //! contributors may be used to endorse or promote products derived | |
| 26 | //! from this software without specific prior written permission. | |
| 27 | //! | |
| 28 | //! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
| 29 | //! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 30 | //! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
| 31 | //! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
| 32 | //! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
| 33 | //! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
| 34 | //! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
| 35 | //! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
| 36 | //! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
| 37 | //! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
| 38 | //! THE POSSIBILITY OF SUCH DAMAGE. | |
| 39 | // | |
| 40 | //***************************************************************************** | |
| 41 | ||
| 42 | #ifndef _W5500_H_ | |
| 43 | #define _W5500_H_ | |
| 44 | ||
| 45 | #include <stdint.h> | |
| 46 | #include "Ethernet/wizchip_conf.h" | |
| 47 | ||
| 48 | #define _W5500_IO_BASE_ 0x00000000 | |
| 49 | ||
| 50 | #define _W5500_SPI_READ_ (0x00 << 2) //< SPI interface Read operation in Control Phase | |
| 51 | #define _W5500_SPI_WRITE_ (0x01 << 2) //< SPI interface Write operation in Control Phase | |
| 52 | ||
| 53 | #define WIZCHIP_CREG_BLOCK 0x00 //< Common register block | |
| 54 | #define WIZCHIP_SREG_BLOCK(N) (1+4*N) //< Socket N register block | |
| 55 | #define WIZCHIP_TXBUF_BLOCK(N) (2+4*N) //< Socket N Tx buffer address block | |
| 56 | #define WIZCHIP_RXBUF_BLOCK(N) (3+4*N) //< Socket N Rx buffer address block | |
| 57 | ||
| 58 | #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address | |
| 59 | ||
| 60 | ||
| 61 | /////////////////////////////////////// | |
| 62 | // Definition For Legacy Chip Driver // | |
| 63 | /////////////////////////////////////// | |
| 64 | #define IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR) ///< The defined for legacy chip driver | |
| 65 | #define IINCHIP_WRITE(ADDR,VAL) WIZCHIP_WRITE(ADDR,VAL) ///< The defined for legacy chip driver | |
| 66 | #define IINCHIP_READ_BUF(ADDR,BUF,LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN) ///< The defined for legacy chip driver | |
| 67 | #define IINCHIP_WRITE_BUF(ADDR,BUF,LEN) WIZCHIP_WRITE(ADDR,BUF,LEN) ///< The defined for legacy chip driver | |
| 68 | ||
| 69 | ////////////////////////////// | |
| 70 | //-------------------------- defgroup --------------------------------- | |
| 71 | /** | |
| 72 | * @defgroup W5500 W5500 | |
| 73 | * | |
| 74 | * @brief WHIZCHIP register defines and I/O functions of @b W5500. | |
| 75 | * | |
| 76 | * - @ref WIZCHIP_register : @ref Common_register_group and @ref Socket_register_group | |
| 77 | * - @ref WIZCHIP_IO_Functions : @ref Basic_IO_function, @ref Common_register_access_function and @ref Socket_register_access_function | |
| 78 | */ | |
| 79 | ||
| 80 | ||
| 81 | /** | |
| 82 | * @defgroup WIZCHIP_register WIZCHIP register | |
| 83 | * @ingroup W5500 | |
| 84 | * | |
| 85 | * @brief WHIZCHIP register defines register group of @b W5500. | |
| 86 | * | |
| 87 | * - @ref Common_register_group : Common register group | |
| 88 | * - @ref Socket_register_group : \c SOCKET n register group | |
| 89 | */ | |
| 90 | ||
| 91 | ||
| 92 | /** | |
| 93 | * @defgroup WIZCHIP_IO_Functions WIZCHIP I/O functions | |
| 94 | * @ingroup W5500 | |
| 95 | * | |
| 96 | * @brief This supports the basic I/O functions for @ref WIZCHIP_register. | |
| 97 | * | |
| 98 | * - <b> Basic I/O function </b> \n | |
| 99 | * WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() \n\n | |
| 100 | * | |
| 101 | * - @ref Common_register_group <b>access functions</b> \n | |
| 102 | * -# @b Mode \n | |
| 103 | * getMR(), setMR() | |
| 104 | * -# @b Interrupt \n | |
| 105 | * getIR(), setIR(), getIMR(), setIMR(), getSIR(), setSIR(), getSIMR(), setSIMR(), getINTLEVEL(), setINTLEVEL() | |
| 106 | * -# <b> Network Information </b> \n | |
| 107 | * getSHAR(), setSHAR(), getGAR(), setGAR(), getSUBR(), setSUBR(), getSIPR(), setSIPR() | |
| 108 | * -# @b Retransmission \n | |
| 109 | * getRCR(), setRCR(), getRTR(), setRTR() | |
| 110 | * -# @b PPPoE \n | |
| 111 | * getPTIMER(), setPTIMER(), getPMAGIC(), getPMAGIC(), getPSID(), setPSID(), getPHAR(), setPHAR(), getPMRU(), setPMRU() | |
| 112 | * -# <b> ICMP packet </b>\n | |
| 113 | * getUIPR(), getUPORTR() | |
| 114 | * -# @b etc. \n | |
| 115 | * getPHYCFGR(), setPHYCFGR(), getVERSIONR() \n\n | |
| 116 | * | |
| 117 | * - \ref Socket_register_group <b>access functions</b> \n | |
| 118 | * -# <b> SOCKET control</b> \n | |
| 119 | * getSn_MR(), setSn_MR(), getSn_CR(), setSn_CR(), getSn_IMR(), setSn_IMR(), getSn_IR(), setSn_IR() | |
| 120 | * -# <b> SOCKET information</b> \n | |
| 121 | * getSn_SR(), getSn_DHAR(), setSn_DHAR(), getSn_PORT(), setSn_PORT(), getSn_DIPR(), setSn_DIPR(), getSn_DPORT(), setSn_DPORT() | |
| 122 | * getSn_MSSR(), setSn_MSSR() | |
| 123 | * -# <b> SOCKET communication </b> \n | |
| 124 | * getSn_RXBUF_SIZE(), setSn_RXBUF_SIZE(), getSn_TXBUF_SIZE(), setSn_TXBUF_SIZE() \n | |
| 125 | * getSn_TX_RD(), getSn_TX_WR(), setSn_TX_WR() \n | |
| 126 | * getSn_RX_RD(), setSn_RX_RD(), getSn_RX_WR() \n | |
| 127 | * getSn_TX_FSR(), getSn_RX_RSR(), getSn_KPALVTR(), setSn_KPALVTR() | |
| 128 | * -# <b> IP header field </b> \n | |
| 129 | * getSn_FRAG(), setSn_FRAG(), getSn_TOS(), setSn_TOS() \n | |
| 130 | * getSn_TTL(), setSn_TTL() | |
| 131 | */ | |
| 132 | ||
| 133 | ||
| 134 | ||
| 135 | /** | |
| 136 | * @defgroup Common_register_group Common register | |
| 137 | * @ingroup WIZCHIP_register | |
| 138 | * | |
| 139 | * @brief Common register group\n | |
| 140 | * It set the basic for the networking\n | |
| 141 | * It set the configuration such as interrupt, network information, ICMP, etc. | |
| 142 | * @details | |
| 143 | * @sa MR : Mode register. | |
| 144 | * @sa GAR, SUBR, SHAR, SIPR | |
| 145 | * @sa INTLEVEL, IR, IMR, SIR, SIMR : Interrupt. | |
| 146 | * @sa RTR, RCR : Data retransmission. | |
| 147 | * @sa PTIMER, PMAGIC, PHAR, PSID, PMRU : PPPoE. | |
| 148 | * @sa UIPR, UPORTR : ICMP message. | |
| 149 | * @sa PHYCFGR, VERSIONR : etc. | |
| 150 | */ | |
| 151 | ||
| 152 | ||
| 153 | ||
| 154 | /** | |
| 155 | * @defgroup Socket_register_group Socket register | |
| 156 | * @ingroup WIZCHIP_register | |
| 157 | * | |
| 158 | * @brief Socket register group.\n | |
| 159 | * Socket register configures and control SOCKETn which is necessary to data communication. | |
| 160 | * @details | |
| 161 | * @sa Sn_MR, Sn_CR, Sn_IR, Sn_IMR : SOCKETn Control | |
| 162 | * @sa Sn_SR, Sn_PORT, Sn_DHAR, Sn_DIPR, Sn_DPORT : SOCKETn Information | |
| 163 | * @sa Sn_MSSR, Sn_TOS, Sn_TTL, Sn_KPALVTR, Sn_FRAG : Internet protocol. | |
| 164 | * @sa Sn_RXBUF_SIZE, Sn_TXBUF_SIZE, Sn_TX_FSR, Sn_TX_RD, Sn_TX_WR, Sn_RX_RSR, Sn_RX_RD, Sn_RX_WR : Data communication | |
| 165 | */ | |
| 166 | ||
| 167 | ||
| 168 | ||
| 169 | /** | |
| 170 | * @defgroup Basic_IO_function Basic I/O function | |
| 171 | * @ingroup WIZCHIP_IO_Functions | |
| 172 | * @brief These are basic input/output functions to read values from register or write values to register. | |
| 173 | */ | |
| 174 | ||
| 175 | /** | |
| 176 | * @defgroup Common_register_access_function Common register access functions | |
| 177 | * @ingroup WIZCHIP_IO_Functions | |
| 178 | * @brief These are functions to access <b>common registers</b>. | |
| 179 | */ | |
| 180 | ||
| 181 | /** | |
| 182 | * @defgroup Socket_register_access_function Socket register access functions | |
| 183 | * @ingroup WIZCHIP_IO_Functions | |
| 184 | * @brief These are functions to access <b>socket registers</b>. | |
| 185 | */ | |
| 186 | ||
| 187 | //------------------------------- defgroup end -------------------------------------------- | |
| 188 | //----------------------------- W5500 Common Registers IOMAP ----------------------------- | |
| 189 | /** | |
| 190 | * @ingroup Common_register_group | |
| 191 | * @brief Mode Register address(R/W)\n | |
| 192 | * @ref MR is used for S/W reset, ping block mode, PPPoE mode and etc. | |
| 193 | * @details Each bit of @ref MR defined as follows. | |
| 194 | * <table> | |
| 195 | * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> | |
| 196 | * <tr> <td>RST</td> <td>Reserved</td> <td>WOL</td> <td>PB</td> <td>PPPoE</td> <td>Reserved</td> <td>FARP</td> <td>Reserved</td> </tr> | |
| 197 | * </table> | |
| 198 | * - \ref MR_RST : Reset | |
| 199 | * - \ref MR_WOL : Wake on LAN | |
| 200 | * - \ref MR_PB : Ping block | |
| 201 | * - \ref MR_PPPOE : PPPoE mode | |
| 202 | * - \ref MR_FARP : Force ARP mode | |
| 203 | */ | |
| 204 | #define MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 205 | ||
| 206 | /** | |
| 207 | * @ingroup Common_register_group | |
| 208 | * @brief Gateway IP Register address(R/W) | |
| 209 | * @details @ref GAR configures the default gateway address. | |
| 210 | */ | |
| 211 | #define GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 212 | ||
| 213 | /** | |
| 214 | * @ingroup Common_register_group | |
| 215 | * @brief Subnet mask Register address(R/W) | |
| 216 | * @details @ref SUBR configures the subnet mask address. | |
| 217 | */ | |
| 218 | #define SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 219 | ||
| 220 | /** | |
| 221 | * @ingroup Common_register_group | |
| 222 | * @brief Source MAC Register address(R/W) | |
| 223 | * @details @ref SHAR configures the source hardware address. | |
| 224 | */ | |
| 225 | #define SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 226 | ||
| 227 | /** | |
| 228 | * @ingroup Common_register_group | |
| 229 | * @brief Source IP Register address(R/W) | |
| 230 | * @details @ref SIPR configures the source IP address. | |
| 231 | */ | |
| 232 | #define SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 233 | ||
| 234 | /** | |
| 235 | * @ingroup Common_register_group | |
| 236 | * @brief Set Interrupt low level timer register address(R/W) | |
| 237 | * @details @ref INTLEVEL configures the Interrupt Assert Time. | |
| 238 | */ | |
| 239 | #define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 240 | ||
| 241 | /** | |
| 242 | * @ingroup Common_register_group | |
| 243 | * @brief Interrupt Register(R/W) | |
| 244 | * @details @ref IR indicates the interrupt status. Each bit of @ref IR will be still until the bit will be written to by the host. | |
| 245 | * If @ref IR is not equal to x00 INTn PIN is asserted to low until it is x00\n\n | |
| 246 | * Each bit of @ref IR defined as follows. | |
| 247 | * <table> | |
| 248 | * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> | |
| 249 | * <tr> <td>CONFLICT</td> <td>UNREACH</td> <td>PPPoE</td> <td>MP</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr> | |
| 250 | * </table> | |
| 251 | * - \ref IR_CONFLICT : IP conflict | |
| 252 | * - \ref IR_UNREACH : Destination unreachable | |
| 253 | * - \ref IR_PPPoE : PPPoE connection close | |
| 254 | * - \ref IR_MP : Magic packet | |
| 255 | */ | |
| 256 | #define IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 257 | ||
| 258 | /** | |
| 259 | * @ingroup Common_register_group | |
| 260 | * @brief Interrupt mask register(R/W) | |
| 261 | * @details @ref IMR is used to mask interrupts. Each bit of @ref IMR corresponds to each bit of @ref IR. | |
| 262 | * When a bit of @ref IMR is and the corresponding bit of @ref IR is an interrupt will be issued. In other words, | |
| 263 | * if a bit of @ref IMR is an interrupt will not be issued even if the corresponding bit of @ref IR is \n\n | |
| 264 | * Each bit of @ref IMR defined as the following. | |
| 265 | * <table> | |
| 266 | * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> | |
| 267 | * <tr> <td>IM_IR7</td> <td>IM_IR6</td> <td>IM_IR5</td> <td>IM_IR4</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr> | |
| 268 | * </table> | |
| 269 | * - \ref IM_IR7 : IP Conflict Interrupt Mask | |
| 270 | * - \ref IM_IR6 : Destination unreachable Interrupt Mask | |
| 271 | * - \ref IM_IR5 : PPPoE Close Interrupt Mask | |
| 272 | * - \ref IM_IR4 : Magic Packet Interrupt Mask | |
| 273 | */ | |
| 274 | #define IMR (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 275 | ||
| 276 | /** | |
| 277 | * @ingroup Common_register_group | |
| 278 | * @brief Socket Interrupt Register(R/W) | |
| 279 | * @details @ref SIR indicates the interrupt status of Socket.\n | |
| 280 | * Each bit of @ref SIR be still until @ref Sn_IR is cleared by the host.\n | |
| 281 | * If @ref Sn_IR is not equal to x00 the n-th bit of @ref SIR is and INTn PIN is asserted until @ref SIR is x00 */ | |
| 282 | #define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 283 | ||
| 284 | /** | |
| 285 | * @ingroup Common_register_group | |
| 286 | * @brief Socket Interrupt Mask Register(R/W) | |
| 287 | * @details Each bit of @ref SIMR corresponds to each bit of @ref SIR. | |
| 288 | * When a bit of @ref SIMR is and the corresponding bit of @ref SIR is Interrupt will be issued. | |
| 289 | * In other words, if a bit of @ref SIMR is an interrupt will be not issued even if the corresponding bit of @ref SIR is | |
| 290 | */ | |
| 291 | #define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 292 | ||
| 293 | /** | |
| 294 | * @ingroup Common_register_group | |
| 295 | * @brief Timeout register address( 1 is 100us )(R/W) | |
| 296 | * @details @ref RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of @ref RTR is x07D0or 000 | |
| 297 | * And so the default timeout period is 200ms(100us X 2000). During the time configured by @ref RTR, W5500 waits for the peer response | |
| 298 | * to the packet that is transmitted by \ref Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). | |
| 299 | * If the peer does not respond within the @ref RTR time, W5500 retransmits the packet or issues timeout. | |
| 300 | */ | |
| 301 | #define RTR (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 302 | ||
| 303 | /** | |
| 304 | * @ingroup Common_register_group | |
| 305 | * @brief Retry count register(R/W) | |
| 306 | * @details @ref RCR configures the number of time of retransmission. | |
| 307 | * When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (@ref Sn_IR[TIMEOUT] = . | |
| 308 | */ | |
| 309 | #define RCR (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 310 | ||
| 311 | /** | |
| 312 | * @ingroup Common_register_group | |
| 313 | * @brief PPP LCP Request Timer register in PPPoE mode(R/W) | |
| 314 | * @details @ref PTIMER configures the time for sending LCP echo request. The unit of time is 25ms. | |
| 315 | */ | |
| 316 | #define PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 317 | ||
| 318 | /** | |
| 319 | * @ingroup Common_register_group | |
| 320 | * @brief PPP LCP Magic number register in PPPoE mode(R/W) | |
| 321 | * @details @ref PMAGIC configures the 4bytes magic number to be used in LCP negotiation. | |
| 322 | */ | |
| 323 | #define PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 324 | ||
| 325 | /** | |
| 326 | * @ingroup Common_register_group | |
| 327 | * @brief PPP Destination MAC Register address(R/W) | |
| 328 | * @details @ref PHAR configures the PPPoE server hardware address that is acquired during PPPoE connection process. | |
| 329 | */ | |
| 330 | #define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 331 | ||
| 332 | /** | |
| 333 | * @ingroup Common_register_group | |
| 334 | * @brief PPP Session Identification Register(R/W) | |
| 335 | * @details @ref PSID configures the PPPoE sever session ID acquired during PPPoE connection process. | |
| 336 | */ | |
| 337 | #define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 338 | ||
| 339 | /** | |
| 340 | * @ingroup Common_register_group | |
| 341 | * @brief PPP Maximum Segment Size(MSS) register(R/W) | |
| 342 | * @details @ref PMRU configures the maximum receive unit of PPPoE. | |
| 343 | */ | |
| 344 | #define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 345 | ||
| 346 | /** | |
| 347 | * @ingroup Common_register_group | |
| 348 | * @brief Unreachable IP register address in UDP mode(R) | |
| 349 | * @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number | |
| 350 | * which socket is not open and @ref UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR indicates | |
| 351 | * the destination IP address & port number respectively. | |
| 352 | */ | |
| 353 | #define UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 354 | ||
| 355 | /** | |
| 356 | * @ingroup Common_register_group | |
| 357 | * @brief Unreachable Port register address in UDP mode(R) | |
| 358 | * @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number | |
| 359 | * which socket is not open and @ref UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR | |
| 360 | * indicates the destination IP address & port number respectively. | |
| 361 | */ | |
| 362 | #define UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 363 | ||
| 364 | /** | |
| 365 | * @ingroup Common_register_group | |
| 366 | * @brief PHY Status Register(R/W) | |
| 367 | * @details @ref PHYCFGR configures PHY operation mode and resets PHY. In addition, @ref PHYCFGR indicates the status of PHY such as duplex, Speed, Link. | |
| 368 | */ | |
| 369 | #define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 370 | ||
| 371 | // Reserved (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 372 | // Reserved (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 373 | // Reserved (_W5500_IO_BASE_ + (0x0031 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 374 | // Reserved (_W5500_IO_BASE_ + (0x0032 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 375 | // Reserved (_W5500_IO_BASE_ + (0x0033 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 376 | // Reserved (_W5500_IO_BASE_ + (0x0034 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 377 | // Reserved (_W5500_IO_BASE_ + (0x0035 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 378 | // Reserved (_W5500_IO_BASE_ + (0x0036 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 379 | // Reserved (_W5500_IO_BASE_ + (0x0037 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 380 | // Reserved (_W5500_IO_BASE_ + (0x0038 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 381 | ||
| 382 | /** | |
| 383 | * @ingroup Common_register_group | |
| 384 | * @brief chip version register address(R) | |
| 385 | * @details @ref VERSIONR always indicates the W5500 version as @b 0x04. | |
| 386 | */ | |
| 387 | #define VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3)) | |
| 388 | ||
| 389 | ||
| 390 | //----------------------------- W5500 Socket Registers IOMAP ----------------------------- | |
| 391 | /** | |
| 392 | * @ingroup Socket_register_group | |
| 393 | * @brief socket Mode register(R/W) | |
| 394 | * @details @ref Sn_MR configures the option or protocol type of Socket n.\n\n | |
| 395 | * Each bit of @ref Sn_MR defined as the following. | |
| 396 | * <table> | |
| 397 | * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> | |
| 398 | * <tr> <td>MULTI/MFEN</td> <td>BCASTB</td> <td>ND/MC/MMB</td> <td>UCASTB/MIP6B</td> <td>Protocol[3]</td> <td>Protocol[2]</td> <td>Protocol[1]</td> <td>Protocol[0]</td> </tr> | |
| 399 | * </table> | |
| 400 | * - @ref Sn_MR_MULTI : Support UDP Multicasting | |
| 401 | * - @ref Sn_MR_BCASTB : Broadcast block <b>in UDP Multicasting</b> | |
| 402 | * - @ref Sn_MR_ND : No Delayed Ack(TCP) flag | |
| 403 | * - @ref Sn_MR_MC : IGMP version used <b>in UDP mulitcasting</b> | |
| 404 | * - @ref Sn_MR_MMB : Multicast Blocking <b>in @ref Sn_MR_MACRAW mode</b> | |
| 405 | * - @ref Sn_MR_UCASTB : Unicast Block <b>in UDP Multicating</b> | |
| 406 | * - @ref Sn_MR_MIP6B : IPv6 packet Blocking <b>in @ref Sn_MR_MACRAW mode</b> | |
| 407 | * - <b>Protocol</b> | |
| 408 | * <table> | |
| 409 | * <tr> <td><b>Protocol[3]</b></td> <td><b>Protocol[2]</b></td> <td><b>Protocol[1]</b></td> <td><b>Protocol[0]</b></td> <td>@b Meaning</td> </tr> | |
| 410 | * <tr> <td>0</td> <td>0</td> <td>0</td> <td>0</td> <td>Closed</td> </tr> | |
| 411 | * <tr> <td>0</td> <td>0</td> <td>0</td> <td>1</td> <td>TCP</td> </tr> | |
| 412 | * <tr> <td>0</td> <td>0</td> <td>1</td> <td>0</td> <td>UDP</td> </tr> | |
| 413 | * <tr> <td>0</td> <td>1</td> <td>0</td> <td>0</td> <td>MACRAW</td> </tr> | |
| 414 | * </table> | |
| 415 | * - @ref Sn_MR_MACRAW : MAC LAYER RAW SOCK \n | |
| 416 | * - @ref Sn_MR_UDP : UDP | |
| 417 | * - @ref Sn_MR_TCP : TCP | |
| 418 | * - @ref Sn_MR_CLOSE : Unused socket | |
| 419 | * @note MACRAW mode should be only used in Socket 0. | |
| 420 | */ | |
| 421 | #define Sn_MR(N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 422 | ||
| 423 | /** | |
| 424 | * @ingroup Socket_register_group | |
| 425 | * @brief Socket command register(R/W) | |
| 426 | * @details This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE.\n | |
| 427 | * After W5500 accepts the command, the @ref Sn_CR register is automatically cleared to 0x00. | |
| 428 | * Even though @ref Sn_CR is cleared to 0x00, the command is still being processed.\n | |
| 429 | * To check whether the command is completed or not, please check the @ref Sn_IR or @ref Sn_SR. | |
| 430 | * - @ref Sn_CR_OPEN : Initialize or open socket. | |
| 431 | * - @ref Sn_CR_LISTEN : Wait connection request in TCP mode(<b>Server mode</b>) | |
| 432 | * - @ref Sn_CR_CONNECT : Send connection request in TCP mode(<b>Client mode</b>) | |
| 433 | * - @ref Sn_CR_DISCON : Send closing request in TCP mode. | |
| 434 | * - @ref Sn_CR_CLOSE : Close socket. | |
| 435 | * - @ref Sn_CR_SEND : Update TX buffer pointer and send data. | |
| 436 | * - @ref Sn_CR_SEND_MAC : Send data with MAC address, so without ARP process. | |
| 437 | * - @ref Sn_CR_SEND_KEEP : Send keep alive message. | |
| 438 | * - @ref Sn_CR_RECV : Update RX buffer pointer and receive data. | |
| 439 | */ | |
| 440 | #define Sn_CR(N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 441 | ||
| 442 | /** | |
| 443 | * @ingroup Socket_register_group | |
| 444 | * @brief Socket interrupt register(R) | |
| 445 | * @details @ref Sn_IR indicates the status of Socket Interrupt such as establishment, termination, receiving data, timeout).\n | |
| 446 | * When an interrupt occurs and the corresponding bit of @ref Sn_IMR is the corresponding bit of @ref Sn_IR becomes \n | |
| 447 | * In order to clear the @ref Sn_IR bit, the host should write the bit to \n | |
| 448 | * <table> | |
| 449 | * <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr> | |
| 450 | * <tr> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>SEND_OK</td> <td>TIMEOUT</td> <td>RECV</td> <td>DISCON</td> <td>CON</td> </tr> | |
| 451 | * </table> | |
| 452 | * - \ref Sn_IR_SENDOK : <b>SEND_OK Interrupt</b> | |
| 453 | * - \ref Sn_IR_TIMEOUT : <b>TIMEOUT Interrupt</b> | |
| 454 | * - \ref Sn_IR_RECV : <b>RECV Interrupt</b> | |
| 455 | * - \ref Sn_IR_DISCON : <b>DISCON Interrupt</b> | |
| 456 | * - \ref Sn_IR_CON : <b>CON Interrupt</b> | |
| 457 | */ | |
| 458 | #define Sn_IR(N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 459 | ||
| 460 | /** | |
| 461 | * @ingroup Socket_register_group | |
| 462 | * @brief Socket status register(R) | |
| 463 | * @details @ref Sn_SR indicates the status of Socket n.\n | |
| 464 | * The status of Socket n is changed by @ref Sn_CR or some special control packet as SYN, FIN packet in TCP. | |
| 465 | * @par Normal status | |
| 466 | * - @ref SOCK_CLOSED : Closed | |
| 467 | * - @ref SOCK_INIT : Initiate state | |
| 468 | * - @ref SOCK_LISTEN : Listen state | |
| 469 | * - @ref SOCK_ESTABLISHED : Success to connect | |
| 470 | * - @ref SOCK_CLOSE_WAIT : Closing state | |
| 471 | * - @ref SOCK_UDP : UDP socket | |
| 472 | * - @ref SOCK_MACRAW : MAC raw mode socket | |
| 473 | *@par Temporary status during changing the status of Socket n. | |
| 474 | * - @ref SOCK_SYNSENT : This indicates Socket n sent the connect-request packet (SYN packet) to a peer. | |
| 475 | * - @ref SOCK_SYNRECV : It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer. | |
| 476 | * - @ref SOCK_FIN_WAIT : Connection state | |
| 477 | * - @ref SOCK_CLOSING : Closing state | |
| 478 | * - @ref SOCK_TIME_WAIT : Closing state | |
| 479 | * - @ref SOCK_LAST_ACK : Closing state | |
| 480 | */ | |
| 481 | #define Sn_SR(N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 482 | ||
| 483 | /** | |
| 484 | * @ingroup Socket_register_group | |
| 485 | * @brief source port register(R/W) | |
| 486 | * @details @ref Sn_PORT configures the source port number of Socket n. | |
| 487 | * It is valid when Socket n is used in TCP/UPD mode. It should be set before OPEN command is ordered. | |
| 488 | */ | |
| 489 | #define Sn_PORT(N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 490 | ||
| 491 | /** | |
| 492 | * @ingroup Socket_register_group | |
| 493 | * @brief Peer MAC register address(R/W) | |
| 494 | * @details @ref Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or | |
| 495 | * it indicates that it is acquired in ARP-process by CONNECT/SEND command. | |
| 496 | */ | |
| 497 | #define Sn_DHAR(N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 498 | ||
| 499 | /** | |
| 500 | * @ingroup Socket_register_group | |
| 501 | * @brief Peer IP register address(R/W) | |
| 502 | * @details @ref Sn_DIPR configures or indicates the destination IP address of Socket n. It is valid when Socket n is used in TCP/UDP mode. | |
| 503 | * In TCP client mode, it configures an IP address of �TCP serverbefore CONNECT command. | |
| 504 | * In TCP server mode, it indicates an IP address of �TCP clientafter successfully establishing connection. | |
| 505 | * In UDP mode, it configures an IP address of peer to be received the UDP packet by SEND or SEND_MAC command. | |
| 506 | */ | |
| 507 | #define Sn_DIPR(N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 508 | ||
| 509 | /** | |
| 510 | * @ingroup Socket_register_group | |
| 511 | * @brief Peer port register address(R/W) | |
| 512 | * @details @ref Sn_DPORT configures or indicates the destination port number of Socket n. It is valid when Socket n is used in TCP/UDP mode. | |
| 513 | * In �TCP clientmode, it configures the listen port number of �TCP serverbefore CONNECT command. | |
| 514 | * In �TCP Servermode, it indicates the port number of TCP client after successfully establishing connection. | |
| 515 | * In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command. | |
| 516 | */ | |
| 517 | #define Sn_DPORT(N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 518 | ||
| 519 | /** | |
| 520 | * @ingroup Socket_register_group | |
| 521 | * @brief Maximum Segment Size(Sn_MSSR0) register address(R/W) | |
| 522 | * @details @ref Sn_MSSR configures or indicates the MTU(Maximum Transfer Unit) of Socket n. | |
| 523 | */ | |
| 524 | #define Sn_MSSR(N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 525 | ||
| 526 | // Reserved (_W5500_IO_BASE_ + (0x0014 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 527 | ||
| 528 | /** | |
| 529 | * @ingroup Socket_register_group | |
| 530 | * @brief IP Type of Service(TOS) Register(R/W) | |
| 531 | * @details @ref Sn_TOS configures the TOS(Type Of Service field in IP Header) of Socket n. | |
| 532 | * It is set before OPEN command. | |
| 533 | */ | |
| 534 | #define Sn_TOS(N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 535 | /** | |
| 536 | * @ingroup Socket_register_group | |
| 537 | * @brief IP Time to live(TTL) Register(R/W) | |
| 538 | * @details @ref Sn_TTL configures the TTL(Time To Live field in IP header) of Socket n. | |
| 539 | * It is set before OPEN command. | |
| 540 | */ | |
| 541 | #define Sn_TTL(N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 542 | // Reserved (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 543 | // Reserved (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 544 | // Reserved (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 545 | // Reserved (_W5500_IO_BASE_ + (0x001A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 546 | // Reserved (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 547 | // Reserved (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 548 | // Reserved (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 549 | ||
| 550 | /** | |
| 551 | * @ingroup Socket_register_group | |
| 552 | * @brief Receive memory size register(R/W) | |
| 553 | * @details @ref Sn_RXBUF_SIZE configures the RX buffer block size of Socket n. | |
| 554 | * Socket n RX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes. | |
| 555 | * If a different size is configured, the data cannot be normally received from a peer. | |
| 556 | * Although Socket n RX Buffer Block size is initially configured to 2Kbytes, | |
| 557 | * user can re-configure its size using @ref Sn_RXBUF_SIZE. The total sum of @ref Sn_RXBUF_SIZE can not be exceed 16Kbytes. | |
| 558 | * When exceeded, the data reception error is occurred. | |
| 559 | */ | |
| 560 | #define Sn_RXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 561 | ||
| 562 | /** | |
| 563 | * @ingroup Socket_register_group | |
| 564 | * @brief Transmit memory size register(R/W) | |
| 565 | * @details @ref Sn_TXBUF_SIZE configures the TX buffer block size of Socket n. Socket n TX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes. | |
| 566 | * If a different size is configured, the data can�t be normally transmitted to a peer. | |
| 567 | * Although Socket n TX Buffer Block size is initially configured to 2Kbytes, | |
| 568 | * user can be re-configure its size using @ref Sn_TXBUF_SIZE. The total sum of @ref Sn_TXBUF_SIZE can not be exceed 16Kbytes. | |
| 569 | * When exceeded, the data transmission error is occurred. | |
| 570 | */ | |
| 571 | #define Sn_TXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 572 | ||
| 573 | /** | |
| 574 | * @ingroup Socket_register_group | |
| 575 | * @brief Transmit free memory size register(R) | |
| 576 | * @details @ref Sn_TX_FSR indicates the free size of Socket n TX Buffer Block. It is initialized to the configured size by @ref Sn_TXBUF_SIZE. | |
| 577 | * Data bigger than @ref Sn_TX_FSR should not be saved in the Socket n TX Buffer because the bigger data overwrites the previous saved data not yet sent. | |
| 578 | * Therefore, check before saving the data to the Socket n TX Buffer, and if data is equal or smaller than its checked size, | |
| 579 | * transmit the data with SEND/SEND_MAC command after saving the data in Socket n TX buffer. But, if data is bigger than its checked size, | |
| 580 | * transmit the data after dividing into the checked size and saving in the Socket n TX buffer. | |
| 581 | */ | |
| 582 | #define Sn_TX_FSR(N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 583 | ||
| 584 | /** | |
| 585 | * @ingroup Socket_register_group | |
| 586 | * @brief Transmit memory read pointer register address(R) | |
| 587 | * @details @ref Sn_TX_RD is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP. | |
| 588 | * After its initialization, it is auto-increased by SEND command. | |
| 589 | * SEND command transmits the saved data from the current @ref Sn_TX_RD to the @ref Sn_TX_WR in the Socket n TX Buffer. | |
| 590 | * After transmitting the saved data, the SEND command increases the @ref Sn_TX_RD as same as the @ref Sn_TX_WR. | |
| 591 | * If its increment value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), | |
| 592 | * then the carry bit is ignored and will automatically update with the lower 16bits value. | |
| 593 | */ | |
| 594 | #define Sn_TX_RD(N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 595 | ||
| 596 | /** | |
| 597 | * @ingroup Socket_register_group | |
| 598 | * @brief Transmit memory write pointer register address(R/W) | |
| 599 | * @details @ref Sn_TX_WR is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP.\n | |
| 600 | * It should be read or be updated like as follows.\n | |
| 601 | * 1. Read the starting address for saving the transmitting data.\n | |
| 602 | * 2. Save the transmitting data from the starting address of Socket n TX buffer.\n | |
| 603 | * 3. After saving the transmitting data, update @ref Sn_TX_WR to the increased value as many as transmitting data size. | |
| 604 | * If the increment value exceeds the maximum value 0xFFFF(greater than 0x10000 and the carry bit occurs), | |
| 605 | * then the carry bit is ignored and will automatically update with the lower 16bits value.\n | |
| 606 | * 4. Transmit the saved data in Socket n TX Buffer by using SEND/SEND command | |
| 607 | */ | |
| 608 | #define Sn_TX_WR(N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 609 | ||
| 610 | /** | |
| 611 | * @ingroup Socket_register_group | |
| 612 | * @brief Received data size register(R) | |
| 613 | * @details @ref Sn_RX_RSR indicates the data size received and saved in Socket n RX Buffer. | |
| 614 | * @ref Sn_RX_RSR does not exceed the @ref Sn_RXBUF_SIZE and is calculated as the difference between | |
| 615 | * �Socket n RX Write Pointer (@ref Sn_RX_WR)and �Socket n RX Read Pointer (@ref Sn_RX_RD) | |
| 616 | */ | |
| 617 | #define Sn_RX_RSR(N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 618 | ||
| 619 | /** | |
| 620 | * @ingroup Socket_register_group | |
| 621 | * @brief Read point of Receive memory(R/W) | |
| 622 | * @details @ref Sn_RX_RD is initialized by OPEN command. Make sure to be read or updated as follows.\n | |
| 623 | * 1. Read the starting save address of the received data.\n | |
| 624 | * 2. Read data from the starting address of Socket n RX Buffer.\n | |
| 625 | * 3. After reading the received data, Update @ref Sn_RX_RD to the increased value as many as the reading size. | |
| 626 | * If the increment value exceeds the maximum value 0xFFFF, that is, is greater than 0x10000 and the carry bit occurs, | |
| 627 | * update with the lower 16bits value ignored the carry bit.\n | |
| 628 | * 4. Order RECV command is for notifying the updated @ref Sn_RX_RD to W5500. | |
| 629 | */ | |
| 630 | #define Sn_RX_RD(N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 631 | ||
| 632 | /** | |
| 633 | * @ingroup Socket_register_group | |
| 634 | * @brief Write point of Receive memory(R) | |
| 635 | * @details @ref Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception. | |
| 636 | * If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), | |
| 637 | * then the carry bit is ignored and will automatically update with the lower 16bits value. | |
| 638 | */ | |
| 639 | #define Sn_RX_WR(N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 640 | ||
| 641 | /** | |
| 642 | * @ingroup Socket_register_group | |
| 643 | * @brief socket interrupt mask register(R) | |
| 644 | * @details @ref Sn_IMR masks the interrupt of Socket n. | |
| 645 | * Each bit corresponds to each bit of @ref Sn_IR. When a Socket n Interrupt is occurred and the corresponding bit of @ref Sn_IMR is | |
| 646 | * the corresponding bit of @ref Sn_IR becomes When both the corresponding bit of @ref Sn_IMR and @ref Sn_IR are and the n-th bit of @ref IR is | |
| 647 | * Host is interrupted by asserted INTn PIN to low. | |
| 648 | */ | |
| 649 | #define Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 650 | ||
| 651 | /** | |
| 652 | * @ingroup Socket_register_group | |
| 653 | * @brief Fragment field value in IP header register(R/W) | |
| 654 | * @details @ref Sn_FRAG configures the FRAG(Fragment field in IP header). | |
| 655 | */ | |
| 656 | #define Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 657 | ||
| 658 | /** | |
| 659 | * @ingroup Socket_register_group | |
| 660 | * @brief Keep Alive Timer register(R/W) | |
| 661 | * @details @ref Sn_KPALVTR configures the transmitting timer of �KEEP ALIVE(KA)packet of SOCKETn. It is valid only in TCP mode, | |
| 662 | * and ignored in other modes. The time unit is 5s. | |
| 663 | * KA packet is transmittable after @ref Sn_SR is changed to SOCK_ESTABLISHED and after the data is transmitted or received to/from a peer at least once. | |
| 664 | * In case of '@ref Sn_KPALVTR > 0', W5500 automatically transmits KA packet after time-period for checking the TCP connection (Auto-keepalive-process). | |
| 665 | * In case of '@ref Sn_KPALVTR = 0', Auto-keep-alive-process will not operate, | |
| 666 | * and KA packet can be transmitted by SEND_KEEP command by the host (Manual-keep-alive-process). | |
| 667 | * Manual-keep-alive-process is ignored in case of '@ref Sn_KPALVTR > 0'. | |
| 668 | */ | |
| 669 | #define Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 670 | ||
| 671 | //#define Sn_TSR(N) (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3)) | |
| 672 | ||
| 673 | ||
| 674 | //----------------------------- W5500 Register values ----------------------------- | |
| 675 | ||
| 676 | /* MODE register values */ | |
| 677 | /** | |
| 678 | * @brief Reset | |
| 679 | * @details If this bit is All internal registers will be initialized. It will be automatically cleared as after S/W reset. | |
| 680 | */ | |
| 681 | #define MR_RST 0x80 | |
| 682 | ||
| 683 | /** | |
| 684 | * @brief Wake on LAN | |
| 685 | * @details 0 : Disable WOL mode\n | |
| 686 | * 1 : Enable WOL mode\n | |
| 687 | * If WOL mode is enabled and the received magic packet over UDP has been normally processed, the Interrupt PIN (INTn) asserts to low. | |
| 688 | * When using WOL mode, the UDP Socket should be opened with any source port number. (Refer to Socket n Mode Register (@ref Sn_MR) for opening Socket.) | |
| 689 | * @note The magic packet over UDP supported by W5500 consists of 6 bytes synchronization stream (xFFFFFFFFFFFF and | |
| 690 | * 16 times Target MAC address stream in UDP payload. The options such like password are ignored. You can use any UDP source port number for WOL mode. | |
| 691 | */ | |
| 692 | #define MR_WOL 0x20 | |
| 693 | ||
| 694 | /** | |
| 695 | * @brief Ping block | |
| 696 | * @details 0 : Disable Ping block\n | |
| 697 | * 1 : Enable Ping block\n | |
| 698 | * If the bit is it blocks the response to a ping request. | |
| 699 | */ | |
| 700 | #define MR_PB 0x10 | |
| 701 | ||
| 702 | /** | |
| 703 | * @brief Enable PPPoE | |
| 704 | * @details 0 : DisablePPPoE mode\n | |
| 705 | * 1 : EnablePPPoE mode\n | |
| 706 | * If you use ADSL, this bit should be | |
| 707 | */ | |
| 708 | #define MR_PPPOE 0x08 | |
| 709 | ||
| 710 | /** | |
| 711 | * @brief Enable UDP_FORCE_ARP CHECHK | |
| 712 | * @details 0 : Disable Force ARP mode\n | |
| 713 | * 1 : Enable Force ARP mode\n | |
| 714 | * In Force ARP mode, It forces on sending ARP Request whenever data is sent. | |
| 715 | */ | |
| 716 | #define MR_FARP 0x02 | |
| 717 | ||
| 718 | /* IR register values */ | |
| 719 | /** | |
| 720 | * @brief Check IP conflict. | |
| 721 | * @details Bit is set as when own source IP address is same with the sender IP address in the received ARP request. | |
| 722 | */ | |
| 723 | #define IR_CONFLICT 0x80 | |
| 724 | ||
| 725 | /** | |
| 726 | * @brief Get the destination unreachable message in UDP sending. | |
| 727 | * @details When receiving the ICMP (Destination port unreachable) packet, this bit is set as | |
| 728 | * When this bit is Destination Information such as IP address and Port number may be checked with the corresponding @ref UIPR & @ref UPORTR. | |
| 729 | */ | |
| 730 | #define IR_UNREACH 0x40 | |
| 731 | ||
| 732 | /** | |
| 733 | * @brief Get the PPPoE close message. | |
| 734 | * @details When PPPoE is disconnected during PPPoE mode, this bit is set. | |
| 735 | */ | |
| 736 | #define IR_PPPoE 0x20 | |
| 737 | ||
| 738 | /** | |
| 739 | * @brief Get the magic packet interrupt. | |
| 740 | * @details When WOL mode is enabled and receives the magic packet over UDP, this bit is set. | |
| 741 | */ | |
| 742 | #define IR_MP 0x10 | |
| 743 | ||
| 744 | ||
| 745 | /* PHYCFGR register value */ | |
| 746 | #define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask. | |
| 747 | #define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value | |
| 748 | #define PHYCFGR_OPMDC_ALLA (7<<3) | |
| 749 | #define PHYCFGR_OPMDC_PDOWN (6<<3) | |
| 750 | #define PHYCFGR_OPMDC_NA (5<<3) | |
| 751 | #define PHYCFGR_OPMDC_100FA (4<<3) | |
| 752 | #define PHYCFGR_OPMDC_100F (3<<3) | |
| 753 | #define PHYCFGR_OPMDC_100H (2<<3) | |
| 754 | #define PHYCFGR_OPMDC_10F (1<<3) | |
| 755 | #define PHYCFGR_OPMDC_10H (0<<3) | |
| 756 | #define PHYCFGR_DPX_FULL (1<<2) | |
| 757 | #define PHYCFGR_DPX_HALF (0<<2) | |
| 758 | #define PHYCFGR_SPD_100 (1<<1) | |
| 759 | #define PHYCFGR_SPD_10 (0<<1) | |
| 760 | #define PHYCFGR_LNK_ON (1<<0) | |
| 761 | #define PHYCFGR_LNK_OFF (0<<0) | |
| 762 | ||
| 763 | /* IMR register values */ | |
| 764 | /** | |
| 765 | * @brief IP Conflict Interrupt Mask. | |
| 766 | * @details 0: Disable IP Conflict Interrupt\n | |
| 767 | * 1: Enable IP Conflict Interrupt | |
| 768 | */ | |
| 769 | #define IM_IR7 0x80 | |
| 770 | ||
| 771 | /** | |
| 772 | * @brief Destination unreachable Interrupt Mask. | |
| 773 | * @details 0: Disable Destination unreachable Interrupt\n | |
| 774 | * 1: Enable Destination unreachable Interrupt | |
| 775 | */ | |
| 776 | #define IM_IR6 0x40 | |
| 777 | ||
| 778 | /** | |
| 779 | * @brief PPPoE Close Interrupt Mask. | |
| 780 | * @details 0: Disable PPPoE Close Interrupt\n | |
| 781 | * 1: Enable PPPoE Close Interrupt | |
| 782 | */ | |
| 783 | #define IM_IR5 0x20 | |
| 784 | ||
| 785 | /** | |
| 786 | * @brief Magic Packet Interrupt Mask. | |
| 787 | * @details 0: Disable Magic Packet Interrupt\n | |
| 788 | * 1: Enable Magic Packet Interrupt | |
| 789 | */ | |
| 790 | #define IM_IR4 0x10 | |
| 791 | ||
| 792 | /* Sn_MR Default values */ | |
| 793 | /** | |
| 794 | * @brief Support UDP Multicasting | |
| 795 | * @details 0 : disable Multicasting\n | |
| 796 | * 1 : enable Multicasting\n | |
| 797 | * This bit is applied only during UDP mode(P[3:0] = 010.\n | |
| 798 | * To use multicasting, @ref Sn_DIPR & @ref Sn_DPORT should be respectively configured with the multicast group IP address & port number | |
| 799 | * before Socket n is opened by OPEN command of @ref Sn_CR. | |
| 800 | */ | |
| 801 | #define Sn_MR_MULTI 0x80 | |
| 802 | ||
| 803 | /** | |
| 804 | * @brief Broadcast block in UDP Multicasting. | |
| 805 | * @details 0 : disable Broadcast Blocking\n | |
| 806 | * 1 : enable Broadcast Blocking\n | |
| 807 | * This bit blocks to receive broadcasting packet during UDP mode(P[3:0] = 010.\m | |
| 808 | * In addition, This bit does when MACRAW mode(P[3:0] = 100 | |
| 809 | */ | |
| 810 | #define Sn_MR_BCASTB 0x40 | |
| 811 | ||
| 812 | /** | |
| 813 | * @brief No Delayed Ack(TCP), Multicast flag | |
| 814 | * @details 0 : Disable No Delayed ACK option\n | |
| 815 | * 1 : Enable No Delayed ACK option\n | |
| 816 | * This bit is applied only during TCP mode (P[3:0] = 001.\n | |
| 817 | * When this bit is It sends the ACK packet without delay as soon as a Data packet is received from a peer.\n | |
| 818 | * When this bit is It sends the ACK packet after waiting for the timeout time configured by @ref RTR. | |
| 819 | */ | |
| 820 | #define Sn_MR_ND 0x20 | |
| 821 | ||
| 822 | /** | |
| 823 | * @brief Unicast Block in UDP Multicasting | |
| 824 | * @details 0 : disable Unicast Blocking\n | |
| 825 | * 1 : enable Unicast Blocking\n | |
| 826 | * This bit blocks receiving the unicast packet during UDP mode(P[3:0] = 010 and MULTI = | |
| 827 | */ | |
| 828 | #define Sn_MR_UCASTB 0x10 | |
| 829 | ||
| 830 | /** | |
| 831 | * @brief MAC LAYER RAW SOCK | |
| 832 | * @details This configures the protocol mode of Socket n. | |
| 833 | * @note MACRAW mode should be only used in Socket 0. | |
| 834 | */ | |
| 835 | #define Sn_MR_MACRAW 0x04 | |
| 836 | ||
| 837 | //#define Sn_MR_IPRAW 0x03 /**< IP LAYER RAW SOCK */ | |
| 838 | ||
| 839 | /** | |
| 840 | * @brief UDP | |
| 841 | * @details This configures the protocol mode of Socket n. | |
| 842 | */ | |
| 843 | #define Sn_MR_UDP 0x02 | |
| 844 | ||
| 845 | /** | |
| 846 | * @brief TCP | |
| 847 | * @details This configures the protocol mode of Socket n. | |
| 848 | */ | |
| 849 | #define Sn_MR_TCP 0x01 | |
| 850 | ||
| 851 | /** | |
| 852 | * @brief Unused socket | |
| 853 | * @details This configures the protocol mode of Socket n. | |
| 854 | */ | |
| 855 | #define Sn_MR_CLOSE 0x00 | |
| 856 | ||
| 857 | /* Sn_MR values used with Sn_MR_MACRAW */ | |
| 858 | /** | |
| 859 | * @brief MAC filter enable in @ref Sn_MR_MACRAW mode | |
| 860 | * @details 0 : disable MAC Filtering\n | |
| 861 | * 1 : enable MAC Filtering\n | |
| 862 | * This bit is applied only during MACRAW mode(P[3:0] = 100.\n | |
| 863 | * When set as W5500 can only receive broadcasting packet or packet sent to itself. | |
| 864 | * When this bit is W5500 can receive all packets on Ethernet. | |
| 865 | * If user wants to implement Hybrid TCP/IP stack, | |
| 866 | * it is recommended that this bit is set as for reducing host overhead to process the all received packets. | |
| 867 | */ | |
| 868 | #define Sn_MR_MFEN Sn_MR_MULTI | |
| 869 | ||
| 870 | /** | |
| 871 | * @brief Multicast Blocking in @ref Sn_MR_MACRAW mode | |
| 872 | * @details 0 : using IGMP version 2\n | |
| 873 | * 1 : using IGMP version 1\n | |
| 874 | * This bit is applied only during UDP mode(P[3:0] = 010 and MULTI = | |
| 875 | * It configures the version for IGMP messages (Join/Leave/Report). | |
| 876 | */ | |
| 877 | #define Sn_MR_MMB Sn_MR_ND | |
| 878 | ||
| 879 | /** | |
| 880 | * @brief IPv6 packet Blocking in @ref Sn_MR_MACRAW mode | |
| 881 | * @details 0 : disable IPv6 Blocking\n | |
| 882 | * 1 : enable IPv6 Blocking\n | |
| 883 | * This bit is applied only during MACRAW mode (P[3:0] = 100. It blocks to receiving the IPv6 packet. | |
| 884 | */ | |
| 885 | #define Sn_MR_MIP6B Sn_MR_UCASTB | |
| 886 | ||
| 887 | /* Sn_MR value used with Sn_MR_UDP & Sn_MR_MULTI */ | |
| 888 | /** | |
| 889 | * @brief IGMP version used in UDP mulitcasting | |
| 890 | * @details 0 : disable Multicast Blocking\n | |
| 891 | * 1 : enable Multicast Blocking\n | |
| 892 | * This bit is applied only when MACRAW mode(P[3:0] = 100. It blocks to receive the packet with multicast MAC address. | |
| 893 | */ | |
| 894 | #define Sn_MR_MC Sn_MR_ND | |
| 895 | ||
| 896 | /* Sn_MR alternate values */ | |
| 897 | /** | |
| 898 | * @brief For Berkeley Socket API | |
| 899 | */ | |
| 900 | #define SOCK_STREAM Sn_MR_TCP | |
| 901 | ||
| 902 | /** | |
| 903 | * @brief For Berkeley Socket API | |
| 904 | */ | |
| 905 | #define SOCK_DGRAM Sn_MR_UDP | |
| 906 | ||
| 907 | ||
| 908 | /* Sn_CR values */ | |
| 909 | /** | |
| 910 | * @brief Initialize or open socket | |
| 911 | * @details Socket n is initialized and opened according to the protocol selected in Sn_MR(P3:P0). | |
| 912 | * The table below shows the value of @ref Sn_SR corresponding to @ref Sn_MR.\n | |
| 913 | * <table> | |
| 914 | * <tr> <td>\b Sn_MR (P[3:0])</td> <td>\b Sn_SR</td> </tr> | |
| 915 | * <tr> <td>Sn_MR_CLOSE (000</td> <td></td> </tr> | |
| 916 | * <tr> <td>Sn_MR_TCP (001</td> <td>SOCK_INIT (0x13)</td> </tr> | |
| 917 | * <tr> <td>Sn_MR_UDP (010</td> <td>SOCK_UDP (0x22)</td> </tr> | |
| 918 | * <tr> <td>S0_MR_MACRAW (100</td> <td>SOCK_MACRAW (0x02)</td> </tr> | |
| 919 | * </table> | |
| 920 | */ | |
| 921 | #define Sn_CR_OPEN 0x01 | |
| 922 | ||
| 923 | /** | |
| 924 | * @brief Wait connection request in TCP mode(Server mode) | |
| 925 | * @details This is valid only in TCP mode (Sn_MR(P3:P0) = Sn_MR_TCP). | |
| 926 | * In this mode, Socket n operates as a �TCP serverand waits for connection-request (SYN packet) from any �TCP client | |
| 927 | * The @ref Sn_SR changes the state from SOCK_INIT to SOCKET_LISTEN. | |
| 928 | * When a �TCP clientconnection request is successfully established, | |
| 929 | * the @ref Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the Sn_IR(0) becomes | |
| 930 | * But when a �TCP clientconnection request is failed, Sn_IR(3) becomes and the status of @ref Sn_SR changes to SOCK_CLOSED. | |
| 931 | */ | |
| 932 | #define Sn_CR_LISTEN 0x02 | |
| 933 | ||
| 934 | /** | |
| 935 | * @brief Send connection request in TCP mode(Client mode) | |
| 936 | * @details To connect, a connect-request (SYN packet) is sent to b>TCP server</b>configured by @ref Sn_DIPR & Sn_DPORT(destination address & port). | |
| 937 | * If the connect-request is successful, the @ref Sn_SR is changed to @ref SOCK_ESTABLISHED and the Sn_IR(0) becomes \n\n | |
| 938 | * The connect-request fails in the following three cases.\n | |
| 939 | * 1. When a @b ARPTO occurs (@ref Sn_IR[3] = ) because destination hardware address is not acquired through the ARP-process.\n | |
| 940 | * 2. When a @b SYN/ACK packet is not received and @b TCPTO (Sn_IR(3) = )\n | |
| 941 | * 3. When a @b RST packet is received instead of a @b SYN/ACK packet. In these cases, @ref Sn_SR is changed to @ref SOCK_CLOSED. | |
| 942 | * @note This is valid only in TCP mode and operates when Socket n acts as b>TCP client</b> | |
| 943 | */ | |
| 944 | #define Sn_CR_CONNECT 0x04 | |
| 945 | ||
| 946 | /** | |
| 947 | * @brief Send closing request in TCP mode | |
| 948 | * @details Regardless of b>TCP server</b>or b>TCP client</b> the DISCON command processes the disconnect-process (b>Active close</b>or b>Passive close</b>.\n | |
| 949 | * @par Active close | |
| 950 | * it transmits disconnect-request(FIN packet) to the connected peer\n | |
| 951 | * @par Passive close | |
| 952 | * When FIN packet is received from peer, a FIN packet is replied back to the peer.\n | |
| 953 | * @details When the disconnect-process is successful (that is, FIN/ACK packet is received successfully), @ref Sn_SR is changed to @ref SOCK_CLOSED.\n | |
| 954 | * Otherwise, TCPTO occurs (Sn_IR(3)=)= and then @ref Sn_SR is changed to @ref SOCK_CLOSED. | |
| 955 | * @note Valid only in TCP mode. | |
| 956 | */ | |
| 957 | #define Sn_CR_DISCON 0x08 | |
| 958 | ||
| 959 | /** | |
| 960 | * @brief Close socket | |
| 961 | * @details Sn_SR is changed to @ref SOCK_CLOSED. | |
| 962 | */ | |
| 963 | #define Sn_CR_CLOSE 0x10 | |
| 964 | ||
| 965 | /** | |
| 966 | * @brief Update TX buffer pointer and send data | |
| 967 | * @details SEND transmits all the data in the Socket n TX buffer.\n | |
| 968 | * For more details, please refer to Socket n TX Free Size Register (@ref Sn_TX_FSR), Socket n, | |
| 969 | * TX Write Pointer Register(@ref Sn_TX_WR), and Socket n TX Read Pointer Register(@ref Sn_TX_RD). | |
| 970 | */ | |
| 971 | #define Sn_CR_SEND 0x20 | |
| 972 | ||
| 973 | /** | |
| 974 | * @brief Send data with MAC address, so without ARP process | |
| 975 | * @details The basic operation is same as SEND.\n | |
| 976 | * Normally SEND transmits data after destination hardware address is acquired by the automatic ARP-process(Address Resolution Protocol).\n | |
| 977 | * But SEND_MAC transmits data without the automatic ARP-process.\n | |
| 978 | * In this case, the destination hardware address is acquired from @ref Sn_DHAR configured by host, instead of APR-process. | |
| 979 | * @note Valid only in UDP mode. | |
| 980 | */ | |
| 981 | #define Sn_CR_SEND_MAC 0x21 | |
| 982 | ||
| 983 | /** | |
| 984 | * @brief Send keep alive message | |
| 985 | * @details It checks the connection status by sending 1byte keep-alive packet.\n | |
| 986 | * If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur. | |
| 987 | * @note Valid only in TCP mode. | |
| 988 | */ | |
| 989 | #define Sn_CR_SEND_KEEP 0x22 | |
| 990 | ||
| 991 | /** | |
| 992 | * @brief Update RX buffer pointer and receive data | |
| 993 | * @details RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (@ref Sn_RX_RD).\n | |
| 994 | * For more details, refer to Socket n RX Received Size Register (@ref Sn_RX_RSR), Socket n RX Write Pointer Register (@ref Sn_RX_WR), | |
| 995 | * and Socket n RX Read Pointer Register (@ref Sn_RX_RD). | |
| 996 | */ | |
| 997 | #define Sn_CR_RECV 0x40 | |
| 998 | ||
| 999 | /* Sn_IR values */ | |
| 1000 | /** | |
| 1001 | * @brief SEND_OK Interrupt | |
| 1002 | * @details This is issued when SEND command is completed. | |
| 1003 | */ | |
| 1004 | #define Sn_IR_SENDOK 0x10 | |
| 1005 | ||
| 1006 | /** | |
| 1007 | * @brief TIMEOUT Interrupt | |
| 1008 | * @details This is issued when ARPTO or TCPTO occurs. | |
| 1009 | */ | |
| 1010 | #define Sn_IR_TIMEOUT 0x08 | |
| 1011 | ||
| 1012 | /** | |
| 1013 | * @brief RECV Interrupt | |
| 1014 | * @details This is issued whenever data is received from a peer. | |
| 1015 | */ | |
| 1016 | #define Sn_IR_RECV 0x04 | |
| 1017 | ||
| 1018 | /** | |
| 1019 | * @brief DISCON Interrupt | |
| 1020 | * @details This is issued when FIN or FIN/ACK packet is received from a peer. | |
| 1021 | */ | |
| 1022 | #define Sn_IR_DISCON 0x02 | |
| 1023 | ||
| 1024 | /** | |
| 1025 | * @brief CON Interrupt | |
| 1026 | * @details This is issued one time when the connection with peer is successful and then @ref Sn_SR is changed to @ref SOCK_ESTABLISHED. | |
| 1027 | */ | |
| 1028 | #define Sn_IR_CON 0x01 | |
| 1029 | ||
| 1030 | /* Sn_SR values */ | |
| 1031 | /** | |
| 1032 | * @brief Closed | |
| 1033 | * @details This indicates that Socket n is released.\N | |
| 1034 | * When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to @ref SOCK_CLOSED regardless of previous status. | |
| 1035 | */ | |
| 1036 | #define SOCK_CLOSED 0x00 | |
| 1037 | ||
| 1038 | /** | |
| 1039 | * @brief Initiate state | |
| 1040 | * @details This indicates Socket n is opened with TCP mode.\N | |
| 1041 | * It is changed to @ref SOCK_INIT when Sn_MR(P[3:0]) = 001and OPEN command is ordered.\N | |
| 1042 | * After @ref SOCK_INIT, user can use LISTEN /CONNECT command. | |
| 1043 | */ | |
| 1044 | #define SOCK_INIT 0x13 | |
| 1045 | ||
| 1046 | /** | |
| 1047 | * @brief Listen state | |
| 1048 | * @details This indicates Socket n is operating as b>TCP server</b>mode and waiting for connection-request (SYN packet) from a peer (b>TCP client</b>.\n | |
| 1049 | * It will change to @ref SOCK_ESTALBLISHED when the connection-request is successfully accepted.\n | |
| 1050 | * Otherwise it will change to @ref SOCK_CLOSED after TCPTO occurred (Sn_IR(TIMEOUT) = . | |
| 1051 | */ | |
| 1052 | #define SOCK_LISTEN 0x14 | |
| 1053 | ||
| 1054 | /** | |
| 1055 | * @brief Connection state | |
| 1056 | * @details This indicates Socket n sent the connect-request packet (SYN packet) to a peer.\n | |
| 1057 | * It is temporarily shown when @ref Sn_SR is changed from @ref SOCK_INIT to @ref SOCK_ESTABLISHED by CONNECT command.\n | |
| 1058 | * If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to @ref SOCK_ESTABLISHED.\n | |
| 1059 | * Otherwise, it changes to @ref SOCK_CLOSED after TCPTO (@ref Sn_IR[TIMEOUT] = is occurred. | |
| 1060 | */ | |
| 1061 | #define SOCK_SYNSENT 0x15 | |
| 1062 | ||
| 1063 | /** | |
| 1064 | * @brief Connection state | |
| 1065 | * @details It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.\n | |
| 1066 | * If socket n sends the response (SYN/ACK packet) to the peer successfully, it changes to @ref SOCK_ESTABLISHED. \n | |
| 1067 | * If not, it changes to @ref SOCK_CLOSED after timeout occurs (@ref Sn_IR[TIMEOUT] = . | |
| 1068 | */ | |
| 1069 | #define SOCK_SYNRECV 0x16 | |
| 1070 | ||
| 1071 | /** | |
| 1072 | * @brief Success to connect | |
| 1073 | * @details This indicates the status of the connection of Socket n.\n | |
| 1074 | * It changes to @ref SOCK_ESTABLISHED when the b>TCP SERVER</b>processed the SYN packet from the b>TCP CLIENT</b>during @ref SOCK_LISTEN, or | |
| 1075 | * when the CONNECT command is successful.\n | |
| 1076 | * During @ref SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command. | |
| 1077 | */ | |
| 1078 | #define SOCK_ESTABLISHED 0x17 | |
| 1079 | ||
| 1080 | /** | |
| 1081 | * @brief Closing state | |
| 1082 | * @details These indicate Socket n is closing.\n | |
| 1083 | * These are shown in disconnect-process such as active-close and passive-close.\n | |
| 1084 | * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED. | |
| 1085 | */ | |
| 1086 | #define SOCK_FIN_WAIT 0x18 | |
| 1087 | ||
| 1088 | /** | |
| 1089 | * @brief Closing state | |
| 1090 | * @details These indicate Socket n is closing.\n | |
| 1091 | * These are shown in disconnect-process such as active-close and passive-close.\n | |
| 1092 | * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED. | |
| 1093 | */ | |
| 1094 | #define SOCK_CLOSING 0x1A | |
| 1095 | ||
| 1096 | /** | |
| 1097 | * @brief Closing state | |
| 1098 | * @details These indicate Socket n is closing.\n | |
| 1099 | * These are shown in disconnect-process such as active-close and passive-close.\n | |
| 1100 | * When Disconnect-process is successfully completed, or when timeout occurs, these change to @ref SOCK_CLOSED. | |
| 1101 | */ | |
| 1102 | #define SOCK_TIME_WAIT 0x1B | |
| 1103 | ||
| 1104 | /** | |
| 1105 | * @brief Closing state | |
| 1106 | * @details This indicates Socket n received the disconnect-request (FIN packet) from the connected peer.\n | |
| 1107 | * This is half-closing status, and data can be transferred.\n | |
| 1108 | * For full-closing, DISCON command is used. But For just-closing, CLOSE command is used. | |
| 1109 | */ | |
| 1110 | #define SOCK_CLOSE_WAIT 0x1C | |
| 1111 | ||
| 1112 | /** | |
| 1113 | * @brief Closing state | |
| 1114 | * @details This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.\n | |
| 1115 | * It changes to @ref SOCK_CLOSED when Socket n received the response successfully, or when timeout occurs (@ref Sn_IR[TIMEOUT] = . | |
| 1116 | */ | |
| 1117 | #define SOCK_LAST_ACK 0x1D | |
| 1118 | ||
| 1119 | /** | |
| 1120 | * @brief UDP socket | |
| 1121 | * @details This indicates Socket n is opened in UDP mode(Sn_MR(P[3:0]) = 010.\n | |
| 1122 | * It changes to SOCK_UPD when Sn_MR(P[3:0]) = 010 and OPEN command is ordered.\n | |
| 1123 | * Unlike TCP mode, data can be transfered without the connection-process. | |
| 1124 | */ | |
| 1125 | #define SOCK_UDP 0x22 | |
| 1126 | ||
| 1127 | //#define SOCK_IPRAW 0x32 /**< IP raw mode socket */ | |
| 1128 | ||
| 1129 | /** | |
| 1130 | * @brief MAC raw mode socket | |
| 1131 | * @details This indicates Socket 0 is opened in MACRAW mode (S0_MR(P[3:0]) = 100and is valid only in Socket 0.\n | |
| 1132 | * It changes to SOCK_MACRAW when S0_MR(P[3:0] = 100and OPEN command is ordered.\n | |
| 1133 | * Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process. | |
| 1134 | */ | |
| 1135 | #define SOCK_MACRAW 0x42 | |
| 1136 | ||
| 1137 | //#define SOCK_PPPOE 0x5F | |
| 1138 | ||
| 1139 | /* IP PROTOCOL */ | |
| 1140 | #define IPPROTO_IP 0 //< Dummy for IP | |
| 1141 | #define IPPROTO_ICMP 1 //< Control message protocol | |
| 1142 | #define IPPROTO_IGMP 2 //< Internet group management protocol | |
| 1143 | #define IPPROTO_GGP 3 //< Gateway^2 (deprecated) | |
| 1144 | #define IPPROTO_TCP 6 //< TCP | |
| 1145 | #define IPPROTO_PUP 12 //< PUP | |
| 1146 | #define IPPROTO_UDP 17 //< UDP | |
| 1147 | #define IPPROTO_IDP 22 //< XNS idp | |
| 1148 | #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol | |
| 1149 | #define IPPROTO_RAW 255 //< Raw IP packet | |
| 1150 | ||
| 1151 | ||
| 1152 | /** | |
| 1153 | * @brief Enter a critical section | |
| 1154 | * | |
| 1155 | * @details It is provided to protect your shared code which are executed without distribution. \n \n | |
| 1156 | * | |
| 1157 | * In non-OS environment, It can be just implemented by disabling whole interrupt.\n | |
| 1158 | * In OS environment, You can replace it to critical section api supported by OS. | |
| 1159 | * | |
| 1160 | * \sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() | |
| 1161 | * \sa WIZCHIP_CRITICAL_EXIT() | |
| 1162 | */ | |
| 1163 | #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter() | |
| 1164 | ||
| 1165 | /** | |
| 1166 | * @brief Exit a critical section | |
| 1167 | * | |
| 1168 | * @details It is provided to protect your shared code which are executed without distribution. \n\n | |
| 1169 | * | |
| 1170 | * In non-OS environment, It can be just implemented by disabling whole interrupt. \n | |
| 1171 | * In OS environment, You can replace it to critical section api supported by OS. | |
| 1172 | * | |
| 1173 | * @sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() | |
| 1174 | * @sa WIZCHIP_CRITICAL_ENTER() | |
| 1175 | */ | |
| 1176 | #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit() | |
| 1177 | ||
| 1178 | ||
| 1179 | ||
| 1180 | //////////////////////// | |
| 1181 | // Basic I/O Function // | |
| 1182 | //////////////////////// | |
| 1183 | ||
| 1184 | /** | |
| 1185 | * @ingroup Basic_IO_function | |
| 1186 | * @brief It reads 1 byte value from a register. | |
| 1187 | * @param AddrSel Register address | |
| 1188 | * @return The value of register | |
| 1189 | */ | |
| 1190 | uint8_t WIZCHIP_READ (uint32_t AddrSel); | |
| 1191 | ||
| 1192 | /** | |
| 1193 | * @ingroup Basic_IO_function | |
| 1194 | * @brief It writes 1 byte value to a register. | |
| 1195 | * @param AddrSel Register address | |
| 1196 | * @param wb Write data | |
| 1197 | * @return void | |
| 1198 | */ | |
| 1199 | void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb ); | |
| 1200 | ||
| 1201 | /** | |
| 1202 | * @ingroup Basic_IO_function | |
| 1203 | * @brief It reads sequence data from registers. | |
| 1204 | * @param AddrSel Register address | |
| 1205 | * @param pBuf Pointer buffer to read data | |
| 1206 | * @param len Data length | |
| 1207 | */ | |
| 1208 | void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len); | |
| 1209 | ||
| 1210 | /** | |
| 1211 | * @ingroup Basic_IO_function | |
| 1212 | * @brief It writes sequence data to registers. | |
| 1213 | * @param AddrSel Register address | |
| 1214 | * @param pBuf Pointer buffer to write data | |
| 1215 | * @param len Data length | |
| 1216 | */ | |
| 1217 | void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len); | |
| 1218 | ||
| 1219 | ///////////////////////////////// | |
| 1220 | // Common Register I/O function // | |
| 1221 | ///////////////////////////////// | |
| 1222 | /** | |
| 1223 | * @ingroup Common_register_access_function | |
| 1224 | * @brief Set Mode Register | |
| 1225 | * @param (uint8_t)mr The value to be set. | |
| 1226 | * @sa getMR() | |
| 1227 | */ | |
| 1228 | #define setMR(mr) \ | |
| 1229 | WIZCHIP_WRITE(MR,mr) | |
| 1230 | ||
| 1231 | ||
| 1232 | /** | |
| 1233 | * @ingroup Common_register_access_function | |
| 1234 | * @brief Get Mode Register | |
| 1235 | * @return uint8_t. The value of Mode register. | |
| 1236 | * @sa setMR() | |
| 1237 | */ | |
| 1238 | #define getMR() \ | |
| 1239 | WIZCHIP_READ(MR) | |
| 1240 | ||
| 1241 | /** | |
| 1242 | * @ingroup Common_register_access_function | |
| 1243 | * @brief Set gateway IP address | |
| 1244 | * @param (uint8_t*)gar Pointer variable to set gateway IP address. It should be allocated 4 bytes. | |
| 1245 | * @sa getGAR() | |
| 1246 | */ | |
| 1247 | #define setGAR(gar) \ | |
| 1248 | WIZCHIP_WRITE_BUF(GAR,gar,4) | |
| 1249 | ||
| 1250 | /** | |
| 1251 | * @ingroup Common_register_access_function | |
| 1252 | * @brief Get gateway IP address | |
| 1253 | * @param (uint8_t*)gar Pointer variable to get gateway IP address. It should be allocated 4 bytes. | |
| 1254 | * @sa setGAR() | |
| 1255 | */ | |
| 1256 | #define getGAR(gar) \ | |
| 1257 | WIZCHIP_READ_BUF(GAR,gar,4) | |
| 1258 | ||
| 1259 | /** | |
| 1260 | * @ingroup Common_register_access_function | |
| 1261 | * @brief Set subnet mask address | |
| 1262 | * @param (uint8_t*)subr Pointer variable to set subnet mask address. It should be allocated 4 bytes. | |
| 1263 | * @sa getSUBR() | |
| 1264 | */ | |
| 1265 | #define setSUBR(subr) \ | |
| 1266 | WIZCHIP_WRITE_BUF(SUBR, subr,4) | |
| 1267 | ||
| 1268 | ||
| 1269 | /** | |
| 1270 | * @ingroup Common_register_access_function | |
| 1271 | * @brief Get subnet mask address | |
| 1272 | * @param (uint8_t*)subr Pointer variable to get subnet mask address. It should be allocated 4 bytes. | |
| 1273 | * @sa setSUBR() | |
| 1274 | */ | |
| 1275 | #define getSUBR(subr) \ | |
| 1276 | WIZCHIP_READ_BUF(SUBR, subr, 4) | |
| 1277 | ||
| 1278 | /** | |
| 1279 | * @ingroup Common_register_access_function | |
| 1280 | * @brief Set local MAC address | |
| 1281 | * @param (uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes. | |
| 1282 | * @sa getSHAR() | |
| 1283 | */ | |
| 1284 | #define setSHAR(shar) \ | |
| 1285 | WIZCHIP_WRITE_BUF(SHAR, shar, 6) | |
| 1286 | ||
| 1287 | /** | |
| 1288 | * @ingroup Common_register_access_function | |
| 1289 | * @brief Get local MAC address | |
| 1290 | * @param (uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes. | |
| 1291 | * @sa setSHAR() | |
| 1292 | */ | |
| 1293 | #define getSHAR(shar) \ | |
| 1294 | WIZCHIP_READ_BUF(SHAR, shar, 6) | |
| 1295 | ||
| 1296 | /** | |
| 1297 | * @ingroup Common_register_access_function | |
| 1298 | * @brief Set local IP address | |
| 1299 | * @param (uint8_t*)sipr Pointer variable to set local IP address. It should be allocated 4 bytes. | |
| 1300 | * @sa getSIPR() | |
| 1301 | */ | |
| 1302 | #define setSIPR(sipr) \ | |
| 1303 | WIZCHIP_WRITE_BUF(SIPR, sipr, 4) | |
| 1304 | ||
| 1305 | /** | |
| 1306 | * @ingroup Common_register_access_function | |
| 1307 | * @brief Get local IP address | |
| 1308 | * @param (uint8_t*)sipr Pointer variable to get local IP address. It should be allocated 4 bytes. | |
| 1309 | * @sa setSIPR() | |
| 1310 | */ | |
| 1311 | #define getSIPR(sipr) \ | |
| 1312 | WIZCHIP_READ_BUF(SIPR, sipr, 4) | |
| 1313 | ||
| 1314 | /** | |
| 1315 | * @ingroup Common_register_access_function | |
| 1316 | * @brief Set INTLEVEL register | |
| 1317 | * @param (uint16_t)intlevel Value to set @ref INTLEVEL register. | |
| 1318 | * @sa getINTLEVEL() | |
| 1319 | */ | |
| 1320 | #define setINTLEVEL(intlevel) {\ | |
| 1321 | WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \ | |
| 1322 | WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \ | |
| 1323 | } | |
| 1324 | ||
| 1325 | ||
| 1326 | /** | |
| 1327 | * @ingroup Common_register_access_function | |
| 1328 | * @brief Get INTLEVEL register | |
| 1329 | * @return uint16_t. Value of @ref INTLEVEL register. | |
| 1330 | * @sa setINTLEVEL() | |
| 1331 | */ | |
| 1332 | #define getINTLEVEL() \ | |
| 1333 | ((WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1))) | |
| 1334 | ||
| 1335 | /** | |
| 1336 | * @ingroup Common_register_access_function | |
| 1337 | * @brief Set @ref IR register | |
| 1338 | * @param (uint8_t)ir Value to set @ref IR register. | |
| 1339 | * @sa getIR() | |
| 1340 | */ | |
| 1341 | #define setIR(ir) \ | |
| 1342 | WIZCHIP_WRITE(IR, (ir & 0xF0)) | |
| 1343 | ||
| 1344 | /** | |
| 1345 | * @ingroup Common_register_access_function | |
| 1346 | * @brief Get @ref IR register | |
| 1347 | * @return uint8_t. Value of @ref IR register. | |
| 1348 | * @sa setIR() | |
| 1349 | */ | |
| 1350 | #define getIR() \ | |
| 1351 | (WIZCHIP_READ(IR) & 0xF0) | |
| 1352 | /** | |
| 1353 | * @ingroup Common_register_access_function | |
| 1354 | * @brief Set @ref IMR register | |
| 1355 | * @param (uint8_t)imr Value to set @ref IMR register. | |
| 1356 | * @sa getIMR() | |
| 1357 | */ | |
| 1358 | #define setIMR(imr) \ | |
| 1359 | WIZCHIP_WRITE(IMR, imr) | |
| 1360 | ||
| 1361 | /** | |
| 1362 | * @ingroup Common_register_access_function | |
| 1363 | * @brief Get @ref IMR register | |
| 1364 | * @return uint8_t. Value of @ref IMR register. | |
| 1365 | * @sa setIMR() | |
| 1366 | */ | |
| 1367 | #define getIMR() \ | |
| 1368 | WIZCHIP_READ(IMR) | |
| 1369 | ||
| 1370 | ||
| 1371 | /** | |
| 1372 | * @ingroup Common_register_access_function | |
| 1373 | * @brief Set @ref SIR register | |
| 1374 | * @param (uint8_t)sir Value to set @ref SIR register. | |
| 1375 | * @sa getSIR() | |
| 1376 | */ | |
| 1377 | #define setSIR(sir) \ | |
| 1378 | WIZCHIP_WRITE(SIR, sir) | |
| 1379 | ||
| 1380 | /** | |
| 1381 | * @ingroup Common_register_access_function | |
| 1382 | * @brief Get @ref SIR register | |
| 1383 | * @return uint8_t. Value of @ref SIR register. | |
| 1384 | * @sa setSIR() | |
| 1385 | */ | |
| 1386 | #define getSIR() \ | |
| 1387 | WIZCHIP_READ(SIR) | |
| 1388 | /** | |
| 1389 | * @ingroup Common_register_access_function | |
| 1390 | * @brief Set @ref SIMR register | |
| 1391 | * @param (uint8_t)simr Value to set @ref SIMR register. | |
| 1392 | * @sa getSIMR() | |
| 1393 | */ | |
| 1394 | #define setSIMR(simr) \ | |
| 1395 | WIZCHIP_WRITE(SIMR, simr) | |
| 1396 | ||
| 1397 | /** | |
| 1398 | * @ingroup Common_register_access_function | |
| 1399 | * @brief Get @ref SIMR register | |
| 1400 | * @return uint8_t. Value of @ref SIMR register. | |
| 1401 | * @sa setSIMR() | |
| 1402 | */ | |
| 1403 | #define getSIMR() \ | |
| 1404 | WIZCHIP_READ(SIMR) | |
| 1405 | ||
| 1406 | /** | |
| 1407 | * @ingroup Common_register_access_function | |
| 1408 | * @brief Set @ref RTR register | |
| 1409 | * @param (uint16_t)rtr Value to set @ref RTR register. | |
| 1410 | * @sa getRTR() | |
| 1411 | */ | |
| 1412 | #define setRTR(rtr) {\ | |
| 1413 | WIZCHIP_WRITE(RTR, (uint8_t)(rtr >> 8)); \ | |
| 1414 | WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(RTR,1), (uint8_t) rtr); \ | |
| 1415 | } | |
| 1416 | ||
| 1417 | /** | |
| 1418 | * @ingroup Common_register_access_function | |
| 1419 | * @brief Get @ref RTR register | |
| 1420 | * @return uint16_t. Value of @ref RTR register. | |
| 1421 | * @sa setRTR() | |
| 1422 | */ | |
| 1423 | #define getRTR() \ | |
| 1424 | ((WIZCHIP_READ(RTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(RTR,1))) | |
| 1425 | ||
| 1426 | /** | |
| 1427 | * @ingroup Common_register_access_function | |
| 1428 | * @brief Set @ref RCR register | |
| 1429 | * @param (uint8_t)rcr Value to set @ref RCR register. | |
| 1430 | * @sa getRCR() | |
| 1431 | */ | |
| 1432 | #define setRCR(rcr) \ | |
| 1433 | WIZCHIP_WRITE(RCR, rcr) | |
| 1434 | ||
| 1435 | /** | |
| 1436 | * @ingroup Common_register_access_function | |
| 1437 | * @brief Get @ref RCR register | |
| 1438 | * @return uint8_t. Value of @ref RCR register. | |
| 1439 | * @sa setRCR() | |
| 1440 | */ | |
| 1441 | #define getRCR() \ | |
| 1442 | WIZCHIP_READ(RCR) | |
| 1443 | ||
| 1444 | //================================================== test done =========================================================== | |
| 1445 | ||
| 1446 | /** | |
| 1447 | * @ingroup Common_register_access_function | |
| 1448 | * @brief Set @ref PTIMER register | |
| 1449 | * @param (uint8_t)ptimer Value to set @ref PTIMER register. | |
| 1450 | * @sa getPTIMER() | |
| 1451 | */ | |
| 1452 | #define setPTIMER(ptimer) \ | |
| 1453 | WIZCHIP_WRITE(PTIMER, ptimer) | |
| 1454 | ||
| 1455 | /** | |
| 1456 | * @ingroup Common_register_access_function | |
| 1457 | * @brief Get @ref PTIMER register | |
| 1458 | * @return uint8_t. Value of @ref PTIMER register. | |
| 1459 | * @sa setPTIMER() | |
| 1460 | */ | |
| 1461 | #define getPTIMER() \ | |
| 1462 | WIZCHIP_READ(PTIMER) | |
| 1463 | ||
| 1464 | /** | |
| 1465 | * @ingroup Common_register_access_function | |
| 1466 | * @brief Set @ref PMAGIC register | |
| 1467 | * @param (uint8_t)pmagic Value to set @ref PMAGIC register. | |
| 1468 | * @sa getPMAGIC() | |
| 1469 | */ | |
| 1470 | #define setPMAGIC(pmagic) \ | |
| 1471 | WIZCHIP_WRITE(PMAGIC, pmagic) | |
| 1472 | ||
| 1473 | /** | |
| 1474 | * @ingroup Common_register_access_function | |
| 1475 | * @brief Get @ref PMAGIC register | |
| 1476 | * @return uint8_t. Value of @ref PMAGIC register. | |
| 1477 | * @sa setPMAGIC() | |
| 1478 | */ | |
| 1479 | #define getPMAGIC() \ | |
| 1480 | WIZCHIP_READ(PMAGIC) | |
| 1481 | ||
| 1482 | /** | |
| 1483 | * @ingroup Common_register_access_function | |
| 1484 | * @brief Set PHAR address | |
| 1485 | * @param (uint8_t*)phar Pointer variable to set PPP destination MAC register address. It should be allocated 6 bytes. | |
| 1486 | * @sa getPHAR() | |
| 1487 | */ | |
| 1488 | #define setPHAR(phar) \ | |
| 1489 | WIZCHIP_WRITE_BUF(PHAR, phar, 6) | |
| 1490 | ||
| 1491 | /** | |
| 1492 | * @ingroup Common_register_access_function | |
| 1493 | * @brief Get local IP address | |
| 1494 | * @param (uint8_t*)phar Pointer variable to PPP destination MAC register address. It should be allocated 6 bytes. | |
| 1495 | * @sa setPHAR() | |
| 1496 | */ | |
| 1497 | #define getPHAR(phar) \ | |
| 1498 | WIZCHIP_READ_BUF(PHAR, phar, 6) | |
| 1499 | ||
| 1500 | /** | |
| 1501 | * @ingroup Common_register_access_function | |
| 1502 | * @brief Set @ref PSID register | |
| 1503 | * @param (uint16_t)psid Value to set @ref PSID register. | |
| 1504 | * @sa getPSID() | |
| 1505 | */ | |
| 1506 | #define setPSID(psid) {\ | |
| 1507 | WIZCHIP_WRITE(PSID, (uint8_t)(psid >> 8)); \ | |
| 1508 | WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); \ | |
| 1509 | } | |
| 1510 | ||
| 1511 | /** | |
| 1512 | * @ingroup Common_register_access_function | |
| 1513 | * @brief Get @ref PSID register | |
| 1514 | * @return uint16_t. Value of @ref PSID register. | |
| 1515 | * @sa setPSID() | |
| 1516 | */ | |
| 1517 | //uint16_t getPSID(void); | |
| 1518 | #define getPSID() \ | |
| 1519 | ((WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1))) | |
| 1520 | ||
| 1521 | /** | |
| 1522 | * @ingroup Common_register_access_function | |
| 1523 | * @brief Set @ref PMRU register | |
| 1524 | * @param (uint16_t)pmru Value to set @ref PMRU register. | |
| 1525 | * @sa getPMRU() | |
| 1526 | */ | |
| 1527 | #define setPMRU(pmru) { \ | |
| 1528 | WIZCHIP_WRITE(PMRU, (uint8_t)(pmru>>8)); \ | |
| 1529 | WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); \ | |
| 1530 | } | |
| 1531 | ||
| 1532 | /** | |
| 1533 | * @ingroup Common_register_access_function | |
| 1534 | * @brief Get @ref PMRU register | |
| 1535 | * @return uint16_t. Value of @ref PMRU register. | |
| 1536 | * @sa setPMRU() | |
| 1537 | */ | |
| 1538 | #define getPMRU() \ | |
| 1539 | ((WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1))) | |
| 1540 | ||
| 1541 | /** | |
| 1542 | * @ingroup Common_register_access_function | |
| 1543 | * @brief Get unreachable IP address | |
| 1544 | * @param (uint8_t*)uipr Pointer variable to get unreachable IP address. It should be allocated 4 bytes. | |
| 1545 | */ | |
| 1546 | #define getUIPR(uipr) \ | |
| 1547 | WIZCHIP_READ_BUF(UIPR,uipr,6) | |
| 1548 | ||
| 1549 | /** | |
| 1550 | * @ingroup Common_register_access_function | |
| 1551 | * @brief Get @ref UPORTR register | |
| 1552 | * @return uint16_t. Value of @ref UPORTR register. | |
| 1553 | */ | |
| 1554 | #define getUPORTR() \ | |
| 1555 | ((WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1))) | |
| 1556 | ||
| 1557 | /** | |
| 1558 | * @ingroup Common_register_access_function | |
| 1559 | * @brief Set @ref PHYCFGR register | |
| 1560 | * @param (uint8_t)phycfgr Value to set @ref PHYCFGR register. | |
| 1561 | * @sa getPHYCFGR() | |
| 1562 | */ | |
| 1563 | #define setPHYCFGR(phycfgr) \ | |
| 1564 | WIZCHIP_WRITE(PHYCFGR, phycfgr) | |
| 1565 | ||
| 1566 | /** | |
| 1567 | * @ingroup Common_register_access_function | |
| 1568 | * @brief Get @ref PHYCFGR register | |
| 1569 | * @return uint8_t. Value of @ref PHYCFGR register. | |
| 1570 | * @sa setPHYCFGR() | |
| 1571 | */ | |
| 1572 | #define getPHYCFGR() \ | |
| 1573 | WIZCHIP_READ(PHYCFGR) | |
| 1574 | ||
| 1575 | /** | |
| 1576 | * @ingroup Common_register_access_function | |
| 1577 | * @brief Get @ref VERSIONR register | |
| 1578 | * @return uint8_t. Value of @ref VERSIONR register. | |
| 1579 | */ | |
| 1580 | #define getVERSIONR() \ | |
| 1581 | WIZCHIP_READ(VERSIONR) | |
| 1582 | ||
| 1583 | ///////////////////////////////////// | |
| 1584 | ||
| 1585 | /////////////////////////////////// | |
| 1586 | // Socket N register I/O function // | |
| 1587 | /////////////////////////////////// | |
| 1588 | /** | |
| 1589 | * @ingroup Socket_register_access_function | |
| 1590 | * @brief Set @ref Sn_MR register | |
| 1591 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1592 | * @param (uint8_t)mr Value to set @ref Sn_MR | |
| 1593 | * @sa getSn_MR() | |
| 1594 | */ | |
| 1595 | #define setSn_MR(sn, mr) \ | |
| 1596 | WIZCHIP_WRITE(Sn_MR(sn),mr) | |
| 1597 | ||
| 1598 | /** | |
| 1599 | * @ingroup Socket_register_access_function | |
| 1600 | * @brief Get @ref Sn_MR register | |
| 1601 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1602 | * @return uint8_t. Value of @ref Sn_MR. | |
| 1603 | * @sa setSn_MR() | |
| 1604 | */ | |
| 1605 | #define getSn_MR(sn) \ | |
| 1606 | WIZCHIP_READ(Sn_MR(sn)) | |
| 1607 | ||
| 1608 | /** | |
| 1609 | * @ingroup Socket_register_access_function | |
| 1610 | * @brief Set @ref Sn_CR register | |
| 1611 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1612 | * @param (uint8_t)cr Value to set @ref Sn_CR | |
| 1613 | * @sa getSn_CR() | |
| 1614 | */ | |
| 1615 | #define setSn_CR(sn, cr) \ | |
| 1616 | WIZCHIP_WRITE(Sn_CR(sn), cr) | |
| 1617 | ||
| 1618 | /** | |
| 1619 | * @ingroup Socket_register_access_function | |
| 1620 | * @brief Get @ref Sn_CR register | |
| 1621 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1622 | * @return uint8_t. Value of @ref Sn_CR. | |
| 1623 | * @sa setSn_CR() | |
| 1624 | */ | |
| 1625 | #define getSn_CR(sn) \ | |
| 1626 | WIZCHIP_READ(Sn_CR(sn)) | |
| 1627 | ||
| 1628 | /** | |
| 1629 | * @ingroup Socket_register_access_function | |
| 1630 | * @brief Set @ref Sn_IR register | |
| 1631 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1632 | * @param (uint8_t)ir Value to set @ref Sn_IR | |
| 1633 | * @sa getSn_IR() | |
| 1634 | */ | |
| 1635 | #define setSn_IR(sn, ir) \ | |
| 1636 | WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F)) | |
| 1637 | ||
| 1638 | /** | |
| 1639 | * @ingroup Socket_register_access_function | |
| 1640 | * @brief Get @ref Sn_IR register | |
| 1641 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1642 | * @return uint8_t. Value of @ref Sn_IR. | |
| 1643 | * @sa setSn_IR() | |
| 1644 | */ | |
| 1645 | #define getSn_IR(sn) \ | |
| 1646 | (WIZCHIP_READ(Sn_IR(sn)) & 0x1F) | |
| 1647 | ||
| 1648 | /** | |
| 1649 | * @ingroup Socket_register_access_function | |
| 1650 | * @brief Set @ref Sn_IMR register | |
| 1651 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1652 | * @param (uint8_t)imr Value to set @ref Sn_IMR | |
| 1653 | * @sa getSn_IMR() | |
| 1654 | */ | |
| 1655 | #define setSn_IMR(sn, imr) \ | |
| 1656 | WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F)) | |
| 1657 | ||
| 1658 | /** | |
| 1659 | * @ingroup Socket_register_access_function | |
| 1660 | * @brief Get @ref Sn_IMR register | |
| 1661 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1662 | * @return uint8_t. Value of @ref Sn_IMR. | |
| 1663 | * @sa setSn_IMR() | |
| 1664 | */ | |
| 1665 | #define getSn_IMR(sn) \ | |
| 1666 | (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F) | |
| 1667 | ||
| 1668 | /** | |
| 1669 | * @ingroup Socket_register_access_function | |
| 1670 | * @brief Get @ref Sn_SR register | |
| 1671 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1672 | * @return uint8_t. Value of @ref Sn_SR. | |
| 1673 | */ | |
| 1674 | #define getSn_SR(sn) \ | |
| 1675 | WIZCHIP_READ(Sn_SR(sn)) | |
| 1676 | ||
| 1677 | /** | |
| 1678 | * @ingroup Socket_register_access_function | |
| 1679 | * @brief Set @ref Sn_PORT register | |
| 1680 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1681 | * @param (uint16_t)port Value to set @ref Sn_PORT. | |
| 1682 | * @sa getSn_PORT() | |
| 1683 | */ | |
| 1684 | #define setSn_PORT(sn, port) { \ | |
| 1685 | WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \ | |
| 1686 | WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \ | |
| 1687 | } | |
| 1688 | ||
| 1689 | /** | |
| 1690 | * @ingroup Socket_register_access_function | |
| 1691 | * @brief Get @ref Sn_PORT register | |
| 1692 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1693 | * @return uint16_t. Value of @ref Sn_PORT. | |
| 1694 | * @sa setSn_PORT() | |
| 1695 | */ | |
| 1696 | #define getSn_PORT(sn) \ | |
| 1697 | ((WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1))) | |
| 1698 | ||
| 1699 | /** | |
| 1700 | * @ingroup Socket_register_access_function | |
| 1701 | * @brief Set @ref Sn_DHAR register | |
| 1702 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1703 | * @param (uint8_t*)dhar Pointer variable to set socket n destination hardware address. It should be allocated 6 bytes. | |
| 1704 | * @sa getSn_DHAR() | |
| 1705 | */ | |
| 1706 | #define setSn_DHAR(sn, dhar) \ | |
| 1707 | WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6) | |
| 1708 | ||
| 1709 | /** | |
| 1710 | * @ingroup Socket_register_access_function | |
| 1711 | * @brief Get @ref Sn_MR register | |
| 1712 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1713 | * @param (uint8_t*)dhar Pointer variable to get socket n destination hardware address. It should be allocated 6 bytes. | |
| 1714 | * @sa setSn_DHAR() | |
| 1715 | */ | |
| 1716 | #define getSn_DHAR(sn, dhar) \ | |
| 1717 | WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6) | |
| 1718 | ||
| 1719 | /** | |
| 1720 | * @ingroup Socket_register_access_function | |
| 1721 | * @brief Set @ref Sn_DIPR register | |
| 1722 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1723 | * @param (uint8_t*)dipr Pointer variable to set socket n destination IP address. It should be allocated 4 bytes. | |
| 1724 | * @sa getSn_DIPR() | |
| 1725 | */ | |
| 1726 | #define setSn_DIPR(sn, dipr) \ | |
| 1727 | WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4) | |
| 1728 | ||
| 1729 | /** | |
| 1730 | * @ingroup Socket_register_access_function | |
| 1731 | * @brief Get @ref Sn_DIPR register | |
| 1732 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1733 | * @param (uint8_t*)dipr Pointer variable to get socket n destination IP address. It should be allocated 4 bytes. | |
| 1734 | * @sa SetSn_DIPR() | |
| 1735 | */ | |
| 1736 | #define getSn_DIPR(sn, dipr) \ | |
| 1737 | WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4) | |
| 1738 | ||
| 1739 | /** | |
| 1740 | * @ingroup Socket_register_access_function | |
| 1741 | * @brief Set @ref Sn_DPORT register | |
| 1742 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1743 | * @param (uint16_t)dport Value to set @ref Sn_DPORT | |
| 1744 | * @sa getSn_DPORT() | |
| 1745 | */ | |
| 1746 | #define setSn_DPORT(sn, dport) { \ | |
| 1747 | WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \ | |
| 1748 | WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \ | |
| 1749 | } | |
| 1750 | ||
| 1751 | /** | |
| 1752 | * @ingroup Socket_register_access_function | |
| 1753 | * @brief Get @ref Sn_DPORT register | |
| 1754 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1755 | * @return uint16_t. Value of @ref Sn_DPORT. | |
| 1756 | * @sa setSn_DPORT() | |
| 1757 | */ | |
| 1758 | #define getSn_DPORT(sn) \ | |
| 1759 | ((WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1))) | |
| 1760 | ||
| 1761 | /** | |
| 1762 | * @ingroup Socket_register_access_function | |
| 1763 | * @brief Set @ref Sn_MSSR register | |
| 1764 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1765 | * @param (uint16_t)mss Value to set @ref Sn_MSSR | |
| 1766 | * @sa setSn_MSSR() | |
| 1767 | */ | |
| 1768 | #define setSn_MSSR(sn, mss) { \ | |
| 1769 | WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \ | |
| 1770 | WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \ | |
| 1771 | } | |
| 1772 | ||
| 1773 | /** | |
| 1774 | * @ingroup Socket_register_access_function | |
| 1775 | * @brief Get @ref Sn_MSSR register | |
| 1776 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1777 | * @return uint16_t. Value of @ref Sn_MSSR. | |
| 1778 | * @sa setSn_MSSR() | |
| 1779 | */ | |
| 1780 | #define getSn_MSSR(sn) \ | |
| 1781 | ((WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1))) | |
| 1782 | ||
| 1783 | /** | |
| 1784 | * @ingroup Socket_register_access_function | |
| 1785 | * @brief Set @ref Sn_TOS register | |
| 1786 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1787 | * @param (uint8_t)tos Value to set @ref Sn_TOS | |
| 1788 | * @sa getSn_TOS() | |
| 1789 | */ | |
| 1790 | #define setSn_TOS(sn, tos) \ | |
| 1791 | WIZCHIP_WRITE(Sn_TOS(sn), tos) | |
| 1792 | ||
| 1793 | /** | |
| 1794 | * @ingroup Socket_register_access_function | |
| 1795 | * @brief Get @ref Sn_TOS register | |
| 1796 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1797 | * @return uint8_t. Value of Sn_TOS. | |
| 1798 | * @sa setSn_TOS() | |
| 1799 | */ | |
| 1800 | #define getSn_TOS(sn) \ | |
| 1801 | WIZCHIP_READ(Sn_TOS(sn)) | |
| 1802 | ||
| 1803 | /** | |
| 1804 | * @ingroup Socket_register_access_function | |
| 1805 | * @brief Set @ref Sn_TTL register | |
| 1806 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1807 | * @param (uint8_t)ttl Value to set @ref Sn_TTL | |
| 1808 | * @sa getSn_TTL() | |
| 1809 | */ | |
| 1810 | #define setSn_TTL(sn, ttl) \ | |
| 1811 | WIZCHIP_WRITE(Sn_TTL(sn), ttl) | |
| 1812 | ||
| 1813 | ||
| 1814 | /** | |
| 1815 | * @ingroup Socket_register_access_function | |
| 1816 | * @brief Get @ref Sn_TTL register | |
| 1817 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1818 | * @return uint8_t. Value of @ref Sn_TTL. | |
| 1819 | * @sa setSn_TTL() | |
| 1820 | */ | |
| 1821 | #define getSn_TTL(sn) \ | |
| 1822 | WIZCHIP_READ(Sn_TTL(sn)) | |
| 1823 | ||
| 1824 | ||
| 1825 | /** | |
| 1826 | * @ingroup Socket_register_access_function | |
| 1827 | * @brief Set @ref Sn_RXBUF_SIZE register | |
| 1828 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1829 | * @param (uint8_t)rxbufsize Value to set @ref Sn_RXBUF_SIZE | |
| 1830 | * @sa getSn_RXBUF_SIZE() | |
| 1831 | */ | |
| 1832 | #define setSn_RXBUF_SIZE(sn, rxbufsize) \ | |
| 1833 | WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize) | |
| 1834 | ||
| 1835 | ||
| 1836 | /** | |
| 1837 | * @ingroup Socket_register_access_function | |
| 1838 | * @brief Get @ref Sn_RXBUF_SIZE register | |
| 1839 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1840 | * @return uint8_t. Value of @ref Sn_RXBUF_SIZE. | |
| 1841 | * @sa setSn_RXBUF_SIZE() | |
| 1842 | */ | |
| 1843 | #define getSn_RXBUF_SIZE(sn) \ | |
| 1844 | WIZCHIP_READ(Sn_RXBUF_SIZE(sn)) | |
| 1845 | ||
| 1846 | /** | |
| 1847 | * @ingroup Socket_register_access_function | |
| 1848 | * @brief Set @ref Sn_TXBUF_SIZE register | |
| 1849 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1850 | * @param (uint8_t)txbufsize Value to set @ref Sn_TXBUF_SIZE | |
| 1851 | * @sa getSn_TXBUF_SIZE() | |
| 1852 | */ | |
| 1853 | #define setSn_TXBUF_SIZE(sn, txbufsize) \ | |
| 1854 | WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize) | |
| 1855 | ||
| 1856 | /** | |
| 1857 | * @ingroup Socket_register_access_function | |
| 1858 | * @brief Get @ref Sn_TXBUF_SIZE register | |
| 1859 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1860 | * @return uint8_t. Value of @ref Sn_TXBUF_SIZE. | |
| 1861 | * @sa setSn_TXBUF_SIZE() | |
| 1862 | */ | |
| 1863 | #define getSn_TXBUF_SIZE(sn) \ | |
| 1864 | WIZCHIP_READ(Sn_TXBUF_SIZE(sn)) | |
| 1865 | ||
| 1866 | /** | |
| 1867 | * @ingroup Socket_register_access_function | |
| 1868 | * @brief Get @ref Sn_TX_FSR register | |
| 1869 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1870 | * @return uint16_t. Value of @ref Sn_TX_FSR. | |
| 1871 | */ | |
| 1872 | uint16_t getSn_TX_FSR(uint8_t sn); | |
| 1873 | ||
| 1874 | /** | |
| 1875 | * @ingroup Socket_register_access_function | |
| 1876 | * @brief Get @ref Sn_TX_RD register | |
| 1877 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1878 | * @return uint16_t. Value of @ref Sn_TX_RD. | |
| 1879 | */ | |
| 1880 | #define getSn_TX_RD(sn) \ | |
| 1881 | ((WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1))) | |
| 1882 | ||
| 1883 | /** | |
| 1884 | * @ingroup Socket_register_access_function | |
| 1885 | * @brief Set @ref Sn_TX_WR register | |
| 1886 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1887 | * @param (uint16_t)txwr Value to set @ref Sn_TX_WR | |
| 1888 | * @sa GetSn_TX_WR() | |
| 1889 | */ | |
| 1890 | #define setSn_TX_WR(sn, txwr) { \ | |
| 1891 | WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \ | |
| 1892 | WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \ | |
| 1893 | } | |
| 1894 | ||
| 1895 | /** | |
| 1896 | * @ingroup Socket_register_access_function | |
| 1897 | * @brief Get @ref Sn_TX_WR register | |
| 1898 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1899 | * @return uint16_t. Value of @ref Sn_TX_WR. | |
| 1900 | * @sa setSn_TX_WR() | |
| 1901 | */ | |
| 1902 | #define getSn_TX_WR(sn) \ | |
| 1903 | ((WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1))) | |
| 1904 | ||
| 1905 | ||
| 1906 | /** | |
| 1907 | * @ingroup Socket_register_access_function | |
| 1908 | * @brief Get @ref Sn_RX_RSR register | |
| 1909 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1910 | * @return uint16_t. Value of @ref Sn_RX_RSR. | |
| 1911 | */ | |
| 1912 | uint16_t getSn_RX_RSR(uint8_t sn); | |
| 1913 | ||
| 1914 | ||
| 1915 | /** | |
| 1916 | * @ingroup Socket_register_access_function | |
| 1917 | * @brief Set @ref Sn_RX_RD register | |
| 1918 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1919 | * @param (uint16_t)rxrd Value to set @ref Sn_RX_RD | |
| 1920 | * @sa getSn_RX_RD() | |
| 1921 | */ | |
| 1922 | #define setSn_RX_RD(sn, rxrd) { \ | |
| 1923 | WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \ | |
| 1924 | WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \ | |
| 1925 | } | |
| 1926 | ||
| 1927 | /** | |
| 1928 | * @ingroup Socket_register_access_function | |
| 1929 | * @brief Get @ref Sn_RX_RD register | |
| 1930 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1931 | * @regurn uint16_t. Value of @ref Sn_RX_RD. | |
| 1932 | * @sa setSn_RX_RD() | |
| 1933 | */ | |
| 1934 | #define getSn_RX_RD(sn) \ | |
| 1935 | ((WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1))) | |
| 1936 | ||
| 1937 | /** | |
| 1938 | * @ingroup Socket_register_access_function | |
| 1939 | * @brief Get @ref Sn_RX_WR register | |
| 1940 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1941 | * @return uint16_t. Value of @ref Sn_RX_WR. | |
| 1942 | */ | |
| 1943 | #define getSn_RX_WR(sn) \ | |
| 1944 | ((WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1))) | |
| 1945 | ||
| 1946 | ||
| 1947 | /** | |
| 1948 | * @ingroup Socket_register_access_function | |
| 1949 | * @brief Set @ref Sn_FRAG register | |
| 1950 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1951 | * @param (uint16_t)frag Value to set @ref Sn_FRAG | |
| 1952 | * @sa getSn_FRAD() | |
| 1953 | */ | |
| 1954 | #define setSn_FRAG(sn, frag) { \ | |
| 1955 | WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \ | |
| 1956 | WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \ | |
| 1957 | } | |
| 1958 | ||
| 1959 | /** | |
| 1960 | * @ingroup Socket_register_access_function | |
| 1961 | * @brief Get @ref Sn_FRAG register | |
| 1962 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1963 | * @return uint16_t. Value of @ref Sn_FRAG. | |
| 1964 | * @sa setSn_FRAG() | |
| 1965 | */ | |
| 1966 | #define getSn_FRAG(sn) \ | |
| 1967 | ((WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1))) | |
| 1968 | ||
| 1969 | /** | |
| 1970 | * @ingroup Socket_register_access_function | |
| 1971 | * @brief Set @ref Sn_KPALVTR register | |
| 1972 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1973 | * @param (uint8_t)kpalvt Value to set @ref Sn_KPALVTR | |
| 1974 | * @sa getSn_KPALVTR() | |
| 1975 | */ | |
| 1976 | #define setSn_KPALVTR(sn, kpalvt) \ | |
| 1977 | WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt) | |
| 1978 | ||
| 1979 | /** | |
| 1980 | * @ingroup Socket_register_access_function | |
| 1981 | * @brief Get @ref Sn_KPALVTR register | |
| 1982 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1983 | * @return uint8_t. Value of @ref Sn_KPALVTR. | |
| 1984 | * @sa setSn_KPALVTR() | |
| 1985 | */ | |
| 1986 | #define getSn_KPALVTR(sn) \ | |
| 1987 | WIZCHIP_READ(Sn_KPALVTR(sn)) | |
| 1988 | ||
| 1989 | ////////////////////////////////////// | |
| 1990 | ||
| 1991 | ///////////////////////////////////// | |
| 1992 | // Sn_TXBUF & Sn_RXBUF IO function // | |
| 1993 | ///////////////////////////////////// | |
| 1994 | /** | |
| 1995 | * @brief Gets the max buffer size of socket sn passed as parameter. | |
| 1996 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 1997 | * @return uint16_t. Value of Socket n RX max buffer size. | |
| 1998 | */ | |
| 1999 | #define getSn_RxMAX(sn) \ | |
| 2000 | (getSn_RXBUF_SIZE(sn) << 10) | |
| 2001 | ||
| 2002 | /** | |
| 2003 | * @brief Gets the max buffer size of socket sn passed as parameters. | |
| 2004 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 2005 | * @return uint16_t. Value of Socket n TX max buffer size. | |
| 2006 | */ | |
| 2007 | //uint16_t getSn_TxMAX(uint8_t sn); | |
| 2008 | #define getSn_TxMAX(sn) \ | |
| 2009 | (getSn_TXBUF_SIZE(sn) << 10) | |
| 2010 | ||
| 2011 | /** | |
| 2012 | * @ingroup Basic_IO_function | |
| 2013 | * @brief It copies data to internal TX memory | |
| 2014 | * | |
| 2015 | * @details This function reads the Tx write pointer register and after that, | |
| 2016 | * it copies the <i>wizdata(pointer buffer)</i> of the length of <i>len(variable)</i> bytes to internal TX memory | |
| 2017 | * and updates the Tx write pointer register. | |
| 2018 | * This function is being called by send() and sendto() function also. | |
| 2019 | * | |
| 2020 | * @note User should read upper byte first and lower byte later to get proper value. | |
| 2021 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 2022 | * @param wizdata Pointer buffer to write data | |
| 2023 | * @param len Data length | |
| 2024 | * @sa wiz_recv_data() | |
| 2025 | */ | |
| 2026 | void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len); | |
| 2027 | ||
| 2028 | /** | |
| 2029 | * @ingroup Basic_IO_function | |
| 2030 | * @brief It copies data to your buffer from internal RX memory | |
| 2031 | * | |
| 2032 | * @details This function read the Rx read pointer register and after that, | |
| 2033 | * it copies the received data from internal RX memory | |
| 2034 | * to <i>wizdata(pointer variable)</i> of the length of <i>len(variable)</i> bytes. | |
| 2035 | * This function is being called by recv() also. | |
| 2036 | * | |
| 2037 | * @note User should read upper byte first and lower byte later to get proper value. | |
| 2038 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 2039 | * @param wizdata Pointer buffer to read data | |
| 2040 | * @param len Data length | |
| 2041 | * @sa wiz_send_data() | |
| 2042 | */ | |
| 2043 | void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len); | |
| 2044 | ||
| 2045 | /** | |
| 2046 | * @ingroup Basic_IO_function | |
| 2047 | * @brief It discard the received data in RX memory. | |
| 2048 | * @details It discards the data of the length of <i>len(variable)</i> bytes in internal RX memory. | |
| 2049 | * @param (uint8_t)sn Socket number. It should be <b>0 ~ 7</b>. | |
| 2050 | * @param len Data length | |
| 2051 | */ | |
| 2052 | void wiz_recv_ignore(uint8_t sn, uint16_t len); | |
| 2053 | ||
| 2054 | #endif // _W5500_H_ | |
