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| 483170 | 1 | ;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** |
| Q | 2 | ;* File Name : startup_stm32f070x6.s |
| 3 | ;* Author : MCD Application Team | |
| 4 | ;* Description : STM32F070x4/STM32F070x6 devices vector table for MDK-ARM toolchain. | |
| 5 | ;* This module performs: | |
| 6 | ;* - Set the initial SP | |
| 7 | ;* - Set the initial PC == Reset_Handler | |
| 8 | ;* - Set the vector table entries with the exceptions ISR address | |
| 9 | ;* - Branches to __main in the C library (which eventually | |
| 10 | ;* calls main()). | |
| 11 | ;* After Reset the CortexM0 processor is in Thread mode, | |
| 12 | ;* priority is Privileged, and the Stack is set to Main. | |
| 13 | ;* <<< Use Configuration Wizard in Context Menu >>> | |
| 14 | ;******************************************************************************* | |
| 15 | ;* | |
| 16 | ;* Redistribution and use in source and binary forms, with or without modification, | |
| 17 | ;* are permitted provided that the following conditions are met: | |
| 18 | ;* 1. Redistributions of source code must retain the above copyright notice, | |
| 19 | ;* this list of conditions and the following disclaimer. | |
| 20 | ;* 2. Redistributions in binary form must reproduce the above copyright notice, | |
| 21 | ;* this list of conditions and the following disclaimer in the documentation | |
| 22 | ;* and/or other materials provided with the distribution. | |
| 23 | ;* 3. Neither the name of STMicroelectronics nor the names of its contributors | |
| 24 | ;* may be used to endorse or promote products derived from this software | |
| 25 | ;* without specific prior written permission. | |
| 26 | ;* | |
| 27 | ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
| 28 | ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 29 | ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
| 30 | ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
| 31 | ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 32 | ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
| 33 | ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
| 34 | ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
| 35 | ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 36 | ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 37 | ; | |
| 38 | ;******************************************************************************* | |
| 39 | ||
| 40 | ; Amount of memory (in bytes) allocated for Stack | |
| 41 | ; Tailor this value to your application needs | |
| 42 | ; <h> Stack Configuration | |
| 43 | ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> | |
| 44 | ; </h> | |
| 45 | ||
| 46 | Stack_Size EQU 0x00000400 | |
| 47 | ||
| 48 | AREA STACK, NOINIT, READWRITE, ALIGN=3 | |
| 49 | Stack_Mem SPACE Stack_Size | |
| 50 | __initial_sp | |
| 51 | ||
| 52 | ||
| 53 | ; <h> Heap Configuration | |
| 54 | ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> | |
| 55 | ; </h> | |
| 56 | ||
| 57 | Heap_Size EQU 0x00000200 | |
| 58 | ||
| 59 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 | |
| 60 | __heap_base | |
| 61 | Heap_Mem SPACE Heap_Size | |
| 62 | __heap_limit | |
| 63 | ||
| 64 | PRESERVE8 | |
| 65 | THUMB | |
| 66 | ||
| 67 | ||
| 68 | ; Vector Table Mapped to Address 0 at Reset | |
| 69 | AREA RESET, DATA, READONLY | |
| 70 | EXPORT __Vectors | |
| 71 | EXPORT __Vectors_End | |
| 72 | EXPORT __Vectors_Size | |
| 73 | ||
| 74 | __Vectors DCD __initial_sp ; Top of Stack | |
| 75 | DCD Reset_Handler ; Reset Handler | |
| 76 | DCD NMI_Handler ; NMI Handler | |
| 77 | DCD HardFault_Handler ; Hard Fault Handler | |
| 78 | DCD 0 ; Reserved | |
| 79 | DCD 0 ; Reserved | |
| 80 | DCD 0 ; Reserved | |
| 81 | DCD 0 ; Reserved | |
| 82 | DCD 0 ; Reserved | |
| 83 | DCD 0 ; Reserved | |
| 84 | DCD 0 ; Reserved | |
| 85 | DCD SVC_Handler ; SVCall Handler | |
| 86 | DCD 0 ; Reserved | |
| 87 | DCD 0 ; Reserved | |
| 88 | DCD PendSV_Handler ; PendSV Handler | |
| 89 | DCD SysTick_Handler ; SysTick Handler | |
| 90 | ||
| 91 | ; External Interrupts | |
| 92 | DCD WWDG_IRQHandler ; Window Watchdog | |
| 93 | DCD 0 ; Reserved | |
| 94 | DCD RTC_IRQHandler ; RTC through EXTI Line | |
| 95 | DCD FLASH_IRQHandler ; FLASH | |
| 96 | DCD RCC_IRQHandler ; RCC | |
| 97 | DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 | |
| 98 | DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 | |
| 99 | DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 | |
| 100 | DCD 0 ; Reserved | |
| 101 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 | |
| 102 | DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 | |
| 103 | DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 | |
| 104 | DCD ADC1_IRQHandler ; ADC1 | |
| 105 | DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation | |
| 106 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare | |
| 107 | DCD 0 ; Reserved | |
| 108 | DCD TIM3_IRQHandler ; TIM3 | |
| 109 | DCD 0 ; Reserved | |
| 110 | DCD 0 ; Reserved | |
| 111 | DCD TIM14_IRQHandler ; TIM14 | |
| 112 | DCD 0 ; Reserved | |
| 113 | DCD TIM16_IRQHandler ; TIM16 | |
| 114 | DCD TIM17_IRQHandler ; TIM17 | |
| 115 | DCD I2C1_IRQHandler ; I2C1 | |
| 116 | DCD 0 ; Reserved | |
| 117 | DCD SPI1_IRQHandler ; SPI1 | |
| 118 | DCD 0 ; Reserved | |
| 119 | DCD USART1_IRQHandler ; USART1 | |
| 120 | DCD USART2_IRQHandler ; USART2 | |
| 121 | DCD 0 ; Reserved | |
| 122 | DCD 0 ; Reserved | |
| 123 | DCD USB_IRQHandler ; USB | |
| 124 | ||
| 125 | __Vectors_End | |
| 126 | ||
| 127 | __Vectors_Size EQU __Vectors_End - __Vectors | |
| 128 | ||
| 129 | AREA |.text|, CODE, READONLY | |
| 130 | ||
| 131 | ; Reset handler routine | |
| 132 | Reset_Handler PROC | |
| 133 | EXPORT Reset_Handler [WEAK] | |
| 134 | IMPORT __main | |
| 135 | IMPORT SystemInit | |
| 136 | ||
| 137 | ||
| 138 | ||
| 139 | LDR R0, =__initial_sp ; set stack pointer | |
| 140 | MSR MSP, R0 | |
| 141 | ||
| 142 | ;;Check if boot space corresponds to test memory | |
| 143 | ||
| 144 | LDR R0,=0x00000004 | |
| 145 | LDR R1, [R0] | |
| 146 | LSRS R1, R1, #24 | |
| 147 | LDR R2,=0x1F | |
| 148 | CMP R1, R2 | |
| 149 | ||
| 150 | BNE ApplicationStart | |
| 151 | ||
| 152 | ;; SYSCFG clock enable | |
| 153 | ||
| 154 | LDR R0,=0x40021018 | |
| 155 | LDR R1,=0x00000001 | |
| 156 | STR R1, [R0] | |
| 157 | ||
| 158 | ;; Set CFGR1 register with flash memory remap at address 0 | |
| 159 | ||
| 160 | LDR R0,=0x40010000 | |
| 161 | LDR R1,=0x00000000 | |
| 162 | STR R1, [R0] | |
| 163 | ApplicationStart | |
| 164 | LDR R0, =SystemInit | |
| 165 | BLX R0 | |
| 166 | LDR R0, =__main | |
| 167 | BX R0 | |
| 168 | ENDP | |
| 169 | ||
| 170 | ; Dummy Exception Handlers (infinite loops which can be modified) | |
| 171 | ||
| 172 | NMI_Handler PROC | |
| 173 | EXPORT NMI_Handler [WEAK] | |
| 174 | B . | |
| 175 | ENDP | |
| 176 | HardFault_Handler\ | |
| 177 | PROC | |
| 178 | EXPORT HardFault_Handler [WEAK] | |
| 179 | B . | |
| 180 | ENDP | |
| 181 | SVC_Handler PROC | |
| 182 | EXPORT SVC_Handler [WEAK] | |
| 183 | B . | |
| 184 | ENDP | |
| 185 | PendSV_Handler PROC | |
| 186 | EXPORT PendSV_Handler [WEAK] | |
| 187 | B . | |
| 188 | ENDP | |
| 189 | SysTick_Handler PROC | |
| 190 | EXPORT SysTick_Handler [WEAK] | |
| 191 | B . | |
| 192 | ENDP | |
| 193 | ||
| 194 | Default_Handler PROC | |
| 195 | ||
| 196 | EXPORT WWDG_IRQHandler [WEAK] | |
| 197 | EXPORT RTC_IRQHandler [WEAK] | |
| 198 | EXPORT FLASH_IRQHandler [WEAK] | |
| 199 | EXPORT RCC_IRQHandler [WEAK] | |
| 200 | EXPORT EXTI0_1_IRQHandler [WEAK] | |
| 201 | EXPORT EXTI2_3_IRQHandler [WEAK] | |
| 202 | EXPORT EXTI4_15_IRQHandler [WEAK] | |
| 203 | EXPORT DMA1_Channel1_IRQHandler [WEAK] | |
| 204 | EXPORT DMA1_Channel2_3_IRQHandler [WEAK] | |
| 205 | EXPORT DMA1_Channel4_5_IRQHandler [WEAK] | |
| 206 | EXPORT ADC1_IRQHandler [WEAK] | |
| 207 | EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] | |
| 208 | EXPORT TIM1_CC_IRQHandler [WEAK] | |
| 209 | EXPORT TIM3_IRQHandler [WEAK] | |
| 210 | EXPORT TIM14_IRQHandler [WEAK] | |
| 211 | EXPORT TIM16_IRQHandler [WEAK] | |
| 212 | EXPORT TIM17_IRQHandler [WEAK] | |
| 213 | EXPORT I2C1_IRQHandler [WEAK] | |
| 214 | EXPORT SPI1_IRQHandler [WEAK] | |
| 215 | EXPORT USART1_IRQHandler [WEAK] | |
| 216 | EXPORT USART2_IRQHandler [WEAK] | |
| 217 | EXPORT USB_IRQHandler [WEAK] | |
| 218 | ||
| 219 | ||
| 220 | WWDG_IRQHandler | |
| 221 | RTC_IRQHandler | |
| 222 | FLASH_IRQHandler | |
| 223 | RCC_IRQHandler | |
| 224 | EXTI0_1_IRQHandler | |
| 225 | EXTI2_3_IRQHandler | |
| 226 | EXTI4_15_IRQHandler | |
| 227 | DMA1_Channel1_IRQHandler | |
| 228 | DMA1_Channel2_3_IRQHandler | |
| 229 | DMA1_Channel4_5_IRQHandler | |
| 230 | ADC1_IRQHandler | |
| 231 | TIM1_BRK_UP_TRG_COM_IRQHandler | |
| 232 | TIM1_CC_IRQHandler | |
| 233 | TIM3_IRQHandler | |
| 234 | TIM14_IRQHandler | |
| 235 | TIM16_IRQHandler | |
| 236 | TIM17_IRQHandler | |
| 237 | I2C1_IRQHandler | |
| 238 | SPI1_IRQHandler | |
| 239 | USART1_IRQHandler | |
| 240 | USART2_IRQHandler | |
| 241 | USB_IRQHandler | |
| 242 | ||
| 243 | B . | |
| 244 | ||
| 245 | ENDP | |
| 246 | ||
| 247 | ALIGN | |
| 248 | ||
| 249 | ;******************************************************************************* | |
| 250 | ; User Stack and Heap initialization | |
| 251 | ;******************************************************************************* | |
| 252 | IF :DEF:__MICROLIB | |
| 253 | ||
| 254 | EXPORT __initial_sp | |
| 255 | EXPORT __heap_base | |
| 256 | EXPORT __heap_limit | |
| 257 | ||
| 258 | ELSE | |
| 259 | ||
| 260 | IMPORT __use_two_region_memory | |
| 261 | EXPORT __user_initial_stackheap | |
| 262 | ||
| 263 | __user_initial_stackheap | |
| 264 | ||
| 265 | LDR R0, = Heap_Mem | |
| 266 | LDR R1, =(Stack_Mem + Stack_Size) | |
| 267 | LDR R2, = (Heap_Mem + Heap_Size) | |
| 268 | LDR R3, = Stack_Mem | |
| 269 | BX LR | |
| 270 | ||
| 271 | ALIGN | |
| 272 | ||
| 273 | ENDIF | |
| 274 | ||
| 275 | END | |
| 276 | ||
| 277 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** | |
