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| 483170 | 1 | /* ---------------------------------------------------------------------- |
| Q | 2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
| 3 | * | |
| 4 | * $Date: 19. March 2015 | |
| 5 | * $Revision: V.1.4.5 | |
| 6 | * | |
| 7 | * Project: CMSIS DSP Library | |
| 8 | * Title: arm_const_structs.c | |
| 9 | * | |
| 10 | * Description: This file has constant structs that are initialized for | |
| 11 | * user convenience. For example, some can be given as | |
| 12 | * arguments to the arm_cfft_f32() function. | |
| 13 | * | |
| 14 | * Target Processor: Cortex-M4/Cortex-M3 | |
| 15 | * | |
| 16 | * Redistribution and use in source and binary forms, with or without | |
| 17 | * modification, are permitted provided that the following conditions | |
| 18 | * are met: | |
| 19 | * - Redistributions of source code must retain the above copyright | |
| 20 | * notice, this list of conditions and the following disclaimer. | |
| 21 | * - Redistributions in binary form must reproduce the above copyright | |
| 22 | * notice, this list of conditions and the following disclaimer in | |
| 23 | * the documentation and/or other materials provided with the | |
| 24 | * distribution. | |
| 25 | * - Neither the name of ARM LIMITED nor the names of its contributors | |
| 26 | * may be used to endorse or promote products derived from this | |
| 27 | * software without specific prior written permission. | |
| 28 | * | |
| 29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 30 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 31 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | |
| 32 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | |
| 33 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
| 34 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, | |
| 35 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
| 36 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
| 37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
| 38 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN | |
| 39 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
| 40 | * POSSIBILITY OF SUCH DAMAGE. | |
| 41 | * -------------------------------------------------------------------- */ | |
| 42 | ||
| 43 | #include "arm_const_structs.h" | |
| 44 | ||
| 45 | //Floating-point structs | |
| 46 | ||
| 47 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { | |
| 48 | 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH | |
| 49 | }; | |
| 50 | ||
| 51 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { | |
| 52 | 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH | |
| 53 | }; | |
| 54 | ||
| 55 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { | |
| 56 | 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH | |
| 57 | }; | |
| 58 | ||
| 59 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { | |
| 60 | 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH | |
| 61 | }; | |
| 62 | ||
| 63 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { | |
| 64 | 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH | |
| 65 | }; | |
| 66 | ||
| 67 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { | |
| 68 | 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH | |
| 69 | }; | |
| 70 | ||
| 71 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { | |
| 72 | 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH | |
| 73 | }; | |
| 74 | ||
| 75 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { | |
| 76 | 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH | |
| 77 | }; | |
| 78 | ||
| 79 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { | |
| 80 | 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH | |
| 81 | }; | |
| 82 | ||
| 83 | //Fixed-point structs | |
| 84 | ||
| 85 | const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = { | |
| 86 | 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH | |
| 87 | }; | |
| 88 | ||
| 89 | const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = { | |
| 90 | 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH | |
| 91 | }; | |
| 92 | ||
| 93 | const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = { | |
| 94 | 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH | |
| 95 | }; | |
| 96 | ||
| 97 | const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = { | |
| 98 | 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH | |
| 99 | }; | |
| 100 | ||
| 101 | const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = { | |
| 102 | 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH | |
| 103 | }; | |
| 104 | ||
| 105 | const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = { | |
| 106 | 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH | |
| 107 | }; | |
| 108 | ||
| 109 | const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = { | |
| 110 | 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH | |
| 111 | }; | |
| 112 | ||
| 113 | const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = { | |
| 114 | 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH | |
| 115 | }; | |
| 116 | ||
| 117 | const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = { | |
| 118 | 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH | |
| 119 | }; | |
| 120 | ||
| 121 | ||
| 122 | const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = { | |
| 123 | 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH | |
| 124 | }; | |
| 125 | ||
| 126 | const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = { | |
| 127 | 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH | |
| 128 | }; | |
| 129 | ||
| 130 | const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = { | |
| 131 | 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH | |
| 132 | }; | |
| 133 | ||
| 134 | const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = { | |
| 135 | 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH | |
| 136 | }; | |
| 137 | ||
| 138 | const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = { | |
| 139 | 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH | |
| 140 | }; | |
| 141 | ||
| 142 | const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = { | |
| 143 | 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH | |
| 144 | }; | |
| 145 | ||
| 146 | const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = { | |
| 147 | 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH | |
| 148 | }; | |
| 149 | ||
| 150 | const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = { | |
| 151 | 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH | |
| 152 | }; | |
| 153 | ||
| 154 | const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = { | |
| 155 | 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH | |
| 156 | }; | |
