F030C8T6_Kbus_MIX.git

move some define from Kbus.h to KBusDefine.h

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2024-02-25 95322c84888cbe2e92024d4d65698f59b016cb52

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483170	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_ll_adc.c
	4	* @author MCD Application Team
	5	* @brief ADC LL module driver
	6	******************************************************************************
	7	* @attention
	8	*
	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	10	*
	11	* Redistribution and use in source and binary forms, with or without modification,
	12	* are permitted provided that the following conditions are met:
	13	* 1. Redistributions of source code must retain the above copyright notice,
	14	* this list of conditions and the following disclaimer.
	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	19	* may be used to endorse or promote products derived from this software
	20	* without specific prior written permission.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	******************************************************************************
	34	*/
	35	#if defined(USE_FULL_LL_DRIVER)
	36
	37	/* Includes ------------------------------------------------------------------*/
	38	#include "stm32f0xx_ll_adc.h"
	39	#include "stm32f0xx_ll_bus.h"
	40
	41	#ifdef USE_FULL_ASSERT
	42	#include "stm32_assert.h"
	43	#else
	44	#define assert_param(expr) ((void)0U)
	45	#endif
	46
	47	/** @addtogroup STM32F0xx_LL_Driver
	48	* @{
	49	*/
	50
	51	#if defined (ADC1)
	52
	53	/** @addtogroup ADC_LL ADC
	54	* @{
	55	*/
	56
	57	/* Private types -------------------------------------------------------------*/
	58	/* Private variables ---------------------------------------------------------*/
	59	/* Private constants ---------------------------------------------------------*/
	60	/** @addtogroup ADC_LL_Private_Constants
	61	* @{
	62	*/
	63
	64	/* Definitions of ADC hardware constraints delays */
	65	/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
	66	/* not timeout values: */
	67	/* Timeout values for ADC operations are dependent to device clock */
	68	/* configuration (system clock versus ADC clock), */
	69	/* and therefore must be defined in user application. */
	70	/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
	71	/* values definition. */
	72	/* Note: ADC timeout values are defined here in CPU cycles to be independent */
	73	/* of device clock setting. */
	74	/* In user application, ADC timeout values should be defined with */
	75	/* temporal values, in function of device clock settings. */
	76	/* Highest ratio CPU clock frequency vs ADC clock frequency: */
	77	/* - ADC clock from synchronous clock with AHB prescaler 512, */
	78	/* APB prescaler 16, ADC prescaler 4. */
	79	/* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
	80	/* with highest ratio CPU clock frequency vs HSI clock frequency: */
	81	/* CPU clock frequency max 48MHz, HSI frequency 14MHz: ratio 4. */
	82	/* Unit: CPU cycles. */
	83	#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
	84	#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
	85	#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
	86
	87	/**
	88	* @}
	89	*/
	90
	91	/* Private macros ------------------------------------------------------------*/
	92
	93	/** @addtogroup ADC_LL_Private_Macros
	94	* @{
	95	*/
	96
	97	/* Check of parameters for configuration of ADC hierarchical scope: */
	98	/* common to several ADC instances. */
	99	/* Check of parameters for configuration of ADC hierarchical scope: */
	100	/* ADC instance. */
	101	#define IS_LL_ADC_CLOCK(__CLOCK__) \
	102	( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
	103	\|\| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
	104	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
	105	)
	106
	107	#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
	108	( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
	109	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
	110	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
	111	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
	112	)
	113
	114	#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
	115	( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
	116	\|\| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
	117	)
	118
	119	#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
	120	( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
	121	\|\| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
	122	\|\| ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
	123	\|\| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
	124	)
	125
	126	/* Check of parameters for configuration of ADC hierarchical scope: */
	127	/* ADC group regular */
	128	#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
	129	( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
	130	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
	131	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4) \
	132	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
	133	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
	134	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
	135	)
	136
	137	#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
	138	( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
	139	\|\| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
	140	)
	141
	142	#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
	143	( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
	144	\|\| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
	145	\|\| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
	146	)
	147
	148	#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
	149	( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
	150	\|\| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
	151	)
	152
	153	#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
	154	( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
	155	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
	156	)
	157
	158	/**
	159	* @}
	160	*/
	161
	162
	163	/* Private function prototypes -----------------------------------------------*/
	164
	165	/* Exported functions --------------------------------------------------------*/
	166	/** @addtogroup ADC_LL_Exported_Functions
	167	* @{
	168	*/
	169
	170	/** @addtogroup ADC_LL_EF_Init
	171	* @{
	172	*/
	173
	174	/**
	175	* @brief De-initialize registers of all ADC instances belonging to
	176	* the same ADC common instance to their default reset values.
	177	* @note This function is performing a hard reset, using high level
	178	* clock source RCC ADC reset.
	179	* @param ADCxy_COMMON ADC common instance
	180	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
	181	* @retval An ErrorStatus enumeration value:
	182	* - SUCCESS: ADC common registers are de-initialized
	183	* - ERROR: not applicable
	184	*/
	185	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
	186	{
	187	/* Check the parameters */
	188	assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
	189
	190	/* Force reset of ADC clock (core clock) */
	191	LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1);
	192
	193	/* Release reset of ADC clock (core clock) */
	194	LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1);
	195
	196	return SUCCESS;
	197	}
	198
	199
	200	/**
	201	* @brief De-initialize registers of the selected ADC instance
	202	* to their default reset values.
	203	* @note To reset all ADC instances quickly (perform a hard reset),
	204	* use function @ref LL_ADC_CommonDeInit().
	205	* @note If this functions returns error status, it means that ADC instance
	206	* is in an unknown state.
	207	* In this case, perform a hard reset using high level
	208	* clock source RCC ADC reset.
	209	* Refer to function @ref LL_ADC_CommonDeInit().
	210	* @param ADCx ADC instance
	211	* @retval An ErrorStatus enumeration value:
	212	* - SUCCESS: ADC registers are de-initialized
	213	* - ERROR: ADC registers are not de-initialized
	214	*/
	215	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
	216	{
	217	ErrorStatus status = SUCCESS;
	218
	219	__IO uint32_t timeout_cpu_cycles = 0U;
	220
	221	/* Check the parameters */
	222	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
	223
	224	/* Disable ADC instance if not already disabled. */
	225	if(LL_ADC_IsEnabled(ADCx) == 1U)
	226	{
	227	/* Set ADC group regular trigger source to SW start to ensure to not */
	228	/* have an external trigger event occurring during the conversion stop */
	229	/* ADC disable process. */
	230	LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
	231
	232	/* Stop potential ADC conversion on going on ADC group regular. */
	233	if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
	234	{
	235	if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
	236	{
	237	LL_ADC_REG_StopConversion(ADCx);
	238	}
	239	}
	240
	241	/* Wait for ADC conversions are effectively stopped */
	242	timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
	243	while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U)
	244	{
	245	if(timeout_cpu_cycles-- == 0U)
	246	{
	247	/* Time-out error */
	248	status = ERROR;
	249	}
	250	}
	251
	252	/* Disable the ADC instance */
	253	LL_ADC_Disable(ADCx);
	254
	255	/* Wait for ADC instance is effectively disabled */
	256	timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
	257	while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
	258	{
	259	if(timeout_cpu_cycles-- == 0U)
	260	{
	261	/* Time-out error */
	262	status = ERROR;
	263	}
	264	}
	265	}
	266
	267	/* Check whether ADC state is compliant with expected state */
	268	if(READ_BIT(ADCx->CR,
	269	( ADC_CR_ADSTP \| ADC_CR_ADSTART
	270	\| ADC_CR_ADDIS \| ADC_CR_ADEN )
	271	)
	272	== 0U)
	273	{
	274	/* ========== Reset ADC registers ========== */
	275	/* Reset register IER */
	276	CLEAR_BIT(ADCx->IER,
	277	( LL_ADC_IT_ADRDY
	278	\| LL_ADC_IT_EOC
	279	\| LL_ADC_IT_EOS
	280	\| LL_ADC_IT_OVR
	281	\| LL_ADC_IT_EOSMP
	282	\| LL_ADC_IT_AWD1 )
	283	);
	284
	285	/* Reset register ISR */
	286	SET_BIT(ADCx->ISR,
	287	( LL_ADC_FLAG_ADRDY
	288	\| LL_ADC_FLAG_EOC
	289	\| LL_ADC_FLAG_EOS
	290	\| LL_ADC_FLAG_OVR
	291	\| LL_ADC_FLAG_EOSMP
	292	\| LL_ADC_FLAG_AWD1 )
	293	);
	294
	295	/* Reset register CR */
	296	/* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
	297	/* "read-set": no direct reset applicable. */
	298	/* No action on register CR */
	299
	300	/* Reset register CFGR1 */
	301	CLEAR_BIT(ADCx->CFGR1,
	302	( ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_DISCEN
	303	\| ADC_CFGR1_AUTOFF \| ADC_CFGR1_WAIT \| ADC_CFGR1_CONT \| ADC_CFGR1_OVRMOD
	304	\| ADC_CFGR1_EXTEN \| ADC_CFGR1_EXTSEL \| ADC_CFGR1_ALIGN \| ADC_CFGR1_RES
	305	\| ADC_CFGR1_SCANDIR \| ADC_CFGR1_DMACFG \| ADC_CFGR1_DMAEN )
	306	);
	307
	308	/* Reset register CFGR2 */
	309	/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
	310	/* already done above. */
	311	CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE);
	312
	313	/* Reset register SMPR */
	314	CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP);
	315
	316	/* Reset register TR */
	317	MODIFY_REG(ADCx->TR, ADC_TR_HT \| ADC_TR_LT, ADC_TR_HT);
	318
	319	/* Reset register CHSELR */
	320	#if defined(ADC_CCR_VBATEN)
	321	CLEAR_BIT(ADCx->CHSELR,
	322	( ADC_CHSELR_CHSEL18 \| ADC_CHSELR_CHSEL17 \| ADC_CHSELR_CHSEL16
	323	\| ADC_CHSELR_CHSEL15 \| ADC_CHSELR_CHSEL14 \| ADC_CHSELR_CHSEL13 \| ADC_CHSELR_CHSEL12
	324	\| ADC_CHSELR_CHSEL11 \| ADC_CHSELR_CHSEL10 \| ADC_CHSELR_CHSEL9 \| ADC_CHSELR_CHSEL8
	325	\| ADC_CHSELR_CHSEL7 \| ADC_CHSELR_CHSEL6 \| ADC_CHSELR_CHSEL5 \| ADC_CHSELR_CHSEL4
	326	\| ADC_CHSELR_CHSEL3 \| ADC_CHSELR_CHSEL2 \| ADC_CHSELR_CHSEL1 \| ADC_CHSELR_CHSEL0 )
	327	);
	328	#else
	329	CLEAR_BIT(ADCx->CHSELR,
	330	( ADC_CHSELR_CHSEL17 \| ADC_CHSELR_CHSEL16
	331	\| ADC_CHSELR_CHSEL15 \| ADC_CHSELR_CHSEL14 \| ADC_CHSELR_CHSEL13 \| ADC_CHSELR_CHSEL12
	332	\| ADC_CHSELR_CHSEL11 \| ADC_CHSELR_CHSEL10 \| ADC_CHSELR_CHSEL9 \| ADC_CHSELR_CHSEL8
	333	\| ADC_CHSELR_CHSEL7 \| ADC_CHSELR_CHSEL6 \| ADC_CHSELR_CHSEL5 \| ADC_CHSELR_CHSEL4
	334	\| ADC_CHSELR_CHSEL3 \| ADC_CHSELR_CHSEL2 \| ADC_CHSELR_CHSEL1 \| ADC_CHSELR_CHSEL0 )
	335	);
	336	#endif
	337
	338	/* Reset register DR */
	339	/* bits in access mode read only, no direct reset applicable */
	340
	341	}
	342	else
	343	{
	344	/* ADC instance is in an unknown state */
	345	/* Need to performing a hard reset of ADC instance, using high level */
	346	/* clock source RCC ADC reset. */
	347	/* Caution: On this STM32 serie, if several ADC instances are available */
	348	/* on the selected device, RCC ADC reset will reset */
	349	/* all ADC instances belonging to the common ADC instance. */
	350	status = ERROR;
	351	}
	352
	353	return status;
	354	}
	355
	356	/**
	357	* @brief Initialize some features of ADC instance.
	358	* @note These parameters have an impact on ADC scope: ADC instance.
	359	* Refer to corresponding unitary functions into
	360	* @ref ADC_LL_EF_Configuration_ADC_Instance .
	361	* @note The setting of these parameters by function @ref LL_ADC_Init()
	362	* is conditioned to ADC state:
	363	* ADC instance must be disabled.
	364	* This condition is applied to all ADC features, for efficiency
	365	* and compatibility over all STM32 families. However, the different
	366	* features can be set under different ADC state conditions
	367	* (setting possible with ADC enabled without conversion on going,
	368	* ADC enabled with conversion on going, ...)
	369	* Each feature can be updated afterwards with a unitary function
	370	* and potentially with ADC in a different state than disabled,
	371	* refer to description of each function for setting
	372	* conditioned to ADC state.
	373	* @note After using this function, some other features must be configured
	374	* using LL unitary functions.
	375	* The minimum configuration remaining to be done is:
	376	* - Set ADC group regular sequencer:
	377	* map channel on rank corresponding to channel number.
	378	* Refer to function @ref LL_ADC_REG_SetSequencerChannels();
	379	* - Set ADC channel sampling time
	380	* Refer to function LL_ADC_SetChannelSamplingTime();
	381	* @param ADCx ADC instance
	382	* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
	383	* @retval An ErrorStatus enumeration value:
	384	* - SUCCESS: ADC registers are initialized
	385	* - ERROR: ADC registers are not initialized
	386	*/
	387	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct)
	388	{
	389	ErrorStatus status = SUCCESS;
	390
	391	/* Check the parameters */
	392	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
	393
	394	assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
	395	assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
	396	assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
	397	assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
	398
	399	/* Note: Hardware constraint (refer to description of this function): */
	400	/* ADC instance must be disabled. */
	401	if(LL_ADC_IsEnabled(ADCx) == 0U)
	402	{
	403	/* Configuration of ADC hierarchical scope: */
	404	/* - ADC instance */
	405	/* - Set ADC data resolution */
	406	/* - Set ADC conversion data alignment */
	407	/* - Set ADC low power mode */
	408	MODIFY_REG(ADCx->CFGR1,
	409	ADC_CFGR1_RES
	410	\| ADC_CFGR1_ALIGN
	411	\| ADC_CFGR1_WAIT
	412	\| ADC_CFGR1_AUTOFF
	413	,
	414	ADC_InitStruct->Resolution
	415	\| ADC_InitStruct->DataAlignment
	416	\| ADC_InitStruct->LowPowerMode
	417	);
	418
	419	}
	420	else
	421	{
	422	/* Initialization error: ADC instance is not disabled. */
	423	status = ERROR;
	424	}
	425	return status;
	426	}
	427
	428	/**
	429	* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
	430	* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
	431	* whose fields will be set to default values.
	432	* @retval None
	433	*/
	434	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
	435	{
	436	/* Set ADC_InitStruct fields to default values */
	437	/* Set fields of ADC instance */
	438	ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
	439	ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
	440	ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
	441	ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
	442
	443	}
	444
	445	/**
	446	* @brief Initialize some features of ADC group regular.
	447	* @note These parameters have an impact on ADC scope: ADC group regular.
	448	* Refer to corresponding unitary functions into
	449	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
	450	* (functions with prefix "REG").
	451	* @note The setting of these parameters by function @ref LL_ADC_Init()
	452	* is conditioned to ADC state:
	453	* ADC instance must be disabled.
	454	* This condition is applied to all ADC features, for efficiency
	455	* and compatibility over all STM32 families. However, the different
	456	* features can be set under different ADC state conditions
	457	* (setting possible with ADC enabled without conversion on going,
	458	* ADC enabled with conversion on going, ...)
	459	* Each feature can be updated afterwards with a unitary function
	460	* and potentially with ADC in a different state than disabled,
	461	* refer to description of each function for setting
	462	* conditioned to ADC state.
	463	* @note After using this function, other features must be configured
	464	* using LL unitary functions.
	465	* The minimum configuration remaining to be done is:
	466	* - Set ADC group regular sequencer:
	467	* map channel on rank corresponding to channel number.
	468	* Refer to function @ref LL_ADC_REG_SetSequencerChannels();
	469	* - Set ADC channel sampling time
	470	* Refer to function LL_ADC_SetChannelSamplingTime();
	471	* @param ADCx ADC instance
	472	* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
	473	* @retval An ErrorStatus enumeration value:
	474	* - SUCCESS: ADC registers are initialized
	475	* - ERROR: ADC registers are not initialized
	476	*/
	477	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct)
	478	{
	479	ErrorStatus status = SUCCESS;
	480
	481	/* Check the parameters */
	482	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
	483	assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
	484	assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
	485	assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
	486	assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
	487	assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
	488
	489	/* Note: Hardware constraint (refer to description of this function): */
	490	/* ADC instance must be disabled. */
	491	if(LL_ADC_IsEnabled(ADCx) == 0U)
	492	{
	493	/* Configuration of ADC hierarchical scope: */
	494	/* - ADC group regular */
	495	/* - Set ADC group regular trigger source */
	496	/* - Set ADC group regular sequencer discontinuous mode */
	497	/* - Set ADC group regular continuous mode */
	498	/* - Set ADC group regular conversion data transfer: no transfer or */
	499	/* transfer by DMA, and DMA requests mode */
	500	/* - Set ADC group regular overrun behavior */
	501	/* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
	502	/* setting of trigger source to SW start. */
	503	MODIFY_REG(ADCx->CFGR1,
	504	ADC_CFGR1_EXTSEL
	505	\| ADC_CFGR1_EXTEN
	506	\| ADC_CFGR1_DISCEN
	507	\| ADC_CFGR1_CONT
	508	\| ADC_CFGR1_DMAEN
	509	\| ADC_CFGR1_DMACFG
	510	\| ADC_CFGR1_OVRMOD
	511	,
	512	ADC_REG_InitStruct->TriggerSource
	513	\| ADC_REG_InitStruct->SequencerDiscont
	514	\| ADC_REG_InitStruct->ContinuousMode
	515	\| ADC_REG_InitStruct->DMATransfer
	516	\| ADC_REG_InitStruct->Overrun
	517	);
	518
	519	}
	520	else
	521	{
	522	/* Initialization error: ADC instance is not disabled. */
	523	status = ERROR;
	524	}
	525	return status;
	526	}
	527
	528	/**
	529	* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
	530	* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
	531	* whose fields will be set to default values.
	532	* @retval None
	533	*/
	534	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
	535	{
	536	/* Set ADC_REG_InitStruct fields to default values */
	537	/* Set fields of ADC group regular */
	538	/* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
	539	/* setting of trigger source to SW start. */
	540	ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
	541	ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
	542	ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
	543	ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
	544	ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
	545	}
	546
	547	/**
	548	* @}
	549	*/
	550
	551	/**
	552	* @}
	553	*/
	554
	555	/**
	556	* @}
	557	*/
	558
	559	#endif /* ADC1 */
	560
	561	/**
	562	* @}
	563	*/
	564
	565	#endif /* USE_FULL_LL_DRIVER */
	566
	567	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/