F030C8T6_Kbus_MIX.git

move some define from Kbus.h to KBusDefine.h

QuakeGod

2024-02-25 95322c84888cbe2e92024d4d65698f59b016cb52

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483170	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_ll_bus.h
	4	* @author MCD Application Team
	5	* @brief Header file of BUS LL module.
	6
	7	@verbatim
	8	##### RCC Limitations #####
	9	==============================================================================
	10	[..]
	11	A delay between an RCC peripheral clock enable and the effective peripheral
	12	enabling should be taken into account in order to manage the peripheral read/write
	13	from/to registers.
	14	(+) This delay depends on the peripheral mapping.
	15	(++) AHB & APB peripherals, 1 dummy read is necessary
	16
	17	[..]
	18	Workarounds:
	19	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
	20	inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
	21
	22	@endverbatim
	23	******************************************************************************
	24	* @attention
	25	*
	26	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	27	*
	28	* Redistribution and use in source and binary forms, with or without modification,
	29	* are permitted provided that the following conditions are met:
	30	* 1. Redistributions of source code must retain the above copyright notice,
	31	* this list of conditions and the following disclaimer.
	32	* 2. Redistributions in binary form must reproduce the above copyright notice,
	33	* this list of conditions and the following disclaimer in the documentation
	34	* and/or other materials provided with the distribution.
	35	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	36	* may be used to endorse or promote products derived from this software
	37	* without specific prior written permission.
	38	*
	39	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	40	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	41	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	42	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	43	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	44	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	45	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	46	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	47	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	48	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	49	*
	50	******************************************************************************
	51	*/
	52
	53	/* Define to prevent recursive inclusion -------------------------------------*/
	54	#ifndef __STM32F0xx_LL_BUS_H
	55	#define __STM32F0xx_LL_BUS_H
	56
	57	#ifdef __cplusplus
	58	extern "C" {
	59	#endif
	60
	61	/* Includes ------------------------------------------------------------------*/
	62	#include "stm32f0xx.h"
	63
	64	/** @addtogroup STM32F0xx_LL_Driver
	65	* @{
	66	*/
	67
	68	#if defined(RCC)
	69
	70	/** @defgroup BUS_LL BUS
	71	* @{
	72	*/
	73
	74	/* Private types -------------------------------------------------------------*/
	75	/* Private variables ---------------------------------------------------------*/
	76
	77	/* Private constants ---------------------------------------------------------*/
	78
	79	/* Private macros ------------------------------------------------------------*/
	80
	81	/* Exported types ------------------------------------------------------------*/
	82	/* Exported constants --------------------------------------------------------*/
	83	/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
	84	* @{
	85	*/
	86
	87	/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
	88	* @{
	89	*/
	90	#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
	91	#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
	92	#if defined(DMA2)
	93	#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
	94	#endif /DMA2/
	95	#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
	96	#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
	97	#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
	98	#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
	99	#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
	100	#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
	101	#if defined(GPIOD)
	102	#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
	103	#endif /GPIOD/
	104	#if defined(GPIOE)
	105	#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
	106	#endif /GPIOE/
	107	#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
	108	#if defined(TSC)
	109	#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
	110	#endif /TSC/
	111	/**
	112	* @}
	113	*/
	114
	115	/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
	116	* @{
	117	*/
	118	#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
	119	#if defined(TIM2)
	120	#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
	121	#endif /TIM2/
	122	#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
	123	#if defined(TIM6)
	124	#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
	125	#endif /TIM6/
	126	#if defined(TIM7)
	127	#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
	128	#endif /TIM7/
	129	#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
	130	#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
	131	#if defined(SPI2)
	132	#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
	133	#endif /SPI2/
	134	#if defined(USART2)
	135	#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
	136	#endif /* USART2 */
	137	#if defined(USART3)
	138	#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
	139	#endif /* USART3 */
	140	#if defined(USART4)
	141	#define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN
	142	#endif /* USART4 */
	143	#if defined(USART5)
	144	#define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN
	145	#endif /* USART5 */
	146	#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
	147	#if defined(I2C2)
	148	#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
	149	#endif /I2C2/
	150	#if defined(USB)
	151	#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
	152	#endif /* USB */
	153	#if defined(CAN)
	154	#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
	155	#endif /CAN/
	156	#if defined(CRS)
	157	#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN
	158	#endif /CRS/
	159	#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
	160	#if defined(DAC)
	161	#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
	162	#endif /DAC/
	163	#if defined(CEC)
	164	#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
	165	#endif /CEC/
	166	/**
	167	* @}
	168	*/
	169
	170	/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
	171	* @{
	172	*/
	173	#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
	174	#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
	175	#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
	176	#if defined(USART8)
	177	#define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN
	178	#endif /USART8/
	179	#if defined(USART7)
	180	#define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN
	181	#endif /USART7/
	182	#if defined(USART6)
	183	#define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN
	184	#endif /USART6/
	185	#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
	186	#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
	187	#define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN
	188	#if defined(TIM15)
	189	#define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
	190	#endif /TIM15/
	191	#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
	192	#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
	193	#define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN
	194	/**
	195	* @}
	196	*/
	197
	198	/**
	199	* @}
	200	*/
	201
	202	/* Exported macro ------------------------------------------------------------*/
	203	/* Exported functions --------------------------------------------------------*/
	204	/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
	205	* @{
	206	*/
	207
	208	/** @defgroup BUS_LL_EF_AHB1 AHB1
	209	* @{
	210	*/
	211
	212	/**
	213	* @brief Enable AHB1 peripherals clock.
	214	* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
	215	* AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
	216	* AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
	217	* AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
	218	* AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
	219	* AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
	220	* AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
	221	* AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
	222	* AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
	223	* AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
	224	* AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
	225	* AHBENR TSCEN LL_AHB1_GRP1_EnableClock
	226	* @param Periphs This parameter can be a combination of the following values:
	227	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
	228	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
	229	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
	230	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
	231	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
	232	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
	233	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
	234	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
	235	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
	236	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
	237	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
	238	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
	239	*
	240	* (*) value not defined in all devices.
	241	* @retval None
	242	*/
	243	__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
	244	{
	245	__IO uint32_t tmpreg;
	246	SET_BIT(RCC->AHBENR, Periphs);
	247	/* Delay after an RCC peripheral clock enabling */
	248	tmpreg = READ_BIT(RCC->AHBENR, Periphs);
	249	(void)tmpreg;
	250	}
	251
	252	/**
	253	* @brief Check if AHB1 peripheral clock is enabled or not
	254	* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
	255	* AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
	256	* AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
	257	* AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
	258	* AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
	259	* AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
	260	* AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
	261	* AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
	262	* AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
	263	* AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
	264	* AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
	265	* AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock
	266	* @param Periphs This parameter can be a combination of the following values:
	267	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
	268	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
	269	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
	270	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
	271	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
	272	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
	273	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
	274	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
	275	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
	276	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
	277	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
	278	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
	279	*
	280	* (*) value not defined in all devices.
	281	* @retval State of Periphs (1 or 0).
	282	*/
	283	__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
	284	{
	285	return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
	286	}
	287
	288	/**
	289	* @brief Disable AHB1 peripherals clock.
	290	* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
	291	* AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
	292	* AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
	293	* AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
	294	* AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
	295	* AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
	296	* AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
	297	* AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
	298	* AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
	299	* AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
	300	* AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
	301	* AHBENR TSCEN LL_AHB1_GRP1_DisableClock
	302	* @param Periphs This parameter can be a combination of the following values:
	303	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
	304	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
	305	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
	306	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
	307	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
	308	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
	309	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
	310	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
	311	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
	312	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
	313	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
	314	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
	315	*
	316	* (*) value not defined in all devices.
	317	* @retval None
	318	*/
	319	__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
	320	{
	321	CLEAR_BIT(RCC->AHBENR, Periphs);
	322	}
	323
	324	/**
	325	* @brief Force AHB1 peripherals reset.
	326	* @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
	327	* AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
	328	* AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
	329	* AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
	330	* AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
	331	* AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
	332	* AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset
	333	* @param Periphs This parameter can be a combination of the following values:
	334	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
	335	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
	336	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
	337	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
	338	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
	339	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
	340	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
	341	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
	342	*
	343	* (*) value not defined in all devices.
	344	* @retval None
	345	*/
	346	__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
	347	{
	348	SET_BIT(RCC->AHBRSTR, Periphs);
	349	}
	350
	351	/**
	352	* @brief Release AHB1 peripherals reset.
	353	* @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
	354	* AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
	355	* AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
	356	* AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
	357	* AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
	358	* AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
	359	* AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset
	360	* @param Periphs This parameter can be a combination of the following values:
	361	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
	362	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
	363	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
	364	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
	365	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
	366	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
	367	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
	368	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
	369	*
	370	* (*) value not defined in all devices.
	371	* @retval None
	372	*/
	373	__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
	374	{
	375	CLEAR_BIT(RCC->AHBRSTR, Periphs);
	376	}
	377
	378	/**
	379	* @}
	380	*/
	381
	382	/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1
	383	* @{
	384	*/
	385
	386	/**
	387	* @brief Enable APB1 peripherals clock (available in register 1).
	388	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
	389	* APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
	390	* APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
	391	* APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
	392	* APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
	393	* APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
	394	* APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
	395	* APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
	396	* APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
	397	* APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n
	398	* APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n
	399	* APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
	400	* APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
	401	* APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
	402	* APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
	403	* APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n
	404	* APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
	405	* APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
	406	* APB1ENR CECEN LL_APB1_GRP1_EnableClock
	407	* @param Periphs This parameter can be a combination of the following values:
	408	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
	409	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
	410	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
	411	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
	412	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
	413	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
	414	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
	415	* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
	416	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
	417	* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
	418	* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
	419	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
	420	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
	421	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
	422	* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
	423	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
	424	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
	425	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
	426	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
	427	*
	428	* (*) value not defined in all devices.
	429	* @retval None
	430	*/
	431	__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
	432	{
	433	__IO uint32_t tmpreg;
	434	SET_BIT(RCC->APB1ENR, Periphs);
	435	/* Delay after an RCC peripheral clock enabling */
	436	tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
	437	(void)tmpreg;
	438	}
	439
	440	/**
	441	* @brief Check if APB1 peripheral clock is enabled or not (available in register 1).
	442	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
	443	* APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
	444	* APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
	445	* APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
	446	* APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
	447	* APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
	448	* APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
	449	* APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
	450	* APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
	451	* APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n
	452	* APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n
	453	* APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
	454	* APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
	455	* APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
	456	* APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
	457	* APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
	458	* APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
	459	* APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
	460	* APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock
	461	* @param Periphs This parameter can be a combination of the following values:
	462	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
	463	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
	464	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
	465	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
	466	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
	467	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
	468	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
	469	* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
	470	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
	471	* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
	472	* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
	473	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
	474	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
	475	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
	476	* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
	477	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
	478	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
	479	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
	480	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
	481	*
	482	* (*) value not defined in all devices.
	483	* @retval State of Periphs (1 or 0).
	484	*/
	485	__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
	486	{
	487	return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
	488	}
	489
	490	/**
	491	* @brief Disable APB1 peripherals clock (available in register 1).
	492	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
	493	* APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
	494	* APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
	495	* APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
	496	* APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
	497	* APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
	498	* APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
	499	* APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
	500	* APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
	501	* APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n
	502	* APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n
	503	* APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
	504	* APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
	505	* APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
	506	* APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
	507	* APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n
	508	* APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
	509	* APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
	510	* APB1ENR CECEN LL_APB1_GRP1_DisableClock
	511	* @param Periphs This parameter can be a combination of the following values:
	512	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
	513	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
	514	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
	515	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
	516	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
	517	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
	518	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
	519	* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
	520	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
	521	* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
	522	* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
	523	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
	524	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
	525	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
	526	* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
	527	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
	528	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
	529	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
	530	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
	531	*
	532	* (*) value not defined in all devices.
	533	* @retval None
	534	*/
	535	__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
	536	{
	537	CLEAR_BIT(RCC->APB1ENR, Periphs);
	538	}
	539
	540	/**
	541	* @brief Force APB1 peripherals reset (available in register 1).
	542	* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
	543	* APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
	544	* APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
	545	* APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
	546	* APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
	547	* APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
	548	* APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
	549	* APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
	550	* APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
	551	* APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n
	552	* APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n
	553	* APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
	554	* APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
	555	* APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
	556	* APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
	557	* APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n
	558	* APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
	559	* APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
	560	* APB1RSTR CECRST LL_APB1_GRP1_ForceReset
	561	* @param Periphs This parameter can be a combination of the following values:
	562	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
	563	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
	564	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
	565	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
	566	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
	567	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
	568	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
	569	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
	570	* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
	571	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
	572	* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
	573	* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
	574	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
	575	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
	576	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
	577	* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
	578	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
	579	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
	580	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
	581	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
	582	*
	583	* (*) value not defined in all devices.
	584	* @retval None
	585	*/
	586	__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
	587	{
	588	SET_BIT(RCC->APB1RSTR, Periphs);
	589	}
	590
	591	/**
	592	* @brief Release APB1 peripherals reset (available in register 1).
	593	* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
	594	* APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
	595	* APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
	596	* APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
	597	* APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
	598	* APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
	599	* APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
	600	* APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
	601	* APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
	602	* APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n
	603	* APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n
	604	* APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
	605	* APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
	606	* APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
	607	* APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
	608	* APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
	609	* APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
	610	* APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
	611	* APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset
	612	* @param Periphs This parameter can be a combination of the following values:
	613	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
	614	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
	615	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
	616	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
	617	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
	618	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
	619	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
	620	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
	621	* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
	622	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
	623	* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
	624	* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
	625	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
	626	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
	627	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
	628	* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
	629	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
	630	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
	631	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
	632	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
	633	*
	634	* (*) value not defined in all devices.
	635	* @retval None
	636	*/
	637	__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
	638	{
	639	CLEAR_BIT(RCC->APB1RSTR, Periphs);
	640	}
	641
	642	/**
	643	* @}
	644	*/
	645
	646	/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2
	647	* @{
	648	*/
	649
	650	/**
	651	* @brief Enable APB1 peripherals clock (available in register 2).
	652	* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n
	653	* APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n
	654	* APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n
	655	* APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n
	656	* APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n
	657	* APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n
	658	* APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n
	659	* APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n
	660	* APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n
	661	* APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n
	662	* APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n
	663	* APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock
	664	* @param Periphs This parameter can be a combination of the following values:
	665	* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
	666	* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
	667	* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
	668	* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
	669	* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
	670	* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
	671	* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
	672	* @arg @ref LL_APB1_GRP2_PERIPH_USART1
	673	* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
	674	* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
	675	* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
	676	* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
	677	*
	678	* (*) value not defined in all devices.
	679	* @retval None
	680	*/
	681	__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
	682	{
	683	__IO uint32_t tmpreg;
	684	SET_BIT(RCC->APB2ENR, Periphs);
	685	/* Delay after an RCC peripheral clock enabling */
	686	tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
	687	(void)tmpreg;
	688	}
	689
	690	/**
	691	* @brief Check if APB1 peripheral clock is enabled or not (available in register 2).
	692	* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n
	693	* APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n
	694	* APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n
	695	* APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n
	696	* APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n
	697	* APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n
	698	* APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n
	699	* APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n
	700	* APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n
	701	* APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n
	702	* APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n
	703	* APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock
	704	* @param Periphs This parameter can be a combination of the following values:
	705	* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
	706	* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
	707	* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
	708	* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
	709	* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
	710	* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
	711	* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
	712	* @arg @ref LL_APB1_GRP2_PERIPH_USART1
	713	* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
	714	* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
	715	* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
	716	* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
	717	*
	718	* (*) value not defined in all devices.
	719	* @retval State of Periphs (1 or 0).
	720	*/
	721	__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
	722	{
	723	return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
	724	}
	725
	726	/**
	727	* @brief Disable APB1 peripherals clock (available in register 2).
	728	* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n
	729	* APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n
	730	* APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n
	731	* APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n
	732	* APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n
	733	* APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n
	734	* APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n
	735	* APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n
	736	* APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n
	737	* APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n
	738	* APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n
	739	* APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock
	740	* @param Periphs This parameter can be a combination of the following values:
	741	* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
	742	* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
	743	* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
	744	* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
	745	* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
	746	* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
	747	* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
	748	* @arg @ref LL_APB1_GRP2_PERIPH_USART1
	749	* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
	750	* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
	751	* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
	752	* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
	753	*
	754	* (*) value not defined in all devices.
	755	* @retval None
	756	*/
	757	__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
	758	{
	759	CLEAR_BIT(RCC->APB2ENR, Periphs);
	760	}
	761
	762	/**
	763	* @brief Force APB1 peripherals reset (available in register 2).
	764	* @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n
	765	* APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n
	766	* APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n
	767	* APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n
	768	* APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n
	769	* APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n
	770	* APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n
	771	* APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n
	772	* APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n
	773	* APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n
	774	* APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n
	775	* APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset
	776	* @param Periphs This parameter can be a combination of the following values:
	777	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
	778	* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
	779	* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
	780	* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
	781	* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
	782	* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
	783	* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
	784	* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
	785	* @arg @ref LL_APB1_GRP2_PERIPH_USART1
	786	* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
	787	* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
	788	* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
	789	* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
	790	*
	791	* (*) value not defined in all devices.
	792	* @retval None
	793	*/
	794	__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
	795	{
	796	SET_BIT(RCC->APB2RSTR, Periphs);
	797	}
	798
	799	/**
	800	* @brief Release APB1 peripherals reset (available in register 2).
	801	* @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n
	802	* APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n
	803	* APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n
	804	* APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n
	805	* APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n
	806	* APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n
	807	* APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n
	808	* APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n
	809	* APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n
	810	* APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n
	811	* APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n
	812	* APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset
	813	* @param Periphs This parameter can be a combination of the following values:
	814	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
	815	* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
	816	* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
	817	* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
	818	* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
	819	* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
	820	* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
	821	* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
	822	* @arg @ref LL_APB1_GRP2_PERIPH_USART1
	823	* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
	824	* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
	825	* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
	826	* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
	827	*
	828	* (*) value not defined in all devices.
	829	* @retval None
	830	*/
	831	__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
	832	{
	833	CLEAR_BIT(RCC->APB2RSTR, Periphs);
	834	}
	835
	836	/**
	837	* @}
	838	*/
	839
	840
	841	/**
	842	* @}
	843	*/
	844
	845	/**
	846	* @}
	847	*/
	848
	849	#endif /* defined(RCC) */
	850
	851	/**
	852	* @}
	853	*/
	854
	855	#ifdef __cplusplus
	856	}
	857	#endif
	858
	859	#endif /* __STM32F0xx_LL_BUS_H */
	860
	861	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/