F030C8T6_Kbus_MIX.git

move some define from Kbus.h to KBusDefine.h

QuakeGod

2024-02-25 95322c84888cbe2e92024d4d65698f59b016cb52

提交 \| 用户 \| age
483170	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_hal_rcc_ex.h
	4	* @author MCD Application Team
	5	* @brief Header file of RCC HAL Extension module.
	6	******************************************************************************
	7	* @attention
	8	*
	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	10	*
	11	* Redistribution and use in source and binary forms, with or without modification,
	12	* are permitted provided that the following conditions are met:
	13	* 1. Redistributions of source code must retain the above copyright notice,
	14	* this list of conditions and the following disclaimer.
	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	19	* may be used to endorse or promote products derived from this software
	20	* without specific prior written permission.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	******************************************************************************
	34	*/
	35
	36	/* Define to prevent recursive inclusion -------------------------------------*/
	37	#ifndef __STM32F0xx_HAL_RCC_EX_H
	38	#define __STM32F0xx_HAL_RCC_EX_H
	39
	40	#ifdef __cplusplus
	41	extern "C" {
	42	#endif
	43
	44	/* Includes ------------------------------------------------------------------*/
	45	#include "stm32f0xx_hal_def.h"
	46
	47	/** @addtogroup STM32F0xx_HAL_Driver
	48	* @{
	49	*/
	50
	51	/** @addtogroup RCC
	52	* @{
	53	*/
	54
	55	/** @addtogroup RCC_Private_Macros
	56	* @{
	57	*/
	58	#if defined(RCC_HSI48_SUPPORT)
	59	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
	60	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
	61	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
	62	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
	63	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
	64	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) \|\| \
	65	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
	66
	67	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
	68	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
	69	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
	70	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
	71
	72	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
	73	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
	74	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
	75	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
	76
	77	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
	78	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
	79	((SOURCE) == RCC_PLLSOURCE_HSE))
	80
	81	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
	82
	83	#else
	84
	85	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
	86	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
	87	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
	88	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
	89	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
	90	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
	91	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
	92	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
	93	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
	94
	95	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
	96	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
	97	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
	98	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
	99	((SOURCE) == RCC_PLLSOURCE_HSE))
	100
	101	#endif /* RCC_HSI48_SUPPORT */
	102
	103	#if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
	104
	105	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
	106	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| \
	107	((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
	108	((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
	109	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| \
	110	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| \
	111	((SOURCE) == RCC_MCO1SOURCE_PLLCLK) \|\| \
	112	((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) \|\| \
	113	((SOURCE) == RCC_MCO1SOURCE_HSI14))
	114
	115	#elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48)
	116
	117	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
	118	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| \
	119	((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
	120	((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
	121	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| \
	122	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| \
	123	((SOURCE) == RCC_MCO1SOURCE_PLLCLK) \|\| \
	124	((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) \|\| \
	125	((SOURCE) == RCC_MCO1SOURCE_HSI14) \|\| \
	126	((SOURCE) == RCC_MCO1SOURCE_HSI48))
	127
	128	#elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
	129
	130	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
	131	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| \
	132	((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
	133	((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
	134	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| \
	135	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| \
	136	((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) \|\| \
	137	((SOURCE) == RCC_MCO1SOURCE_HSI14))
	138
	139	#endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */
	140
	141	/**
	142	* @}
	143	*/
	144
	145	/** @addtogroup RCC_Exported_Constants
	146	* @{
	147	*/
	148	#if defined(RCC_HSI48_SUPPORT)
	149
	150	/** @addtogroup RCC_PLL_Clock_Source
	151	* @{
	152	*/
	153	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
	154	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
	155
	156	/**
	157	* @}
	158	*/
	159
	160	/** @addtogroup RCC_Interrupt
	161	* @{
	162	*/
	163	#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
	164	/**
	165	* @}
	166	*/
	167
	168	/** @addtogroup RCC_Flag
	169	* @{
	170	*/
	171	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) \| RCC_CR2_HSI48RDY_BitNumber))
	172	/**
	173	* @}
	174	*/
	175
	176	/** @addtogroup RCC_System_Clock_Source
	177	* @{
	178	*/
	179	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
	180	/**
	181	* @}
	182	*/
	183
	184	/** @addtogroup RCC_System_Clock_Source_Status
	185	* @{
	186	*/
	187	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
	188	/**
	189	* @}
	190	*/
	191
	192	#else
	193	/** @addtogroup RCC_PLL_Clock_Source
	194	* @{
	195	*/
	196
	197	#if defined(STM32F070xB) \|\| defined(STM32F070x6) \|\| defined(STM32F030xC)
	198	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
	199	#else
	200	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
	201	#endif
	202
	203	/**
	204	* @}
	205	*/
	206
	207	#endif /* RCC_HSI48_SUPPORT */
	208
	209	/** @addtogroup RCC_MCO_Clock_Source
	210	* @{
	211	*/
	212
	213	#if defined(RCC_CFGR_PLLNODIV)
	214
	215	#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
	216
	217	#endif /* RCC_CFGR_PLLNODIV */
	218
	219	#if defined(RCC_CFGR_MCO_HSI48)
	220
	221	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
	222
	223	#endif /* SRCC_CFGR_MCO_HSI48 */
	224	/**
	225	* @}
	226	*/
	227
	228	/**
	229	* @}
	230	*/
	231
	232	/**
	233	* @}
	234	*/
	235
	236	/** @addtogroup RCCEx
	237	* @{
	238	*/
	239
	240	/* Private Constants -------------------------------------------------------------*/
	241	#if defined(CRS)
	242	/** @addtogroup RCCEx_Private_Constants
	243	* @{
	244	*/
	245
	246	/* CRS IT Error Mask */
	247	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
	248
	249	/* CRS Flag Error Mask */
	250	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
	251
	252	/**
	253	* @}
	254	*/
	255	#endif /* CRS */
	256
	257	/* Private macro -------------------------------------------------------------*/
	258	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
	259	* @{
	260	*/
	261	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
	262	\|\| defined(STM32F030xC)
	263
	264	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
	265	RCC_PERIPHCLK_RTC))
	266	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
	267	STM32F030xC */
	268
	269	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
	270
	271	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
	272	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
	273	#endif /* STM32F070x6 \|\| STM32F070xB */
	274
	275	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
	276
	277	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
	278	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
	279	RCC_PERIPHCLK_USB))
	280	#endif /* STM32F042x6 \|\| STM32F048xx */
	281
	282	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
	283
	284	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
	285	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
	286	#endif /* STM32F051x8 \|\| STM32F058xx */
	287
	288	#if defined(STM32F071xB)
	289
	290	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
	291	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
	292	RCC_PERIPHCLK_RTC))
	293	#endif /* STM32F071xB */
	294
	295	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
	296
	297	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
	298	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
	299	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
	300	#endif /* STM32F072xB \|\| STM32F078xx */
	301
	302	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
	303
	304	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
	305	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
	306	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
	307	#endif /* STM32F091xC \|\| STM32F098xx */
	308
	309	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
	310
	311	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
	312	((SOURCE) == RCC_USBCLKSOURCE_PLL))
	313
	314	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
	315
	316	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
	317
	318	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) \|\| \
	319	((SOURCE) == RCC_USBCLKSOURCE_PLL))
	320
	321	#endif /* STM32F070x6 \|\| STM32F070xB */
	322
	323	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	324	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	325
	326	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
	327	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
	328	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
	329	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
	330
	331	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	332	/* STM32F091xC \|\| STM32F098xx */
	333
	334	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
	335
	336	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
	337	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
	338	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
	339	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
	340	#endif /* STM32F091xC \|\| STM32F098xx */
	341
	342
	343	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
	344	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	345	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	346	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	347
	348	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
	349	((SOURCE) == RCC_CECCLKSOURCE_LSE))
	350	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
	351	/* STM32F051x8 \|\| STM32F058xx \|\| */
	352	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	353	/* STM32F091xC \|\| STM32F098xx */
	354
	355	#if defined(RCC_CFGR_MCOPRE)
	356
	357	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
	358	((DIV) == RCC_MCODIV_4) \|\| ((DIV) == RCC_MCODIV_8) \|\| \
	359	((DIV) == RCC_MCODIV_16) \|\| ((DIV) == RCC_MCODIV_32) \|\| \
	360	((DIV) == RCC_MCODIV_64) \|\| ((DIV) == RCC_MCODIV_128))
	361	#else
	362
	363	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
	364
	365	#endif /* RCC_CFGR_MCOPRE */
	366
	367	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| \
	368	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
	369	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
	370	((__DRIVE__) == RCC_LSEDRIVE_HIGH))
	371
	372	#if defined(CRS)
	373
	374	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
	375	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
	376	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
	377	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
	378	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
	379	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
	380	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
	381	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
	382	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
	383	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU))
	384	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU))
	385	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU))
	386	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
	387	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
	388	#endif /* CRS */
	389	/**
	390	* @}
	391	*/
	392
	393	/* Exported types ------------------------------------------------------------*/
	394
	395	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
	396	* @{
	397	*/
	398
	399	/**
	400	* @brief RCC extended clocks structure definition
	401	*/
	402	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
	403	\|\| defined(STM32F030xC)
	404	typedef struct
	405	{
	406	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
	407	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
	408
	409	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
	410	This parameter can be a value of @ref RCC_RTC_Clock_Source */
	411
	412	uint32_t Usart1ClockSelection; /*!< USART1 clock source
	413	This parameter can be a value of @ref RCC_USART1_Clock_Source */
	414
	415	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
	416	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
	417
	418	}RCC_PeriphCLKInitTypeDef;
	419	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
	420	STM32F030xC */
	421
	422	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
	423	typedef struct
	424	{
	425	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
	426	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
	427
	428	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
	429	This parameter can be a value of @ref RCC_RTC_Clock_Source */
	430
	431	uint32_t Usart1ClockSelection; /*!< USART1 clock source
	432	This parameter can be a value of @ref RCC_USART1_Clock_Source */
	433
	434	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
	435	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
	436
	437	uint32_t UsbClockSelection; /*!< USB clock source
	438	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
	439
	440	}RCC_PeriphCLKInitTypeDef;
	441	#endif /* STM32F070x6 \|\| STM32F070xB */
	442
	443	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
	444	typedef struct
	445	{
	446	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
	447	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
	448
	449	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
	450	This parameter can be a value of @ref RCC_RTC_Clock_Source */
	451
	452	uint32_t Usart1ClockSelection; /*!< USART1 clock source
	453	This parameter can be a value of @ref RCC_USART1_Clock_Source */
	454
	455	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
	456	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
	457
	458	uint32_t CecClockSelection; /*!< HDMI CEC clock source
	459	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
	460
	461	uint32_t UsbClockSelection; /*!< USB clock source
	462	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
	463
	464	}RCC_PeriphCLKInitTypeDef;
	465	#endif /* STM32F042x6 \|\| STM32F048xx */
	466
	467	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
	468	typedef struct
	469	{
	470	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
	471	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
	472
	473	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
	474	This parameter can be a value of @ref RCC_RTC_Clock_Source */
	475
	476	uint32_t Usart1ClockSelection; /*!< USART1 clock source
	477	This parameter can be a value of @ref RCC_USART1_Clock_Source */
	478
	479	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
	480	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
	481
	482	uint32_t CecClockSelection; /*!< HDMI CEC clock source
	483	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
	484
	485	}RCC_PeriphCLKInitTypeDef;
	486	#endif /* STM32F051x8 \|\| STM32F058xx */
	487
	488	#if defined(STM32F071xB)
	489	typedef struct
	490	{
	491	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
	492	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
	493
	494	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
	495	This parameter can be a value of @ref RCC_RTC_Clock_Source */
	496
	497	uint32_t Usart1ClockSelection; /*!< USART1 clock source
	498	This parameter can be a value of @ref RCC_USART1_Clock_Source */
	499
	500	uint32_t Usart2ClockSelection; /*!< USART2 clock source
	501	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
	502
	503	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
	504	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
	505
	506	uint32_t CecClockSelection; /*!< HDMI CEC clock source
	507	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
	508
	509	}RCC_PeriphCLKInitTypeDef;
	510	#endif /* STM32F071xB */
	511
	512	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
	513	typedef struct
	514	{
	515	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
	516	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
	517
	518	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
	519	This parameter can be a value of @ref RCC_RTC_Clock_Source */
	520
	521	uint32_t Usart1ClockSelection; /*!< USART1 clock source
	522	This parameter can be a value of @ref RCC_USART1_Clock_Source */
	523
	524	uint32_t Usart2ClockSelection; /*!< USART2 clock source
	525	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
	526
	527	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
	528	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
	529
	530	uint32_t CecClockSelection; /*!< HDMI CEC clock source
	531	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
	532
	533	uint32_t UsbClockSelection; /*!< USB clock source
	534	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
	535
	536	}RCC_PeriphCLKInitTypeDef;
	537	#endif /* STM32F072xB \|\| STM32F078xx */
	538
	539
	540	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
	541	typedef struct
	542	{
	543	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
	544	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
	545
	546	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
	547	This parameter can be a value of @ref RCC_RTC_Clock_Source */
	548
	549	uint32_t Usart1ClockSelection; /*!< USART1 clock source
	550	This parameter can be a value of @ref RCC_USART1_Clock_Source */
	551
	552	uint32_t Usart2ClockSelection; /*!< USART2 clock source
	553	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
	554
	555	uint32_t Usart3ClockSelection; /*!< USART3 clock source
	556	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
	557
	558	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
	559	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
	560
	561	uint32_t CecClockSelection; /*!< HDMI CEC clock source
	562	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
	563
	564	}RCC_PeriphCLKInitTypeDef;
	565	#endif /* STM32F091xC \|\| STM32F098xx */
	566
	567	#if defined(CRS)
	568
	569	/**
	570	* @brief RCC_CRS Init structure definition
	571	*/
	572	typedef struct
	573	{
	574	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
	575	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
	576
	577	uint32_t Source; /*!< Specifies the SYNC signal source.
	578	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
	579
	580	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
	581	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
	582
	583	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
	584	It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
	585	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
	586
	587	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
	588	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
	589
	590	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
	591	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
	592
	593	}RCC_CRSInitTypeDef;
	594
	595	/**
	596	* @brief RCC_CRS Synchronization structure definition
	597	*/
	598	typedef struct
	599	{
	600	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
	601	This parameter must be a number between 0 and 0xFFFFU */
	602
	603	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
	604	This parameter must be a number between 0 and 0x3FU */
	605
	606	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
	607	value latched in the time of the last SYNC event.
	608	This parameter must be a number between 0 and 0xFFFFU */
	609
	610	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
	611	frequency error counter latched in the time of the last SYNC event.
	612	It shows whether the actual frequency is below or above the target.
	613	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
	614
	615	}RCC_CRSSynchroInfoTypeDef;
	616
	617	#endif /* CRS */
	618
	619	/**
	620	* @}
	621	*/
	622
	623	/* Exported constants --------------------------------------------------------*/
	624
	625	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
	626	* @{
	627	*/
	628
	629	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
	630	* @{
	631	*/
	632	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
	633	\|\| defined(STM32F030xC)
	634	#define RCC_PERIPHCLK_USART1 (0x00000001U)
	635	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
	636	#define RCC_PERIPHCLK_RTC (0x00010000U)
	637
	638	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
	639	STM32F030xC */
	640
	641	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
	642	#define RCC_PERIPHCLK_USART1 (0x00000001U)
	643	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
	644	#define RCC_PERIPHCLK_RTC (0x00010000U)
	645	#define RCC_PERIPHCLK_USB (0x00020000U)
	646
	647	#endif /* STM32F070x6 \|\| STM32F070xB */
	648
	649	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
	650	#define RCC_PERIPHCLK_USART1 (0x00000001U)
	651	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
	652	#define RCC_PERIPHCLK_CEC (0x00000400U)
	653	#define RCC_PERIPHCLK_RTC (0x00010000U)
	654	#define RCC_PERIPHCLK_USB (0x00020000U)
	655
	656	#endif /* STM32F042x6 \|\| STM32F048xx */
	657
	658	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
	659	#define RCC_PERIPHCLK_USART1 (0x00000001U)
	660	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
	661	#define RCC_PERIPHCLK_CEC (0x00000400U)
	662	#define RCC_PERIPHCLK_RTC (0x00010000U)
	663
	664	#endif /* STM32F051x8 \|\| STM32F058xx */
	665
	666	#if defined(STM32F071xB)
	667	#define RCC_PERIPHCLK_USART1 (0x00000001U)
	668	#define RCC_PERIPHCLK_USART2 (0x00000002U)
	669	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
	670	#define RCC_PERIPHCLK_CEC (0x00000400U)
	671	#define RCC_PERIPHCLK_RTC (0x00010000U)
	672
	673	#endif /* STM32F071xB */
	674
	675	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
	676	#define RCC_PERIPHCLK_USART1 (0x00000001U)
	677	#define RCC_PERIPHCLK_USART2 (0x00000002U)
	678	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
	679	#define RCC_PERIPHCLK_CEC (0x00000400U)
	680	#define RCC_PERIPHCLK_RTC (0x00010000U)
	681	#define RCC_PERIPHCLK_USB (0x00020000U)
	682
	683	#endif /* STM32F072xB \|\| STM32F078xx */
	684
	685	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
	686	#define RCC_PERIPHCLK_USART1 (0x00000001U)
	687	#define RCC_PERIPHCLK_USART2 (0x00000002U)
	688	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
	689	#define RCC_PERIPHCLK_CEC (0x00000400U)
	690	#define RCC_PERIPHCLK_RTC (0x00010000U)
	691	#define RCC_PERIPHCLK_USART3 (0x00040000U)
	692
	693	#endif /* STM32F091xC \|\| STM32F098xx */
	694
	695	/**
	696	* @}
	697	*/
	698
	699	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
	700
	701	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
	702	* @{
	703	*/
	704	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /!< HSI48 clock selected as USB clock source /
	705	#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /!< PLL clock (PLLCLK) selected as USB clock /
	706
	707	/**
	708	* @}
	709	*/
	710
	711	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
	712
	713	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
	714
	715	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
	716	* @{
	717	*/
	718	#define RCC_USBCLKSOURCE_NONE (0x00000000U) /!< USB clock disabled /
	719	#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /!< PLL clock (PLLCLK) selected as USB clock /
	720
	721	/**
	722	* @}
	723	*/
	724
	725	#endif /* STM32F070x6 \|\| STM32F070xB */
	726
	727	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	728	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	729
	730	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
	731	* @{
	732	*/
	733	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
	734	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
	735	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
	736	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
	737
	738	/**
	739	* @}
	740	*/
	741
	742	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	743	/* STM32F091xC \|\| STM32F098xx */
	744
	745	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
	746
	747	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
	748	* @{
	749	*/
	750	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
	751	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
	752	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
	753	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
	754
	755	/**
	756	* @}
	757	*/
	758
	759	#endif /* STM32F091xC \|\| STM32F098xx */
	760
	761
	762	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
	763	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	764	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	765	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	766
	767	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
	768	* @{
	769	*/
	770	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
	771	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
	772
	773	/**
	774	* @}
	775	*/
	776
	777	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
	778	/* STM32F051x8 \|\| STM32F058xx \|\| */
	779	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	780	/* STM32F091xC \|\| STM32F098xx */
	781
	782	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
	783	* @{
	784	*/
	785
	786	#if defined(RCC_CFGR_MCOPRE)
	787
	788	#define RCC_MCODIV_1 (0x00000000U)
	789	#define RCC_MCODIV_2 (0x10000000U)
	790	#define RCC_MCODIV_4 (0x20000000U)
	791	#define RCC_MCODIV_8 (0x30000000U)
	792	#define RCC_MCODIV_16 (0x40000000U)
	793	#define RCC_MCODIV_32 (0x50000000U)
	794	#define RCC_MCODIV_64 (0x60000000U)
	795	#define RCC_MCODIV_128 (0x70000000U)
	796
	797	#else
	798
	799	#define RCC_MCODIV_1 (0x00000000U)
	800
	801	#endif /* RCC_CFGR_MCOPRE */
	802
	803	/**
	804	* @}
	805	*/
	806
	807	/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
	808	* @{
	809	*/
	810
	811	#define RCC_LSEDRIVE_LOW (0x00000000U) /!< Xtal mode lower driving capability /
	812	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /!< Xtal mode medium low driving capability /
	813	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /!< Xtal mode medium high driving capability /
	814	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
	815
	816	/**
	817	* @}
	818	*/
	819
	820	#if defined(CRS)
	821
	822	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
	823	* @{
	824	*/
	825	#define RCC_CRS_NONE (0x00000000U)
	826	#define RCC_CRS_TIMEOUT (0x00000001U)
	827	#define RCC_CRS_SYNCOK (0x00000002U)
	828	#define RCC_CRS_SYNCWARN (0x00000004U)
	829	#define RCC_CRS_SYNCERR (0x00000008U)
	830	#define RCC_CRS_SYNCMISS (0x00000010U)
	831	#define RCC_CRS_TRIMOVF (0x00000020U)
	832
	833	/**
	834	* @}
	835	*/
	836
	837	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source
	838	* @{
	839	*/
	840	#define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /!< Synchro Signal source GPIO /
	841	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
	842	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
	843	/**
	844	* @}
	845	*/
	846
	847	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider
	848	* @{
	849	*/
	850	#define RCC_CRS_SYNC_DIV1 (0x00000000U) /!< Synchro Signal not divided (default) /
	851	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
	852	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
	853	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
	854	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
	855	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
	856	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
	857	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
	858	/**
	859	* @}
	860	*/
	861
	862	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity
	863	* @{
	864	*/
	865	#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /!< Synchro Active on rising edge (default) /
	866	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
	867	/**
	868	* @}
	869	*/
	870
	871	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value
	872	* @{
	873	*/
	874	#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
	875	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
	876	/**
	877	* @}
	878	*/
	879
	880	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value
	881	* @{
	882	*/
	883	#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /!< Default Frequency error limit /
	884	/**
	885	* @}
	886	*/
	887
	888	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye
	889	* @{
	890	*/
	891	#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
	892	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
	893	corresponds to a higher output frequency */
	894	/**
	895	* @}
	896	*/
	897
	898	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction
	899	* @{
	900	*/
	901	#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /!< Upcounting direction, the actual frequency is above the target /
	902	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
	903	/**
	904	* @}
	905	*/
	906
	907	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
	908	* @{
	909	*/
	910	#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /!< SYNC event OK /
	911	#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /!< SYNC warning /
	912	#define RCC_CRS_IT_ERR CRS_CR_ERRIE /!< Error /
	913	#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /!< Expected SYNC /
	914	#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /!< SYNC error /
	915	#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /!< SYNC missed /
	916	#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /!< Trimming overflow or underflow /
	917
	918	/**
	919	* @}
	920	*/
	921
	922	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
	923	* @{
	924	*/
	925	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK flag /
	926	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning flag /
	927	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /!< Error flag /
	928	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC flag /
	929	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
	930	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
	931	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
	932
	933	/**
	934	* @}
	935	*/
	936
	937	#endif /* CRS */
	938
	939	/**
	940	* @}
	941	*/
	942
	943	/* Exported macros ------------------------------------------------------------*/
	944	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
	945	* @{
	946	*/
	947
	948	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
	949	* @brief Enables or disables the AHB1 peripheral clock.
	950	* @note After reset, the peripheral clock (used for registers read/write access)
	951	* is disabled and the application software has to enable this clock before
	952	* using it.
	953	* @{
	954	*/
	955	#if defined(GPIOD)
	956
	957	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
	958	__IO uint32_t tmpreg; \
	959	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
	960	/* Delay after an RCC peripheral clock enabling */ \
	961	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
	962	UNUSED(tmpreg); \
	963	} while(0U)
	964
	965	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
	966
	967	#endif /* GPIOD */
	968
	969	#if defined(GPIOE)
	970
	971	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
	972	__IO uint32_t tmpreg; \
	973	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
	974	/* Delay after an RCC peripheral clock enabling */ \
	975	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
	976	UNUSED(tmpreg); \
	977	} while(0U)
	978
	979	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
	980
	981	#endif /* GPIOE */
	982
	983	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
	984	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	985	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	986	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	987
	988	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
	989	__IO uint32_t tmpreg; \
	990	SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
	991	/* Delay after an RCC peripheral clock enabling */ \
	992	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
	993	UNUSED(tmpreg); \
	994	} while(0U)
	995
	996	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
	997
	998	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
	999	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1000	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1001	/* STM32F091xC \|\| STM32F098xx */
	1002
	1003	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
	1004
	1005	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
	1006	__IO uint32_t tmpreg; \
	1007	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
	1008	/* Delay after an RCC peripheral clock enabling */ \
	1009	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
	1010	UNUSED(tmpreg); \
	1011	} while(0U)
	1012
	1013	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
	1014
	1015	#endif /* STM32F091xC \|\| STM32F098xx */
	1016
	1017	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
	1018	* @note After reset, the peripheral clock (used for registers read/write access)
	1019	* is disabled and the application software has to enable this clock before
	1020	* using it.
	1021	*/
	1022	#if defined(STM32F030x8)\
	1023	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
	1024	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1025	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1026	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1027
	1028	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
	1029	__IO uint32_t tmpreg; \
	1030	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
	1031	/* Delay after an RCC peripheral clock enabling */ \
	1032	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
	1033	UNUSED(tmpreg); \
	1034	} while(0U)
	1035
	1036	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
	1037
	1038	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
	1039	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
	1040	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1041	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1042
	1043	#if defined(STM32F030x8)\
	1044	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1045	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1046	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1047	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1048
	1049	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
	1050	__IO uint32_t tmpreg; \
	1051	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
	1052	/* Delay after an RCC peripheral clock enabling */ \
	1053	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
	1054	UNUSED(tmpreg); \
	1055	} while(0U)
	1056
	1057	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
	1058
	1059	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
	1060	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1061	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1062	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1063
	1064	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
	1065	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1066	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1067	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1068	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1069
	1070	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
	1071	__IO uint32_t tmpreg; \
	1072	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
	1073	/* Delay after an RCC peripheral clock enabling */ \
	1074	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
	1075	UNUSED(tmpreg); \
	1076	} while(0U)
	1077
	1078	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
	1079
	1080	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
	1081	/* STM32F042x6 \|\| STM32F048xx \|\| */
	1082	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1083	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1084	/* STM32F091xC \|\| STM32F098xx */
	1085
	1086	#if defined(STM32F030x8) \
	1087	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1088	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1089	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1090
	1091	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
	1092	__IO uint32_t tmpreg; \
	1093	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
	1094	/* Delay after an RCC peripheral clock enabling */ \
	1095	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
	1096	UNUSED(tmpreg); \
	1097	} while(0U)
	1098	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
	1099	__IO uint32_t tmpreg; \
	1100	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
	1101	/* Delay after an RCC peripheral clock enabling */ \
	1102	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
	1103	UNUSED(tmpreg); \
	1104	} while(0U)
	1105
	1106	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
	1107	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
	1108
	1109	#endif /* STM32F030x8 \|\| */
	1110	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1111	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1112	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1113
	1114	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1115	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1116	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1117
	1118	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
	1119	__IO uint32_t tmpreg; \
	1120	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
	1121	/* Delay after an RCC peripheral clock enabling */ \
	1122	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
	1123	UNUSED(tmpreg); \
	1124	} while(0U)
	1125
	1126	#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
	1127
	1128	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
	1129	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1130	/* STM32F091xC \|\| STM32F098xx */
	1131
	1132	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1133	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1134	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1135	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1136
	1137	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
	1138	__IO uint32_t tmpreg; \
	1139	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
	1140	/* Delay after an RCC peripheral clock enabling */ \
	1141	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
	1142	UNUSED(tmpreg); \
	1143	} while(0U)
	1144
	1145	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
	1146
	1147	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
	1148	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1149	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1150	/* STM32F091xC \|\| STM32F098xx */
	1151
	1152	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1153	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1154
	1155	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
	1156	__IO uint32_t tmpreg; \
	1157	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
	1158	/* Delay after an RCC peripheral clock enabling */ \
	1159	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
	1160	UNUSED(tmpreg); \
	1161	} while(0U)
	1162	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
	1163	__IO uint32_t tmpreg; \
	1164	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
	1165	/* Delay after an RCC peripheral clock enabling */ \
	1166	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
	1167	UNUSED(tmpreg); \
	1168	} while(0U)
	1169	#define __HAL_RCC_USART4_CLK_ENABLE() do { \
	1170	__IO uint32_t tmpreg; \
	1171	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
	1172	/* Delay after an RCC peripheral clock enabling */ \
	1173	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
	1174	UNUSED(tmpreg); \
	1175	} while(0U)
	1176
	1177	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
	1178	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
	1179	#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
	1180
	1181	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1182	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1183
	1184	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
	1185	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
	1186
	1187	#define __HAL_RCC_USB_CLK_ENABLE() do { \
	1188	__IO uint32_t tmpreg; \
	1189	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
	1190	/* Delay after an RCC peripheral clock enabling */ \
	1191	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
	1192	UNUSED(tmpreg); \
	1193	} while(0U)
	1194
	1195	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
	1196
	1197	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
	1198	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
	1199
	1200	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
	1201	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1202
	1203	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
	1204	__IO uint32_t tmpreg; \
	1205	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
	1206	/* Delay after an RCC peripheral clock enabling */ \
	1207	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
	1208	UNUSED(tmpreg); \
	1209	} while(0U)
	1210	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
	1211
	1212	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
	1213	/* STM32F091xC \|\| STM32F098xx */
	1214
	1215	#if defined(CRS)
	1216
	1217	#define __HAL_RCC_CRS_CLK_ENABLE() do { \
	1218	__IO uint32_t tmpreg; \
	1219	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
	1220	/* Delay after an RCC peripheral clock enabling */ \
	1221	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
	1222	UNUSED(tmpreg); \
	1223	} while(0U)
	1224
	1225	#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
	1226
	1227	#endif /* CRS */
	1228
	1229	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1230
	1231	#define __HAL_RCC_USART5_CLK_ENABLE() do { \
	1232	__IO uint32_t tmpreg; \
	1233	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
	1234	/* Delay after an RCC peripheral clock enabling */ \
	1235	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
	1236	UNUSED(tmpreg); \
	1237	} while(0U)
	1238
	1239	#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
	1240
	1241	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1242
	1243	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
	1244	* @note After reset, the peripheral clock (used for registers read/write access)
	1245	* is disabled and the application software has to enable this clock before
	1246	* using it.
	1247	*/
	1248	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
	1249	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1250	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1251	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1252
	1253	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
	1254	__IO uint32_t tmpreg; \
	1255	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
	1256	/* Delay after an RCC peripheral clock enabling */ \
	1257	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
	1258	UNUSED(tmpreg); \
	1259	} while(0U)
	1260
	1261	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
	1262
	1263	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
	1264	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1265	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1266	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1267
	1268	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1269
	1270	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
	1271	__IO uint32_t tmpreg; \
	1272	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
	1273	/* Delay after an RCC peripheral clock enabling */ \
	1274	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
	1275	UNUSED(tmpreg); \
	1276	} while(0U)
	1277
	1278	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
	1279
	1280	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1281
	1282	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
	1283
	1284	#define __HAL_RCC_USART7_CLK_ENABLE() do { \
	1285	__IO uint32_t tmpreg; \
	1286	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
	1287	/* Delay after an RCC peripheral clock enabling */ \
	1288	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
	1289	UNUSED(tmpreg); \
	1290	} while(0U)
	1291	#define __HAL_RCC_USART8_CLK_ENABLE() do { \
	1292	__IO uint32_t tmpreg; \
	1293	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
	1294	/* Delay after an RCC peripheral clock enabling */ \
	1295	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
	1296	UNUSED(tmpreg); \
	1297	} while(0U)
	1298
	1299	#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
	1300	#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
	1301
	1302	#endif /* STM32F091xC \|\| STM32F098xx */
	1303
	1304	/**
	1305	* @}
	1306	*/
	1307
	1308
	1309	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
	1310	* @brief Forces or releases peripheral reset.
	1311	* @{
	1312	*/
	1313
	1314	/** @brief Force or release AHB peripheral reset.
	1315	*/
	1316	#if defined(GPIOD)
	1317
	1318	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
	1319
	1320	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
	1321
	1322	#endif /* GPIOD */
	1323
	1324	#if defined(GPIOE)
	1325
	1326	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
	1327
	1328	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
	1329
	1330	#endif /* GPIOE */
	1331
	1332	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1333	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1334	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1335	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1336
	1337	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
	1338
	1339	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
	1340
	1341	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
	1342	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1343	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1344	/* STM32F091xC \|\| STM32F098xx */
	1345
	1346	/** @brief Force or release APB1 peripheral reset.
	1347	*/
	1348	#if defined(STM32F030x8) \
	1349	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
	1350	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1351	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1352	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1353
	1354	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
	1355	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
	1356
	1357	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
	1358	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
	1359
	1360	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
	1361	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1362	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1363	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1364
	1365	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
	1366	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1367	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1368	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1369	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1370
	1371	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
	1372
	1373	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
	1374
	1375	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
	1376	/* STM32F042x6 \|\| STM32F048xx \|\| */
	1377	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1378	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1379	/* STM32F091xC \|\| STM32F098xx */
	1380
	1381	#if defined(STM32F030x8) \
	1382	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1383	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1384	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1385
	1386	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
	1387	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
	1388
	1389	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
	1390	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
	1391
	1392	#endif /* STM32F030x8 \|\| */
	1393	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1394	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1395	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1396
	1397	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1398	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1399	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1400
	1401	#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
	1402
	1403	#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
	1404
	1405	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
	1406	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1407	/* STM32F091xC \|\| STM32F098xx */
	1408
	1409	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1410	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1411	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1412	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1413
	1414	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
	1415
	1416	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
	1417
	1418	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
	1419	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1420	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1421	/* STM32F091xC \|\| STM32F098xx */
	1422
	1423	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1424	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1425
	1426	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
	1427	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
	1428	#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
	1429
	1430	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
	1431	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
	1432	#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
	1433
	1434	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1435	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1436
	1437	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
	1438	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
	1439
	1440	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
	1441
	1442	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
	1443
	1444	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
	1445	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
	1446
	1447	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
	1448	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1449
	1450	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
	1451
	1452	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
	1453
	1454	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
	1455	/* STM32F091xC \|\| STM32F098xx */
	1456
	1457	#if defined(CRS)
	1458
	1459	#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
	1460
	1461	#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
	1462
	1463	#endif /* CRS */
	1464
	1465	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1466
	1467	#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
	1468
	1469	#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
	1470
	1471	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1472
	1473
	1474	/** @brief Force or release APB2 peripheral reset.
	1475	*/
	1476	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
	1477	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1478	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1479	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1480
	1481	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
	1482
	1483	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
	1484
	1485	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
	1486	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1487	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1488	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1489
	1490	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1491
	1492	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
	1493
	1494	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
	1495
	1496	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1497
	1498	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
	1499
	1500	#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
	1501	#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
	1502
	1503	#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
	1504	#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
	1505
	1506	#endif /* STM32F091xC \|\| STM32F098xx */
	1507
	1508	/**
	1509	* @}
	1510	*/
	1511
	1512	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
	1513	* @brief Get the enable or disable status of peripheral clock.
	1514	* @note After reset, the peripheral clock (used for registers read/write access)
	1515	* is disabled and the application software has to enable this clock before
	1516	* using it.
	1517	* @{
	1518	*/
	1519	/** @brief AHB Peripheral Clock Enable Disable Status
	1520	*/
	1521	#if defined(GPIOD)
	1522
	1523	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
	1524	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
	1525
	1526	#endif /* GPIOD */
	1527
	1528	#if defined(GPIOE)
	1529
	1530	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
	1531	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
	1532
	1533	#endif /* GPIOE */
	1534
	1535	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1536	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1537	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1538	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1539
	1540	#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
	1541	#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
	1542
	1543	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
	1544	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1545	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1546	/* STM32F091xC \|\| STM32F098xx */
	1547
	1548	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
	1549
	1550	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
	1551	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
	1552
	1553	#endif /* STM32F091xC \|\| STM32F098xx */
	1554
	1555	/** @brief APB1 Peripheral Clock Enable Disable Status
	1556	*/
	1557	#if defined(STM32F030x8)\
	1558	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
	1559	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1560	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1561	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1562
	1563	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
	1564	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
	1565
	1566	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
	1567	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
	1568	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1569	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1570
	1571	#if defined(STM32F030x8)\
	1572	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1573	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1574	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1575	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1576
	1577	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
	1578	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
	1579
	1580	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
	1581	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1582	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1583	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1584
	1585	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
	1586	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1587	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1588	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1589	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1590
	1591	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
	1592	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
	1593
	1594	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
	1595	/* STM32F042x6 \|\| STM32F048xx \|\| */
	1596	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1597	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1598	/* STM32F091xC \|\| STM32F098xx */
	1599
	1600	#if defined(STM32F030x8) \
	1601	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1602	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1603	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1604
	1605	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
	1606	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
	1607	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
	1608	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
	1609
	1610	#endif /* STM32F030x8 \|\| */
	1611	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1612	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1613	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1614
	1615	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1616	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1617	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1618
	1619	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
	1620	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
	1621
	1622	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
	1623	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1624	/* STM32F091xC \|\| STM32F098xx */
	1625
	1626	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1627	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1628	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1629	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1630
	1631	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
	1632	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
	1633
	1634	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
	1635	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1636	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1637	/* STM32F091xC \|\| STM32F098xx */
	1638
	1639	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1640	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1641
	1642	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
	1643	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
	1644	#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET)
	1645	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
	1646	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
	1647	#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET)
	1648
	1649	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1650	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1651
	1652	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
	1653	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
	1654
	1655	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
	1656	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
	1657
	1658	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
	1659	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
	1660
	1661	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
	1662	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1663
	1664	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
	1665	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
	1666
	1667	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
	1668	/* STM32F091xC \|\| STM32F098xx */
	1669
	1670	#if defined(CRS)
	1671
	1672	#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
	1673	#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
	1674
	1675	#endif /* CRS */
	1676
	1677	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1678
	1679	#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET)
	1680	#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET)
	1681
	1682	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1683
	1684	/** @brief APB1 Peripheral Clock Enable Disable Status
	1685	*/
	1686	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
	1687	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1688	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
	1689	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1690
	1691	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
	1692	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
	1693
	1694	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
	1695	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1696	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
	1697	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1698
	1699	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
	1700
	1701	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
	1702	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
	1703
	1704	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
	1705
	1706	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
	1707
	1708	#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET)
	1709	#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET)
	1710	#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET)
	1711	#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET)
	1712
	1713	#endif /* STM32F091xC \|\| STM32F098xx */
	1714	/**
	1715	* @}
	1716	*/
	1717
	1718
	1719	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
	1720	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
	1721	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
	1722	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
	1723	* you have to select another source of the system clock then stop the HSI14.
	1724	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
	1725	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
	1726	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
	1727	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
	1728	* clock cycles.
	1729	* @{
	1730	*/
	1731	#if defined(RCC_HSI48_SUPPORT)
	1732
	1733	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
	1734	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
	1735
	1736	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
	1737	* @retval The clock source can be one of the following values:
	1738	* @arg @ref RCC_HSI48_ON HSI48 enabled
	1739	* @arg @ref RCC_HSI48_OFF HSI48 disabled
	1740	*/
	1741	#define __HAL_RCC_GET_HSI48_STATE() \
	1742	(((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
	1743
	1744	#endif /* RCC_HSI48_SUPPORT */
	1745
	1746	/**
	1747	* @}
	1748	*/
	1749
	1750	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
	1751	* @{
	1752	*/
	1753	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1754	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1755	\|\| defined(STM32F070x6) \|\| defined(STM32F070xB)
	1756
	1757	/** @brief Macro to configure the USB clock (USBCLK).
	1758	* @param __USBCLKSOURCE__ specifies the USB clock source.
	1759	* This parameter can be one of the following values:
	1760	@if STM32F070xB
	1761	@elseif STM32F070x6
	1762	@else
	1763	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
	1764	@endif
	1765	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
	1766	*/
	1767	#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
	1768	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__))
	1769
	1770	/** @brief Macro to get the USB clock source.
	1771	* @retval The clock source can be one of the following values:
	1772	@if STM32F070xB
	1773	@elseif STM32F070x6
	1774	@else
	1775	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
	1776	@endif
	1777	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
	1778	*/
	1779	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
	1780
	1781	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
	1782	/* STM32F072xB \|\| STM32F078xx \|\| */
	1783	/* STM32F070x6 \|\| STM32F070xB */
	1784
	1785	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
	1786	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
	1787	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1788	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1789
	1790	/** @brief Macro to configure the CEC clock.
	1791	* @param __CECCLKSOURCE__ specifies the CEC clock source.
	1792	* This parameter can be one of the following values:
	1793	* @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
	1794	* @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
	1795	*/
	1796	#define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \
	1797	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__))
	1798
	1799	/** @brief Macro to get the HDMI CEC clock source.
	1800	* @retval The clock source can be one of the following values:
	1801	* @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
	1802	* @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
	1803	*/
	1804	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
	1805
	1806	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
	1807	/* STM32F051x8 \|\| STM32F058xx \|\| */
	1808	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
	1809	/* STM32F091xC \|\| defined(STM32F098xx) */
	1810
	1811	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
	1812	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
	1813	/** @brief Macro to configure the USART2 clock (USART2CLK).
	1814	* @param __USART2CLKSOURCE__ specifies the USART2 clock source.
	1815	* This parameter can be one of the following values:
	1816	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
	1817	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
	1818	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
	1819	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
	1820	*/
	1821	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
	1822	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
	1823
	1824	/** @brief Macro to get the USART2 clock source.
	1825	* @retval The clock source can be one of the following values:
	1826	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
	1827	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
	1828	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
	1829	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
	1830	*/
	1831	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
	1832	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx*/
	1833
	1834	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
	1835	/** @brief Macro to configure the USART3 clock (USART3CLK).
	1836	* @param __USART3CLKSOURCE__ specifies the USART3 clock source.
	1837	* This parameter can be one of the following values:
	1838	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
	1839	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
	1840	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
	1841	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
	1842	*/
	1843	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
	1844	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
	1845
	1846	/** @brief Macro to get the USART3 clock source.
	1847	* @retval The clock source can be one of the following values:
	1848	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
	1849	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
	1850	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
	1851	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
	1852	*/
	1853	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
	1854
	1855	#endif /* STM32F091xC \|\| STM32F098xx */
	1856	/**
	1857	* @}
	1858	*/
	1859
	1860	/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
	1861	* @{
	1862	*/
	1863
	1864	/**
	1865	* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
	1866	* @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
	1867	* This parameter can be one of the following values:
	1868	* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
	1869	* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
	1870	* @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
	1871	* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
	1872	* @retval None
	1873	*/
	1874	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
	1875	RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
	1876
	1877	/**
	1878	* @}
	1879	*/
	1880
	1881	#if defined(CRS)
	1882
	1883	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
	1884	* @{
	1885	*/
	1886	/* Interrupt & Flag management */
	1887
	1888	/**
	1889	* @brief Enable the specified CRS interrupts.
	1890	* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
	1891	* This parameter can be any combination of the following values:
	1892	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
	1893	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
	1894	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
	1895	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
	1896	* @retval None
	1897	*/
	1898	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
	1899
	1900	/**
	1901	* @brief Disable the specified CRS interrupts.
	1902	* @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
	1903	* This parameter can be any combination of the following values:
	1904	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
	1905	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
	1906	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
	1907	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
	1908	* @retval None
	1909	*/
	1910	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
	1911
	1912	/** @brief Check whether the CRS interrupt has occurred or not.
	1913	* @param __INTERRUPT__ specifies the CRS interrupt source to check.
	1914	* This parameter can be one of the following values:
	1915	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
	1916	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
	1917	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
	1918	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
	1919	* @retval The new state of __INTERRUPT__ (SET or RESET).
	1920	*/
	1921	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
	1922
	1923	/** @brief Clear the CRS interrupt pending bits
	1924	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
	1925	* This parameter can be any combination of the following values:
	1926	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
	1927	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
	1928	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
	1929	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
	1930	* @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
	1931	* @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
	1932	* @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
	1933	*/
	1934	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
	1935	if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
	1936	{ \
	1937	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
	1938	} \
	1939	else \
	1940	{ \
	1941	WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
	1942	} \
	1943	} while(0U)
	1944
	1945	/**
	1946	* @brief Check whether the specified CRS flag is set or not.
	1947	* @param __FLAG__ specifies the flag to check.
	1948	* This parameter can be one of the following values:
	1949	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
	1950	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
	1951	* @arg @ref RCC_CRS_FLAG_ERR Error
	1952	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
	1953	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
	1954	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
	1955	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
	1956	* @retval The new state of _FLAG_ (TRUE or FALSE).
	1957	*/
	1958	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
	1959
	1960	/**
	1961	* @brief Clear the CRS specified FLAG.
	1962	* @param __FLAG__ specifies the flag to clear.
	1963	* This parameter can be one of the following values:
	1964	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
	1965	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
	1966	* @arg @ref RCC_CRS_FLAG_ERR Error
	1967	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
	1968	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
	1969	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
	1970	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
	1971	* @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
	1972	* @retval None
	1973	*/
	1974	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
	1975	if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
	1976	{ \
	1977	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
	1978	} \
	1979	else \
	1980	{ \
	1981	WRITE_REG(CRS->ICR, (__FLAG__)); \
	1982	} \
	1983	} while(0U)
	1984
	1985	/**
	1986	* @}
	1987	*/
	1988
	1989	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
	1990	* @{
	1991	*/
	1992	/**
	1993	* @brief Enable the oscillator clock for frequency error counter.
	1994	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
	1995	* @retval None
	1996	*/
	1997	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
	1998
	1999	/**
	2000	* @brief Disable the oscillator clock for frequency error counter.
	2001	* @retval None
	2002	*/
	2003	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
	2004
	2005	/**
	2006	* @brief Enable the automatic hardware adjustement of TRIM bits.
	2007	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
	2008	* @retval None
	2009	*/
	2010	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
	2011
	2012	/**
	2013	* @brief Disable the automatic hardware adjustement of TRIM bits.
	2014	* @retval None
	2015	*/
	2016	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
	2017
	2018	/**
	2019	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
	2020	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
	2021	* of the synchronization source after prescaling. It is then decreased by one in order to
	2022	* reach the expected synchronization on the zero value. The formula is the following:
	2023	* RELOAD = (fTARGET / fSYNC) -1
	2024	* @param __FTARGET__ Target frequency (value in Hz)
	2025	* @param __FSYNC__ Synchronization signal frequency (value in Hz)
	2026	* @retval None
	2027	*/
	2028	#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
	2029
	2030	/**
	2031	* @}
	2032	*/
	2033
	2034	#endif /* CRS */
	2035
	2036	/**
	2037	* @}
	2038	*/
	2039
	2040	/* Exported functions --------------------------------------------------------*/
	2041	/** @addtogroup RCCEx_Exported_Functions
	2042	* @{
	2043	*/
	2044
	2045	/** @addtogroup RCCEx_Exported_Functions_Group1
	2046	* @{
	2047	*/
	2048
	2049	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
	2050	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
	2051	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
	2052
	2053	/**
	2054	* @}
	2055	*/
	2056
	2057	#if defined(CRS)
	2058
	2059	/** @addtogroup RCCEx_Exported_Functions_Group3
	2060	* @{
	2061	*/
	2062
	2063	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
	2064	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
	2065	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
	2066	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
	2067	void HAL_RCCEx_CRS_IRQHandler(void);
	2068	void HAL_RCCEx_CRS_SyncOkCallback(void);
	2069	void HAL_RCCEx_CRS_SyncWarnCallback(void);
	2070	void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
	2071	void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
	2072
	2073	/**
	2074	* @}
	2075	*/
	2076
	2077	#endif /* CRS */
	2078
	2079	/**
	2080	* @}
	2081	*/
	2082
	2083	/**
	2084	* @}
	2085	*/
	2086
	2087	/**
	2088	* @}
	2089	*/
	2090
	2091	/**
	2092	* @}
	2093	*/
	2094
	2095	#ifdef __cplusplus
	2096	}
	2097	#endif
	2098
	2099	#endif /* __STM32F0xx_HAL_RCC_EX_H */
	2100
	2101	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/