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2024-02-24 8b51c78f1b88d94a89bb8c37ae38a54f523cb597

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8b51c7	1	/**
Q	2	******************************************************************************
	3	* @file stm32f051x8.h
	4	* @author MCD Application Team
	5	* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
	6	* This file contains all the peripheral register's definitions, bits
	7	* definitions and memory mapping for STM32F0xx devices.
	8	*
	9	* This file contains:
	10	* - Data structures and the address mapping for all peripherals
	11	* - Peripheral's registers declarations and bits definition
	12	* - Macros to access peripheral抯 registers hardware
	13	*
	14	******************************************************************************
	15	* @attention
	16	*
	17	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	18	*
	19	* Redistribution and use in source and binary forms, with or without modification,
	20	* are permitted provided that the following conditions are met:
	21	* 1. Redistributions of source code must retain the above copyright notice,
	22	* this list of conditions and the following disclaimer.
	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
	24	* this list of conditions and the following disclaimer in the documentation
	25	* and/or other materials provided with the distribution.
	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	27	* may be used to endorse or promote products derived from this software
	28	* without specific prior written permission.
	29	*
	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	40	*
	41	******************************************************************************
	42	*/
	43
	44	/** @addtogroup CMSIS
	45	* @{
	46	*/
	47
	48	/** @addtogroup stm32f051x8
	49	* @{
	50	*/
	51
	52	#ifndef __STM32F051x8_H
	53	#define __STM32F051x8_H
	54
	55	#ifdef __cplusplus
	56	extern "C" {
	57	#endif /* __cplusplus */
	58
	59	/** @addtogroup Configuration_section_for_CMSIS
	60	* @{
	61	*/
	62	/**
	63	* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
	64	*/
	65	#define __CM0_REV 0 /!< Core Revision r0p0 /
	66	#define __MPU_PRESENT 0 /!< STM32F0xx do not provide MPU /
	67	#define __NVIC_PRIO_BITS 2 /!< STM32F0xx uses 2 Bits for the Priority Levels /
	68	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
	69
	70	/**
	71	* @}
	72	*/
	73
	74	/** @addtogroup Peripheral_interrupt_number_definition
	75	* @{
	76	*/
	77
	78	/**
	79	* @brief STM32F0xx Interrupt Number Definition, according to the selected device
	80	* in @ref Library_configuration_section
	81	*/
	82
	83	/!< Interrupt Number Definition /
	84	typedef enum
	85	{
	86	/**** Cortex-M0 Processor Exceptions Numbers ************************************************************/
	87	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
	88	HardFault_IRQn = -13, /!< 3 Cortex-M0 Hard Fault Interrupt /
	89	SVC_IRQn = -5, /!< 11 Cortex-M0 SV Call Interrupt /
	90	PendSV_IRQn = -2, /!< 14 Cortex-M0 Pend SV Interrupt /
	91	SysTick_IRQn = -1, /!< 15 Cortex-M0 System Tick Interrupt /
	92
	93	/**** STM32F0 specific Interrupt Numbers ****************************************************************/
	94	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
	95	PVD_IRQn = 1, /!< PVD Interrupt through EXTI Lines 16 /
	96	RTC_IRQn = 2, /!< RTC Interrupt through EXTI Lines 17, 19 and 20 /
	97	FLASH_IRQn = 3, /!< FLASH global Interrupt /
	98	RCC_IRQn = 4, /!< RCC global Interrupt /
	99	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupt /
	100	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupt /
	101	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupt /
	102	TSC_IRQn = 8, /!< Touch Sensing Controller Interrupts /
	103	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
	104	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupt /
	105	DMA1_Channel4_5_IRQn = 11, /!< DMA1 Channel 4 and Channel 5 Interrupt /
	106	ADC1_COMP_IRQn = 12, /!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 /
	107	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupt /
	108	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
	109	TIM2_IRQn = 15, /!< TIM2 global Interrupt /
	110	TIM3_IRQn = 16, /!< TIM3 global Interrupt /
	111	TIM6_DAC_IRQn = 17, /!< TIM6 global and DAC channel underrun error Interrupt /
	112	TIM14_IRQn = 19, /!< TIM14 global Interrupt /
	113	TIM15_IRQn = 20, /!< TIM15 global Interrupt /
	114	TIM16_IRQn = 21, /!< TIM16 global Interrupt /
	115	TIM17_IRQn = 22, /!< TIM17 global Interrupt /
	116	I2C1_IRQn = 23, /!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) /
	117	I2C2_IRQn = 24, /!< I2C2 Event Interrupt /
	118	SPI1_IRQn = 25, /!< SPI1 global Interrupt /
	119	SPI2_IRQn = 26, /!< SPI2 global Interrupt /
	120	USART1_IRQn = 27, /!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) /
	121	USART2_IRQn = 28, /!< USART2 global Interrupt /
	122	CEC_CAN_IRQn = 30 /!< CEC and CAN global Interrupts & EXTI Line27 Interrupt /
	123	} IRQn_Type;
	124
	125	/**
	126	* @}
	127	*/
	128
	129	#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
	130	#include "system_stm32f0xx.h" /* STM32F0xx System Header */
	131	#include <stdint.h>
	132
	133	/** @addtogroup Peripheral_registers_structures
	134	* @{
	135	*/
	136
	137	/**
	138	* @brief Analog to Digital Converter
	139	*/
	140
	141	typedef struct
	142	{
	143	__IO uint32_t ISR; /!< ADC interrupt and status register, Address offset: 0x00 /
	144	__IO uint32_t IER; /!< ADC interrupt enable register, Address offset: 0x04 /
	145	__IO uint32_t CR; /!< ADC control register, Address offset: 0x08 /
	146	__IO uint32_t CFGR1; /!< ADC configuration register 1, Address offset: 0x0C /
	147	__IO uint32_t CFGR2; /!< ADC configuration register 2, Address offset: 0x10 /
	148	__IO uint32_t SMPR; /!< ADC sampling time register, Address offset: 0x14 /
	149	uint32_t RESERVED1; /!< Reserved, 0x18 /
	150	uint32_t RESERVED2; /!< Reserved, 0x1C /
	151	__IO uint32_t TR; /!< ADC analog watchdog 1 threshold register, Address offset: 0x20 /
	152	uint32_t RESERVED3; /!< Reserved, 0x24 /
	153	__IO uint32_t CHSELR; /!< ADC group regular sequencer register, Address offset: 0x28 /
	154	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
	155	__IO uint32_t DR; /!< ADC group regular data register, Address offset: 0x40 /
	156	} ADC_TypeDef;
	157
	158	typedef struct
	159	{
	160	__IO uint32_t CCR; /!< ADC common configuration register, Address offset: ADC1 base address + 0x308 /
	161	} ADC_Common_TypeDef;
	162
	163	/**
	164	* @brief HDMI-CEC
	165	*/
	166
	167	typedef struct
	168	{
	169	__IO uint32_t CR; /!< CEC control register, Address offset:0x00 /
	170	__IO uint32_t CFGR; /!< CEC configuration register, Address offset:0x04 /
	171	__IO uint32_t TXDR; /!< CEC Tx data register , Address offset:0x08 /
	172	__IO uint32_t RXDR; /!< CEC Rx Data Register, Address offset:0x0C /
	173	__IO uint32_t ISR; /!< CEC Interrupt and Status Register, Address offset:0x10 /
	174	__IO uint32_t IER; /!< CEC interrupt enable register, Address offset:0x14 /
	175	}CEC_TypeDef;
	176
	177	/**
	178	* @brief Comparator
	179	*/
	180
	181	typedef struct
	182	{
	183	__IO uint16_t CSR; /!< COMP control and status register, Address offset: 0x00 /
	184	} COMP_TypeDef;
	185
	186	typedef struct
	187	{
	188	__IO uint32_t CSR; /!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 /
	189	} COMP_Common_TypeDef;
	190
	191	/* Legacy defines */
	192	typedef struct
	193	{
	194	__IO uint32_t CSR; /!< Kept for legacy purpose. Use structure 'COMP_Common_TypeDef'. /
	195	}COMP1_2_TypeDef;
	196
	197	/**
	198	* @brief CRC calculation unit
	199	*/
	200
	201	typedef struct
	202	{
	203	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
	204	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
	205	uint8_t RESERVED0; /!< Reserved, 0x05 /
	206	uint16_t RESERVED1; /!< Reserved, 0x06 /
	207	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
	208	uint32_t RESERVED2; /!< Reserved, 0x0C /
	209	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
	210	__IO uint32_t RESERVED3; /!< Reserved, 0x14 /
	211	} CRC_TypeDef;
	212
	213	/**
	214	* @brief Digital to Analog Converter
	215	*/
	216
	217	typedef struct
	218	{
	219	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
	220	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
	221	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
	222	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
	223	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
	224	uint32_t RESERVED1[6]; /!< Reserved, Address offset: 0x14 to 0x28 /
	225	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
	226	uint32_t RESERVED2; /!< Reserved, Address offset: 0x30 /
	227	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
	228	} DAC_TypeDef;
	229
	230	/**
	231	* @brief Debug MCU
	232	*/
	233
	234	typedef struct
	235	{
	236	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
	237	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
	238	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
	239	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
	240	}DBGMCU_TypeDef;
	241
	242	/**
	243	* @brief DMA Controller
	244	*/
	245
	246	typedef struct
	247	{
	248	__IO uint32_t CCR; /!< DMA channel x configuration register /
	249	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
	250	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
	251	__IO uint32_t CMAR; /!< DMA channel x memory address register /
	252	} DMA_Channel_TypeDef;
	253
	254	typedef struct
	255	{
	256	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
	257	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
	258	} DMA_TypeDef;
	259
	260	/**
	261	* @brief External Interrupt/Event Controller
	262	*/
	263
	264	typedef struct
	265	{
	266	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
	267	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
	268	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
	269	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
	270	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
	271	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
	272	} EXTI_TypeDef;
	273
	274	/**
	275	* @brief FLASH Registers
	276	*/
	277	typedef struct
	278	{
	279	__IO uint32_t ACR; /!<FLASH access control register, Address offset: 0x00 /
	280	__IO uint32_t KEYR; /!<FLASH key register, Address offset: 0x04 /
	281	__IO uint32_t OPTKEYR; /!<FLASH OPT key register, Address offset: 0x08 /
	282	__IO uint32_t SR; /!<FLASH status register, Address offset: 0x0C /
	283	__IO uint32_t CR; /!<FLASH control register, Address offset: 0x10 /
	284	__IO uint32_t AR; /!<FLASH address register, Address offset: 0x14 /
	285	__IO uint32_t RESERVED; /!< Reserved, 0x18 /
	286	__IO uint32_t OBR; /!<FLASH option bytes register, Address offset: 0x1C /
	287	__IO uint32_t WRPR; /!<FLASH option bytes register, Address offset: 0x20 /
	288	} FLASH_TypeDef;
	289
	290	/**
	291	* @brief Option Bytes Registers
	292	*/
	293	typedef struct
	294	{
	295	__IO uint16_t RDP; /!< FLASH option byte Read protection, Address offset: 0x00 /
	296	__IO uint16_t USER; /!< FLASH option byte user options, Address offset: 0x02 /
	297	__IO uint16_t DATA0; /!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 /
	298	__IO uint16_t DATA1; /!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 /
	299	__IO uint16_t WRP0; /!< FLASH option byte write protection 0, Address offset: 0x08 /
	300	__IO uint16_t WRP1; /!< FLASH option byte write protection 1, Address offset: 0x0A /
	301	} OB_TypeDef;
	302
	303	/**
	304	* @brief General Purpose I/O
	305	*/
	306
	307	typedef struct
	308	{
	309	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
	310	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
	311	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
	312	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
	313	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
	314	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
	315	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x1A /
	316	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
	317	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
	318	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
	319	} GPIO_TypeDef;
	320
	321	/**
	322	* @brief SysTem Configuration
	323	*/
	324
	325	typedef struct
	326	{
	327	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
	328	uint32_t RESERVED; /!< Reserved, 0x04 /
	329	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
	330	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
	331	} SYSCFG_TypeDef;
	332
	333	/**
	334	* @brief Inter-integrated Circuit Interface
	335	*/
	336
	337	typedef struct
	338	{
	339	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
	340	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
	341	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
	342	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
	343	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
	344	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
	345	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
	346	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
	347	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
	348	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
	349	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
	350	} I2C_TypeDef;
	351
	352	/**
	353	* @brief Independent WATCHDOG
	354	*/
	355
	356	typedef struct
	357	{
	358	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
	359	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
	360	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
	361	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
	362	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
	363	} IWDG_TypeDef;
	364
	365	/**
	366	* @brief Power Control
	367	*/
	368
	369	typedef struct
	370	{
	371	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
	372	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
	373	} PWR_TypeDef;
	374
	375	/**
	376	* @brief Reset and Clock Control
	377	*/
	378
	379	typedef struct
	380	{
	381	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
	382	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
	383	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
	384	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
	385	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
	386	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
	387	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
	388	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
	389	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
	390	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
	391	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
	392	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
	393	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
	394	__IO uint32_t CR2; /!< RCC clock control register 2, Address offset: 0x34 /
	395	} RCC_TypeDef;
	396
	397	/**
	398	* @brief Real-Time Clock
	399	*/
	400	typedef struct
	401	{
	402	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
	403	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
	404	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
	405	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
	406	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
	407	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
	408	uint32_t RESERVED2; /!< Reserved, Address offset: 0x18 /
	409	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
	410	uint32_t RESERVED3; /!< Reserved, Address offset: 0x20 /
	411	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
	412	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
	413	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
	414	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
	415	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
	416	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
	417	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
	418	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
	419	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
	420	uint32_t RESERVED4; /!< Reserved, Address offset: 0x48 /
	421	uint32_t RESERVED5; /!< Reserved, Address offset: 0x4C /
	422	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
	423	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
	424	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
	425	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
	426	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
	427	} RTC_TypeDef;
	428
	429	/**
	430	* @brief Serial Peripheral Interface
	431	*/
	432
	433	typedef struct
	434	{
	435	__IO uint32_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
	436	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
	437	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
	438	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
	439	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
	440	__IO uint32_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
	441	__IO uint32_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
	442	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
	443	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
	444	} SPI_TypeDef;
	445
	446	/**
	447	* @brief TIM
	448	*/
	449	typedef struct
	450	{
	451	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
	452	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
	453	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
	454	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
	455	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
	456	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
	457	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
	458	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
	459	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
	460	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
	461	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
	462	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
	463	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
	464	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
	465	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
	466	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
	467	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
	468	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
	469	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
	470	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
	471	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
	472	} TIM_TypeDef;
	473
	474	/**
	475	* @brief Touch Sensing Controller (TSC)
	476	*/
	477	typedef struct
	478	{
	479	__IO uint32_t CR; /!< TSC control register, Address offset: 0x00 /
	480	__IO uint32_t IER; /!< TSC interrupt enable register, Address offset: 0x04 /
	481	__IO uint32_t ICR; /!< TSC interrupt clear register, Address offset: 0x08 /
	482	__IO uint32_t ISR; /!< TSC interrupt status register, Address offset: 0x0C /
	483	__IO uint32_t IOHCR; /!< TSC I/O hysteresis control register, Address offset: 0x10 /
	484	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
	485	__IO uint32_t IOASCR; /!< TSC I/O analog switch control register, Address offset: 0x18 /
	486	uint32_t RESERVED2; /!< Reserved, Address offset: 0x1C /
	487	__IO uint32_t IOSCR; /!< TSC I/O sampling control register, Address offset: 0x20 /
	488	uint32_t RESERVED3; /!< Reserved, Address offset: 0x24 /
	489	__IO uint32_t IOCCR; /!< TSC I/O channel control register, Address offset: 0x28 /
	490	uint32_t RESERVED4; /!< Reserved, Address offset: 0x2C /
	491	__IO uint32_t IOGCSR; /!< TSC I/O group control status register, Address offset: 0x30 /
	492	__IO uint32_t IOGXCR[8]; /!< TSC I/O group x counter register, Address offset: 0x34-50 /
	493	}TSC_TypeDef;
	494
	495	/**
	496	* @brief Universal Synchronous Asynchronous Receiver Transmitter
	497	*/
	498
	499	typedef struct
	500	{
	501	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
	502	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
	503	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
	504	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
	505	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
	506	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
	507	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
	508	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
	509	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
	510	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
	511	uint16_t RESERVED1; /!< Reserved, 0x26 /
	512	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
	513	uint16_t RESERVED2; /!< Reserved, 0x2A /
	514	} USART_TypeDef;
	515
	516	/**
	517	* @brief Window WATCHDOG
	518	*/
	519	typedef struct
	520	{
	521	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
	522	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
	523	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
	524	} WWDG_TypeDef;
	525
	526	/**
	527	* @}
	528	*/
	529
	530	/** @addtogroup Peripheral_memory_map
	531	* @{
	532	*/
	533
	534	#define FLASH_BASE ((uint32_t)0x08000000U) /!< FLASH base address in the alias region /
	535	#define FLASH_BANK1_END ((uint32_t)0x0800FFFFU) /!< FLASH END address of bank1 /
	536	#define SRAM_BASE ((uint32_t)0x20000000U) /!< SRAM base address in the alias region /
	537	#define PERIPH_BASE ((uint32_t)0x40000000U) /!< Peripheral base address in the alias region /
	538
	539	/!< Peripheral memory map /
	540	#define APBPERIPH_BASE PERIPH_BASE
	541	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
	542	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
	543
	544	/!< APB peripherals /
	545	#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
	546	#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
	547	#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
	548	#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
	549	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
	550	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
	551	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
	552	#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
	553	#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
	554	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
	555	#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
	556	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
	557	#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
	558
	559	#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
	560
	561	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
	562	#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
	563	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
	564	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
	565	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
	566	#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
	567	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
	568	#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
	569	#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
	570	#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
	571	#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
	572	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
	573
	574	/!< AHB peripherals /
	575	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
	576	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
	577	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
	578	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
	579	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
	580	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
	581
	582	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
	583	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
	584	#define OB_BASE ((uint32_t)0x1FFFF800U) /!< FLASH Option Bytes base address /
	585	#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /!< FLASH Size register base address /
	586	#define UID_BASE ((uint32_t)0x1FFFF7ACU) /!< Unique device ID register base address /
	587	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
	588	#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
	589
	590	/!< AHB2 peripherals /
	591	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
	592	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
	593	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
	594	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
	595	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
	596
	597	/**
	598	* @}
	599	*/
	600
	601	/** @addtogroup Peripheral_declaration
	602	* @{
	603	*/
	604
	605	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
	606	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
	607	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
	608	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
	609	#define RTC ((RTC_TypeDef *) RTC_BASE)
	610	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
	611	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
	612	#define USART2 ((USART_TypeDef *) USART2_BASE)
	613	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
	614	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
	615	#define PWR ((PWR_TypeDef *) PWR_BASE)
	616	#define DAC1 ((DAC_TypeDef *) DAC_BASE)
	617	#define DAC ((DAC_TypeDef ) DAC_BASE) / Kept for legacy purpose */
	618	#define CEC ((CEC_TypeDef *) CEC_BASE)
	619	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
	620	#define COMP1 ((COMP_TypeDef *) COMP_BASE)
	621	#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
	622	#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE)
	623	#define COMP ((COMP1_2_TypeDef ) COMP_BASE) / Kept for legacy purpose */
	624	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
	625	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
	626	#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
	627	#define ADC ((ADC_Common_TypeDef ) ADC_BASE) / Kept for legacy purpose */
	628	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
	629	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
	630	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
	631	#define USART1 ((USART_TypeDef *) USART1_BASE)
	632	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
	633	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
	634	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
	635	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
	636	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
	637	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
	638	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
	639	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
	640	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
	641	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
	642	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
	643	#define OB ((OB_TypeDef *) OB_BASE)
	644	#define RCC ((RCC_TypeDef *) RCC_BASE)
	645	#define CRC ((CRC_TypeDef *) CRC_BASE)
	646	#define TSC ((TSC_TypeDef *) TSC_BASE)
	647	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
	648	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
	649	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
	650	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
	651	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
	652	/**
	653	* @}
	654	*/
	655
	656	/** @addtogroup Exported_constants
	657	* @{
	658	*/
	659
	660	/** @addtogroup Peripheral_Registers_Bits_Definition
	661	* @{
	662	*/
	663
	664	/******************************************************************************/
	665	/* Peripheral Registers Bits Definition */
	666	/******************************************************************************/
	667
	668	/******************************************************************************/
	669	/* */
	670	/* Analog to Digital Converter (ADC) */
	671	/* */
	672	/******************************************************************************/
	673
	674	/*
	675	* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
	676	*/
	677	#define ADC_CHANNEL_VBAT_SUPPORT /!< ADC feature available only on specific devices: ADC internal channel Vbat /
	678
	679	/****************** Bits definition for ADC_ISR register ****************/
	680	#define ADC_ISR_ADRDY_Pos (0U)
	681	#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /!< 0x00000001 /
	682	#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /!< ADC ready flag /
	683	#define ADC_ISR_EOSMP_Pos (1U)
	684	#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /!< 0x00000002 /
	685	#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /!< ADC group regular end of sampling flag /
	686	#define ADC_ISR_EOC_Pos (2U)
	687	#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /!< 0x00000004 /
	688	#define ADC_ISR_EOC ADC_ISR_EOC_Msk /!< ADC group regular end of unitary conversion flag /
	689	#define ADC_ISR_EOS_Pos (3U)
	690	#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /!< 0x00000008 /
	691	#define ADC_ISR_EOS ADC_ISR_EOS_Msk /!< ADC group regular end of sequence conversions flag /
	692	#define ADC_ISR_OVR_Pos (4U)
	693	#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /!< 0x00000010 /
	694	#define ADC_ISR_OVR ADC_ISR_OVR_Msk /!< ADC group regular overrun flag /
	695	#define ADC_ISR_AWD1_Pos (7U)
	696	#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /!< 0x00000080 /
	697	#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /!< ADC analog watchdog 1 flag /
	698
	699	/* Legacy defines */
	700	#define ADC_ISR_AWD (ADC_ISR_AWD1)
	701	#define ADC_ISR_EOSEQ (ADC_ISR_EOS)
	702
	703	/****************** Bits definition for ADC_IER register ****************/
	704	#define ADC_IER_ADRDYIE_Pos (0U)
	705	#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /!< 0x00000001 /
	706	#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /!< ADC ready interrupt /
	707	#define ADC_IER_EOSMPIE_Pos (1U)
	708	#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /!< 0x00000002 /
	709	#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /!< ADC group regular end of sampling interrupt /
	710	#define ADC_IER_EOCIE_Pos (2U)
	711	#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /!< 0x00000004 /
	712	#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /!< ADC group regular end of unitary conversion interrupt /
	713	#define ADC_IER_EOSIE_Pos (3U)
	714	#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /!< 0x00000008 /
	715	#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /!< ADC group regular end of sequence conversions interrupt /
	716	#define ADC_IER_OVRIE_Pos (4U)
	717	#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /!< 0x00000010 /
	718	#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /!< ADC group regular overrun interrupt /
	719	#define ADC_IER_AWD1IE_Pos (7U)
	720	#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /!< 0x00000080 /
	721	#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /!< ADC analog watchdog 1 interrupt /
	722
	723	/* Legacy defines */
	724	#define ADC_IER_AWDIE (ADC_IER_AWD1IE)
	725	#define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
	726
	727	/****************** Bits definition for ADC_CR register *****************/
	728	#define ADC_CR_ADEN_Pos (0U)
	729	#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /!< 0x00000001 /
	730	#define ADC_CR_ADEN ADC_CR_ADEN_Msk /!< ADC enable /
	731	#define ADC_CR_ADDIS_Pos (1U)
	732	#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /!< 0x00000002 /
	733	#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /!< ADC disable /
	734	#define ADC_CR_ADSTART_Pos (2U)
	735	#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /!< 0x00000004 /
	736	#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /!< ADC group regular conversion start /
	737	#define ADC_CR_ADSTP_Pos (4U)
	738	#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /!< 0x00000010 /
	739	#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /!< ADC group regular conversion stop /
	740	#define ADC_CR_ADCAL_Pos (31U)
	741	#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /!< 0x80000000 /
	742	#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /!< ADC calibration /
	743
	744	/***************** Bits definition for ADC_CFGR1 register ***************/
	745	#define ADC_CFGR1_DMAEN_Pos (0U)
	746	#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /!< 0x00000001 /
	747	#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /!< ADC DMA transfer enable /
	748	#define ADC_CFGR1_DMACFG_Pos (1U)
	749	#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /!< 0x00000002 /
	750	#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /!< ADC DMA transfer configuration /
	751	#define ADC_CFGR1_SCANDIR_Pos (2U)
	752	#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /!< 0x00000004 /
	753	#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /!< ADC group regular sequencer scan direction /
	754
	755	#define ADC_CFGR1_RES_Pos (3U)
	756	#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /!< 0x00000018 /
	757	#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /!< ADC data resolution /
	758	#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /!< 0x00000008 /
	759	#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /!< 0x00000010 /
	760
	761	#define ADC_CFGR1_ALIGN_Pos (5U)
	762	#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /!< 0x00000020 /
	763	#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /!< ADC data alignement /
	764
	765	#define ADC_CFGR1_EXTSEL_Pos (6U)
	766	#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /!< 0x000001C0 /
	767	#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /!< ADC group regular external trigger source /
	768	#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /!< 0x00000040 /
	769	#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /!< 0x00000080 /
	770	#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /!< 0x00000100 /
	771
	772	#define ADC_CFGR1_EXTEN_Pos (10U)
	773	#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /!< 0x00000C00 /
	774	#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /!< ADC group regular external trigger polarity /
	775	#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /!< 0x00000400 /
	776	#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /!< 0x00000800 /
	777
	778	#define ADC_CFGR1_OVRMOD_Pos (12U)
	779	#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /!< 0x00001000 /
	780	#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /!< ADC group regular overrun configuration /
	781	#define ADC_CFGR1_CONT_Pos (13U)
	782	#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /!< 0x00002000 /
	783	#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /!< ADC group regular continuous conversion mode /
	784	#define ADC_CFGR1_WAIT_Pos (14U)
	785	#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /!< 0x00004000 /
	786	#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /!< ADC low power auto wait /
	787	#define ADC_CFGR1_AUTOFF_Pos (15U)
	788	#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /!< 0x00008000 /
	789	#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /!< ADC low power auto power off /
	790	#define ADC_CFGR1_DISCEN_Pos (16U)
	791	#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /!< 0x00010000 /
	792	#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /!< ADC group regular sequencer discontinuous mode /
	793
	794	#define ADC_CFGR1_AWD1SGL_Pos (22U)
	795	#define ADC_CFGR1_AWD1SGL_Msk (0x1U << ADC_CFGR1_AWD1SGL_Pos) /!< 0x00400000 /
	796	#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /!< ADC analog watchdog 1 monitoring a single channel or all channels /
	797	#define ADC_CFGR1_AWD1EN_Pos (23U)
	798	#define ADC_CFGR1_AWD1EN_Msk (0x1U << ADC_CFGR1_AWD1EN_Pos) /!< 0x00800000 /
	799	#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /!< ADC analog watchdog 1 enable on scope ADC group regular /
	800
	801	#define ADC_CFGR1_AWD1CH_Pos (26U)
	802	#define ADC_CFGR1_AWD1CH_Msk (0x1FU << ADC_CFGR1_AWD1CH_Pos) /!< 0x7C000000 /
	803	#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /!< ADC analog watchdog 1 monitored channel selection /
	804	#define ADC_CFGR1_AWD1CH_0 (0x01U << ADC_CFGR1_AWD1CH_Pos) /!< 0x04000000 /
	805	#define ADC_CFGR1_AWD1CH_1 (0x02U << ADC_CFGR1_AWD1CH_Pos) /!< 0x08000000 /
	806	#define ADC_CFGR1_AWD1CH_2 (0x04U << ADC_CFGR1_AWD1CH_Pos) /!< 0x10000000 /
	807	#define ADC_CFGR1_AWD1CH_3 (0x08U << ADC_CFGR1_AWD1CH_Pos) /!< 0x20000000 /
	808	#define ADC_CFGR1_AWD1CH_4 (0x10U << ADC_CFGR1_AWD1CH_Pos) /!< 0x40000000 /
	809
	810	/* Legacy defines */
	811	#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
	812	#define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL)
	813	#define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN)
	814	#define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH)
	815	#define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0)
	816	#define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)
	817	#define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2)
	818	#define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3)
	819	#define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4)
	820
	821	/***************** Bits definition for ADC_CFGR2 register ***************/
	822	#define ADC_CFGR2_CKMODE_Pos (30U)
	823	#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /!< 0xC0000000 /
	824	#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /!< ADC clock source and prescaler (prescaler only for clock source synchronous) /
	825	#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /!< 0x80000000 /
	826	#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /!< 0x40000000 /
	827
	828	/* Legacy defines */
	829	#define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /!< ADC clocked by PCLK div4 /
	830	#define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /!< ADC clocked by PCLK div2 /
	831
	832	/**************** Bit definition for ADC_SMPR register ******************/
	833	#define ADC_SMPR_SMP_Pos (0U)
	834	#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /!< 0x00000007 /
	835	#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /!< ADC group of channels sampling time 2 /
	836	#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /!< 0x00000001 /
	837	#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /!< 0x00000002 /
	838	#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /!< 0x00000004 /
	839
	840	/* Legacy defines */
	841	#define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /!< SMP[2:0] bits (Sampling time selection) /
	842	#define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /!< bit 0 /
	843	#define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /!< bit 1 /
	844	#define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /!< bit 2 /
	845
	846	/***************** Bit definition for ADC_TR register ******************/
	847	#define ADC_TR1_LT1_Pos (0U)
	848	#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /!< 0x00000FFF /
	849	#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /!< ADC analog watchdog 1 threshold low /
	850	#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /!< 0x00000001 /
	851	#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /!< 0x00000002 /
	852	#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /!< 0x00000004 /
	853	#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /!< 0x00000008 /
	854	#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /!< 0x00000010 /
	855	#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /!< 0x00000020 /
	856	#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /!< 0x00000040 /
	857	#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /!< 0x00000080 /
	858	#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /!< 0x00000100 /
	859	#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /!< 0x00000200 /
	860	#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /!< 0x00000400 /
	861	#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /!< 0x00000800 /
	862
	863	#define ADC_TR1_HT1_Pos (16U)
	864	#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /!< 0x0FFF0000 /
	865	#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /!< ADC Analog watchdog 1 threshold high /
	866	#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /!< 0x00010000 /
	867	#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /!< 0x00020000 /
	868	#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /!< 0x00040000 /
	869	#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /!< 0x00080000 /
	870	#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /!< 0x00100000 /
	871	#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /!< 0x00200000 /
	872	#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /!< 0x00400000 /
	873	#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /!< 0x00800000 /
	874	#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /!< 0x01000000 /
	875	#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /!< 0x02000000 /
	876	#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /!< 0x04000000 /
	877	#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /!< 0x08000000 /
	878
	879	/* Legacy defines */
	880	#define ADC_TR_HT (ADC_TR1_HT1)
	881	#define ADC_TR_LT (ADC_TR1_LT1)
	882	#define ADC_HTR_HT (ADC_TR1_HT1)
	883	#define ADC_LTR_LT (ADC_TR1_LT1)
	884
	885	/**************** Bit definition for ADC_CHSELR register ****************/
	886	#define ADC_CHSELR_CHSEL_Pos (0U)
	887	#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /!< 0x0007FFFF /
	888	#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset /
	889	#define ADC_CHSELR_CHSEL18_Pos (18U)
	890	#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /!< 0x00040000 /
	891	#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset /
	892	#define ADC_CHSELR_CHSEL17_Pos (17U)
	893	#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /!< 0x00020000 /
	894	#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset /
	895	#define ADC_CHSELR_CHSEL16_Pos (16U)
	896	#define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /!< 0x00010000 /
	897	#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset /
	898	#define ADC_CHSELR_CHSEL15_Pos (15U)
	899	#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /!< 0x00008000 /
	900	#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset /
	901	#define ADC_CHSELR_CHSEL14_Pos (14U)
	902	#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /!< 0x00004000 /
	903	#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset /
	904	#define ADC_CHSELR_CHSEL13_Pos (13U)
	905	#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /!< 0x00002000 /
	906	#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset /
	907	#define ADC_CHSELR_CHSEL12_Pos (12U)
	908	#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /!< 0x00001000 /
	909	#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset /
	910	#define ADC_CHSELR_CHSEL11_Pos (11U)
	911	#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /!< 0x00000800 /
	912	#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset /
	913	#define ADC_CHSELR_CHSEL10_Pos (10U)
	914	#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /!< 0x00000400 /
	915	#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset /
	916	#define ADC_CHSELR_CHSEL9_Pos (9U)
	917	#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /!< 0x00000200 /
	918	#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset /
	919	#define ADC_CHSELR_CHSEL8_Pos (8U)
	920	#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /!< 0x00000100 /
	921	#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset /
	922	#define ADC_CHSELR_CHSEL7_Pos (7U)
	923	#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /!< 0x00000080 /
	924	#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset /
	925	#define ADC_CHSELR_CHSEL6_Pos (6U)
	926	#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /!< 0x00000040 /
	927	#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset /
	928	#define ADC_CHSELR_CHSEL5_Pos (5U)
	929	#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /!< 0x00000020 /
	930	#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset /
	931	#define ADC_CHSELR_CHSEL4_Pos (4U)
	932	#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /!< 0x00000010 /
	933	#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset /
	934	#define ADC_CHSELR_CHSEL3_Pos (3U)
	935	#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /!< 0x00000008 /
	936	#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset /
	937	#define ADC_CHSELR_CHSEL2_Pos (2U)
	938	#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /!< 0x00000004 /
	939	#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset /
	940	#define ADC_CHSELR_CHSEL1_Pos (1U)
	941	#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /!< 0x00000002 /
	942	#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset /
	943	#define ADC_CHSELR_CHSEL0_Pos (0U)
	944	#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /!< 0x00000001 /
	945	#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset /
	946
	947	/****************** Bit definition for ADC_DR register ******************/
	948	#define ADC_DR_DATA_Pos (0U)
	949	#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /!< 0x0000FFFF /
	950	#define ADC_DR_DATA ADC_DR_DATA_Msk /!< ADC group regular conversion data /
	951	#define ADC_DR_DATA_0 (0x0001U << ADC_DR_DATA_Pos) /!< 0x00000001 /
	952	#define ADC_DR_DATA_1 (0x0002U << ADC_DR_DATA_Pos) /!< 0x00000002 /
	953	#define ADC_DR_DATA_2 (0x0004U << ADC_DR_DATA_Pos) /!< 0x00000004 /
	954	#define ADC_DR_DATA_3 (0x0008U << ADC_DR_DATA_Pos) /!< 0x00000008 /
	955	#define ADC_DR_DATA_4 (0x0010U << ADC_DR_DATA_Pos) /!< 0x00000010 /
	956	#define ADC_DR_DATA_5 (0x0020U << ADC_DR_DATA_Pos) /!< 0x00000020 /
	957	#define ADC_DR_DATA_6 (0x0040U << ADC_DR_DATA_Pos) /!< 0x00000040 /
	958	#define ADC_DR_DATA_7 (0x0080U << ADC_DR_DATA_Pos) /!< 0x00000080 /
	959	#define ADC_DR_DATA_8 (0x0100U << ADC_DR_DATA_Pos) /!< 0x00000100 /
	960	#define ADC_DR_DATA_9 (0x0200U << ADC_DR_DATA_Pos) /!< 0x00000200 /
	961	#define ADC_DR_DATA_10 (0x0400U << ADC_DR_DATA_Pos) /!< 0x00000400 /
	962	#define ADC_DR_DATA_11 (0x0800U << ADC_DR_DATA_Pos) /!< 0x00000800 /
	963	#define ADC_DR_DATA_12 (0x1000U << ADC_DR_DATA_Pos) /!< 0x00001000 /
	964	#define ADC_DR_DATA_13 (0x2000U << ADC_DR_DATA_Pos) /!< 0x00002000 /
	965	#define ADC_DR_DATA_14 (0x4000U << ADC_DR_DATA_Pos) /!< 0x00004000 /
	966	#define ADC_DR_DATA_15 (0x8000U << ADC_DR_DATA_Pos) /!< 0x00008000 /
	967
	968	/*********************** ADC Common registers ***************************/
	969	/***************** Bit definition for ADC_CCR register ******************/
	970	#define ADC_CCR_VREFEN_Pos (22U)
	971	#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /!< 0x00400000 /
	972	#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /!< ADC internal path to VrefInt enable /
	973	#define ADC_CCR_TSEN_Pos (23U)
	974	#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /!< 0x00800000 /
	975	#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /!< ADC internal path to temperature sensor enable /
	976
	977	#define ADC_CCR_VBATEN_Pos (24U)
	978	#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /!< 0x01000000 /
	979	#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /!< ADC internal path to battery voltage enable /
	980
	981	/******************************************************************************/
	982	/* */
	983	/* HDMI-CEC (CEC) */
	984	/* */
	985	/******************************************************************************/
	986
	987	/***************** Bit definition for CEC_CR register *******************/
	988	#define CEC_CR_CECEN_Pos (0U)
	989	#define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /!< 0x00000001 /
	990	#define CEC_CR_CECEN CEC_CR_CECEN_Msk /!< CEC Enable /
	991	#define CEC_CR_TXSOM_Pos (1U)
	992	#define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /!< 0x00000002 /
	993	#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /!< CEC Tx Start Of Message /
	994	#define CEC_CR_TXEOM_Pos (2U)
	995	#define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /!< 0x00000004 /
	996	#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /!< CEC Tx End Of Message /
	997
	998	/***************** Bit definition for CEC_CFGR register *****************/
	999	#define CEC_CFGR_SFT_Pos (0U)
	1000	#define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /!< 0x00000007 /
	1001	#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /!< CEC Signal Free Time /
	1002	#define CEC_CFGR_RXTOL_Pos (3U)
	1003	#define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /!< 0x00000008 /
	1004	#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /!< CEC Tolerance /
	1005	#define CEC_CFGR_BRESTP_Pos (4U)
	1006	#define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /!< 0x00000010 /
	1007	#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /!< CEC Rx Stop /
	1008	#define CEC_CFGR_BREGEN_Pos (5U)
	1009	#define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /!< 0x00000020 /
	1010	#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /!< CEC Bit Rising Error generation /
	1011	#define CEC_CFGR_LBPEGEN_Pos (6U)
	1012	#define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /!< 0x00000040 /
	1013	#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /!< CEC Long Bit Period Error gener. /
	1014	#define CEC_CFGR_BRDNOGEN_Pos (7U)
	1015	#define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /!< 0x00000080 /
	1016	#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /!< CEC Broadcast No Error generation /
	1017	#define CEC_CFGR_SFTOPT_Pos (8U)
	1018	#define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /!< 0x00000100 /
	1019	#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /!< CEC Signal Free Time optional /
	1020	#define CEC_CFGR_OAR_Pos (16U)
	1021	#define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /!< 0x7FFF0000 /
	1022	#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /!< CEC Own Address /
	1023	#define CEC_CFGR_LSTN_Pos (31U)
	1024	#define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /!< 0x80000000 /
	1025	#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /!< CEC Listen mode /
	1026
	1027	/***************** Bit definition for CEC_TXDR register *****************/
	1028	#define CEC_TXDR_TXD_Pos (0U)
	1029	#define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /!< 0x000000FF /
	1030	#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /!< CEC Tx Data /
	1031
	1032	/***************** Bit definition for CEC_RXDR register *****************/
	1033	#define CEC_TXDR_RXD_Pos (0U)
	1034	#define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /!< 0x000000FF /
	1035	#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /!< CEC Rx Data /
	1036
	1037	/***************** Bit definition for CEC_ISR register ******************/
	1038	#define CEC_ISR_RXBR_Pos (0U)
	1039	#define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /!< 0x00000001 /
	1040	#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /!< CEC Rx-Byte Received /
	1041	#define CEC_ISR_RXEND_Pos (1U)
	1042	#define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /!< 0x00000002 /
	1043	#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /!< CEC End Of Reception /
	1044	#define CEC_ISR_RXOVR_Pos (2U)
	1045	#define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /!< 0x00000004 /
	1046	#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /!< CEC Rx-Overrun /
	1047	#define CEC_ISR_BRE_Pos (3U)
	1048	#define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /!< 0x00000008 /
	1049	#define CEC_ISR_BRE CEC_ISR_BRE_Msk /!< CEC Rx Bit Rising Error /
	1050	#define CEC_ISR_SBPE_Pos (4U)
	1051	#define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /!< 0x00000010 /
	1052	#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /!< CEC Rx Short Bit period Error /
	1053	#define CEC_ISR_LBPE_Pos (5U)
	1054	#define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /!< 0x00000020 /
	1055	#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /!< CEC Rx Long Bit period Error /
	1056	#define CEC_ISR_RXACKE_Pos (6U)
	1057	#define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /!< 0x00000040 /
	1058	#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /!< CEC Rx Missing Acknowledge /
	1059	#define CEC_ISR_ARBLST_Pos (7U)
	1060	#define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /!< 0x00000080 /
	1061	#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /!< CEC Arbitration Lost /
	1062	#define CEC_ISR_TXBR_Pos (8U)
	1063	#define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /!< 0x00000100 /
	1064	#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /!< CEC Tx Byte Request /
	1065	#define CEC_ISR_TXEND_Pos (9U)
	1066	#define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /!< 0x00000200 /
	1067	#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /!< CEC End of Transmission /
	1068	#define CEC_ISR_TXUDR_Pos (10U)
	1069	#define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /!< 0x00000400 /
	1070	#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /!< CEC Tx-Buffer Underrun /
	1071	#define CEC_ISR_TXERR_Pos (11U)
	1072	#define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /!< 0x00000800 /
	1073	#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /!< CEC Tx-Error /
	1074	#define CEC_ISR_TXACKE_Pos (12U)
	1075	#define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /!< 0x00001000 /
	1076	#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /!< CEC Tx Missing Acknowledge /
	1077
	1078	/***************** Bit definition for CEC_IER register ******************/
	1079	#define CEC_IER_RXBRIE_Pos (0U)
	1080	#define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /!< 0x00000001 /
	1081	#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /!< CEC Rx-Byte Received IT Enable /
	1082	#define CEC_IER_RXENDIE_Pos (1U)
	1083	#define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /!< 0x00000002 /
	1084	#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /!< CEC End Of Reception IT Enable /
	1085	#define CEC_IER_RXOVRIE_Pos (2U)
	1086	#define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /!< 0x00000004 /
	1087	#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /!< CEC Rx-Overrun IT Enable /
	1088	#define CEC_IER_BREIE_Pos (3U)
	1089	#define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /!< 0x00000008 /
	1090	#define CEC_IER_BREIE CEC_IER_BREIE_Msk /!< CEC Rx Bit Rising Error IT Enable /
	1091	#define CEC_IER_SBPEIE_Pos (4U)
	1092	#define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /!< 0x00000010 /
	1093	#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /!< CEC Rx Short Bit period Error IT Enable/
	1094	#define CEC_IER_LBPEIE_Pos (5U)
	1095	#define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /!< 0x00000020 /
	1096	#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /!< CEC Rx Long Bit period Error IT Enable /
	1097	#define CEC_IER_RXACKEIE_Pos (6U)
	1098	#define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /!< 0x00000040 /
	1099	#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /!< CEC Rx Missing Acknowledge IT Enable /
	1100	#define CEC_IER_ARBLSTIE_Pos (7U)
	1101	#define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /!< 0x00000080 /
	1102	#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /!< CEC Arbitration Lost IT Enable /
	1103	#define CEC_IER_TXBRIE_Pos (8U)
	1104	#define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /!< 0x00000100 /
	1105	#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /!< CEC Tx Byte Request IT Enable /
	1106	#define CEC_IER_TXENDIE_Pos (9U)
	1107	#define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /!< 0x00000200 /
	1108	#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /!< CEC End of Transmission IT Enable /
	1109	#define CEC_IER_TXUDRIE_Pos (10U)
	1110	#define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /!< 0x00000400 /
	1111	#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /!< CEC Tx-Buffer Underrun IT Enable /
	1112	#define CEC_IER_TXERRIE_Pos (11U)
	1113	#define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /!< 0x00000800 /
	1114	#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /!< CEC Tx-Error IT Enable /
	1115	#define CEC_IER_TXACKEIE_Pos (12U)
	1116	#define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /!< 0x00001000 /
	1117	#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /!< CEC Tx Missing Acknowledge IT Enable /
	1118
	1119	/******************************************************************************/
	1120	/* */
	1121	/* Analog Comparators (COMP) */
	1122	/* */
	1123	/******************************************************************************/
	1124	/********************* Bit definition for COMP_CSR register *************/
	1125	/* COMP1 bits definition */
	1126	#define COMP_CSR_COMP1EN_Pos (0U)
	1127	#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /!< 0x00000001 /
	1128	#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /!< COMP1 enable /
	1129	#define COMP_CSR_COMP1SW1_Pos (1U)
	1130	#define COMP_CSR_COMP1SW1_Msk (0x1U << COMP_CSR_COMP1SW1_Pos) /!< 0x00000002 /
	1131	#define COMP_CSR_COMP1SW1 COMP_CSR_COMP1SW1_Msk /!< COMP1 SW1 switch control /
	1132	#define COMP_CSR_COMP1MODE_Pos (2U)
	1133	#define COMP_CSR_COMP1MODE_Msk (0x3U << COMP_CSR_COMP1MODE_Pos) /!< 0x0000000C /
	1134	#define COMP_CSR_COMP1MODE COMP_CSR_COMP1MODE_Msk /!< COMP1 power mode /
	1135	#define COMP_CSR_COMP1MODE_0 (0x1U << COMP_CSR_COMP1MODE_Pos) /!< 0x00000004 /
	1136	#define COMP_CSR_COMP1MODE_1 (0x2U << COMP_CSR_COMP1MODE_Pos) /!< 0x00000008 /
	1137	#define COMP_CSR_COMP1INSEL_Pos (4U)
	1138	#define COMP_CSR_COMP1INSEL_Msk (0x7U << COMP_CSR_COMP1INSEL_Pos) /!< 0x00000070 /
	1139	#define COMP_CSR_COMP1INSEL COMP_CSR_COMP1INSEL_Msk /!< COMP1 inverting input select /
	1140	#define COMP_CSR_COMP1INSEL_0 (0x1U << COMP_CSR_COMP1INSEL_Pos) /!< 0x00000010 /
	1141	#define COMP_CSR_COMP1INSEL_1 (0x2U << COMP_CSR_COMP1INSEL_Pos) /!< 0x00000020 /
	1142	#define COMP_CSR_COMP1INSEL_2 (0x4U << COMP_CSR_COMP1INSEL_Pos) /!< 0x00000040 /
	1143	#define COMP_CSR_COMP1OUTSEL_Pos (8U)
	1144	#define COMP_CSR_COMP1OUTSEL_Msk (0x7U << COMP_CSR_COMP1OUTSEL_Pos) /!< 0x00000700 /
	1145	#define COMP_CSR_COMP1OUTSEL COMP_CSR_COMP1OUTSEL_Msk /!< COMP1 output select /
	1146	#define COMP_CSR_COMP1OUTSEL_0 (0x1U << COMP_CSR_COMP1OUTSEL_Pos) /!< 0x00000100 /
	1147	#define COMP_CSR_COMP1OUTSEL_1 (0x2U << COMP_CSR_COMP1OUTSEL_Pos) /!< 0x00000200 /
	1148	#define COMP_CSR_COMP1OUTSEL_2 (0x4U << COMP_CSR_COMP1OUTSEL_Pos) /!< 0x00000400 /
	1149	#define COMP_CSR_COMP1POL_Pos (11U)
	1150	#define COMP_CSR_COMP1POL_Msk (0x1U << COMP_CSR_COMP1POL_Pos) /!< 0x00000800 /
	1151	#define COMP_CSR_COMP1POL COMP_CSR_COMP1POL_Msk /!< COMP1 output polarity /
	1152	#define COMP_CSR_COMP1HYST_Pos (12U)
	1153	#define COMP_CSR_COMP1HYST_Msk (0x3U << COMP_CSR_COMP1HYST_Pos) /!< 0x00003000 /
	1154	#define COMP_CSR_COMP1HYST COMP_CSR_COMP1HYST_Msk /!< COMP1 hysteresis /
	1155	#define COMP_CSR_COMP1HYST_0 (0x1U << COMP_CSR_COMP1HYST_Pos) /!< 0x00001000 /
	1156	#define COMP_CSR_COMP1HYST_1 (0x2U << COMP_CSR_COMP1HYST_Pos) /!< 0x00002000 /
	1157	#define COMP_CSR_COMP1OUT_Pos (14U)
	1158	#define COMP_CSR_COMP1OUT_Msk (0x1U << COMP_CSR_COMP1OUT_Pos) /!< 0x00004000 /
	1159	#define COMP_CSR_COMP1OUT COMP_CSR_COMP1OUT_Msk /!< COMP1 output level /
	1160	#define COMP_CSR_COMP1LOCK_Pos (15U)
	1161	#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /!< 0x00008000 /
	1162	#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /!< COMP1 lock /
	1163	/* COMP2 bits definition */
	1164	#define COMP_CSR_COMP2EN_Pos (16U)
	1165	#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /!< 0x00010000 /
	1166	#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /!< COMP2 enable /
	1167	#define COMP_CSR_COMP2MODE_Pos (18U)
	1168	#define COMP_CSR_COMP2MODE_Msk (0x3U << COMP_CSR_COMP2MODE_Pos) /!< 0x000C0000 /
	1169	#define COMP_CSR_COMP2MODE COMP_CSR_COMP2MODE_Msk /!< COMP2 power mode /
	1170	#define COMP_CSR_COMP2MODE_0 (0x1U << COMP_CSR_COMP2MODE_Pos) /!< 0x00040000 /
	1171	#define COMP_CSR_COMP2MODE_1 (0x2U << COMP_CSR_COMP2MODE_Pos) /!< 0x00080000 /
	1172	#define COMP_CSR_COMP2INSEL_Pos (20U)
	1173	#define COMP_CSR_COMP2INSEL_Msk (0x7U << COMP_CSR_COMP2INSEL_Pos) /!< 0x00700000 /
	1174	#define COMP_CSR_COMP2INSEL COMP_CSR_COMP2INSEL_Msk /!< COMP2 inverting input select /
	1175	#define COMP_CSR_COMP2INSEL_0 (0x1U << COMP_CSR_COMP2INSEL_Pos) /!< 0x00100000 /
	1176	#define COMP_CSR_COMP2INSEL_1 (0x2U << COMP_CSR_COMP2INSEL_Pos) /!< 0x00200000 /
	1177	#define COMP_CSR_COMP2INSEL_2 (0x4U << COMP_CSR_COMP2INSEL_Pos) /!< 0x00400000 /
	1178	#define COMP_CSR_WNDWEN_Pos (23U)
	1179	#define COMP_CSR_WNDWEN_Msk (0x1U << COMP_CSR_WNDWEN_Pos) /!< 0x00800000 /
	1180	#define COMP_CSR_WNDWEN COMP_CSR_WNDWEN_Msk /!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) /
	1181	#define COMP_CSR_COMP2OUTSEL_Pos (24U)
	1182	#define COMP_CSR_COMP2OUTSEL_Msk (0x7U << COMP_CSR_COMP2OUTSEL_Pos) /!< 0x07000000 /
	1183	#define COMP_CSR_COMP2OUTSEL COMP_CSR_COMP2OUTSEL_Msk /!< COMP2 output select /
	1184	#define COMP_CSR_COMP2OUTSEL_0 (0x1U << COMP_CSR_COMP2OUTSEL_Pos) /!< 0x01000000 /
	1185	#define COMP_CSR_COMP2OUTSEL_1 (0x2U << COMP_CSR_COMP2OUTSEL_Pos) /!< 0x02000000 /
	1186	#define COMP_CSR_COMP2OUTSEL_2 (0x4U << COMP_CSR_COMP2OUTSEL_Pos) /!< 0x04000000 /
	1187	#define COMP_CSR_COMP2POL_Pos (27U)
	1188	#define COMP_CSR_COMP2POL_Msk (0x1U << COMP_CSR_COMP2POL_Pos) /!< 0x08000000 /
	1189	#define COMP_CSR_COMP2POL COMP_CSR_COMP2POL_Msk /!< COMP2 output polarity /
	1190	#define COMP_CSR_COMP2HYST_Pos (28U)
	1191	#define COMP_CSR_COMP2HYST_Msk (0x3U << COMP_CSR_COMP2HYST_Pos) /!< 0x30000000 /
	1192	#define COMP_CSR_COMP2HYST COMP_CSR_COMP2HYST_Msk /!< COMP2 hysteresis /
	1193	#define COMP_CSR_COMP2HYST_0 (0x1U << COMP_CSR_COMP2HYST_Pos) /!< 0x10000000 /
	1194	#define COMP_CSR_COMP2HYST_1 (0x2U << COMP_CSR_COMP2HYST_Pos) /!< 0x20000000 /
	1195	#define COMP_CSR_COMP2OUT_Pos (30U)
	1196	#define COMP_CSR_COMP2OUT_Msk (0x1U << COMP_CSR_COMP2OUT_Pos) /!< 0x40000000 /
	1197	#define COMP_CSR_COMP2OUT COMP_CSR_COMP2OUT_Msk /!< COMP2 output level /
	1198	#define COMP_CSR_COMP2LOCK_Pos (31U)
	1199	#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /!< 0x80000000 /
	1200	#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /!< COMP2 lock /
	1201	/* COMPx bits definition */
	1202	#define COMP_CSR_COMPxEN_Pos (0U)
	1203	#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /!< 0x00000001 /
	1204	#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /!< COMPx enable /
	1205	#define COMP_CSR_COMPxMODE_Pos (2U)
	1206	#define COMP_CSR_COMPxMODE_Msk (0x3U << COMP_CSR_COMPxMODE_Pos) /!< 0x0000000C /
	1207	#define COMP_CSR_COMPxMODE COMP_CSR_COMPxMODE_Msk /!< COMPx power mode /
	1208	#define COMP_CSR_COMPxMODE_0 (0x1U << COMP_CSR_COMPxMODE_Pos) /!< 0x00000004 /
	1209	#define COMP_CSR_COMPxMODE_1 (0x2U << COMP_CSR_COMPxMODE_Pos) /!< 0x00000008 /
	1210	#define COMP_CSR_COMPxINSEL_Pos (4U)
	1211	#define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /!< 0x00000070 /
	1212	#define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /!< COMPx inverting input select /
	1213	#define COMP_CSR_COMPxINSEL_0 (0x1U << COMP_CSR_COMPxINSEL_Pos) /!< 0x00000010 /
	1214	#define COMP_CSR_COMPxINSEL_1 (0x2U << COMP_CSR_COMPxINSEL_Pos) /!< 0x00000020 /
	1215	#define COMP_CSR_COMPxINSEL_2 (0x4U << COMP_CSR_COMPxINSEL_Pos) /!< 0x00000040 /
	1216	#define COMP_CSR_COMPxOUTSEL_Pos (8U)
	1217	#define COMP_CSR_COMPxOUTSEL_Msk (0x7U << COMP_CSR_COMPxOUTSEL_Pos) /!< 0x00000700 /
	1218	#define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /!< COMPx output select /
	1219	#define COMP_CSR_COMPxOUTSEL_0 (0x1U << COMP_CSR_COMPxOUTSEL_Pos) /!< 0x00000100 /
	1220	#define COMP_CSR_COMPxOUTSEL_1 (0x2U << COMP_CSR_COMPxOUTSEL_Pos) /!< 0x00000200 /
	1221	#define COMP_CSR_COMPxOUTSEL_2 (0x4U << COMP_CSR_COMPxOUTSEL_Pos) /!< 0x00000400 /
	1222	#define COMP_CSR_COMPxPOL_Pos (11U)
	1223	#define COMP_CSR_COMPxPOL_Msk (0x1U << COMP_CSR_COMPxPOL_Pos) /!< 0x00000800 /
	1224	#define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /!< COMPx output polarity /
	1225	#define COMP_CSR_COMPxHYST_Pos (12U)
	1226	#define COMP_CSR_COMPxHYST_Msk (0x3U << COMP_CSR_COMPxHYST_Pos) /!< 0x00003000 /
	1227	#define COMP_CSR_COMPxHYST COMP_CSR_COMPxHYST_Msk /!< COMPx hysteresis /
	1228	#define COMP_CSR_COMPxHYST_0 (0x1U << COMP_CSR_COMPxHYST_Pos) /!< 0x00001000 /
	1229	#define COMP_CSR_COMPxHYST_1 (0x2U << COMP_CSR_COMPxHYST_Pos) /!< 0x00002000 /
	1230	#define COMP_CSR_COMPxOUT_Pos (14U)
	1231	#define COMP_CSR_COMPxOUT_Msk (0x1U << COMP_CSR_COMPxOUT_Pos) /!< 0x00004000 /
	1232	#define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /!< COMPx output level /
	1233	#define COMP_CSR_COMPxLOCK_Pos (15U)
	1234	#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /!< 0x00008000 /
	1235	#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /!< COMPx lock /
	1236
	1237	/******************************************************************************/
	1238	/* */
	1239	/* CRC calculation unit (CRC) */
	1240	/* */
	1241	/******************************************************************************/
	1242	/***************** Bit definition for CRC_DR register *******************/
	1243	#define CRC_DR_DR_Pos (0U)
	1244	#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /!< 0xFFFFFFFF /
	1245	#define CRC_DR_DR CRC_DR_DR_Msk /!< Data register bits /
	1246
	1247	/***************** Bit definition for CRC_IDR register ******************/
	1248	#define CRC_IDR_IDR ((uint8_t)0xFFU) /!< General-purpose 8-bit data register bits /
	1249
	1250	/****************** Bit definition for CRC_CR register ******************/
	1251	#define CRC_CR_RESET_Pos (0U)
	1252	#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /!< 0x00000001 /
	1253	#define CRC_CR_RESET CRC_CR_RESET_Msk /!< RESET the CRC computation unit bit /
	1254	#define CRC_CR_REV_IN_Pos (5U)
	1255	#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /!< 0x00000060 /
	1256	#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /!< REV_IN Reverse Input Data bits /
	1257	#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /!< 0x00000020 /
	1258	#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /!< 0x00000040 /
	1259	#define CRC_CR_REV_OUT_Pos (7U)
	1260	#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /!< 0x00000080 /
	1261	#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /!< REV_OUT Reverse Output Data bits /
	1262
	1263	/***************** Bit definition for CRC_INIT register *****************/
	1264	#define CRC_INIT_INIT_Pos (0U)
	1265	#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /!< 0xFFFFFFFF /
	1266	#define CRC_INIT_INIT CRC_INIT_INIT_Msk /!< Initial CRC value bits /
	1267
	1268	/******************************************************************************/
	1269	/* */
	1270	/* Digital to Analog Converter (DAC) */
	1271	/* */
	1272	/******************************************************************************/
	1273
	1274	/*
	1275	* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
	1276	*/
	1277	/* Note: No specific macro feature on this device */
	1278
	1279	/****************** Bit definition for DAC_CR register ******************/
	1280	#define DAC_CR_EN1_Pos (0U)
	1281	#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /!< 0x00000001 /
	1282	#define DAC_CR_EN1 DAC_CR_EN1_Msk /!< DAC channel1 enable /
	1283	#define DAC_CR_BOFF1_Pos (1U)
	1284	#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /!< 0x00000002 /
	1285	#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /!< DAC channel1 output buffer disable /
	1286	#define DAC_CR_TEN1_Pos (2U)
	1287	#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /!< 0x00000004 /
	1288	#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /!< DAC channel1 Trigger enable /
	1289
	1290	#define DAC_CR_TSEL1_Pos (3U)
	1291	#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /!< 0x00000038 /
	1292	#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
	1293	#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /!< 0x00000008 /
	1294	#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /!< 0x00000010 /
	1295	#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /!< 0x00000020 /
	1296
	1297	#define DAC_CR_DMAEN1_Pos (12U)
	1298	#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /!< 0x00001000 /
	1299	#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /!< DAC channel1 DMA enable /
	1300	#define DAC_CR_DMAUDRIE1_Pos (13U)
	1301	#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /!< 0x00002000 /
	1302	#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /!< DAC channel1 DMA Underrun Interrupt enable /
	1303
	1304
	1305	/*************** Bit definition for DAC_SWTRIGR register ****************/
	1306	#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
	1307	#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /!< 0x00000001 /
	1308	#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /!< DAC channel1 software trigger /
	1309
	1310	/*************** Bit definition for DAC_DHR12R1 register ****************/
	1311	#define DAC_DHR12R1_DACC1DHR_Pos (0U)
	1312	#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /!< 0x00000FFF /
	1313	#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /!< DAC channel1 12-bit Right aligned data /
	1314
	1315	/*************** Bit definition for DAC_DHR12L1 register ****************/
	1316	#define DAC_DHR12L1_DACC1DHR_Pos (4U)
	1317	#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /!< 0x0000FFF0 /
	1318	#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /!< DAC channel1 12-bit Left aligned data /
	1319
	1320	/**************** Bit definition for DAC_DHR8R1 register ****************/
	1321	#define DAC_DHR8R1_DACC1DHR_Pos (0U)
	1322	#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /!< 0x000000FF /
	1323	#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /!< DAC channel1 8-bit Right aligned data /
	1324
	1325	/***************** Bit definition for DAC_DOR1 register *****************/
	1326	#define DAC_DOR1_DACC1DOR_Pos (0U)
	1327	#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /!< 0x00000FFF /
	1328	#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /!< DAC channel1 data output /
	1329
	1330	/****************** Bit definition for DAC_SR register ******************/
	1331	#define DAC_SR_DMAUDR1_Pos (13U)
	1332	#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /!< 0x00002000 /
	1333	#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /!< DAC channel1 DMA underrun flag /
	1334	#define DAC_SR_DMAUDR2_Pos (29U)
	1335	#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /!< 0x20000000 /
	1336	#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /!< DAC channel2 DMA underrun flag /
	1337
	1338	/******************************************************************************/
	1339	/* */
	1340	/* Debug MCU (DBGMCU) */
	1341	/* */
	1342	/******************************************************************************/
	1343
	1344	/************** Bit definition for DBGMCU_IDCODE register ***************/
	1345	#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
	1346	#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /!< 0x00000FFF /
	1347	#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /!< Device Identifier /
	1348
	1349	#define DBGMCU_IDCODE_REV_ID_Pos (16U)
	1350	#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /!< 0xFFFF0000 /
	1351	#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /!< REV_ID[15:0] bits (Revision Identifier) /
	1352	#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00010000 /
	1353	#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00020000 /
	1354	#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00040000 /
	1355	#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00080000 /
	1356	#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00100000 /
	1357	#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00200000 /
	1358	#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00400000 /
	1359	#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00800000 /
	1360	#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x01000000 /
	1361	#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x02000000 /
	1362	#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x04000000 /
	1363	#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x08000000 /
	1364	#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x10000000 /
	1365	#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x20000000 /
	1366	#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x40000000 /
	1367	#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x80000000 /
	1368
	1369	/**************** Bit definition for DBGMCU_CR register *****************/
	1370	#define DBGMCU_CR_DBG_STOP_Pos (1U)
	1371	#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /!< 0x00000002 /
	1372	#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /!< Debug Stop Mode /
	1373	#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
	1374	#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /!< 0x00000004 /
	1375	#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /!< Debug Standby mode /
	1376
	1377	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
	1378	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
	1379	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /!< 0x00000001 /
	1380	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /!< TIM2 counter stopped when core is halted /
	1381	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
	1382	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /!< 0x00000002 /
	1383	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /!< TIM3 counter stopped when core is halted /
	1384	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
	1385	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /!< 0x00000010 /
	1386	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /!< TIM6 counter stopped when core is halted /
	1387	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
	1388	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /!< 0x00000100 /
	1389	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /!< TIM14 counter stopped when core is halted /
	1390	#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
	1391	#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /!< 0x00000400 /
	1392	#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /!< RTC Calendar frozen when core is halted /
	1393	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
	1394	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /!< 0x00000800 /
	1395	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /!< Debug Window Watchdog stopped when Core is halted /
	1396	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
	1397	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /!< 0x00001000 /
	1398	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /!< Debug Independent Watchdog stopped when Core is halted /
	1399	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
	1400	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /!< 0x00200000 /
	1401	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /!< I2C1 SMBUS timeout mode stopped when Core is halted /
	1402
	1403	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
	1404	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U)
	1405	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /!< 0x00000800 /
	1406	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /!< TIM1 counter stopped when core is halted /
	1407	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U)
	1408	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /!< 0x00010000 /
	1409	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /!< TIM15 counter stopped when core is halted /
	1410	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U)
	1411	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /!< 0x00020000 /
	1412	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /!< TIM16 counter stopped when core is halted /
	1413	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U)
	1414	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /!< 0x00040000 /
	1415	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /!< TIM17 counter stopped when core is halted /
	1416
	1417	/******************************************************************************/
	1418	/* */
	1419	/* DMA Controller (DMA) */
	1420	/* */
	1421	/******************************************************************************/
	1422	/***************** Bit definition for DMA_ISR register ******************/
	1423	#define DMA_ISR_GIF1_Pos (0U)
	1424	#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /!< 0x00000001 /
	1425	#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /!< Channel 1 Global interrupt flag /
	1426	#define DMA_ISR_TCIF1_Pos (1U)
	1427	#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /!< 0x00000002 /
	1428	#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /!< Channel 1 Transfer Complete flag /
	1429	#define DMA_ISR_HTIF1_Pos (2U)
	1430	#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /!< 0x00000004 /
	1431	#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /!< Channel 1 Half Transfer flag /
	1432	#define DMA_ISR_TEIF1_Pos (3U)
	1433	#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /!< 0x00000008 /
	1434	#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /!< Channel 1 Transfer Error flag /
	1435	#define DMA_ISR_GIF2_Pos (4U)
	1436	#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /!< 0x00000010 /
	1437	#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /!< Channel 2 Global interrupt flag /
	1438	#define DMA_ISR_TCIF2_Pos (5U)
	1439	#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /!< 0x00000020 /
	1440	#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /!< Channel 2 Transfer Complete flag /
	1441	#define DMA_ISR_HTIF2_Pos (6U)
	1442	#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /!< 0x00000040 /
	1443	#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /!< Channel 2 Half Transfer flag /
	1444	#define DMA_ISR_TEIF2_Pos (7U)
	1445	#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /!< 0x00000080 /
	1446	#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /!< Channel 2 Transfer Error flag /
	1447	#define DMA_ISR_GIF3_Pos (8U)
	1448	#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /!< 0x00000100 /
	1449	#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /!< Channel 3 Global interrupt flag /
	1450	#define DMA_ISR_TCIF3_Pos (9U)
	1451	#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /!< 0x00000200 /
	1452	#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /!< Channel 3 Transfer Complete flag /
	1453	#define DMA_ISR_HTIF3_Pos (10U)
	1454	#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /!< 0x00000400 /
	1455	#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /!< Channel 3 Half Transfer flag /
	1456	#define DMA_ISR_TEIF3_Pos (11U)
	1457	#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /!< 0x00000800 /
	1458	#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /!< Channel 3 Transfer Error flag /
	1459	#define DMA_ISR_GIF4_Pos (12U)
	1460	#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /!< 0x00001000 /
	1461	#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /!< Channel 4 Global interrupt flag /
	1462	#define DMA_ISR_TCIF4_Pos (13U)
	1463	#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /!< 0x00002000 /
	1464	#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /!< Channel 4 Transfer Complete flag /
	1465	#define DMA_ISR_HTIF4_Pos (14U)
	1466	#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /!< 0x00004000 /
	1467	#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /!< Channel 4 Half Transfer flag /
	1468	#define DMA_ISR_TEIF4_Pos (15U)
	1469	#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /!< 0x00008000 /
	1470	#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /!< Channel 4 Transfer Error flag /
	1471	#define DMA_ISR_GIF5_Pos (16U)
	1472	#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /!< 0x00010000 /
	1473	#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /!< Channel 5 Global interrupt flag /
	1474	#define DMA_ISR_TCIF5_Pos (17U)
	1475	#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /!< 0x00020000 /
	1476	#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /!< Channel 5 Transfer Complete flag /
	1477	#define DMA_ISR_HTIF5_Pos (18U)
	1478	#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /!< 0x00040000 /
	1479	#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /!< Channel 5 Half Transfer flag /
	1480	#define DMA_ISR_TEIF5_Pos (19U)
	1481	#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /!< 0x00080000 /
	1482	#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /!< Channel 5 Transfer Error flag /
	1483
	1484	/***************** Bit definition for DMA_IFCR register *****************/
	1485	#define DMA_IFCR_CGIF1_Pos (0U)
	1486	#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /!< 0x00000001 /
	1487	#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /!< Channel 1 Global interrupt clear /
	1488	#define DMA_IFCR_CTCIF1_Pos (1U)
	1489	#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /!< 0x00000002 /
	1490	#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /!< Channel 1 Transfer Complete clear /
	1491	#define DMA_IFCR_CHTIF1_Pos (2U)
	1492	#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /!< 0x00000004 /
	1493	#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /!< Channel 1 Half Transfer clear /
	1494	#define DMA_IFCR_CTEIF1_Pos (3U)
	1495	#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /!< 0x00000008 /
	1496	#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /!< Channel 1 Transfer Error clear /
	1497	#define DMA_IFCR_CGIF2_Pos (4U)
	1498	#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /!< 0x00000010 /
	1499	#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /!< Channel 2 Global interrupt clear /
	1500	#define DMA_IFCR_CTCIF2_Pos (5U)
	1501	#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /!< 0x00000020 /
	1502	#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /!< Channel 2 Transfer Complete clear /
	1503	#define DMA_IFCR_CHTIF2_Pos (6U)
	1504	#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /!< 0x00000040 /
	1505	#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /!< Channel 2 Half Transfer clear /
	1506	#define DMA_IFCR_CTEIF2_Pos (7U)
	1507	#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /!< 0x00000080 /
	1508	#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /!< Channel 2 Transfer Error clear /
	1509	#define DMA_IFCR_CGIF3_Pos (8U)
	1510	#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /!< 0x00000100 /
	1511	#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /!< Channel 3 Global interrupt clear /
	1512	#define DMA_IFCR_CTCIF3_Pos (9U)
	1513	#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /!< 0x00000200 /
	1514	#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /!< Channel 3 Transfer Complete clear /
	1515	#define DMA_IFCR_CHTIF3_Pos (10U)
	1516	#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /!< 0x00000400 /
	1517	#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /!< Channel 3 Half Transfer clear /
	1518	#define DMA_IFCR_CTEIF3_Pos (11U)
	1519	#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /!< 0x00000800 /
	1520	#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /!< Channel 3 Transfer Error clear /
	1521	#define DMA_IFCR_CGIF4_Pos (12U)
	1522	#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /!< 0x00001000 /
	1523	#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /!< Channel 4 Global interrupt clear /
	1524	#define DMA_IFCR_CTCIF4_Pos (13U)
	1525	#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /!< 0x00002000 /
	1526	#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /!< Channel 4 Transfer Complete clear /
	1527	#define DMA_IFCR_CHTIF4_Pos (14U)
	1528	#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /!< 0x00004000 /
	1529	#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /!< Channel 4 Half Transfer clear /
	1530	#define DMA_IFCR_CTEIF4_Pos (15U)
	1531	#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /!< 0x00008000 /
	1532	#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /!< Channel 4 Transfer Error clear /
	1533	#define DMA_IFCR_CGIF5_Pos (16U)
	1534	#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /!< 0x00010000 /
	1535	#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /!< Channel 5 Global interrupt clear /
	1536	#define DMA_IFCR_CTCIF5_Pos (17U)
	1537	#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /!< 0x00020000 /
	1538	#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /!< Channel 5 Transfer Complete clear /
	1539	#define DMA_IFCR_CHTIF5_Pos (18U)
	1540	#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /!< 0x00040000 /
	1541	#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /!< Channel 5 Half Transfer clear /
	1542	#define DMA_IFCR_CTEIF5_Pos (19U)
	1543	#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /!< 0x00080000 /
	1544	#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /!< Channel 5 Transfer Error clear /
	1545
	1546	/***************** Bit definition for DMA_CCR register ******************/
	1547	#define DMA_CCR_EN_Pos (0U)
	1548	#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /!< 0x00000001 /
	1549	#define DMA_CCR_EN DMA_CCR_EN_Msk /!< Channel enable /
	1550	#define DMA_CCR_TCIE_Pos (1U)
	1551	#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /!< 0x00000002 /
	1552	#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /!< Transfer complete interrupt enable /
	1553	#define DMA_CCR_HTIE_Pos (2U)
	1554	#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /!< 0x00000004 /
	1555	#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /!< Half Transfer interrupt enable /
	1556	#define DMA_CCR_TEIE_Pos (3U)
	1557	#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /!< 0x00000008 /
	1558	#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /!< Transfer error interrupt enable /
	1559	#define DMA_CCR_DIR_Pos (4U)
	1560	#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /!< 0x00000010 /
	1561	#define DMA_CCR_DIR DMA_CCR_DIR_Msk /!< Data transfer direction /
	1562	#define DMA_CCR_CIRC_Pos (5U)
	1563	#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /!< 0x00000020 /
	1564	#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /!< Circular mode /
	1565	#define DMA_CCR_PINC_Pos (6U)
	1566	#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /!< 0x00000040 /
	1567	#define DMA_CCR_PINC DMA_CCR_PINC_Msk /!< Peripheral increment mode /
	1568	#define DMA_CCR_MINC_Pos (7U)
	1569	#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /!< 0x00000080 /
	1570	#define DMA_CCR_MINC DMA_CCR_MINC_Msk /!< Memory increment mode /
	1571
	1572	#define DMA_CCR_PSIZE_Pos (8U)
	1573	#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /!< 0x00000300 /
	1574	#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /!< PSIZE[1:0] bits (Peripheral size) /
	1575	#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /!< 0x00000100 /
	1576	#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /!< 0x00000200 /
	1577
	1578	#define DMA_CCR_MSIZE_Pos (10U)
	1579	#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /!< 0x00000C00 /
	1580	#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /!< MSIZE[1:0] bits (Memory size) /
	1581	#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /!< 0x00000400 /
	1582	#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /!< 0x00000800 /
	1583
	1584	#define DMA_CCR_PL_Pos (12U)
	1585	#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /!< 0x00003000 /
	1586	#define DMA_CCR_PL DMA_CCR_PL_Msk /!< PL[1:0] bits(Channel Priority level)/
	1587	#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /!< 0x00001000 /
	1588	#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /!< 0x00002000 /
	1589
	1590	#define DMA_CCR_MEM2MEM_Pos (14U)
	1591	#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /!< 0x00004000 /
	1592	#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /!< Memory to memory mode /
	1593
	1594	/**************** Bit definition for DMA_CNDTR register *****************/
	1595	#define DMA_CNDTR_NDT_Pos (0U)
	1596	#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /!< 0x0000FFFF /
	1597	#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /!< Number of data to Transfer /
	1598
	1599	/**************** Bit definition for DMA_CPAR register ******************/
	1600	#define DMA_CPAR_PA_Pos (0U)
	1601	#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /!< 0xFFFFFFFF /
	1602	#define DMA_CPAR_PA DMA_CPAR_PA_Msk /!< Peripheral Address /
	1603
	1604	/**************** Bit definition for DMA_CMAR register ******************/
	1605	#define DMA_CMAR_MA_Pos (0U)
	1606	#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /!< 0xFFFFFFFF /
	1607	#define DMA_CMAR_MA DMA_CMAR_MA_Msk /!< Memory Address /
	1608
	1609	/******************************************************************************/
	1610	/* */
	1611	/* External Interrupt/Event Controller (EXTI) */
	1612	/* */
	1613	/******************************************************************************/
	1614	/***************** Bit definition for EXTI_IMR register *****************/
	1615	#define EXTI_IMR_MR0_Pos (0U)
	1616	#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /!< 0x00000001 /
	1617	#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /!< Interrupt Mask on line 0 /
	1618	#define EXTI_IMR_MR1_Pos (1U)
	1619	#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /!< 0x00000002 /
	1620	#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /!< Interrupt Mask on line 1 /
	1621	#define EXTI_IMR_MR2_Pos (2U)
	1622	#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /!< 0x00000004 /
	1623	#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /!< Interrupt Mask on line 2 /
	1624	#define EXTI_IMR_MR3_Pos (3U)
	1625	#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /!< 0x00000008 /
	1626	#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /!< Interrupt Mask on line 3 /
	1627	#define EXTI_IMR_MR4_Pos (4U)
	1628	#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /!< 0x00000010 /
	1629	#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /!< Interrupt Mask on line 4 /
	1630	#define EXTI_IMR_MR5_Pos (5U)
	1631	#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /!< 0x00000020 /
	1632	#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /!< Interrupt Mask on line 5 /
	1633	#define EXTI_IMR_MR6_Pos (6U)
	1634	#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /!< 0x00000040 /
	1635	#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /!< Interrupt Mask on line 6 /
	1636	#define EXTI_IMR_MR7_Pos (7U)
	1637	#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /!< 0x00000080 /
	1638	#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /!< Interrupt Mask on line 7 /
	1639	#define EXTI_IMR_MR8_Pos (8U)
	1640	#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /!< 0x00000100 /
	1641	#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /!< Interrupt Mask on line 8 /
	1642	#define EXTI_IMR_MR9_Pos (9U)
	1643	#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /!< 0x00000200 /
	1644	#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /!< Interrupt Mask on line 9 /
	1645	#define EXTI_IMR_MR10_Pos (10U)
	1646	#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /!< 0x00000400 /
	1647	#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /!< Interrupt Mask on line 10 /
	1648	#define EXTI_IMR_MR11_Pos (11U)
	1649	#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /!< 0x00000800 /
	1650	#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /!< Interrupt Mask on line 11 /
	1651	#define EXTI_IMR_MR12_Pos (12U)
	1652	#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /!< 0x00001000 /
	1653	#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /!< Interrupt Mask on line 12 /
	1654	#define EXTI_IMR_MR13_Pos (13U)
	1655	#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /!< 0x00002000 /
	1656	#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /!< Interrupt Mask on line 13 /
	1657	#define EXTI_IMR_MR14_Pos (14U)
	1658	#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /!< 0x00004000 /
	1659	#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /!< Interrupt Mask on line 14 /
	1660	#define EXTI_IMR_MR15_Pos (15U)
	1661	#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /!< 0x00008000 /
	1662	#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /!< Interrupt Mask on line 15 /
	1663	#define EXTI_IMR_MR16_Pos (16U)
	1664	#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /!< 0x00010000 /
	1665	#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /!< Interrupt Mask on line 16 /
	1666	#define EXTI_IMR_MR17_Pos (17U)
	1667	#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /!< 0x00020000 /
	1668	#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /!< Interrupt Mask on line 17 /
	1669	#define EXTI_IMR_MR18_Pos (18U)
	1670	#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /!< 0x00040000 /
	1671	#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /!< Interrupt Mask on line 18 /
	1672	#define EXTI_IMR_MR19_Pos (19U)
	1673	#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /!< 0x00080000 /
	1674	#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /!< Interrupt Mask on line 19 /
	1675	#define EXTI_IMR_MR21_Pos (21U)
	1676	#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /!< 0x00200000 /
	1677	#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /!< Interrupt Mask on line 21 /
	1678	#define EXTI_IMR_MR22_Pos (22U)
	1679	#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /!< 0x00400000 /
	1680	#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /!< Interrupt Mask on line 22 /
	1681	#define EXTI_IMR_MR23_Pos (23U)
	1682	#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /!< 0x00800000 /
	1683	#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /!< Interrupt Mask on line 23 /
	1684	#define EXTI_IMR_MR25_Pos (25U)
	1685	#define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /!< 0x02000000 /
	1686	#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /!< Interrupt Mask on line 25 /
	1687	#define EXTI_IMR_MR27_Pos (27U)
	1688	#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /!< 0x08000000 /
	1689	#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /!< Interrupt Mask on line 27 /
	1690
	1691	/* References Defines */
	1692	#define EXTI_IMR_IM0 EXTI_IMR_MR0
	1693	#define EXTI_IMR_IM1 EXTI_IMR_MR1
	1694	#define EXTI_IMR_IM2 EXTI_IMR_MR2
	1695	#define EXTI_IMR_IM3 EXTI_IMR_MR3
	1696	#define EXTI_IMR_IM4 EXTI_IMR_MR4
	1697	#define EXTI_IMR_IM5 EXTI_IMR_MR5
	1698	#define EXTI_IMR_IM6 EXTI_IMR_MR6
	1699	#define EXTI_IMR_IM7 EXTI_IMR_MR7
	1700	#define EXTI_IMR_IM8 EXTI_IMR_MR8
	1701	#define EXTI_IMR_IM9 EXTI_IMR_MR9
	1702	#define EXTI_IMR_IM10 EXTI_IMR_MR10
	1703	#define EXTI_IMR_IM11 EXTI_IMR_MR11
	1704	#define EXTI_IMR_IM12 EXTI_IMR_MR12
	1705	#define EXTI_IMR_IM13 EXTI_IMR_MR13
	1706	#define EXTI_IMR_IM14 EXTI_IMR_MR14
	1707	#define EXTI_IMR_IM15 EXTI_IMR_MR15
	1708	#define EXTI_IMR_IM16 EXTI_IMR_MR16
	1709	#define EXTI_IMR_IM17 EXTI_IMR_MR17
	1710	#define EXTI_IMR_IM18 EXTI_IMR_MR18
	1711	#define EXTI_IMR_IM19 EXTI_IMR_MR19
	1712	#define EXTI_IMR_IM21 EXTI_IMR_MR21
	1713	#define EXTI_IMR_IM22 EXTI_IMR_MR22
	1714	#define EXTI_IMR_IM23 EXTI_IMR_MR23
	1715	#define EXTI_IMR_IM25 EXTI_IMR_MR25
	1716	#define EXTI_IMR_IM27 EXTI_IMR_MR27
	1717
	1718	#define EXTI_IMR_IM_Pos (0U)
	1719	#define EXTI_IMR_IM_Msk (0xAEFFFFFU << EXTI_IMR_IM_Pos) /!< 0x0AEFFFFF /
	1720	#define EXTI_IMR_IM EXTI_IMR_IM_Msk /!< Interrupt Mask All /
	1721
	1722
	1723	/**************** Bit definition for EXTI_EMR register ******************/
	1724	#define EXTI_EMR_MR0_Pos (0U)
	1725	#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /!< 0x00000001 /
	1726	#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /!< Event Mask on line 0 /
	1727	#define EXTI_EMR_MR1_Pos (1U)
	1728	#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /!< 0x00000002 /
	1729	#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /!< Event Mask on line 1 /
	1730	#define EXTI_EMR_MR2_Pos (2U)
	1731	#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /!< 0x00000004 /
	1732	#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /!< Event Mask on line 2 /
	1733	#define EXTI_EMR_MR3_Pos (3U)
	1734	#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /!< 0x00000008 /
	1735	#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /!< Event Mask on line 3 /
	1736	#define EXTI_EMR_MR4_Pos (4U)
	1737	#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /!< 0x00000010 /
	1738	#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /!< Event Mask on line 4 /
	1739	#define EXTI_EMR_MR5_Pos (5U)
	1740	#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /!< 0x00000020 /
	1741	#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /!< Event Mask on line 5 /
	1742	#define EXTI_EMR_MR6_Pos (6U)
	1743	#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /!< 0x00000040 /
	1744	#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /!< Event Mask on line 6 /
	1745	#define EXTI_EMR_MR7_Pos (7U)
	1746	#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /!< 0x00000080 /
	1747	#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /!< Event Mask on line 7 /
	1748	#define EXTI_EMR_MR8_Pos (8U)
	1749	#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /!< 0x00000100 /
	1750	#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /!< Event Mask on line 8 /
	1751	#define EXTI_EMR_MR9_Pos (9U)
	1752	#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /!< 0x00000200 /
	1753	#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /!< Event Mask on line 9 /
	1754	#define EXTI_EMR_MR10_Pos (10U)
	1755	#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /!< 0x00000400 /
	1756	#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /!< Event Mask on line 10 /
	1757	#define EXTI_EMR_MR11_Pos (11U)
	1758	#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /!< 0x00000800 /
	1759	#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /!< Event Mask on line 11 /
	1760	#define EXTI_EMR_MR12_Pos (12U)
	1761	#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /!< 0x00001000 /
	1762	#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /!< Event Mask on line 12 /
	1763	#define EXTI_EMR_MR13_Pos (13U)
	1764	#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /!< 0x00002000 /
	1765	#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /!< Event Mask on line 13 /
	1766	#define EXTI_EMR_MR14_Pos (14U)
	1767	#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /!< 0x00004000 /
	1768	#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /!< Event Mask on line 14 /
	1769	#define EXTI_EMR_MR15_Pos (15U)
	1770	#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /!< 0x00008000 /
	1771	#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /!< Event Mask on line 15 /
	1772	#define EXTI_EMR_MR16_Pos (16U)
	1773	#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /!< 0x00010000 /
	1774	#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /!< Event Mask on line 16 /
	1775	#define EXTI_EMR_MR17_Pos (17U)
	1776	#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /!< 0x00020000 /
	1777	#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /!< Event Mask on line 17 /
	1778	#define EXTI_EMR_MR18_Pos (18U)
	1779	#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /!< 0x00040000 /
	1780	#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /!< Event Mask on line 18 /
	1781	#define EXTI_EMR_MR19_Pos (19U)
	1782	#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /!< 0x00080000 /
	1783	#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /!< Event Mask on line 19 /
	1784	#define EXTI_EMR_MR21_Pos (21U)
	1785	#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /!< 0x00200000 /
	1786	#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /!< Event Mask on line 21 /
	1787	#define EXTI_EMR_MR22_Pos (22U)
	1788	#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /!< 0x00400000 /
	1789	#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /!< Event Mask on line 22 /
	1790	#define EXTI_EMR_MR23_Pos (23U)
	1791	#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /!< 0x00800000 /
	1792	#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /!< Event Mask on line 23 /
	1793	#define EXTI_EMR_MR25_Pos (25U)
	1794	#define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /!< 0x02000000 /
	1795	#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /!< Event Mask on line 25 /
	1796	#define EXTI_EMR_MR27_Pos (27U)
	1797	#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /!< 0x08000000 /
	1798	#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /!< Event Mask on line 27 /
	1799
	1800	/* References Defines */
	1801	#define EXTI_EMR_EM0 EXTI_EMR_MR0
	1802	#define EXTI_EMR_EM1 EXTI_EMR_MR1
	1803	#define EXTI_EMR_EM2 EXTI_EMR_MR2
	1804	#define EXTI_EMR_EM3 EXTI_EMR_MR3
	1805	#define EXTI_EMR_EM4 EXTI_EMR_MR4
	1806	#define EXTI_EMR_EM5 EXTI_EMR_MR5
	1807	#define EXTI_EMR_EM6 EXTI_EMR_MR6
	1808	#define EXTI_EMR_EM7 EXTI_EMR_MR7
	1809	#define EXTI_EMR_EM8 EXTI_EMR_MR8
	1810	#define EXTI_EMR_EM9 EXTI_EMR_MR9
	1811	#define EXTI_EMR_EM10 EXTI_EMR_MR10
	1812	#define EXTI_EMR_EM11 EXTI_EMR_MR11
	1813	#define EXTI_EMR_EM12 EXTI_EMR_MR12
	1814	#define EXTI_EMR_EM13 EXTI_EMR_MR13
	1815	#define EXTI_EMR_EM14 EXTI_EMR_MR14
	1816	#define EXTI_EMR_EM15 EXTI_EMR_MR15
	1817	#define EXTI_EMR_EM16 EXTI_EMR_MR16
	1818	#define EXTI_EMR_EM17 EXTI_EMR_MR17
	1819	#define EXTI_EMR_EM18 EXTI_EMR_MR18
	1820	#define EXTI_EMR_EM19 EXTI_EMR_MR19
	1821	#define EXTI_EMR_EM21 EXTI_EMR_MR21
	1822	#define EXTI_EMR_EM22 EXTI_EMR_MR22
	1823	#define EXTI_EMR_EM23 EXTI_EMR_MR23
	1824	#define EXTI_EMR_EM25 EXTI_EMR_MR25
	1825	#define EXTI_EMR_EM27 EXTI_EMR_MR27
	1826
	1827	/***************** Bit definition for EXTI_RTSR register ****************/
	1828	#define EXTI_RTSR_TR0_Pos (0U)
	1829	#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /!< 0x00000001 /
	1830	#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /!< Rising trigger event configuration bit of line 0 /
	1831	#define EXTI_RTSR_TR1_Pos (1U)
	1832	#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /!< 0x00000002 /
	1833	#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /!< Rising trigger event configuration bit of line 1 /
	1834	#define EXTI_RTSR_TR2_Pos (2U)
	1835	#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /!< 0x00000004 /
	1836	#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /!< Rising trigger event configuration bit of line 2 /
	1837	#define EXTI_RTSR_TR3_Pos (3U)
	1838	#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /!< 0x00000008 /
	1839	#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /!< Rising trigger event configuration bit of line 3 /
	1840	#define EXTI_RTSR_TR4_Pos (4U)
	1841	#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /!< 0x00000010 /
	1842	#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /!< Rising trigger event configuration bit of line 4 /
	1843	#define EXTI_RTSR_TR5_Pos (5U)
	1844	#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /!< 0x00000020 /
	1845	#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /!< Rising trigger event configuration bit of line 5 /
	1846	#define EXTI_RTSR_TR6_Pos (6U)
	1847	#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /!< 0x00000040 /
	1848	#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /!< Rising trigger event configuration bit of line 6 /
	1849	#define EXTI_RTSR_TR7_Pos (7U)
	1850	#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /!< 0x00000080 /
	1851	#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /!< Rising trigger event configuration bit of line 7 /
	1852	#define EXTI_RTSR_TR8_Pos (8U)
	1853	#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /!< 0x00000100 /
	1854	#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /!< Rising trigger event configuration bit of line 8 /
	1855	#define EXTI_RTSR_TR9_Pos (9U)
	1856	#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /!< 0x00000200 /
	1857	#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /!< Rising trigger event configuration bit of line 9 /
	1858	#define EXTI_RTSR_TR10_Pos (10U)
	1859	#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /!< 0x00000400 /
	1860	#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /!< Rising trigger event configuration bit of line 10 /
	1861	#define EXTI_RTSR_TR11_Pos (11U)
	1862	#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /!< 0x00000800 /
	1863	#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /!< Rising trigger event configuration bit of line 11 /
	1864	#define EXTI_RTSR_TR12_Pos (12U)
	1865	#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /!< 0x00001000 /
	1866	#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /!< Rising trigger event configuration bit of line 12 /
	1867	#define EXTI_RTSR_TR13_Pos (13U)
	1868	#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /!< 0x00002000 /
	1869	#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /!< Rising trigger event configuration bit of line 13 /
	1870	#define EXTI_RTSR_TR14_Pos (14U)
	1871	#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /!< 0x00004000 /
	1872	#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /!< Rising trigger event configuration bit of line 14 /
	1873	#define EXTI_RTSR_TR15_Pos (15U)
	1874	#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /!< 0x00008000 /
	1875	#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /!< Rising trigger event configuration bit of line 15 /
	1876	#define EXTI_RTSR_TR16_Pos (16U)
	1877	#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /!< 0x00010000 /
	1878	#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /!< Rising trigger event configuration bit of line 16 /
	1879	#define EXTI_RTSR_TR17_Pos (17U)
	1880	#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /!< 0x00020000 /
	1881	#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /!< Rising trigger event configuration bit of line 17 /
	1882	#define EXTI_RTSR_TR19_Pos (19U)
	1883	#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /!< 0x00080000 /
	1884	#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /!< Rising trigger event configuration bit of line 19 /
	1885	#define EXTI_RTSR_TR21_Pos (21U)
	1886	#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /!< 0x00200000 /
	1887	#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /!< Rising trigger event configuration bit of line 21 /
	1888	#define EXTI_RTSR_TR22_Pos (22U)
	1889	#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /!< 0x00400000 /
	1890	#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /!< Rising trigger event configuration bit of line 22 /
	1891
	1892	/* References Defines */
	1893	#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
	1894	#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
	1895	#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
	1896	#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
	1897	#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
	1898	#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
	1899	#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
	1900	#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
	1901	#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
	1902	#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
	1903	#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
	1904	#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
	1905	#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
	1906	#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
	1907	#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
	1908	#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
	1909	#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
	1910	#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
	1911	#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
	1912	#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
	1913	#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
	1914
	1915	/***************** Bit definition for EXTI_FTSR register *****************/
	1916	#define EXTI_FTSR_TR0_Pos (0U)
	1917	#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /!< 0x00000001 /
	1918	#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /!< Falling trigger event configuration bit of line 0 /
	1919	#define EXTI_FTSR_TR1_Pos (1U)
	1920	#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /!< 0x00000002 /
	1921	#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /!< Falling trigger event configuration bit of line 1 /
	1922	#define EXTI_FTSR_TR2_Pos (2U)
	1923	#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /!< 0x00000004 /
	1924	#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /!< Falling trigger event configuration bit of line 2 /
	1925	#define EXTI_FTSR_TR3_Pos (3U)
	1926	#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /!< 0x00000008 /
	1927	#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /!< Falling trigger event configuration bit of line 3 /
	1928	#define EXTI_FTSR_TR4_Pos (4U)
	1929	#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /!< 0x00000010 /
	1930	#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /!< Falling trigger event configuration bit of line 4 /
	1931	#define EXTI_FTSR_TR5_Pos (5U)
	1932	#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /!< 0x00000020 /
	1933	#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /!< Falling trigger event configuration bit of line 5 /
	1934	#define EXTI_FTSR_TR6_Pos (6U)
	1935	#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /!< 0x00000040 /
	1936	#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /!< Falling trigger event configuration bit of line 6 /
	1937	#define EXTI_FTSR_TR7_Pos (7U)
	1938	#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /!< 0x00000080 /
	1939	#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /!< Falling trigger event configuration bit of line 7 /
	1940	#define EXTI_FTSR_TR8_Pos (8U)
	1941	#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /!< 0x00000100 /
	1942	#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /!< Falling trigger event configuration bit of line 8 /
	1943	#define EXTI_FTSR_TR9_Pos (9U)
	1944	#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /!< 0x00000200 /
	1945	#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /!< Falling trigger event configuration bit of line 9 /
	1946	#define EXTI_FTSR_TR10_Pos (10U)
	1947	#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /!< 0x00000400 /
	1948	#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /!< Falling trigger event configuration bit of line 10 /
	1949	#define EXTI_FTSR_TR11_Pos (11U)
	1950	#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /!< 0x00000800 /
	1951	#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /!< Falling trigger event configuration bit of line 11 /
	1952	#define EXTI_FTSR_TR12_Pos (12U)
	1953	#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /!< 0x00001000 /
	1954	#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /!< Falling trigger event configuration bit of line 12 /
	1955	#define EXTI_FTSR_TR13_Pos (13U)
	1956	#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /!< 0x00002000 /
	1957	#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /!< Falling trigger event configuration bit of line 13 /
	1958	#define EXTI_FTSR_TR14_Pos (14U)
	1959	#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /!< 0x00004000 /
	1960	#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /!< Falling trigger event configuration bit of line 14 /
	1961	#define EXTI_FTSR_TR15_Pos (15U)
	1962	#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /!< 0x00008000 /
	1963	#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /!< Falling trigger event configuration bit of line 15 /
	1964	#define EXTI_FTSR_TR16_Pos (16U)
	1965	#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /!< 0x00010000 /
	1966	#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /!< Falling trigger event configuration bit of line 16 /
	1967	#define EXTI_FTSR_TR17_Pos (17U)
	1968	#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /!< 0x00020000 /
	1969	#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /!< Falling trigger event configuration bit of line 17 /
	1970	#define EXTI_FTSR_TR19_Pos (19U)
	1971	#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /!< 0x00080000 /
	1972	#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /!< Falling trigger event configuration bit of line 19 /
	1973	#define EXTI_FTSR_TR21_Pos (21U)
	1974	#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /!< 0x00200000 /
	1975	#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /!< Falling trigger event configuration bit of line 21 /
	1976	#define EXTI_FTSR_TR22_Pos (22U)
	1977	#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /!< 0x00400000 /
	1978	#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /!< Falling trigger event configuration bit of line 22 /
	1979
	1980	/* References Defines */
	1981	#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
	1982	#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
	1983	#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
	1984	#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
	1985	#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
	1986	#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
	1987	#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
	1988	#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
	1989	#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
	1990	#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
	1991	#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
	1992	#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
	1993	#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
	1994	#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
	1995	#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
	1996	#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
	1997	#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
	1998	#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
	1999	#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
	2000	#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
	2001	#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
	2002
	2003	/***************** Bit definition for EXTI_SWIER register *****************/
	2004	#define EXTI_SWIER_SWIER0_Pos (0U)
	2005	#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /!< 0x00000001 /
	2006	#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /!< Software Interrupt on line 0 /
	2007	#define EXTI_SWIER_SWIER1_Pos (1U)
	2008	#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /!< 0x00000002 /
	2009	#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /!< Software Interrupt on line 1 /
	2010	#define EXTI_SWIER_SWIER2_Pos (2U)
	2011	#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /!< 0x00000004 /
	2012	#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /!< Software Interrupt on line 2 /
	2013	#define EXTI_SWIER_SWIER3_Pos (3U)
	2014	#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /!< 0x00000008 /
	2015	#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /!< Software Interrupt on line 3 /
	2016	#define EXTI_SWIER_SWIER4_Pos (4U)
	2017	#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /!< 0x00000010 /
	2018	#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /!< Software Interrupt on line 4 /
	2019	#define EXTI_SWIER_SWIER5_Pos (5U)
	2020	#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /!< 0x00000020 /
	2021	#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /!< Software Interrupt on line 5 /
	2022	#define EXTI_SWIER_SWIER6_Pos (6U)
	2023	#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /!< 0x00000040 /
	2024	#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /!< Software Interrupt on line 6 /
	2025	#define EXTI_SWIER_SWIER7_Pos (7U)
	2026	#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /!< 0x00000080 /
	2027	#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /!< Software Interrupt on line 7 /
	2028	#define EXTI_SWIER_SWIER8_Pos (8U)
	2029	#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /!< 0x00000100 /
	2030	#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /!< Software Interrupt on line 8 /
	2031	#define EXTI_SWIER_SWIER9_Pos (9U)
	2032	#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /!< 0x00000200 /
	2033	#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /!< Software Interrupt on line 9 /
	2034	#define EXTI_SWIER_SWIER10_Pos (10U)
	2035	#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /!< 0x00000400 /
	2036	#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /!< Software Interrupt on line 10 /
	2037	#define EXTI_SWIER_SWIER11_Pos (11U)
	2038	#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /!< 0x00000800 /
	2039	#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /!< Software Interrupt on line 11 /
	2040	#define EXTI_SWIER_SWIER12_Pos (12U)
	2041	#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /!< 0x00001000 /
	2042	#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /!< Software Interrupt on line 12 /
	2043	#define EXTI_SWIER_SWIER13_Pos (13U)
	2044	#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /!< 0x00002000 /
	2045	#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /!< Software Interrupt on line 13 /
	2046	#define EXTI_SWIER_SWIER14_Pos (14U)
	2047	#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /!< 0x00004000 /
	2048	#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /!< Software Interrupt on line 14 /
	2049	#define EXTI_SWIER_SWIER15_Pos (15U)
	2050	#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /!< 0x00008000 /
	2051	#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /!< Software Interrupt on line 15 /
	2052	#define EXTI_SWIER_SWIER16_Pos (16U)
	2053	#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /!< 0x00010000 /
	2054	#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /!< Software Interrupt on line 16 /
	2055	#define EXTI_SWIER_SWIER17_Pos (17U)
	2056	#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /!< 0x00020000 /
	2057	#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /!< Software Interrupt on line 17 /
	2058	#define EXTI_SWIER_SWIER19_Pos (19U)
	2059	#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /!< 0x00080000 /
	2060	#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /!< Software Interrupt on line 19 /
	2061	#define EXTI_SWIER_SWIER21_Pos (21U)
	2062	#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /!< 0x00200000 /
	2063	#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /!< Software Interrupt on line 21 /
	2064	#define EXTI_SWIER_SWIER22_Pos (22U)
	2065	#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /!< 0x00400000 /
	2066	#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /!< Software Interrupt on line 22 /
	2067
	2068	/* References Defines */
	2069	#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
	2070	#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
	2071	#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
	2072	#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
	2073	#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
	2074	#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
	2075	#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
	2076	#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
	2077	#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
	2078	#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
	2079	#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
	2080	#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
	2081	#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
	2082	#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
	2083	#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
	2084	#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
	2085	#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
	2086	#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
	2087	#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
	2088	#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
	2089	#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
	2090
	2091	/**************** Bit definition for EXTI_PR register *******************/
	2092	#define EXTI_PR_PR0_Pos (0U)
	2093	#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /!< 0x00000001 /
	2094	#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /!< Pending bit 0 /
	2095	#define EXTI_PR_PR1_Pos (1U)
	2096	#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /!< 0x00000002 /
	2097	#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /!< Pending bit 1 /
	2098	#define EXTI_PR_PR2_Pos (2U)
	2099	#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /!< 0x00000004 /
	2100	#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /!< Pending bit 2 /
	2101	#define EXTI_PR_PR3_Pos (3U)
	2102	#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /!< 0x00000008 /
	2103	#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /!< Pending bit 3 /
	2104	#define EXTI_PR_PR4_Pos (4U)
	2105	#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /!< 0x00000010 /
	2106	#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /!< Pending bit 4 /
	2107	#define EXTI_PR_PR5_Pos (5U)
	2108	#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /!< 0x00000020 /
	2109	#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /!< Pending bit 5 /
	2110	#define EXTI_PR_PR6_Pos (6U)
	2111	#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /!< 0x00000040 /
	2112	#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /!< Pending bit 6 /
	2113	#define EXTI_PR_PR7_Pos (7U)
	2114	#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /!< 0x00000080 /
	2115	#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /!< Pending bit 7 /
	2116	#define EXTI_PR_PR8_Pos (8U)
	2117	#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /!< 0x00000100 /
	2118	#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /!< Pending bit 8 /
	2119	#define EXTI_PR_PR9_Pos (9U)
	2120	#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /!< 0x00000200 /
	2121	#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /!< Pending bit 9 /
	2122	#define EXTI_PR_PR10_Pos (10U)
	2123	#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /!< 0x00000400 /
	2124	#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /!< Pending bit 10 /
	2125	#define EXTI_PR_PR11_Pos (11U)
	2126	#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /!< 0x00000800 /
	2127	#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /!< Pending bit 11 /
	2128	#define EXTI_PR_PR12_Pos (12U)
	2129	#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /!< 0x00001000 /
	2130	#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /!< Pending bit 12 /
	2131	#define EXTI_PR_PR13_Pos (13U)
	2132	#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /!< 0x00002000 /
	2133	#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /!< Pending bit 13 /
	2134	#define EXTI_PR_PR14_Pos (14U)
	2135	#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /!< 0x00004000 /
	2136	#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /!< Pending bit 14 /
	2137	#define EXTI_PR_PR15_Pos (15U)
	2138	#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /!< 0x00008000 /
	2139	#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /!< Pending bit 15 /
	2140	#define EXTI_PR_PR16_Pos (16U)
	2141	#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /!< 0x00010000 /
	2142	#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /!< Pending bit 16 /
	2143	#define EXTI_PR_PR17_Pos (17U)
	2144	#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /!< 0x00020000 /
	2145	#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /!< Pending bit 17 /
	2146	#define EXTI_PR_PR19_Pos (19U)
	2147	#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /!< 0x00080000 /
	2148	#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /!< Pending bit 19 /
	2149	#define EXTI_PR_PR21_Pos (21U)
	2150	#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /!< 0x00200000 /
	2151	#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /!< Pending bit 21 /
	2152	#define EXTI_PR_PR22_Pos (22U)
	2153	#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /!< 0x00400000 /
	2154	#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /!< Pending bit 22 /
	2155
	2156	/* References Defines */
	2157	#define EXTI_PR_PIF0 EXTI_PR_PR0
	2158	#define EXTI_PR_PIF1 EXTI_PR_PR1
	2159	#define EXTI_PR_PIF2 EXTI_PR_PR2
	2160	#define EXTI_PR_PIF3 EXTI_PR_PR3
	2161	#define EXTI_PR_PIF4 EXTI_PR_PR4
	2162	#define EXTI_PR_PIF5 EXTI_PR_PR5
	2163	#define EXTI_PR_PIF6 EXTI_PR_PR6
	2164	#define EXTI_PR_PIF7 EXTI_PR_PR7
	2165	#define EXTI_PR_PIF8 EXTI_PR_PR8
	2166	#define EXTI_PR_PIF9 EXTI_PR_PR9
	2167	#define EXTI_PR_PIF10 EXTI_PR_PR10
	2168	#define EXTI_PR_PIF11 EXTI_PR_PR11
	2169	#define EXTI_PR_PIF12 EXTI_PR_PR12
	2170	#define EXTI_PR_PIF13 EXTI_PR_PR13
	2171	#define EXTI_PR_PIF14 EXTI_PR_PR14
	2172	#define EXTI_PR_PIF15 EXTI_PR_PR15
	2173	#define EXTI_PR_PIF16 EXTI_PR_PR16
	2174	#define EXTI_PR_PIF17 EXTI_PR_PR17
	2175	#define EXTI_PR_PIF19 EXTI_PR_PR19
	2176	#define EXTI_PR_PIF21 EXTI_PR_PR21
	2177	#define EXTI_PR_PIF22 EXTI_PR_PR22
	2178
	2179	/******************************************************************************/
	2180	/* */
	2181	/* FLASH and Option Bytes Registers */
	2182	/* */
	2183	/******************************************************************************/
	2184
	2185	/***************** Bit definition for FLASH_ACR register ****************/
	2186	#define FLASH_ACR_LATENCY_Pos (0U)
	2187	#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /!< 0x00000001 /
	2188	#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /!< LATENCY bit (Latency) /
	2189
	2190	#define FLASH_ACR_PRFTBE_Pos (4U)
	2191	#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /!< 0x00000010 /
	2192	#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /!< Prefetch Buffer Enable /
	2193	#define FLASH_ACR_PRFTBS_Pos (5U)
	2194	#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /!< 0x00000020 /
	2195	#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /!< Prefetch Buffer Status /
	2196
	2197	/**************** Bit definition for FLASH_KEYR register ****************/
	2198	#define FLASH_KEYR_FKEYR_Pos (0U)
	2199	#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /!< 0xFFFFFFFF /
	2200	#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /!< FPEC Key /
	2201
	2202	/*************** Bit definition for FLASH_OPTKEYR register **************/
	2203	#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
	2204	#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /!< 0xFFFFFFFF /
	2205	#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /!< Option Byte Key /
	2206
	2207	/**************** FLASH Keys ********************************************/
	2208	#define FLASH_KEY1_Pos (0U)
	2209	#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /!< 0x45670123 /
	2210	#define FLASH_KEY1 FLASH_KEY1_Msk /!< Flash program erase key1 /
	2211	#define FLASH_KEY2_Pos (0U)
	2212	#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /!< 0xCDEF89AB /
	2213	#define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1
	2214	to unlock the write access to the FPEC. */
	2215
	2216	#define FLASH_OPTKEY1_Pos (0U)
	2217	#define FLASH_OPTKEY1_Msk (0x45670123U << FLASH_OPTKEY1_Pos) /!< 0x45670123 /
	2218	#define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /!< Flash option key1 /
	2219	#define FLASH_OPTKEY2_Pos (0U)
	2220	#define FLASH_OPTKEY2_Msk (0xCDEF89ABU << FLASH_OPTKEY2_Pos) /!< 0xCDEF89AB /
	2221	#define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to
	2222	unlock the write access to the option byte block */
	2223
	2224	/**************** Bit definition for FLASH_SR register *****************/
	2225	#define FLASH_SR_BSY_Pos (0U)
	2226	#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /!< 0x00000001 /
	2227	#define FLASH_SR_BSY FLASH_SR_BSY_Msk /!< Busy /
	2228	#define FLASH_SR_PGERR_Pos (2U)
	2229	#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /!< 0x00000004 /
	2230	#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /!< Programming Error /
	2231	#define FLASH_SR_WRPRTERR_Pos (4U)
	2232	#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /!< 0x00000010 /
	2233	#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /!< Write Protection Error /
	2234	#define FLASH_SR_EOP_Pos (5U)
	2235	#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /!< 0x00000020 /
	2236	#define FLASH_SR_EOP FLASH_SR_EOP_Msk /!< End of operation /
	2237	#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /!< Legacy of Write Protection Error /
	2238
	2239	/***************** Bit definition for FLASH_CR register *****************/
	2240	#define FLASH_CR_PG_Pos (0U)
	2241	#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /!< 0x00000001 /
	2242	#define FLASH_CR_PG FLASH_CR_PG_Msk /!< Programming /
	2243	#define FLASH_CR_PER_Pos (1U)
	2244	#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /!< 0x00000002 /
	2245	#define FLASH_CR_PER FLASH_CR_PER_Msk /!< Page Erase /
	2246	#define FLASH_CR_MER_Pos (2U)
	2247	#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /!< 0x00000004 /
	2248	#define FLASH_CR_MER FLASH_CR_MER_Msk /!< Mass Erase /
	2249	#define FLASH_CR_OPTPG_Pos (4U)
	2250	#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /!< 0x00000010 /
	2251	#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /!< Option Byte Programming /
	2252	#define FLASH_CR_OPTER_Pos (5U)
	2253	#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /!< 0x00000020 /
	2254	#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /!< Option Byte Erase /
	2255	#define FLASH_CR_STRT_Pos (6U)
	2256	#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /!< 0x00000040 /
	2257	#define FLASH_CR_STRT FLASH_CR_STRT_Msk /!< Start /
	2258	#define FLASH_CR_LOCK_Pos (7U)
	2259	#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /!< 0x00000080 /
	2260	#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /!< Lock /
	2261	#define FLASH_CR_OPTWRE_Pos (9U)
	2262	#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /!< 0x00000200 /
	2263	#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /!< Option Bytes Write Enable /
	2264	#define FLASH_CR_ERRIE_Pos (10U)
	2265	#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /!< 0x00000400 /
	2266	#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /!< Error Interrupt Enable /
	2267	#define FLASH_CR_EOPIE_Pos (12U)
	2268	#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /!< 0x00001000 /
	2269	#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /!< End of operation interrupt enable /
	2270	#define FLASH_CR_OBL_LAUNCH_Pos (13U)
	2271	#define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /!< 0x00002000 /
	2272	#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /!< Option Bytes Loader Launch /
	2273
	2274	/***************** Bit definition for FLASH_AR register *****************/
	2275	#define FLASH_AR_FAR_Pos (0U)
	2276	#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /!< 0xFFFFFFFF /
	2277	#define FLASH_AR_FAR FLASH_AR_FAR_Msk /!< Flash Address /
	2278
	2279	/**************** Bit definition for FLASH_OBR register *****************/
	2280	#define FLASH_OBR_OPTERR_Pos (0U)
	2281	#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /!< 0x00000001 /
	2282	#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /!< Option Byte Error /
	2283	#define FLASH_OBR_RDPRT1_Pos (1U)
	2284	#define FLASH_OBR_RDPRT1_Msk (0x1U << FLASH_OBR_RDPRT1_Pos) /!< 0x00000002 /
	2285	#define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /!< Read protection Level 1 /
	2286	#define FLASH_OBR_RDPRT2_Pos (2U)
	2287	#define FLASH_OBR_RDPRT2_Msk (0x1U << FLASH_OBR_RDPRT2_Pos) /!< 0x00000004 /
	2288	#define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /!< Read protection Level 2 /
	2289
	2290	#define FLASH_OBR_USER_Pos (8U)
	2291	#define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /!< 0x00007700 /
	2292	#define FLASH_OBR_USER FLASH_OBR_USER_Msk /!< User Option Bytes /
	2293	#define FLASH_OBR_IWDG_SW_Pos (8U)
	2294	#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /!< 0x00000100 /
	2295	#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /!< IWDG SW /
	2296	#define FLASH_OBR_nRST_STOP_Pos (9U)
	2297	#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /!< 0x00000200 /
	2298	#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /!< nRST_STOP /
	2299	#define FLASH_OBR_nRST_STDBY_Pos (10U)
	2300	#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /!< 0x00000400 /
	2301	#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /!< nRST_STDBY /
	2302	#define FLASH_OBR_nBOOT1_Pos (12U)
	2303	#define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /!< 0x00001000 /
	2304	#define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /!< nBOOT1 /
	2305	#define FLASH_OBR_VDDA_MONITOR_Pos (13U)
	2306	#define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /!< 0x00002000 /
	2307	#define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /!< VDDA power supply supervisor /
	2308	#define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U)
	2309	#define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /!< 0x00004000 /
	2310	#define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /!< RAM parity check /
	2311	#define FLASH_OBR_DATA0_Pos (16U)
	2312	#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /!< 0x00FF0000 /
	2313	#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /!< Data0 /
	2314	#define FLASH_OBR_DATA1_Pos (24U)
	2315	#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /!< 0xFF000000 /
	2316	#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /!< Data1 /
	2317
	2318	/* Old BOOT1 bit definition, maintained for legacy purpose */
	2319	#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
	2320
	2321	/* Old OBR_VDDA bit definition, maintained for legacy purpose */
	2322	#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
	2323
	2324	/**************** Bit definition for FLASH_WRPR register ****************/
	2325	#define FLASH_WRPR_WRP_Pos (0U)
	2326	#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /!< 0x0000FFFF /
	2327	#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /!< Write Protect /
	2328
	2329	/----------------------------------------------------------------------------/
	2330
	2331	/**************** Bit definition for OB_RDP register ********************/
	2332	#define OB_RDP_RDP_Pos (0U)
	2333	#define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /!< 0x000000FF /
	2334	#define OB_RDP_RDP OB_RDP_RDP_Msk /!< Read protection option byte /
	2335	#define OB_RDP_nRDP_Pos (8U)
	2336	#define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /!< 0x0000FF00 /
	2337	#define OB_RDP_nRDP OB_RDP_nRDP_Msk /!< Read protection complemented option byte /
	2338
	2339	/**************** Bit definition for OB_USER register *******************/
	2340	#define OB_USER_USER_Pos (16U)
	2341	#define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /!< 0x00FF0000 /
	2342	#define OB_USER_USER OB_USER_USER_Msk /!< User option byte /
	2343	#define OB_USER_nUSER_Pos (24U)
	2344	#define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /!< 0xFF000000 /
	2345	#define OB_USER_nUSER OB_USER_nUSER_Msk /!< User complemented option byte /
	2346
	2347	/**************** Bit definition for OB_WRP0 register *******************/
	2348	#define OB_WRP0_WRP0_Pos (0U)
	2349	#define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /!< 0x000000FF /
	2350	#define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /!< Flash memory write protection option bytes /
	2351	#define OB_WRP0_nWRP0_Pos (8U)
	2352	#define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /!< 0x0000FF00 /
	2353	#define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /!< Flash memory write protection complemented option bytes /
	2354
	2355	/**************** Bit definition for OB_WRP1 register *******************/
	2356	#define OB_WRP1_WRP1_Pos (16U)
	2357	#define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /!< 0x00FF0000 /
	2358	#define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /!< Flash memory write protection option bytes /
	2359	#define OB_WRP1_nWRP1_Pos (24U)
	2360	#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /!< 0xFF000000 /
	2361	#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /!< Flash memory write protection complemented option bytes /
	2362
	2363	/******************************************************************************/
	2364	/* */
	2365	/* General Purpose IOs (GPIO) */
	2366	/* */
	2367	/******************************************************************************/
	2368	/***************** Bit definition for GPIO_MODER register ***************/
	2369	#define GPIO_MODER_MODER0_Pos (0U)
	2370	#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /!< 0x00000003 /
	2371	#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
	2372	#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /!< 0x00000001 /
	2373	#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /!< 0x00000002 /
	2374	#define GPIO_MODER_MODER1_Pos (2U)
	2375	#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /!< 0x0000000C /
	2376	#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
	2377	#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /!< 0x00000004 /
	2378	#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /!< 0x00000008 /
	2379	#define GPIO_MODER_MODER2_Pos (4U)
	2380	#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /!< 0x00000030 /
	2381	#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
	2382	#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /!< 0x00000010 /
	2383	#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /!< 0x00000020 /
	2384	#define GPIO_MODER_MODER3_Pos (6U)
	2385	#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /!< 0x000000C0 /
	2386	#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
	2387	#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /!< 0x00000040 /
	2388	#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /!< 0x00000080 /
	2389	#define GPIO_MODER_MODER4_Pos (8U)
	2390	#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /!< 0x00000300 /
	2391	#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
	2392	#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /!< 0x00000100 /
	2393	#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /!< 0x00000200 /
	2394	#define GPIO_MODER_MODER5_Pos (10U)
	2395	#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /!< 0x00000C00 /
	2396	#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
	2397	#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /!< 0x00000400 /
	2398	#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /!< 0x00000800 /
	2399	#define GPIO_MODER_MODER6_Pos (12U)
	2400	#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /!< 0x00003000 /
	2401	#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
	2402	#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /!< 0x00001000 /
	2403	#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /!< 0x00002000 /
	2404	#define GPIO_MODER_MODER7_Pos (14U)
	2405	#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /!< 0x0000C000 /
	2406	#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
	2407	#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /!< 0x00004000 /
	2408	#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /!< 0x00008000 /
	2409	#define GPIO_MODER_MODER8_Pos (16U)
	2410	#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /!< 0x00030000 /
	2411	#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
	2412	#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /!< 0x00010000 /
	2413	#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /!< 0x00020000 /
	2414	#define GPIO_MODER_MODER9_Pos (18U)
	2415	#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /!< 0x000C0000 /
	2416	#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
	2417	#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /!< 0x00040000 /
	2418	#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /!< 0x00080000 /
	2419	#define GPIO_MODER_MODER10_Pos (20U)
	2420	#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /!< 0x00300000 /
	2421	#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
	2422	#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /!< 0x00100000 /
	2423	#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /!< 0x00200000 /
	2424	#define GPIO_MODER_MODER11_Pos (22U)
	2425	#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /!< 0x00C00000 /
	2426	#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
	2427	#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /!< 0x00400000 /
	2428	#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /!< 0x00800000 /
	2429	#define GPIO_MODER_MODER12_Pos (24U)
	2430	#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /!< 0x03000000 /
	2431	#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
	2432	#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /!< 0x01000000 /
	2433	#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /!< 0x02000000 /
	2434	#define GPIO_MODER_MODER13_Pos (26U)
	2435	#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /!< 0x0C000000 /
	2436	#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
	2437	#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /!< 0x04000000 /
	2438	#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /!< 0x08000000 /
	2439	#define GPIO_MODER_MODER14_Pos (28U)
	2440	#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /!< 0x30000000 /
	2441	#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
	2442	#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /!< 0x10000000 /
	2443	#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /!< 0x20000000 /
	2444	#define GPIO_MODER_MODER15_Pos (30U)
	2445	#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /!< 0xC0000000 /
	2446	#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
	2447	#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /!< 0x40000000 /
	2448	#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /!< 0x80000000 /
	2449
	2450	/**************** Bit definition for GPIO_OTYPER register ***************/
	2451	#define GPIO_OTYPER_OT_0 (0x00000001U)
	2452	#define GPIO_OTYPER_OT_1 (0x00000002U)
	2453	#define GPIO_OTYPER_OT_2 (0x00000004U)
	2454	#define GPIO_OTYPER_OT_3 (0x00000008U)
	2455	#define GPIO_OTYPER_OT_4 (0x00000010U)
	2456	#define GPIO_OTYPER_OT_5 (0x00000020U)
	2457	#define GPIO_OTYPER_OT_6 (0x00000040U)
	2458	#define GPIO_OTYPER_OT_7 (0x00000080U)
	2459	#define GPIO_OTYPER_OT_8 (0x00000100U)
	2460	#define GPIO_OTYPER_OT_9 (0x00000200U)
	2461	#define GPIO_OTYPER_OT_10 (0x00000400U)
	2462	#define GPIO_OTYPER_OT_11 (0x00000800U)
	2463	#define GPIO_OTYPER_OT_12 (0x00001000U)
	2464	#define GPIO_OTYPER_OT_13 (0x00002000U)
	2465	#define GPIO_OTYPER_OT_14 (0x00004000U)
	2466	#define GPIO_OTYPER_OT_15 (0x00008000U)
	2467
	2468	/************** Bit definition for GPIO_OSPEEDR register ****************/
	2469	#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
	2470	#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /!< 0x00000003 /
	2471	#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
	2472	#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /!< 0x00000001 /
	2473	#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /!< 0x00000002 /
	2474	#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
	2475	#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /!< 0x0000000C /
	2476	#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
	2477	#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /!< 0x00000004 /
	2478	#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /!< 0x00000008 /
	2479	#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
	2480	#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /!< 0x00000030 /
	2481	#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
	2482	#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /!< 0x00000010 /
	2483	#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /!< 0x00000020 /
	2484	#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
	2485	#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /!< 0x000000C0 /
	2486	#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
	2487	#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /!< 0x00000040 /
	2488	#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /!< 0x00000080 /
	2489	#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
	2490	#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /!< 0x00000300 /
	2491	#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
	2492	#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /!< 0x00000100 /
	2493	#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /!< 0x00000200 /
	2494	#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
	2495	#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /!< 0x00000C00 /
	2496	#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
	2497	#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /!< 0x00000400 /
	2498	#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /!< 0x00000800 /
	2499	#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
	2500	#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /!< 0x00003000 /
	2501	#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
	2502	#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /!< 0x00001000 /
	2503	#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /!< 0x00002000 /
	2504	#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
	2505	#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /!< 0x0000C000 /
	2506	#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
	2507	#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /!< 0x00004000 /
	2508	#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /!< 0x00008000 /
	2509	#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
	2510	#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /!< 0x00030000 /
	2511	#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
	2512	#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /!< 0x00010000 /
	2513	#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /!< 0x00020000 /
	2514	#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
	2515	#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /!< 0x000C0000 /
	2516	#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
	2517	#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /!< 0x00040000 /
	2518	#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /!< 0x00080000 /
	2519	#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
	2520	#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /!< 0x00300000 /
	2521	#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
	2522	#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /!< 0x00100000 /
	2523	#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /!< 0x00200000 /
	2524	#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
	2525	#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /!< 0x00C00000 /
	2526	#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
	2527	#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /!< 0x00400000 /
	2528	#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /!< 0x00800000 /
	2529	#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
	2530	#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /!< 0x03000000 /
	2531	#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
	2532	#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /!< 0x01000000 /
	2533	#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /!< 0x02000000 /
	2534	#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
	2535	#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /!< 0x0C000000 /
	2536	#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
	2537	#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /!< 0x04000000 /
	2538	#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /!< 0x08000000 /
	2539	#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
	2540	#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /!< 0x30000000 /
	2541	#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
	2542	#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /!< 0x10000000 /
	2543	#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /!< 0x20000000 /
	2544	#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
	2545	#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /!< 0xC0000000 /
	2546	#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
	2547	#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /!< 0x40000000 /
	2548	#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /!< 0x80000000 /
	2549
	2550	/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
	2551	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
	2552	#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
	2553	#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
	2554	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
	2555	#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
	2556	#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
	2557	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
	2558	#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
	2559	#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
	2560	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
	2561	#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
	2562	#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
	2563	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
	2564	#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
	2565	#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
	2566	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
	2567	#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
	2568	#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
	2569	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
	2570	#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
	2571	#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
	2572	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
	2573	#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
	2574	#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
	2575	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
	2576	#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
	2577	#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
	2578	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
	2579	#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
	2580	#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
	2581	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
	2582	#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
	2583	#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
	2584	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
	2585	#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
	2586	#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
	2587	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
	2588	#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
	2589	#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
	2590	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
	2591	#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
	2592	#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
	2593	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
	2594	#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
	2595	#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
	2596	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
	2597	#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
	2598	#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
	2599
	2600	/***************** Bit definition for GPIO_PUPDR register ****************/
	2601	#define GPIO_PUPDR_PUPDR0_Pos (0U)
	2602	#define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /!< 0x00000003 /
	2603	#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
	2604	#define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /!< 0x00000001 /
	2605	#define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /!< 0x00000002 /
	2606	#define GPIO_PUPDR_PUPDR1_Pos (2U)
	2607	#define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /!< 0x0000000C /
	2608	#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
	2609	#define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /!< 0x00000004 /
	2610	#define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /!< 0x00000008 /
	2611	#define GPIO_PUPDR_PUPDR2_Pos (4U)
	2612	#define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /!< 0x00000030 /
	2613	#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
	2614	#define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /!< 0x00000010 /
	2615	#define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /!< 0x00000020 /
	2616	#define GPIO_PUPDR_PUPDR3_Pos (6U)
	2617	#define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /!< 0x000000C0 /
	2618	#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
	2619	#define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /!< 0x00000040 /
	2620	#define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /!< 0x00000080 /
	2621	#define GPIO_PUPDR_PUPDR4_Pos (8U)
	2622	#define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /!< 0x00000300 /
	2623	#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
	2624	#define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /!< 0x00000100 /
	2625	#define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /!< 0x00000200 /
	2626	#define GPIO_PUPDR_PUPDR5_Pos (10U)
	2627	#define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /!< 0x00000C00 /
	2628	#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
	2629	#define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /!< 0x00000400 /
	2630	#define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /!< 0x00000800 /
	2631	#define GPIO_PUPDR_PUPDR6_Pos (12U)
	2632	#define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /!< 0x00003000 /
	2633	#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
	2634	#define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /!< 0x00001000 /
	2635	#define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /!< 0x00002000 /
	2636	#define GPIO_PUPDR_PUPDR7_Pos (14U)
	2637	#define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /!< 0x0000C000 /
	2638	#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
	2639	#define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /!< 0x00004000 /
	2640	#define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /!< 0x00008000 /
	2641	#define GPIO_PUPDR_PUPDR8_Pos (16U)
	2642	#define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /!< 0x00030000 /
	2643	#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
	2644	#define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /!< 0x00010000 /
	2645	#define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /!< 0x00020000 /
	2646	#define GPIO_PUPDR_PUPDR9_Pos (18U)
	2647	#define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /!< 0x000C0000 /
	2648	#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
	2649	#define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /!< 0x00040000 /
	2650	#define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /!< 0x00080000 /
	2651	#define GPIO_PUPDR_PUPDR10_Pos (20U)
	2652	#define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /!< 0x00300000 /
	2653	#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
	2654	#define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /!< 0x00100000 /
	2655	#define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /!< 0x00200000 /
	2656	#define GPIO_PUPDR_PUPDR11_Pos (22U)
	2657	#define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /!< 0x00C00000 /
	2658	#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
	2659	#define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /!< 0x00400000 /
	2660	#define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /!< 0x00800000 /
	2661	#define GPIO_PUPDR_PUPDR12_Pos (24U)
	2662	#define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /!< 0x03000000 /
	2663	#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
	2664	#define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /!< 0x01000000 /
	2665	#define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /!< 0x02000000 /
	2666	#define GPIO_PUPDR_PUPDR13_Pos (26U)
	2667	#define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /!< 0x0C000000 /
	2668	#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
	2669	#define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /!< 0x04000000 /
	2670	#define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /!< 0x08000000 /
	2671	#define GPIO_PUPDR_PUPDR14_Pos (28U)
	2672	#define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /!< 0x30000000 /
	2673	#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
	2674	#define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /!< 0x10000000 /
	2675	#define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /!< 0x20000000 /
	2676	#define GPIO_PUPDR_PUPDR15_Pos (30U)
	2677	#define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /!< 0xC0000000 /
	2678	#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
	2679	#define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /!< 0x40000000 /
	2680	#define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /!< 0x80000000 /
	2681
	2682	/***************** Bit definition for GPIO_IDR register *****************/
	2683	#define GPIO_IDR_0 (0x00000001U)
	2684	#define GPIO_IDR_1 (0x00000002U)
	2685	#define GPIO_IDR_2 (0x00000004U)
	2686	#define GPIO_IDR_3 (0x00000008U)
	2687	#define GPIO_IDR_4 (0x00000010U)
	2688	#define GPIO_IDR_5 (0x00000020U)
	2689	#define GPIO_IDR_6 (0x00000040U)
	2690	#define GPIO_IDR_7 (0x00000080U)
	2691	#define GPIO_IDR_8 (0x00000100U)
	2692	#define GPIO_IDR_9 (0x00000200U)
	2693	#define GPIO_IDR_10 (0x00000400U)
	2694	#define GPIO_IDR_11 (0x00000800U)
	2695	#define GPIO_IDR_12 (0x00001000U)
	2696	#define GPIO_IDR_13 (0x00002000U)
	2697	#define GPIO_IDR_14 (0x00004000U)
	2698	#define GPIO_IDR_15 (0x00008000U)
	2699
	2700	/**************** Bit definition for GPIO_ODR register ******************/
	2701	#define GPIO_ODR_0 (0x00000001U)
	2702	#define GPIO_ODR_1 (0x00000002U)
	2703	#define GPIO_ODR_2 (0x00000004U)
	2704	#define GPIO_ODR_3 (0x00000008U)
	2705	#define GPIO_ODR_4 (0x00000010U)
	2706	#define GPIO_ODR_5 (0x00000020U)
	2707	#define GPIO_ODR_6 (0x00000040U)
	2708	#define GPIO_ODR_7 (0x00000080U)
	2709	#define GPIO_ODR_8 (0x00000100U)
	2710	#define GPIO_ODR_9 (0x00000200U)
	2711	#define GPIO_ODR_10 (0x00000400U)
	2712	#define GPIO_ODR_11 (0x00000800U)
	2713	#define GPIO_ODR_12 (0x00001000U)
	2714	#define GPIO_ODR_13 (0x00002000U)
	2715	#define GPIO_ODR_14 (0x00004000U)
	2716	#define GPIO_ODR_15 (0x00008000U)
	2717
	2718	/**************** Bit definition for GPIO_BSRR register ******************/
	2719	#define GPIO_BSRR_BS_0 (0x00000001U)
	2720	#define GPIO_BSRR_BS_1 (0x00000002U)
	2721	#define GPIO_BSRR_BS_2 (0x00000004U)
	2722	#define GPIO_BSRR_BS_3 (0x00000008U)
	2723	#define GPIO_BSRR_BS_4 (0x00000010U)
	2724	#define GPIO_BSRR_BS_5 (0x00000020U)
	2725	#define GPIO_BSRR_BS_6 (0x00000040U)
	2726	#define GPIO_BSRR_BS_7 (0x00000080U)
	2727	#define GPIO_BSRR_BS_8 (0x00000100U)
	2728	#define GPIO_BSRR_BS_9 (0x00000200U)
	2729	#define GPIO_BSRR_BS_10 (0x00000400U)
	2730	#define GPIO_BSRR_BS_11 (0x00000800U)
	2731	#define GPIO_BSRR_BS_12 (0x00001000U)
	2732	#define GPIO_BSRR_BS_13 (0x00002000U)
	2733	#define GPIO_BSRR_BS_14 (0x00004000U)
	2734	#define GPIO_BSRR_BS_15 (0x00008000U)
	2735	#define GPIO_BSRR_BR_0 (0x00010000U)
	2736	#define GPIO_BSRR_BR_1 (0x00020000U)
	2737	#define GPIO_BSRR_BR_2 (0x00040000U)
	2738	#define GPIO_BSRR_BR_3 (0x00080000U)
	2739	#define GPIO_BSRR_BR_4 (0x00100000U)
	2740	#define GPIO_BSRR_BR_5 (0x00200000U)
	2741	#define GPIO_BSRR_BR_6 (0x00400000U)
	2742	#define GPIO_BSRR_BR_7 (0x00800000U)
	2743	#define GPIO_BSRR_BR_8 (0x01000000U)
	2744	#define GPIO_BSRR_BR_9 (0x02000000U)
	2745	#define GPIO_BSRR_BR_10 (0x04000000U)
	2746	#define GPIO_BSRR_BR_11 (0x08000000U)
	2747	#define GPIO_BSRR_BR_12 (0x10000000U)
	2748	#define GPIO_BSRR_BR_13 (0x20000000U)
	2749	#define GPIO_BSRR_BR_14 (0x40000000U)
	2750	#define GPIO_BSRR_BR_15 (0x80000000U)
	2751
	2752	/**************** Bit definition for GPIO_LCKR register ******************/
	2753	#define GPIO_LCKR_LCK0_Pos (0U)
	2754	#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /!< 0x00000001 /
	2755	#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
	2756	#define GPIO_LCKR_LCK1_Pos (1U)
	2757	#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /!< 0x00000002 /
	2758	#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
	2759	#define GPIO_LCKR_LCK2_Pos (2U)
	2760	#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /!< 0x00000004 /
	2761	#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
	2762	#define GPIO_LCKR_LCK3_Pos (3U)
	2763	#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /!< 0x00000008 /
	2764	#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
	2765	#define GPIO_LCKR_LCK4_Pos (4U)
	2766	#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /!< 0x00000010 /
	2767	#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
	2768	#define GPIO_LCKR_LCK5_Pos (5U)
	2769	#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /!< 0x00000020 /
	2770	#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
	2771	#define GPIO_LCKR_LCK6_Pos (6U)
	2772	#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /!< 0x00000040 /
	2773	#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
	2774	#define GPIO_LCKR_LCK7_Pos (7U)
	2775	#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /!< 0x00000080 /
	2776	#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
	2777	#define GPIO_LCKR_LCK8_Pos (8U)
	2778	#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /!< 0x00000100 /
	2779	#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
	2780	#define GPIO_LCKR_LCK9_Pos (9U)
	2781	#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /!< 0x00000200 /
	2782	#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
	2783	#define GPIO_LCKR_LCK10_Pos (10U)
	2784	#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /!< 0x00000400 /
	2785	#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
	2786	#define GPIO_LCKR_LCK11_Pos (11U)
	2787	#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /!< 0x00000800 /
	2788	#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
	2789	#define GPIO_LCKR_LCK12_Pos (12U)
	2790	#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /!< 0x00001000 /
	2791	#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
	2792	#define GPIO_LCKR_LCK13_Pos (13U)
	2793	#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /!< 0x00002000 /
	2794	#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
	2795	#define GPIO_LCKR_LCK14_Pos (14U)
	2796	#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /!< 0x00004000 /
	2797	#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
	2798	#define GPIO_LCKR_LCK15_Pos (15U)
	2799	#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /!< 0x00008000 /
	2800	#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
	2801	#define GPIO_LCKR_LCKK_Pos (16U)
	2802	#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /!< 0x00010000 /
	2803	#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
	2804
	2805	/**************** Bit definition for GPIO_AFRL register ******************/
	2806	#define GPIO_AFRL_AFSEL0_Pos (0U)
	2807	#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /!< 0x0000000F /
	2808	#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
	2809	#define GPIO_AFRL_AFSEL1_Pos (4U)
	2810	#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /!< 0x000000F0 /
	2811	#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
	2812	#define GPIO_AFRL_AFSEL2_Pos (8U)
	2813	#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /!< 0x00000F00 /
	2814	#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
	2815	#define GPIO_AFRL_AFSEL3_Pos (12U)
	2816	#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /!< 0x0000F000 /
	2817	#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
	2818	#define GPIO_AFRL_AFSEL4_Pos (16U)
	2819	#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /!< 0x000F0000 /
	2820	#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
	2821	#define GPIO_AFRL_AFSEL5_Pos (20U)
	2822	#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /!< 0x00F00000 /
	2823	#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
	2824	#define GPIO_AFRL_AFSEL6_Pos (24U)
	2825	#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /!< 0x0F000000 /
	2826	#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
	2827	#define GPIO_AFRL_AFSEL7_Pos (28U)
	2828	#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /!< 0xF0000000 /
	2829	#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
	2830
	2831	/* Legacy aliases */
	2832	#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos
	2833	#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk
	2834	#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
	2835	#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos
	2836	#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk
	2837	#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
	2838	#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos
	2839	#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk
	2840	#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
	2841	#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos
	2842	#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk
	2843	#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
	2844	#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos
	2845	#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk
	2846	#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
	2847	#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos
	2848	#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk
	2849	#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
	2850	#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos
	2851	#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk
	2852	#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
	2853	#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos
	2854	#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk
	2855	#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
	2856
	2857	/**************** Bit definition for GPIO_AFRH register ******************/
	2858	#define GPIO_AFRH_AFSEL8_Pos (0U)
	2859	#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /!< 0x0000000F /
	2860	#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
	2861	#define GPIO_AFRH_AFSEL9_Pos (4U)
	2862	#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /!< 0x000000F0 /
	2863	#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
	2864	#define GPIO_AFRH_AFSEL10_Pos (8U)
	2865	#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /!< 0x00000F00 /
	2866	#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
	2867	#define GPIO_AFRH_AFSEL11_Pos (12U)
	2868	#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /!< 0x0000F000 /
	2869	#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
	2870	#define GPIO_AFRH_AFSEL12_Pos (16U)
	2871	#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /!< 0x000F0000 /
	2872	#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
	2873	#define GPIO_AFRH_AFSEL13_Pos (20U)
	2874	#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /!< 0x00F00000 /
	2875	#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
	2876	#define GPIO_AFRH_AFSEL14_Pos (24U)
	2877	#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /!< 0x0F000000 /
	2878	#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
	2879	#define GPIO_AFRH_AFSEL15_Pos (28U)
	2880	#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /!< 0xF0000000 /
	2881	#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
	2882
	2883	/* Legacy aliases */
	2884	#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos
	2885	#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk
	2886	#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
	2887	#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos
	2888	#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk
	2889	#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
	2890	#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos
	2891	#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk
	2892	#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
	2893	#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos
	2894	#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk
	2895	#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
	2896	#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos
	2897	#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk
	2898	#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
	2899	#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos
	2900	#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk
	2901	#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
	2902	#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos
	2903	#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk
	2904	#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
	2905	#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos
	2906	#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk
	2907	#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
	2908
	2909	/**************** Bit definition for GPIO_BRR register *******************/
	2910	#define GPIO_BRR_BR_0 (0x00000001U)
	2911	#define GPIO_BRR_BR_1 (0x00000002U)
	2912	#define GPIO_BRR_BR_2 (0x00000004U)
	2913	#define GPIO_BRR_BR_3 (0x00000008U)
	2914	#define GPIO_BRR_BR_4 (0x00000010U)
	2915	#define GPIO_BRR_BR_5 (0x00000020U)
	2916	#define GPIO_BRR_BR_6 (0x00000040U)
	2917	#define GPIO_BRR_BR_7 (0x00000080U)
	2918	#define GPIO_BRR_BR_8 (0x00000100U)
	2919	#define GPIO_BRR_BR_9 (0x00000200U)
	2920	#define GPIO_BRR_BR_10 (0x00000400U)
	2921	#define GPIO_BRR_BR_11 (0x00000800U)
	2922	#define GPIO_BRR_BR_12 (0x00001000U)
	2923	#define GPIO_BRR_BR_13 (0x00002000U)
	2924	#define GPIO_BRR_BR_14 (0x00004000U)
	2925	#define GPIO_BRR_BR_15 (0x00008000U)
	2926
	2927	/******************************************************************************/
	2928	/* */
	2929	/* Inter-integrated Circuit Interface (I2C) */
	2930	/* */
	2931	/******************************************************************************/
	2932
	2933	/***************** Bit definition for I2C_CR1 register *****************/
	2934	#define I2C_CR1_PE_Pos (0U)
	2935	#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /!< 0x00000001 /
	2936	#define I2C_CR1_PE I2C_CR1_PE_Msk /!< Peripheral enable /
	2937	#define I2C_CR1_TXIE_Pos (1U)
	2938	#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /!< 0x00000002 /
	2939	#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /!< TX interrupt enable /
	2940	#define I2C_CR1_RXIE_Pos (2U)
	2941	#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /!< 0x00000004 /
	2942	#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /!< RX interrupt enable /
	2943	#define I2C_CR1_ADDRIE_Pos (3U)
	2944	#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /!< 0x00000008 /
	2945	#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /!< Address match interrupt enable /
	2946	#define I2C_CR1_NACKIE_Pos (4U)
	2947	#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /!< 0x00000010 /
	2948	#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /!< NACK received interrupt enable /
	2949	#define I2C_CR1_STOPIE_Pos (5U)
	2950	#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /!< 0x00000020 /
	2951	#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /!< STOP detection interrupt enable /
	2952	#define I2C_CR1_TCIE_Pos (6U)
	2953	#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /!< 0x00000040 /
	2954	#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /!< Transfer complete interrupt enable /
	2955	#define I2C_CR1_ERRIE_Pos (7U)
	2956	#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /!< 0x00000080 /
	2957	#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /!< Errors interrupt enable /
	2958	#define I2C_CR1_DNF_Pos (8U)
	2959	#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /!< 0x00000F00 /
	2960	#define I2C_CR1_DNF I2C_CR1_DNF_Msk /!< Digital noise filter /
	2961	#define I2C_CR1_ANFOFF_Pos (12U)
	2962	#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /!< 0x00001000 /
	2963	#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /!< Analog noise filter OFF /
	2964	#define I2C_CR1_SWRST_Pos (13U)
	2965	#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /!< 0x00002000 /
	2966	#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /!< Software reset /
	2967	#define I2C_CR1_TXDMAEN_Pos (14U)
	2968	#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /!< 0x00004000 /
	2969	#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /!< DMA transmission requests enable /
	2970	#define I2C_CR1_RXDMAEN_Pos (15U)
	2971	#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /!< 0x00008000 /
	2972	#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /!< DMA reception requests enable /
	2973	#define I2C_CR1_SBC_Pos (16U)
	2974	#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /!< 0x00010000 /
	2975	#define I2C_CR1_SBC I2C_CR1_SBC_Msk /!< Slave byte control /
	2976	#define I2C_CR1_NOSTRETCH_Pos (17U)
	2977	#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /!< 0x00020000 /
	2978	#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /!< Clock stretching disable /
	2979	#define I2C_CR1_WUPEN_Pos (18U)
	2980	#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /!< 0x00040000 /
	2981	#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /!< Wakeup from STOP enable /
	2982	#define I2C_CR1_GCEN_Pos (19U)
	2983	#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /!< 0x00080000 /
	2984	#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /!< General call enable /
	2985	#define I2C_CR1_SMBHEN_Pos (20U)
	2986	#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /!< 0x00100000 /
	2987	#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /!< SMBus host address enable /
	2988	#define I2C_CR1_SMBDEN_Pos (21U)
	2989	#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /!< 0x00200000 /
	2990	#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /!< SMBus device default address enable /
	2991	#define I2C_CR1_ALERTEN_Pos (22U)
	2992	#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /!< 0x00400000 /
	2993	#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /!< SMBus alert enable /
	2994	#define I2C_CR1_PECEN_Pos (23U)
	2995	#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /!< 0x00800000 /
	2996	#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /!< PEC enable /
	2997
	2998	/**************** Bit definition for I2C_CR2 register ******************/
	2999	#define I2C_CR2_SADD_Pos (0U)
	3000	#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /!< 0x000003FF /
	3001	#define I2C_CR2_SADD I2C_CR2_SADD_Msk /!< Slave address (master mode) /
	3002	#define I2C_CR2_RD_WRN_Pos (10U)
	3003	#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /!< 0x00000400 /
	3004	#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /!< Transfer direction (master mode) /
	3005	#define I2C_CR2_ADD10_Pos (11U)
	3006	#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /!< 0x00000800 /
	3007	#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /!< 10-bit addressing mode (master mode) /
	3008	#define I2C_CR2_HEAD10R_Pos (12U)
	3009	#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /!< 0x00001000 /
	3010	#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /!< 10-bit address header only read direction (master mode) /
	3011	#define I2C_CR2_START_Pos (13U)
	3012	#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /!< 0x00002000 /
	3013	#define I2C_CR2_START I2C_CR2_START_Msk /!< START generation /
	3014	#define I2C_CR2_STOP_Pos (14U)
	3015	#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /!< 0x00004000 /
	3016	#define I2C_CR2_STOP I2C_CR2_STOP_Msk /!< STOP generation (master mode) /
	3017	#define I2C_CR2_NACK_Pos (15U)
	3018	#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /!< 0x00008000 /
	3019	#define I2C_CR2_NACK I2C_CR2_NACK_Msk /!< NACK generation (slave mode) /
	3020	#define I2C_CR2_NBYTES_Pos (16U)
	3021	#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /!< 0x00FF0000 /
	3022	#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /!< Number of bytes /
	3023	#define I2C_CR2_RELOAD_Pos (24U)
	3024	#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /!< 0x01000000 /
	3025	#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /!< NBYTES reload mode /
	3026	#define I2C_CR2_AUTOEND_Pos (25U)
	3027	#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /!< 0x02000000 /
	3028	#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /!< Automatic end mode (master mode) /
	3029	#define I2C_CR2_PECBYTE_Pos (26U)
	3030	#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /!< 0x04000000 /
	3031	#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /!< Packet error checking byte /
	3032
	3033	/***************** Bit definition for I2C_OAR1 register ****************/
	3034	#define I2C_OAR1_OA1_Pos (0U)
	3035	#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /!< 0x000003FF /
	3036	#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /!< Interface own address 1 /
	3037	#define I2C_OAR1_OA1MODE_Pos (10U)
	3038	#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /!< 0x00000400 /
	3039	#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /!< Own address 1 10-bit mode /
	3040	#define I2C_OAR1_OA1EN_Pos (15U)
	3041	#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /!< 0x00008000 /
	3042	#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /!< Own address 1 enable /
	3043
	3044	/***************** Bit definition for I2C_OAR2 register ****************/
	3045	#define I2C_OAR2_OA2_Pos (1U)
	3046	#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /!< 0x000000FE /
	3047	#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /!< Interface own address 2 /
	3048	#define I2C_OAR2_OA2MSK_Pos (8U)
	3049	#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /!< 0x00000700 /
	3050	#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /!< Own address 2 masks /
	3051	#define I2C_OAR2_OA2NOMASK (0x00000000U) /!< No mask /
	3052	#define I2C_OAR2_OA2MASK01_Pos (8U)
	3053	#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /!< 0x00000100 /
	3054	#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /!< OA2[1] is masked, Only OA2[7:2] are compared /
	3055	#define I2C_OAR2_OA2MASK02_Pos (9U)
	3056	#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /!< 0x00000200 /
	3057	#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /!< OA2[2:1] is masked, Only OA2[7:3] are compared /
	3058	#define I2C_OAR2_OA2MASK03_Pos (8U)
	3059	#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /!< 0x00000300 /
	3060	#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /!< OA2[3:1] is masked, Only OA2[7:4] are compared /
	3061	#define I2C_OAR2_OA2MASK04_Pos (10U)
	3062	#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /!< 0x00000400 /
	3063	#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /!< OA2[4:1] is masked, Only OA2[7:5] are compared /
	3064	#define I2C_OAR2_OA2MASK05_Pos (8U)
	3065	#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /!< 0x00000500 /
	3066	#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /!< OA2[5:1] is masked, Only OA2[7:6] are compared /
	3067	#define I2C_OAR2_OA2MASK06_Pos (9U)
	3068	#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /!< 0x00000600 /
	3069	#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /!< OA2[6:1] is masked, Only OA2[7] are compared /
	3070	#define I2C_OAR2_OA2MASK07_Pos (8U)
	3071	#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /!< 0x00000700 /
	3072	#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /!< OA2[7:1] is masked, No comparison is done /
	3073	#define I2C_OAR2_OA2EN_Pos (15U)
	3074	#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /!< 0x00008000 /
	3075	#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /!< Own address 2 enable /
	3076
	3077	/***************** Bit definition for I2C_TIMINGR register **************/
	3078	#define I2C_TIMINGR_SCLL_Pos (0U)
	3079	#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /!< 0x000000FF /
	3080	#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /!< SCL low period (master mode) /
	3081	#define I2C_TIMINGR_SCLH_Pos (8U)
	3082	#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /!< 0x0000FF00 /
	3083	#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /!< SCL high period (master mode) /
	3084	#define I2C_TIMINGR_SDADEL_Pos (16U)
	3085	#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /!< 0x000F0000 /
	3086	#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /!< Data hold time /
	3087	#define I2C_TIMINGR_SCLDEL_Pos (20U)
	3088	#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /!< 0x00F00000 /
	3089	#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /!< Data setup time /
	3090	#define I2C_TIMINGR_PRESC_Pos (28U)
	3091	#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /!< 0xF0000000 /
	3092	#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /!< Timings prescaler /
	3093
	3094	/***************** Bit definition for I2C_TIMEOUTR register **************/
	3095	#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
	3096	#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /!< 0x00000FFF /
	3097	#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /!< Bus timeout A /
	3098	#define I2C_TIMEOUTR_TIDLE_Pos (12U)
	3099	#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /!< 0x00001000 /
	3100	#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /!< Idle clock timeout detection /
	3101	#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
	3102	#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /!< 0x00008000 /
	3103	#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /!< Clock timeout enable /
	3104	#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
	3105	#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /!< 0x0FFF0000 /
	3106	#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /!< Bus timeout B/
	3107	#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
	3108	#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /!< 0x80000000 /
	3109	#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /!< Extended clock timeout enable /
	3110
	3111	/**************** Bit definition for I2C_ISR register ******************/
	3112	#define I2C_ISR_TXE_Pos (0U)
	3113	#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /!< 0x00000001 /
	3114	#define I2C_ISR_TXE I2C_ISR_TXE_Msk /!< Transmit data register empty /
	3115	#define I2C_ISR_TXIS_Pos (1U)
	3116	#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /!< 0x00000002 /
	3117	#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /!< Transmit interrupt status /
	3118	#define I2C_ISR_RXNE_Pos (2U)
	3119	#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /!< 0x00000004 /
	3120	#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /!< Receive data register not empty /
	3121	#define I2C_ISR_ADDR_Pos (3U)
	3122	#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /!< 0x00000008 /
	3123	#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /!< Address matched (slave mode)/
	3124	#define I2C_ISR_NACKF_Pos (4U)
	3125	#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /!< 0x00000010 /
	3126	#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /!< NACK received flag /
	3127	#define I2C_ISR_STOPF_Pos (5U)
	3128	#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /!< 0x00000020 /
	3129	#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /!< STOP detection flag /
	3130	#define I2C_ISR_TC_Pos (6U)
	3131	#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /!< 0x00000040 /
	3132	#define I2C_ISR_TC I2C_ISR_TC_Msk /!< Transfer complete (master mode) /
	3133	#define I2C_ISR_TCR_Pos (7U)
	3134	#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /!< 0x00000080 /
	3135	#define I2C_ISR_TCR I2C_ISR_TCR_Msk /!< Transfer complete reload /
	3136	#define I2C_ISR_BERR_Pos (8U)
	3137	#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /!< 0x00000100 /
	3138	#define I2C_ISR_BERR I2C_ISR_BERR_Msk /!< Bus error /
	3139	#define I2C_ISR_ARLO_Pos (9U)
	3140	#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /!< 0x00000200 /
	3141	#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /!< Arbitration lost /
	3142	#define I2C_ISR_OVR_Pos (10U)
	3143	#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /!< 0x00000400 /
	3144	#define I2C_ISR_OVR I2C_ISR_OVR_Msk /!< Overrun/Underrun /
	3145	#define I2C_ISR_PECERR_Pos (11U)
	3146	#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /!< 0x00000800 /
	3147	#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /!< PEC error in reception /
	3148	#define I2C_ISR_TIMEOUT_Pos (12U)
	3149	#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /!< 0x00001000 /
	3150	#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /!< Timeout or Tlow detection flag /
	3151	#define I2C_ISR_ALERT_Pos (13U)
	3152	#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /!< 0x00002000 /
	3153	#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /!< SMBus alert /
	3154	#define I2C_ISR_BUSY_Pos (15U)
	3155	#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /!< 0x00008000 /
	3156	#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /!< Bus busy /
	3157	#define I2C_ISR_DIR_Pos (16U)
	3158	#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /!< 0x00010000 /
	3159	#define I2C_ISR_DIR I2C_ISR_DIR_Msk /!< Transfer direction (slave mode) /
	3160	#define I2C_ISR_ADDCODE_Pos (17U)
	3161	#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /!< 0x00FE0000 /
	3162	#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /!< Address match code (slave mode) /
	3163
	3164	/**************** Bit definition for I2C_ICR register ******************/
	3165	#define I2C_ICR_ADDRCF_Pos (3U)
	3166	#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /!< 0x00000008 /
	3167	#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /!< Address matched clear flag /
	3168	#define I2C_ICR_NACKCF_Pos (4U)
	3169	#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /!< 0x00000010 /
	3170	#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /!< NACK clear flag /
	3171	#define I2C_ICR_STOPCF_Pos (5U)
	3172	#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /!< 0x00000020 /
	3173	#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /!< STOP detection clear flag /
	3174	#define I2C_ICR_BERRCF_Pos (8U)
	3175	#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /!< 0x00000100 /
	3176	#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /!< Bus error clear flag /
	3177	#define I2C_ICR_ARLOCF_Pos (9U)
	3178	#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /!< 0x00000200 /
	3179	#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /!< Arbitration lost clear flag /
	3180	#define I2C_ICR_OVRCF_Pos (10U)
	3181	#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /!< 0x00000400 /
	3182	#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /!< Overrun/Underrun clear flag /
	3183	#define I2C_ICR_PECCF_Pos (11U)
	3184	#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /!< 0x00000800 /
	3185	#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /!< PAC error clear flag /
	3186	#define I2C_ICR_TIMOUTCF_Pos (12U)
	3187	#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /!< 0x00001000 /
	3188	#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /!< Timeout clear flag /
	3189	#define I2C_ICR_ALERTCF_Pos (13U)
	3190	#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /!< 0x00002000 /
	3191	#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /!< Alert clear flag /
	3192
	3193	/**************** Bit definition for I2C_PECR register *****************/
	3194	#define I2C_PECR_PEC_Pos (0U)
	3195	#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /!< 0x000000FF /
	3196	#define I2C_PECR_PEC I2C_PECR_PEC_Msk /!< PEC register /
	3197
	3198	/**************** Bit definition for I2C_RXDR register *******************/
	3199	#define I2C_RXDR_RXDATA_Pos (0U)
	3200	#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /!< 0x000000FF /
	3201	#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /!< 8-bit receive data /
	3202
	3203	/**************** Bit definition for I2C_TXDR register *****************/
	3204	#define I2C_TXDR_TXDATA_Pos (0U)
	3205	#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /!< 0x000000FF /
	3206	#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /!< 8-bit transmit data /
	3207
	3208	/*****************************************************************************/
	3209	/* */
	3210	/* Independent WATCHDOG (IWDG) */
	3211	/* */
	3212	/*****************************************************************************/
	3213	/***************** Bit definition for IWDG_KR register *****************/
	3214	#define IWDG_KR_KEY_Pos (0U)
	3215	#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /!< 0x0000FFFF /
	3216	#define IWDG_KR_KEY IWDG_KR_KEY_Msk /!< Key value (write only, read 0000h) /
	3217
	3218	/***************** Bit definition for IWDG_PR register *****************/
	3219	#define IWDG_PR_PR_Pos (0U)
	3220	#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /!< 0x00000007 /
	3221	#define IWDG_PR_PR IWDG_PR_PR_Msk /!< PR[2:0] (Prescaler divider) /
	3222	#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /!< 0x01 /
	3223	#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /!< 0x02 /
	3224	#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /!< 0x04 /
	3225
	3226	/***************** Bit definition for IWDG_RLR register ****************/
	3227	#define IWDG_RLR_RL_Pos (0U)
	3228	#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /!< 0x00000FFF /
	3229	#define IWDG_RLR_RL IWDG_RLR_RL_Msk /!< Watchdog counter reload value /
	3230
	3231	/***************** Bit definition for IWDG_SR register *****************/
	3232	#define IWDG_SR_PVU_Pos (0U)
	3233	#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /!< 0x00000001 /
	3234	#define IWDG_SR_PVU IWDG_SR_PVU_Msk /!< Watchdog prescaler value update /
	3235	#define IWDG_SR_RVU_Pos (1U)
	3236	#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /!< 0x00000002 /
	3237	#define IWDG_SR_RVU IWDG_SR_RVU_Msk /!< Watchdog counter reload value update /
	3238	#define IWDG_SR_WVU_Pos (2U)
	3239	#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /!< 0x00000004 /
	3240	#define IWDG_SR_WVU IWDG_SR_WVU_Msk /!< Watchdog counter window value update /
	3241
	3242	/***************** Bit definition for IWDG_KR register *****************/
	3243	#define IWDG_WINR_WIN_Pos (0U)
	3244	#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /!< 0x00000FFF /
	3245	#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /!< Watchdog counter window value /
	3246
	3247	/*****************************************************************************/
	3248	/* */
	3249	/* Power Control (PWR) */
	3250	/* */
	3251	/*****************************************************************************/
	3252
	3253	#define PWR_PVD_SUPPORT /!< PWR feature available only on specific devices: Power Voltage Detection feature /
	3254
	3255
	3256	/****************** Bit definition for PWR_CR register *****************/
	3257	#define PWR_CR_LPDS_Pos (0U)
	3258	#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /!< 0x00000001 /
	3259	#define PWR_CR_LPDS PWR_CR_LPDS_Msk /!< Low-power Deepsleep /
	3260	#define PWR_CR_PDDS_Pos (1U)
	3261	#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /!< 0x00000002 /
	3262	#define PWR_CR_PDDS PWR_CR_PDDS_Msk /!< Power Down Deepsleep /
	3263	#define PWR_CR_CWUF_Pos (2U)
	3264	#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /!< 0x00000004 /
	3265	#define PWR_CR_CWUF PWR_CR_CWUF_Msk /!< Clear Wakeup Flag /
	3266	#define PWR_CR_CSBF_Pos (3U)
	3267	#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /!< 0x00000008 /
	3268	#define PWR_CR_CSBF PWR_CR_CSBF_Msk /!< Clear Standby Flag /
	3269	#define PWR_CR_PVDE_Pos (4U)
	3270	#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /!< 0x00000010 /
	3271	#define PWR_CR_PVDE PWR_CR_PVDE_Msk /!< Power Voltage Detector Enable /
	3272
	3273	#define PWR_CR_PLS_Pos (5U)
	3274	#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /!< 0x000000E0 /
	3275	#define PWR_CR_PLS PWR_CR_PLS_Msk /!< PLS[2:0] bits (PVD Level Selection) /
	3276	#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /!< 0x00000020 /
	3277	#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /!< 0x00000040 /
	3278	#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /!< 0x00000080 /
	3279
	3280	/!< PVD level configuration /
	3281	#define PWR_CR_PLS_LEV0 (0x00000000U) /!< PVD level 0 /
	3282	#define PWR_CR_PLS_LEV1 (0x00000020U) /!< PVD level 1 /
	3283	#define PWR_CR_PLS_LEV2 (0x00000040U) /!< PVD level 2 /
	3284	#define PWR_CR_PLS_LEV3 (0x00000060U) /!< PVD level 3 /
	3285	#define PWR_CR_PLS_LEV4 (0x00000080U) /!< PVD level 4 /
	3286	#define PWR_CR_PLS_LEV5 (0x000000A0U) /!< PVD level 5 /
	3287	#define PWR_CR_PLS_LEV6 (0x000000C0U) /!< PVD level 6 /
	3288	#define PWR_CR_PLS_LEV7 (0x000000E0U) /!< PVD level 7 /
	3289
	3290	#define PWR_CR_DBP_Pos (8U)
	3291	#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /!< 0x00000100 /
	3292	#define PWR_CR_DBP PWR_CR_DBP_Msk /!< Disable Backup Domain write protection /
	3293
	3294	/***************** Bit definition for PWR_CSR register *****************/
	3295	#define PWR_CSR_WUF_Pos (0U)
	3296	#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /!< 0x00000001 /
	3297	#define PWR_CSR_WUF PWR_CSR_WUF_Msk /!< Wakeup Flag /
	3298	#define PWR_CSR_SBF_Pos (1U)
	3299	#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /!< 0x00000002 /
	3300	#define PWR_CSR_SBF PWR_CSR_SBF_Msk /!< Standby Flag /
	3301	#define PWR_CSR_PVDO_Pos (2U)
	3302	#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /!< 0x00000004 /
	3303	#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /!< PVD Output /
	3304	#define PWR_CSR_VREFINTRDYF_Pos (3U)
	3305	#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /!< 0x00000008 /
	3306	#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /!< Internal voltage reference (VREFINT) ready flag /
	3307
	3308	#define PWR_CSR_EWUP1_Pos (8U)
	3309	#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /!< 0x00000100 /
	3310	#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /!< Enable WKUP pin 1 /
	3311	#define PWR_CSR_EWUP2_Pos (9U)
	3312	#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /!< 0x00000200 /
	3313	#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /!< Enable WKUP pin 2 /
	3314
	3315	/*****************************************************************************/
	3316	/* */
	3317	/* Reset and Clock Control */
	3318	/* */
	3319	/*****************************************************************************/
	3320	/*
	3321	* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
	3322	*/
	3323
	3324	/****************** Bit definition for RCC_CR register *****************/
	3325	#define RCC_CR_HSION_Pos (0U)
	3326	#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /!< 0x00000001 /
	3327	#define RCC_CR_HSION RCC_CR_HSION_Msk /!< Internal High Speed clock enable /
	3328	#define RCC_CR_HSIRDY_Pos (1U)
	3329	#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /!< 0x00000002 /
	3330	#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /!< Internal High Speed clock ready flag /
	3331
	3332	#define RCC_CR_HSITRIM_Pos (3U)
	3333	#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /!< 0x000000F8 /
	3334	#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /!< Internal High Speed clock trimming /
	3335	#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /!< 0x00000008 /
	3336	#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /!< 0x00000010 /
	3337	#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /!< 0x00000020 /
	3338	#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /!< 0x00000040 /
	3339	#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /!< 0x00000080 /
	3340
	3341	#define RCC_CR_HSICAL_Pos (8U)
	3342	#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /!< 0x0000FF00 /
	3343	#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /!< Internal High Speed clock Calibration /
	3344	#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /!< 0x00000100 /
	3345	#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /!< 0x00000200 /
	3346	#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /!< 0x00000400 /
	3347	#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /!< 0x00000800 /
	3348	#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /!< 0x00001000 /
	3349	#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /!< 0x00002000 /
	3350	#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /!< 0x00004000 /
	3351	#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /!< 0x00008000 /
	3352
	3353	#define RCC_CR_HSEON_Pos (16U)
	3354	#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /!< 0x00010000 /
	3355	#define RCC_CR_HSEON RCC_CR_HSEON_Msk /!< External High Speed clock enable /
	3356	#define RCC_CR_HSERDY_Pos (17U)
	3357	#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /!< 0x00020000 /
	3358	#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /!< External High Speed clock ready flag /
	3359	#define RCC_CR_HSEBYP_Pos (18U)
	3360	#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /!< 0x00040000 /
	3361	#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /!< External High Speed clock Bypass /
	3362	#define RCC_CR_CSSON_Pos (19U)
	3363	#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /!< 0x00080000 /
	3364	#define RCC_CR_CSSON RCC_CR_CSSON_Msk /!< Clock Security System enable /
	3365	#define RCC_CR_PLLON_Pos (24U)
	3366	#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /!< 0x01000000 /
	3367	#define RCC_CR_PLLON RCC_CR_PLLON_Msk /!< PLL enable /
	3368	#define RCC_CR_PLLRDY_Pos (25U)
	3369	#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /!< 0x02000000 /
	3370	#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /!< PLL clock ready flag /
	3371
	3372	/****************** Bit definition for RCC_CFGR register ***************/
	3373	/!< SW configuration /
	3374	#define RCC_CFGR_SW_Pos (0U)
	3375	#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /!< 0x00000003 /
	3376	#define RCC_CFGR_SW RCC_CFGR_SW_Msk /!< SW[1:0] bits (System clock Switch) /
	3377	#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /!< 0x00000001 /
	3378	#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /!< 0x00000002 /
	3379
	3380	#define RCC_CFGR_SW_HSI (0x00000000U) /!< HSI selected as system clock /
	3381	#define RCC_CFGR_SW_HSE (0x00000001U) /!< HSE selected as system clock /
	3382	#define RCC_CFGR_SW_PLL (0x00000002U) /!< PLL selected as system clock /
	3383
	3384	/!< SWS configuration /
	3385	#define RCC_CFGR_SWS_Pos (2U)
	3386	#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /!< 0x0000000C /
	3387	#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /!< SWS[1:0] bits (System Clock Switch Status) /
	3388	#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /!< 0x00000004 /
	3389	#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /!< 0x00000008 /
	3390
	3391	#define RCC_CFGR_SWS_HSI (0x00000000U) /!< HSI oscillator used as system clock /
	3392	#define RCC_CFGR_SWS_HSE (0x00000004U) /!< HSE oscillator used as system clock /
	3393	#define RCC_CFGR_SWS_PLL (0x00000008U) /!< PLL used as system clock /
	3394
	3395	/!< HPRE configuration /
	3396	#define RCC_CFGR_HPRE_Pos (4U)
	3397	#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /!< 0x000000F0 /
	3398	#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /!< HPRE[3:0] bits (AHB prescaler) /
	3399	#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /!< 0x00000010 /
	3400	#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /!< 0x00000020 /
	3401	#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /!< 0x00000040 /
	3402	#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /!< 0x00000080 /
	3403
	3404	#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /!< SYSCLK not divided /
	3405	#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /!< SYSCLK divided by 2 /
	3406	#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /!< SYSCLK divided by 4 /
	3407	#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /!< SYSCLK divided by 8 /
	3408	#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /!< SYSCLK divided by 16 /
	3409	#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /!< SYSCLK divided by 64 /
	3410	#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /!< SYSCLK divided by 128 /
	3411	#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /!< SYSCLK divided by 256 /
	3412	#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /!< SYSCLK divided by 512 /
	3413
	3414	/!< PPRE configuration /
	3415	#define RCC_CFGR_PPRE_Pos (8U)
	3416	#define RCC_CFGR_PPRE_Msk (0x7U << RCC_CFGR_PPRE_Pos) /!< 0x00000700 /
	3417	#define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /!< PRE[2:0] bits (APB prescaler) /
	3418	#define RCC_CFGR_PPRE_0 (0x1U << RCC_CFGR_PPRE_Pos) /!< 0x00000100 /
	3419	#define RCC_CFGR_PPRE_1 (0x2U << RCC_CFGR_PPRE_Pos) /!< 0x00000200 /
	3420	#define RCC_CFGR_PPRE_2 (0x4U << RCC_CFGR_PPRE_Pos) /!< 0x00000400 /
	3421
	3422	#define RCC_CFGR_PPRE_DIV1 (0x00000000U) /!< HCLK not divided /
	3423	#define RCC_CFGR_PPRE_DIV2_Pos (10U)
	3424	#define RCC_CFGR_PPRE_DIV2_Msk (0x1U << RCC_CFGR_PPRE_DIV2_Pos) /!< 0x00000400 /
	3425	#define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /!< HCLK divided by 2 /
	3426	#define RCC_CFGR_PPRE_DIV4_Pos (8U)
	3427	#define RCC_CFGR_PPRE_DIV4_Msk (0x5U << RCC_CFGR_PPRE_DIV4_Pos) /!< 0x00000500 /
	3428	#define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /!< HCLK divided by 4 /
	3429	#define RCC_CFGR_PPRE_DIV8_Pos (9U)
	3430	#define RCC_CFGR_PPRE_DIV8_Msk (0x3U << RCC_CFGR_PPRE_DIV8_Pos) /!< 0x00000600 /
	3431	#define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /!< HCLK divided by 8 /
	3432	#define RCC_CFGR_PPRE_DIV16_Pos (8U)
	3433	#define RCC_CFGR_PPRE_DIV16_Msk (0x7U << RCC_CFGR_PPRE_DIV16_Pos) /!< 0x00000700 /
	3434	#define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /!< HCLK divided by 16 /
	3435
	3436	/!< ADCPPRE configuration /
	3437	#define RCC_CFGR_ADCPRE_Pos (14U)
	3438	#define RCC_CFGR_ADCPRE_Msk (0x1U << RCC_CFGR_ADCPRE_Pos) /!< 0x00004000 /
	3439	#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /!< ADCPRE bit (ADC prescaler) /
	3440
	3441	#define RCC_CFGR_ADCPRE_DIV2 (0x00000000U) /!< PCLK divided by 2 /
	3442	#define RCC_CFGR_ADCPRE_DIV4 (0x00004000U) /!< PCLK divided by 4 /
	3443
	3444	#define RCC_CFGR_PLLSRC_Pos (16U)
	3445	#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /!< 0x00010000 /
	3446	#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /!< PLL entry clock source /
	3447	#define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /!< HSI clock divided by 2 selected as PLL entry clock source /
	3448	#define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /!< HSE/PREDIV clock selected as PLL entry clock source /
	3449
	3450	#define RCC_CFGR_PLLXTPRE_Pos (17U)
	3451	#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /!< 0x00020000 /
	3452	#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /!< HSE divider for PLL entry /
	3453	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /!< HSE/PREDIV clock not divided for PLL entry /
	3454	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /!< HSE/PREDIV clock divided by 2 for PLL entry /
	3455
	3456	/!< PLLMUL configuration /
	3457	#define RCC_CFGR_PLLMUL_Pos (18U)
	3458	#define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /!< 0x003C0000 /
	3459	#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /!< PLLMUL[3:0] bits (PLL multiplication factor) /
	3460	#define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /!< 0x00040000 /
	3461	#define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /!< 0x00080000 /
	3462	#define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /!< 0x00100000 /
	3463	#define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /!< 0x00200000 /
	3464
	3465	#define RCC_CFGR_PLLMUL2 (0x00000000U) /!< PLL input clock2 */
	3466	#define RCC_CFGR_PLLMUL3 (0x00040000U) /!< PLL input clock3 */
	3467	#define RCC_CFGR_PLLMUL4 (0x00080000U) /!< PLL input clock4 */
	3468	#define RCC_CFGR_PLLMUL5 (0x000C0000U) /!< PLL input clock5 */
	3469	#define RCC_CFGR_PLLMUL6 (0x00100000U) /!< PLL input clock6 */
	3470	#define RCC_CFGR_PLLMUL7 (0x00140000U) /!< PLL input clock7 */
	3471	#define RCC_CFGR_PLLMUL8 (0x00180000U) /!< PLL input clock8 */
	3472	#define RCC_CFGR_PLLMUL9 (0x001C0000U) /!< PLL input clock9 */
	3473	#define RCC_CFGR_PLLMUL10 (0x00200000U) /!< PLL input clock10 /
	3474	#define RCC_CFGR_PLLMUL11 (0x00240000U) /!< PLL input clock11 */
	3475	#define RCC_CFGR_PLLMUL12 (0x00280000U) /!< PLL input clock12 */
	3476	#define RCC_CFGR_PLLMUL13 (0x002C0000U) /!< PLL input clock13 */
	3477	#define RCC_CFGR_PLLMUL14 (0x00300000U) /!< PLL input clock14 */
	3478	#define RCC_CFGR_PLLMUL15 (0x00340000U) /!< PLL input clock15 */
	3479	#define RCC_CFGR_PLLMUL16 (0x00380000U) /!< PLL input clock16 */
	3480
	3481	/!< MCO configuration /
	3482	#define RCC_CFGR_MCO_Pos (24U)
	3483	#define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /!< 0x0F000000 /
	3484	#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /!< MCO[3:0] bits (Microcontroller Clock Output) /
	3485	#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /!< 0x01000000 /
	3486	#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /!< 0x02000000 /
	3487	#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /!< 0x04000000 /
	3488
	3489	#define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /!< No clock /
	3490	#define RCC_CFGR_MCO_HSI14 (0x01000000U) /!< HSI14 clock selected as MCO source /
	3491	#define RCC_CFGR_MCO_LSI (0x02000000U) /!< LSI clock selected as MCO source /
	3492	#define RCC_CFGR_MCO_LSE (0x03000000U) /!< LSE clock selected as MCO source /
	3493	#define RCC_CFGR_MCO_SYSCLK (0x04000000U) /!< System clock selected as MCO source /
	3494	#define RCC_CFGR_MCO_HSI (0x05000000U) /!< HSI clock selected as MCO source /
	3495	#define RCC_CFGR_MCO_HSE (0x06000000U) /!< HSE clock selected as MCO source /
	3496	#define RCC_CFGR_MCO_PLL (0x07000000U) /!< PLL clock divided by 2 selected as MCO source /
	3497
	3498	/* Reference defines */
	3499	#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
	3500	#define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
	3501	#define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
	3502	#define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
	3503	#define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
	3504	#define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14
	3505	#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
	3506	#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
	3507	#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
	3508	#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
	3509	#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
	3510	#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
	3511
	3512	/!<*************** Bit definition for RCC_CIR register ***************/
	3513	#define RCC_CIR_LSIRDYF_Pos (0U)
	3514	#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /!< 0x00000001 /
	3515	#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /!< LSI Ready Interrupt flag /
	3516	#define RCC_CIR_LSERDYF_Pos (1U)
	3517	#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /!< 0x00000002 /
	3518	#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /!< LSE Ready Interrupt flag /
	3519	#define RCC_CIR_HSIRDYF_Pos (2U)
	3520	#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /!< 0x00000004 /
	3521	#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /!< HSI Ready Interrupt flag /
	3522	#define RCC_CIR_HSERDYF_Pos (3U)
	3523	#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /!< 0x00000008 /
	3524	#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /!< HSE Ready Interrupt flag /
	3525	#define RCC_CIR_PLLRDYF_Pos (4U)
	3526	#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /!< 0x00000010 /
	3527	#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /!< PLL Ready Interrupt flag /
	3528	#define RCC_CIR_HSI14RDYF_Pos (5U)
	3529	#define RCC_CIR_HSI14RDYF_Msk (0x1U << RCC_CIR_HSI14RDYF_Pos) /!< 0x00000020 /
	3530	#define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /!< HSI14 Ready Interrupt flag /
	3531	#define RCC_CIR_CSSF_Pos (7U)
	3532	#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /!< 0x00000080 /
	3533	#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /!< Clock Security System Interrupt flag /
	3534	#define RCC_CIR_LSIRDYIE_Pos (8U)
	3535	#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /!< 0x00000100 /
	3536	#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /!< LSI Ready Interrupt Enable /
	3537	#define RCC_CIR_LSERDYIE_Pos (9U)
	3538	#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /!< 0x00000200 /
	3539	#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /!< LSE Ready Interrupt Enable /
	3540	#define RCC_CIR_HSIRDYIE_Pos (10U)
	3541	#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /!< 0x00000400 /
	3542	#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /!< HSI Ready Interrupt Enable /
	3543	#define RCC_CIR_HSERDYIE_Pos (11U)
	3544	#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /!< 0x00000800 /
	3545	#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /!< HSE Ready Interrupt Enable /
	3546	#define RCC_CIR_PLLRDYIE_Pos (12U)
	3547	#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /!< 0x00001000 /
	3548	#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /!< PLL Ready Interrupt Enable /
	3549	#define RCC_CIR_HSI14RDYIE_Pos (13U)
	3550	#define RCC_CIR_HSI14RDYIE_Msk (0x1U << RCC_CIR_HSI14RDYIE_Pos) /!< 0x00002000 /
	3551	#define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /!< HSI14 Ready Interrupt Enable /
	3552	#define RCC_CIR_LSIRDYC_Pos (16U)
	3553	#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /!< 0x00010000 /
	3554	#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /!< LSI Ready Interrupt Clear /
	3555	#define RCC_CIR_LSERDYC_Pos (17U)
	3556	#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /!< 0x00020000 /
	3557	#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /!< LSE Ready Interrupt Clear /
	3558	#define RCC_CIR_HSIRDYC_Pos (18U)
	3559	#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /!< 0x00040000 /
	3560	#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /!< HSI Ready Interrupt Clear /
	3561	#define RCC_CIR_HSERDYC_Pos (19U)
	3562	#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /!< 0x00080000 /
	3563	#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /!< HSE Ready Interrupt Clear /
	3564	#define RCC_CIR_PLLRDYC_Pos (20U)
	3565	#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /!< 0x00100000 /
	3566	#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /!< PLL Ready Interrupt Clear /
	3567	#define RCC_CIR_HSI14RDYC_Pos (21U)
	3568	#define RCC_CIR_HSI14RDYC_Msk (0x1U << RCC_CIR_HSI14RDYC_Pos) /!< 0x00200000 /
	3569	#define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /!< HSI14 Ready Interrupt Clear /
	3570	#define RCC_CIR_CSSC_Pos (23U)
	3571	#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /!< 0x00800000 /
	3572	#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /!< Clock Security System Interrupt Clear /
	3573
	3574	/*************** Bit definition for RCC_APB2RSTR register **************/
	3575	#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
	3576	#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /!< 0x00000001 /
	3577	#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /!< SYSCFG reset /
	3578	#define RCC_APB2RSTR_ADCRST_Pos (9U)
	3579	#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /!< 0x00000200 /
	3580	#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /!< ADC reset /
	3581	#define RCC_APB2RSTR_TIM1RST_Pos (11U)
	3582	#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /!< 0x00000800 /
	3583	#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /!< TIM1 reset /
	3584	#define RCC_APB2RSTR_SPI1RST_Pos (12U)
	3585	#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /!< 0x00001000 /
	3586	#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /!< SPI1 reset /
	3587	#define RCC_APB2RSTR_USART1RST_Pos (14U)
	3588	#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /!< 0x00004000 /
	3589	#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /!< USART1 reset /
	3590	#define RCC_APB2RSTR_TIM15RST_Pos (16U)
	3591	#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /!< 0x00010000 /
	3592	#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /!< TIM15 reset /
	3593	#define RCC_APB2RSTR_TIM16RST_Pos (17U)
	3594	#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /!< 0x00020000 /
	3595	#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /!< TIM16 reset /
	3596	#define RCC_APB2RSTR_TIM17RST_Pos (18U)
	3597	#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /!< 0x00040000 /
	3598	#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /!< TIM17 reset /
	3599	#define RCC_APB2RSTR_DBGMCURST_Pos (22U)
	3600	#define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /!< 0x00400000 /
	3601	#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /!< DBGMCU reset /
	3602
	3603	/!< Old ADC1 reset bit definition maintained for legacy purpose /
	3604	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
	3605
	3606	/*************** Bit definition for RCC_APB1RSTR register **************/
	3607	#define RCC_APB1RSTR_TIM2RST_Pos (0U)
	3608	#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /!< 0x00000001 /
	3609	#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /!< Timer 2 reset /
	3610	#define RCC_APB1RSTR_TIM3RST_Pos (1U)
	3611	#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /!< 0x00000002 /
	3612	#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /!< Timer 3 reset /
	3613	#define RCC_APB1RSTR_TIM6RST_Pos (4U)
	3614	#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /!< 0x00000010 /
	3615	#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /!< Timer 6 reset /
	3616	#define RCC_APB1RSTR_TIM14RST_Pos (8U)
	3617	#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /!< 0x00000100 /
	3618	#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /!< Timer 14 reset /
	3619	#define RCC_APB1RSTR_WWDGRST_Pos (11U)
	3620	#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /!< 0x00000800 /
	3621	#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /!< Window Watchdog reset /
	3622	#define RCC_APB1RSTR_SPI2RST_Pos (14U)
	3623	#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /!< 0x00004000 /
	3624	#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /!< SPI2 reset /
	3625	#define RCC_APB1RSTR_USART2RST_Pos (17U)
	3626	#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /!< 0x00020000 /
	3627	#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /!< USART 2 reset /
	3628	#define RCC_APB1RSTR_I2C1RST_Pos (21U)
	3629	#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /!< 0x00200000 /
	3630	#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /!< I2C 1 reset /
	3631	#define RCC_APB1RSTR_I2C2RST_Pos (22U)
	3632	#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /!< 0x00400000 /
	3633	#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /!< I2C 2 reset /
	3634	#define RCC_APB1RSTR_PWRRST_Pos (28U)
	3635	#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /!< 0x10000000 /
	3636	#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /!< PWR reset /
	3637	#define RCC_APB1RSTR_DACRST_Pos (29U)
	3638	#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /!< 0x20000000 /
	3639	#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /!< DAC reset /
	3640	#define RCC_APB1RSTR_CECRST_Pos (30U)
	3641	#define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /!< 0x40000000 /
	3642	#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /!< CEC reset /
	3643
	3644	/**************** Bit definition for RCC_AHBENR register ***************/
	3645	#define RCC_AHBENR_DMAEN_Pos (0U)
	3646	#define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /!< 0x00000001 /
	3647	#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /!< DMA1 clock enable /
	3648	#define RCC_AHBENR_SRAMEN_Pos (2U)
	3649	#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /!< 0x00000004 /
	3650	#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /!< SRAM interface clock enable /
	3651	#define RCC_AHBENR_FLITFEN_Pos (4U)
	3652	#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /!< 0x00000010 /
	3653	#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /!< FLITF clock enable /
	3654	#define RCC_AHBENR_CRCEN_Pos (6U)
	3655	#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /!< 0x00000040 /
	3656	#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /!< CRC clock enable /
	3657	#define RCC_AHBENR_GPIOAEN_Pos (17U)
	3658	#define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /!< 0x00020000 /
	3659	#define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /!< GPIOA clock enable /
	3660	#define RCC_AHBENR_GPIOBEN_Pos (18U)
	3661	#define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /!< 0x00040000 /
	3662	#define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /!< GPIOB clock enable /
	3663	#define RCC_AHBENR_GPIOCEN_Pos (19U)
	3664	#define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /!< 0x00080000 /
	3665	#define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /!< GPIOC clock enable /
	3666	#define RCC_AHBENR_GPIODEN_Pos (20U)
	3667	#define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /!< 0x00100000 /
	3668	#define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /!< GPIOD clock enable /
	3669	#define RCC_AHBENR_GPIOFEN_Pos (22U)
	3670	#define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /!< 0x00400000 /
	3671	#define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /!< GPIOF clock enable /
	3672	#define RCC_AHBENR_TSCEN_Pos (24U)
	3673	#define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /!< 0x01000000 /
	3674	#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /!< TS controller clock enable /
	3675
	3676	/* Old Bit definition maintained for legacy purpose */
	3677	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
	3678	#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /!< TS clock enable /
	3679
	3680	/*************** Bit definition for RCC_APB2ENR register ***************/
	3681	#define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U)
	3682	#define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1U << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /!< 0x00000001 /
	3683	#define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /!< SYSCFG and comparator clock enable /
	3684	#define RCC_APB2ENR_ADCEN_Pos (9U)
	3685	#define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /!< 0x00000200 /
	3686	#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /!< ADC1 clock enable /
	3687	#define RCC_APB2ENR_TIM1EN_Pos (11U)
	3688	#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /!< 0x00000800 /
	3689	#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /!< TIM1 clock enable /
	3690	#define RCC_APB2ENR_SPI1EN_Pos (12U)
	3691	#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /!< 0x00001000 /
	3692	#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /!< SPI1 clock enable /
	3693	#define RCC_APB2ENR_USART1EN_Pos (14U)
	3694	#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /!< 0x00004000 /
	3695	#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /!< USART1 clock enable /
	3696	#define RCC_APB2ENR_TIM15EN_Pos (16U)
	3697	#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /!< 0x00010000 /
	3698	#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /!< TIM15 clock enable /
	3699	#define RCC_APB2ENR_TIM16EN_Pos (17U)
	3700	#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /!< 0x00020000 /
	3701	#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /!< TIM16 clock enable /
	3702	#define RCC_APB2ENR_TIM17EN_Pos (18U)
	3703	#define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /!< 0x00040000 /
	3704	#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /!< TIM17 clock enable /
	3705	#define RCC_APB2ENR_DBGMCUEN_Pos (22U)
	3706	#define RCC_APB2ENR_DBGMCUEN_Msk (0x1U << RCC_APB2ENR_DBGMCUEN_Pos) /!< 0x00400000 /
	3707	#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /!< DBGMCU clock enable /
	3708
	3709	/* Old Bit definition maintained for legacy purpose */
	3710	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /!< SYSCFG clock enable /
	3711	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
	3712
	3713	/*************** Bit definition for RCC_APB1ENR register ***************/
	3714	#define RCC_APB1ENR_TIM2EN_Pos (0U)
	3715	#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /!< 0x00000001 /
	3716	#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /!< Timer 2 clock enable /
	3717	#define RCC_APB1ENR_TIM3EN_Pos (1U)
	3718	#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /!< 0x00000002 /
	3719	#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /!< Timer 3 clock enable /
	3720	#define RCC_APB1ENR_TIM6EN_Pos (4U)
	3721	#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /!< 0x00000010 /
	3722	#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /!< Timer 6 clock enable /
	3723	#define RCC_APB1ENR_TIM14EN_Pos (8U)
	3724	#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /!< 0x00000100 /
	3725	#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /!< Timer 14 clock enable /
	3726	#define RCC_APB1ENR_WWDGEN_Pos (11U)
	3727	#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /!< 0x00000800 /
	3728	#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /!< Window Watchdog clock enable /
	3729	#define RCC_APB1ENR_SPI2EN_Pos (14U)
	3730	#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /!< 0x00004000 /
	3731	#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /!< SPI2 clock enable /
	3732	#define RCC_APB1ENR_USART2EN_Pos (17U)
	3733	#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /!< 0x00020000 /
	3734	#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /!< USART2 clock enable /
	3735	#define RCC_APB1ENR_I2C1EN_Pos (21U)
	3736	#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /!< 0x00200000 /
	3737	#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /!< I2C1 clock enable /
	3738	#define RCC_APB1ENR_I2C2EN_Pos (22U)
	3739	#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /!< 0x00400000 /
	3740	#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /!< I2C2 clock enable /
	3741	#define RCC_APB1ENR_PWREN_Pos (28U)
	3742	#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /!< 0x10000000 /
	3743	#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /!< PWR clock enable /
	3744	#define RCC_APB1ENR_DACEN_Pos (29U)
	3745	#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /!< 0x20000000 /
	3746	#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /!< DAC clock enable /
	3747	#define RCC_APB1ENR_CECEN_Pos (30U)
	3748	#define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /!< 0x40000000 /
	3749	#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /!< CEC clock enable /
	3750
	3751	/***************** Bit definition for RCC_BDCR register ****************/
	3752	#define RCC_BDCR_LSEON_Pos (0U)
	3753	#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /!< 0x00000001 /
	3754	#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /!< External Low Speed oscillator enable /
	3755	#define RCC_BDCR_LSERDY_Pos (1U)
	3756	#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /!< 0x00000002 /
	3757	#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /!< External Low Speed oscillator Ready /
	3758	#define RCC_BDCR_LSEBYP_Pos (2U)
	3759	#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /!< 0x00000004 /
	3760	#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /!< External Low Speed oscillator Bypass /
	3761
	3762	#define RCC_BDCR_LSEDRV_Pos (3U)
	3763	#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /!< 0x00000018 /
	3764	#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
	3765	#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /!< 0x00000008 /
	3766	#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /!< 0x00000010 /
	3767
	3768	#define RCC_BDCR_RTCSEL_Pos (8U)
	3769	#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000300 /
	3770	#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /!< RTCSEL[1:0] bits (RTC clock source selection) /
	3771	#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000100 /
	3772	#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000200 /
	3773
	3774	/!< RTC configuration /
	3775	#define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /!< No clock /
	3776	#define RCC_BDCR_RTCSEL_LSE (0x00000100U) /!< LSE oscillator clock used as RTC clock /
	3777	#define RCC_BDCR_RTCSEL_LSI (0x00000200U) /!< LSI oscillator clock used as RTC clock /
	3778	#define RCC_BDCR_RTCSEL_HSE (0x00000300U) /!< HSE oscillator clock divided by 128 used as RTC clock /
	3779
	3780	#define RCC_BDCR_RTCEN_Pos (15U)
	3781	#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /!< 0x00008000 /
	3782	#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /!< RTC clock enable /
	3783	#define RCC_BDCR_BDRST_Pos (16U)
	3784	#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /!< 0x00010000 /
	3785	#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /!< Backup domain software reset /
	3786
	3787	/***************** Bit definition for RCC_CSR register *****************/
	3788	#define RCC_CSR_LSION_Pos (0U)
	3789	#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /!< 0x00000001 /
	3790	#define RCC_CSR_LSION RCC_CSR_LSION_Msk /!< Internal Low Speed oscillator enable /
	3791	#define RCC_CSR_LSIRDY_Pos (1U)
	3792	#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /!< 0x00000002 /
	3793	#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /!< Internal Low Speed oscillator Ready /
	3794	#define RCC_CSR_V18PWRRSTF_Pos (23U)
	3795	#define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /!< 0x00800000 /
	3796	#define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /!< V1.8 power domain reset flag /
	3797	#define RCC_CSR_RMVF_Pos (24U)
	3798	#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /!< 0x01000000 /
	3799	#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /!< Remove reset flag /
	3800	#define RCC_CSR_OBLRSTF_Pos (25U)
	3801	#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /!< 0x02000000 /
	3802	#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /!< OBL reset flag /
	3803	#define RCC_CSR_PINRSTF_Pos (26U)
	3804	#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /!< 0x04000000 /
	3805	#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /!< PIN reset flag /
	3806	#define RCC_CSR_PORRSTF_Pos (27U)
	3807	#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /!< 0x08000000 /
	3808	#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /!< POR/PDR reset flag /
	3809	#define RCC_CSR_SFTRSTF_Pos (28U)
	3810	#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /!< 0x10000000 /
	3811	#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /!< Software Reset flag /
	3812	#define RCC_CSR_IWDGRSTF_Pos (29U)
	3813	#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /!< 0x20000000 /
	3814	#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /!< Independent Watchdog reset flag /
	3815	#define RCC_CSR_WWDGRSTF_Pos (30U)
	3816	#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /!< 0x40000000 /
	3817	#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /!< Window watchdog reset flag /
	3818	#define RCC_CSR_LPWRRSTF_Pos (31U)
	3819	#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /!< 0x80000000 /
	3820	#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /!< Low-Power reset flag /
	3821
	3822	/* Old Bit definition maintained for legacy purpose */
	3823	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
	3824
	3825	/***************** Bit definition for RCC_AHBRSTR register *************/
	3826	#define RCC_AHBRSTR_GPIOARST_Pos (17U)
	3827	#define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /!< 0x00020000 /
	3828	#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /!< GPIOA reset /
	3829	#define RCC_AHBRSTR_GPIOBRST_Pos (18U)
	3830	#define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /!< 0x00040000 /
	3831	#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /!< GPIOB reset /
	3832	#define RCC_AHBRSTR_GPIOCRST_Pos (19U)
	3833	#define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /!< 0x00080000 /
	3834	#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /!< GPIOC reset /
	3835	#define RCC_AHBRSTR_GPIODRST_Pos (20U)
	3836	#define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /!< 0x00100000 /
	3837	#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /!< GPIOD reset /
	3838	#define RCC_AHBRSTR_GPIOFRST_Pos (22U)
	3839	#define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /!< 0x00400000 /
	3840	#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /!< GPIOF reset /
	3841	#define RCC_AHBRSTR_TSCRST_Pos (24U)
	3842	#define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /!< 0x01000000 /
	3843	#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /!< TS reset /
	3844
	3845	/* Old Bit definition maintained for legacy purpose */
	3846	#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /!< TS reset /
	3847
	3848	/***************** Bit definition for RCC_CFGR2 register ***************/
	3849	/!< PREDIV configuration /
	3850	#define RCC_CFGR2_PREDIV_Pos (0U)
	3851	#define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /!< 0x0000000F /
	3852	#define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /!< PREDIV[3:0] bits /
	3853	#define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /!< 0x00000001 /
	3854	#define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /!< 0x00000002 /
	3855	#define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /!< 0x00000004 /
	3856	#define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /!< 0x00000008 /
	3857
	3858	#define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /!< PREDIV input clock not divided /
	3859	#define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /!< PREDIV input clock divided by 2 /
	3860	#define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /!< PREDIV input clock divided by 3 /
	3861	#define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /!< PREDIV input clock divided by 4 /
	3862	#define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /!< PREDIV input clock divided by 5 /
	3863	#define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /!< PREDIV input clock divided by 6 /
	3864	#define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /!< PREDIV input clock divided by 7 /
	3865	#define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /!< PREDIV input clock divided by 8 /
	3866	#define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /!< PREDIV input clock divided by 9 /
	3867	#define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /!< PREDIV input clock divided by 10 /
	3868	#define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /!< PREDIV input clock divided by 11 /
	3869	#define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /!< PREDIV input clock divided by 12 /
	3870	#define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /!< PREDIV input clock divided by 13 /
	3871	#define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /!< PREDIV input clock divided by 14 /
	3872	#define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /!< PREDIV input clock divided by 15 /
	3873	#define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /!< PREDIV input clock divided by 16 /
	3874
	3875	/***************** Bit definition for RCC_CFGR3 register ***************/
	3876	/!< USART1 Clock source selection /
	3877	#define RCC_CFGR3_USART1SW_Pos (0U)
	3878	#define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /!< 0x00000003 /
	3879	#define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /!< USART1SW[1:0] bits /
	3880	#define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /!< 0x00000001 /
	3881	#define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /!< 0x00000002 /
	3882
	3883	#define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /!< PCLK clock used as USART1 clock source /
	3884	#define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /!< System clock selected as USART1 clock source /
	3885	#define RCC_CFGR3_USART1SW_LSE (0x00000002U) /!< LSE oscillator clock used as USART1 clock source /
	3886	#define RCC_CFGR3_USART1SW_HSI (0x00000003U) /!< HSI oscillator clock used as USART1 clock source /
	3887
	3888	/!< I2C1 Clock source selection /
	3889	#define RCC_CFGR3_I2C1SW_Pos (4U)
	3890	#define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /!< 0x00000010 /
	3891	#define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /!< I2C1SW bits /
	3892
	3893	#define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /!< HSI oscillator clock used as I2C1 clock source /
	3894	#define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
	3895	#define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /!< 0x00000010 /
	3896	#define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /!< System clock selected as I2C1 clock source /
	3897
	3898	/!< CEC Clock source selection /
	3899	#define RCC_CFGR3_CECSW_Pos (6U)
	3900	#define RCC_CFGR3_CECSW_Msk (0x1U << RCC_CFGR3_CECSW_Pos) /!< 0x00000040 /
	3901	#define RCC_CFGR3_CECSW RCC_CFGR3_CECSW_Msk /!< CECSW bits /
	3902
	3903	#define RCC_CFGR3_CECSW_HSI_DIV244 (0x00000000U) /!< HSI clock divided by 244 selected as HDMI CEC entry clock source /
	3904	#define RCC_CFGR3_CECSW_LSE_Pos (6U)
	3905	#define RCC_CFGR3_CECSW_LSE_Msk (0x1U << RCC_CFGR3_CECSW_LSE_Pos) /!< 0x00000040 /
	3906	#define RCC_CFGR3_CECSW_LSE RCC_CFGR3_CECSW_LSE_Msk /!< LSE clock selected as HDMI CEC entry clock source /
	3907
	3908	/***************** Bit definition for RCC_CR2 register *****************/
	3909	#define RCC_CR2_HSI14ON_Pos (0U)
	3910	#define RCC_CR2_HSI14ON_Msk (0x1U << RCC_CR2_HSI14ON_Pos) /!< 0x00000001 /
	3911	#define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /!< Internal High Speed 14MHz clock enable /
	3912	#define RCC_CR2_HSI14RDY_Pos (1U)
	3913	#define RCC_CR2_HSI14RDY_Msk (0x1U << RCC_CR2_HSI14RDY_Pos) /!< 0x00000002 /
	3914	#define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /!< Internal High Speed 14MHz clock ready flag /
	3915	#define RCC_CR2_HSI14DIS_Pos (2U)
	3916	#define RCC_CR2_HSI14DIS_Msk (0x1U << RCC_CR2_HSI14DIS_Pos) /!< 0x00000004 /
	3917	#define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /!< Internal High Speed 14MHz clock disable /
	3918	#define RCC_CR2_HSI14TRIM_Pos (3U)
	3919	#define RCC_CR2_HSI14TRIM_Msk (0x1FU << RCC_CR2_HSI14TRIM_Pos) /!< 0x000000F8 /
	3920	#define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /!< Internal High Speed 14MHz clock trimming /
	3921	#define RCC_CR2_HSI14CAL_Pos (8U)
	3922	#define RCC_CR2_HSI14CAL_Msk (0xFFU << RCC_CR2_HSI14CAL_Pos) /!< 0x0000FF00 /
	3923	#define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /!< Internal High Speed 14MHz clock Calibration /
	3924
	3925	/*****************************************************************************/
	3926	/* */
	3927	/* Real-Time Clock (RTC) */
	3928	/* */
	3929	/*****************************************************************************/
	3930	/*
	3931	* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
	3932	*/
	3933	#define RTC_TAMPER1_SUPPORT /!< TAMPER 1 feature support /
	3934	#define RTC_TAMPER2_SUPPORT /!< TAMPER 2 feature support /
	3935	#define RTC_BACKUP_SUPPORT /!< BACKUP register feature support /
	3936
	3937	/****************** Bits definition for RTC_TR register ****************/
	3938	#define RTC_TR_PM_Pos (22U)
	3939	#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /!< 0x00400000 /
	3940	#define RTC_TR_PM RTC_TR_PM_Msk
	3941	#define RTC_TR_HT_Pos (20U)
	3942	#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /!< 0x00300000 /
	3943	#define RTC_TR_HT RTC_TR_HT_Msk
	3944	#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /!< 0x00100000 /
	3945	#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /!< 0x00200000 /
	3946	#define RTC_TR_HU_Pos (16U)
	3947	#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /!< 0x000F0000 /
	3948	#define RTC_TR_HU RTC_TR_HU_Msk
	3949	#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /!< 0x00010000 /
	3950	#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /!< 0x00020000 /
	3951	#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /!< 0x00040000 /
	3952	#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /!< 0x00080000 /
	3953	#define RTC_TR_MNT_Pos (12U)
	3954	#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /!< 0x00007000 /
	3955	#define RTC_TR_MNT RTC_TR_MNT_Msk
	3956	#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /!< 0x00001000 /
	3957	#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /!< 0x00002000 /
	3958	#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /!< 0x00004000 /
	3959	#define RTC_TR_MNU_Pos (8U)
	3960	#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /!< 0x00000F00 /
	3961	#define RTC_TR_MNU RTC_TR_MNU_Msk
	3962	#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /!< 0x00000100 /
	3963	#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /!< 0x00000200 /
	3964	#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /!< 0x00000400 /
	3965	#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /!< 0x00000800 /
	3966	#define RTC_TR_ST_Pos (4U)
	3967	#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /!< 0x00000070 /
	3968	#define RTC_TR_ST RTC_TR_ST_Msk
	3969	#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /!< 0x00000010 /
	3970	#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /!< 0x00000020 /
	3971	#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /!< 0x00000040 /
	3972	#define RTC_TR_SU_Pos (0U)
	3973	#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /!< 0x0000000F /
	3974	#define RTC_TR_SU RTC_TR_SU_Msk
	3975	#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /!< 0x00000001 /
	3976	#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /!< 0x00000002 /
	3977	#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /!< 0x00000004 /
	3978	#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /!< 0x00000008 /
	3979
	3980	/****************** Bits definition for RTC_DR register ****************/
	3981	#define RTC_DR_YT_Pos (20U)
	3982	#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /!< 0x00F00000 /
	3983	#define RTC_DR_YT RTC_DR_YT_Msk
	3984	#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /!< 0x00100000 /
	3985	#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /!< 0x00200000 /
	3986	#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /!< 0x00400000 /
	3987	#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /!< 0x00800000 /
	3988	#define RTC_DR_YU_Pos (16U)
	3989	#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /!< 0x000F0000 /
	3990	#define RTC_DR_YU RTC_DR_YU_Msk
	3991	#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /!< 0x00010000 /
	3992	#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /!< 0x00020000 /
	3993	#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /!< 0x00040000 /
	3994	#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /!< 0x00080000 /
	3995	#define RTC_DR_WDU_Pos (13U)
	3996	#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /!< 0x0000E000 /
	3997	#define RTC_DR_WDU RTC_DR_WDU_Msk
	3998	#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /!< 0x00002000 /
	3999	#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /!< 0x00004000 /
	4000	#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /!< 0x00008000 /
	4001	#define RTC_DR_MT_Pos (12U)
	4002	#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /!< 0x00001000 /
	4003	#define RTC_DR_MT RTC_DR_MT_Msk
	4004	#define RTC_DR_MU_Pos (8U)
	4005	#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /!< 0x00000F00 /
	4006	#define RTC_DR_MU RTC_DR_MU_Msk
	4007	#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /!< 0x00000100 /
	4008	#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /!< 0x00000200 /
	4009	#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /!< 0x00000400 /
	4010	#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /!< 0x00000800 /
	4011	#define RTC_DR_DT_Pos (4U)
	4012	#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /!< 0x00000030 /
	4013	#define RTC_DR_DT RTC_DR_DT_Msk
	4014	#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /!< 0x00000010 /
	4015	#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /!< 0x00000020 /
	4016	#define RTC_DR_DU_Pos (0U)
	4017	#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /!< 0x0000000F /
	4018	#define RTC_DR_DU RTC_DR_DU_Msk
	4019	#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /!< 0x00000001 /
	4020	#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /!< 0x00000002 /
	4021	#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /!< 0x00000004 /
	4022	#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /!< 0x00000008 /
	4023
	4024	/****************** Bits definition for RTC_CR register ****************/
	4025	#define RTC_CR_COE_Pos (23U)
	4026	#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /!< 0x00800000 /
	4027	#define RTC_CR_COE RTC_CR_COE_Msk
	4028	#define RTC_CR_OSEL_Pos (21U)
	4029	#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /!< 0x00600000 /
	4030	#define RTC_CR_OSEL RTC_CR_OSEL_Msk
	4031	#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /!< 0x00200000 /
	4032	#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /!< 0x00400000 /
	4033	#define RTC_CR_POL_Pos (20U)
	4034	#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /!< 0x00100000 /
	4035	#define RTC_CR_POL RTC_CR_POL_Msk
	4036	#define RTC_CR_COSEL_Pos (19U)
	4037	#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /!< 0x00080000 /
	4038	#define RTC_CR_COSEL RTC_CR_COSEL_Msk
	4039	#define RTC_CR_BKP_Pos (18U)
	4040	#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /!< 0x00040000 /
	4041	#define RTC_CR_BKP RTC_CR_BKP_Msk
	4042	#define RTC_CR_SUB1H_Pos (17U)
	4043	#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /!< 0x00020000 /
	4044	#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
	4045	#define RTC_CR_ADD1H_Pos (16U)
	4046	#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /!< 0x00010000 /
	4047	#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
	4048	#define RTC_CR_TSIE_Pos (15U)
	4049	#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /!< 0x00008000 /
	4050	#define RTC_CR_TSIE RTC_CR_TSIE_Msk
	4051	#define RTC_CR_ALRAIE_Pos (12U)
	4052	#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /!< 0x00001000 /
	4053	#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
	4054	#define RTC_CR_TSE_Pos (11U)
	4055	#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /!< 0x00000800 /
	4056	#define RTC_CR_TSE RTC_CR_TSE_Msk
	4057	#define RTC_CR_ALRAE_Pos (8U)
	4058	#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /!< 0x00000100 /
	4059	#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
	4060	#define RTC_CR_FMT_Pos (6U)
	4061	#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /!< 0x00000040 /
	4062	#define RTC_CR_FMT RTC_CR_FMT_Msk
	4063	#define RTC_CR_BYPSHAD_Pos (5U)
	4064	#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /!< 0x00000020 /
	4065	#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
	4066	#define RTC_CR_REFCKON_Pos (4U)
	4067	#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /!< 0x00000010 /
	4068	#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
	4069	#define RTC_CR_TSEDGE_Pos (3U)
	4070	#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /!< 0x00000008 /
	4071	#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
	4072
	4073	/* Legacy defines */
	4074	#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
	4075	#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
	4076	#define RTC_CR_BCK RTC_CR_BKP
	4077
	4078	/****************** Bits definition for RTC_ISR register ***************/
	4079	#define RTC_ISR_RECALPF_Pos (16U)
	4080	#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /!< 0x00010000 /
	4081	#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
	4082	#define RTC_ISR_TAMP2F_Pos (14U)
	4083	#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /!< 0x00004000 /
	4084	#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
	4085	#define RTC_ISR_TAMP1F_Pos (13U)
	4086	#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /!< 0x00002000 /
	4087	#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
	4088	#define RTC_ISR_TSOVF_Pos (12U)
	4089	#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /!< 0x00001000 /
	4090	#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
	4091	#define RTC_ISR_TSF_Pos (11U)
	4092	#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /!< 0x00000800 /
	4093	#define RTC_ISR_TSF RTC_ISR_TSF_Msk
	4094	#define RTC_ISR_ALRAF_Pos (8U)
	4095	#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /!< 0x00000100 /
	4096	#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
	4097	#define RTC_ISR_INIT_Pos (7U)
	4098	#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /!< 0x00000080 /
	4099	#define RTC_ISR_INIT RTC_ISR_INIT_Msk
	4100	#define RTC_ISR_INITF_Pos (6U)
	4101	#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /!< 0x00000040 /
	4102	#define RTC_ISR_INITF RTC_ISR_INITF_Msk
	4103	#define RTC_ISR_RSF_Pos (5U)
	4104	#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /!< 0x00000020 /
	4105	#define RTC_ISR_RSF RTC_ISR_RSF_Msk
	4106	#define RTC_ISR_INITS_Pos (4U)
	4107	#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /!< 0x00000010 /
	4108	#define RTC_ISR_INITS RTC_ISR_INITS_Msk
	4109	#define RTC_ISR_SHPF_Pos (3U)
	4110	#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /!< 0x00000008 /
	4111	#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
	4112	#define RTC_ISR_ALRAWF_Pos (0U)
	4113	#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /!< 0x00000001 /
	4114	#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
	4115
	4116	/****************** Bits definition for RTC_PRER register **************/
	4117	#define RTC_PRER_PREDIV_A_Pos (16U)
	4118	#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /!< 0x007F0000 /
	4119	#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
	4120	#define RTC_PRER_PREDIV_S_Pos (0U)
	4121	#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /!< 0x00007FFF /
	4122	#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
	4123
	4124	/****************** Bits definition for RTC_ALRMAR register ************/
	4125	#define RTC_ALRMAR_MSK4_Pos (31U)
	4126	#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /!< 0x80000000 /
	4127	#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
	4128	#define RTC_ALRMAR_WDSEL_Pos (30U)
	4129	#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /!< 0x40000000 /
	4130	#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
	4131	#define RTC_ALRMAR_DT_Pos (28U)
	4132	#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /!< 0x30000000 /
	4133	#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
	4134	#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /!< 0x10000000 /
	4135	#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /!< 0x20000000 /
	4136	#define RTC_ALRMAR_DU_Pos (24U)
	4137	#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /!< 0x0F000000 /
	4138	#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
	4139	#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /!< 0x01000000 /
	4140	#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /!< 0x02000000 /
	4141	#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /!< 0x04000000 /
	4142	#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /!< 0x08000000 /
	4143	#define RTC_ALRMAR_MSK3_Pos (23U)
	4144	#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /!< 0x00800000 /
	4145	#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
	4146	#define RTC_ALRMAR_PM_Pos (22U)
	4147	#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /!< 0x00400000 /
	4148	#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
	4149	#define RTC_ALRMAR_HT_Pos (20U)
	4150	#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /!< 0x00300000 /
	4151	#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
	4152	#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /!< 0x00100000 /
	4153	#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /!< 0x00200000 /
	4154	#define RTC_ALRMAR_HU_Pos (16U)
	4155	#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /!< 0x000F0000 /
	4156	#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
	4157	#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /!< 0x00010000 /
	4158	#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /!< 0x00020000 /
	4159	#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /!< 0x00040000 /
	4160	#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /!< 0x00080000 /
	4161	#define RTC_ALRMAR_MSK2_Pos (15U)
	4162	#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /!< 0x00008000 /
	4163	#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
	4164	#define RTC_ALRMAR_MNT_Pos (12U)
	4165	#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /!< 0x00007000 /
	4166	#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
	4167	#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /!< 0x00001000 /
	4168	#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /!< 0x00002000 /
	4169	#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /!< 0x00004000 /
	4170	#define RTC_ALRMAR_MNU_Pos (8U)
	4171	#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /!< 0x00000F00 /
	4172	#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
	4173	#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /!< 0x00000100 /
	4174	#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /!< 0x00000200 /
	4175	#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /!< 0x00000400 /
	4176	#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /!< 0x00000800 /
	4177	#define RTC_ALRMAR_MSK1_Pos (7U)
	4178	#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /!< 0x00000080 /
	4179	#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
	4180	#define RTC_ALRMAR_ST_Pos (4U)
	4181	#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /!< 0x00000070 /
	4182	#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
	4183	#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /!< 0x00000010 /
	4184	#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /!< 0x00000020 /
	4185	#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /!< 0x00000040 /
	4186	#define RTC_ALRMAR_SU_Pos (0U)
	4187	#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /!< 0x0000000F /
	4188	#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
	4189	#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /!< 0x00000001 /
	4190	#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /!< 0x00000002 /
	4191	#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /!< 0x00000004 /
	4192	#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /!< 0x00000008 /
	4193
	4194	/****************** Bits definition for RTC_WPR register ***************/
	4195	#define RTC_WPR_KEY_Pos (0U)
	4196	#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /!< 0x000000FF /
	4197	#define RTC_WPR_KEY RTC_WPR_KEY_Msk
	4198
	4199	/****************** Bits definition for RTC_SSR register ***************/
	4200	#define RTC_SSR_SS_Pos (0U)
	4201	#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /!< 0x0000FFFF /
	4202	#define RTC_SSR_SS RTC_SSR_SS_Msk
	4203
	4204	/****************** Bits definition for RTC_SHIFTR register ************/
	4205	#define RTC_SHIFTR_SUBFS_Pos (0U)
	4206	#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /!< 0x00007FFF /
	4207	#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
	4208	#define RTC_SHIFTR_ADD1S_Pos (31U)
	4209	#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /!< 0x80000000 /
	4210	#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
	4211
	4212	/****************** Bits definition for RTC_TSTR register **************/
	4213	#define RTC_TSTR_PM_Pos (22U)
	4214	#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /!< 0x00400000 /
	4215	#define RTC_TSTR_PM RTC_TSTR_PM_Msk
	4216	#define RTC_TSTR_HT_Pos (20U)
	4217	#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /!< 0x00300000 /
	4218	#define RTC_TSTR_HT RTC_TSTR_HT_Msk
	4219	#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /!< 0x00100000 /
	4220	#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /!< 0x00200000 /
	4221	#define RTC_TSTR_HU_Pos (16U)
	4222	#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /!< 0x000F0000 /
	4223	#define RTC_TSTR_HU RTC_TSTR_HU_Msk
	4224	#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /!< 0x00010000 /
	4225	#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /!< 0x00020000 /
	4226	#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /!< 0x00040000 /
	4227	#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /!< 0x00080000 /
	4228	#define RTC_TSTR_MNT_Pos (12U)
	4229	#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /!< 0x00007000 /
	4230	#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
	4231	#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /!< 0x00001000 /
	4232	#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /!< 0x00002000 /
	4233	#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /!< 0x00004000 /
	4234	#define RTC_TSTR_MNU_Pos (8U)
	4235	#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /!< 0x00000F00 /
	4236	#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
	4237	#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /!< 0x00000100 /
	4238	#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /!< 0x00000200 /
	4239	#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /!< 0x00000400 /
	4240	#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /!< 0x00000800 /
	4241	#define RTC_TSTR_ST_Pos (4U)
	4242	#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /!< 0x00000070 /
	4243	#define RTC_TSTR_ST RTC_TSTR_ST_Msk
	4244	#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /!< 0x00000010 /
	4245	#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /!< 0x00000020 /
	4246	#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /!< 0x00000040 /
	4247	#define RTC_TSTR_SU_Pos (0U)
	4248	#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /!< 0x0000000F /
	4249	#define RTC_TSTR_SU RTC_TSTR_SU_Msk
	4250	#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /!< 0x00000001 /
	4251	#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /!< 0x00000002 /
	4252	#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /!< 0x00000004 /
	4253	#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /!< 0x00000008 /
	4254
	4255	/****************** Bits definition for RTC_TSDR register **************/
	4256	#define RTC_TSDR_WDU_Pos (13U)
	4257	#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /!< 0x0000E000 /
	4258	#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
	4259	#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /!< 0x00002000 /
	4260	#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /!< 0x00004000 /
	4261	#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /!< 0x00008000 /
	4262	#define RTC_TSDR_MT_Pos (12U)
	4263	#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /!< 0x00001000 /
	4264	#define RTC_TSDR_MT RTC_TSDR_MT_Msk
	4265	#define RTC_TSDR_MU_Pos (8U)
	4266	#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /!< 0x00000F00 /
	4267	#define RTC_TSDR_MU RTC_TSDR_MU_Msk
	4268	#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /!< 0x00000100 /
	4269	#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /!< 0x00000200 /
	4270	#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /!< 0x00000400 /
	4271	#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /!< 0x00000800 /
	4272	#define RTC_TSDR_DT_Pos (4U)
	4273	#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /!< 0x00000030 /
	4274	#define RTC_TSDR_DT RTC_TSDR_DT_Msk
	4275	#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /!< 0x00000010 /
	4276	#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /!< 0x00000020 /
	4277	#define RTC_TSDR_DU_Pos (0U)
	4278	#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /!< 0x0000000F /
	4279	#define RTC_TSDR_DU RTC_TSDR_DU_Msk
	4280	#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /!< 0x00000001 /
	4281	#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /!< 0x00000002 /
	4282	#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /!< 0x00000004 /
	4283	#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /!< 0x00000008 /
	4284
	4285	/****************** Bits definition for RTC_TSSSR register *************/
	4286	#define RTC_TSSSR_SS_Pos (0U)
	4287	#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /!< 0x0000FFFF /
	4288	#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
	4289
	4290	/****************** Bits definition for RTC_CALR register **************/
	4291	#define RTC_CALR_CALP_Pos (15U)
	4292	#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /!< 0x00008000 /
	4293	#define RTC_CALR_CALP RTC_CALR_CALP_Msk
	4294	#define RTC_CALR_CALW8_Pos (14U)
	4295	#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /!< 0x00004000 /
	4296	#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
	4297	#define RTC_CALR_CALW16_Pos (13U)
	4298	#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /!< 0x00002000 /
	4299	#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
	4300	#define RTC_CALR_CALM_Pos (0U)
	4301	#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /!< 0x000001FF /
	4302	#define RTC_CALR_CALM RTC_CALR_CALM_Msk
	4303	#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /!< 0x00000001 /
	4304	#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /!< 0x00000002 /
	4305	#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /!< 0x00000004 /
	4306	#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /!< 0x00000008 /
	4307	#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /!< 0x00000010 /
	4308	#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /!< 0x00000020 /
	4309	#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /!< 0x00000040 /
	4310	#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /!< 0x00000080 /
	4311	#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /!< 0x00000100 /
	4312
	4313	/****************** Bits definition for RTC_TAFCR register *************/
	4314	#define RTC_TAFCR_PC15MODE_Pos (23U)
	4315	#define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /!< 0x00800000 /
	4316	#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
	4317	#define RTC_TAFCR_PC15VALUE_Pos (22U)
	4318	#define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /!< 0x00400000 /
	4319	#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
	4320	#define RTC_TAFCR_PC14MODE_Pos (21U)
	4321	#define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /!< 0x00200000 /
	4322	#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
	4323	#define RTC_TAFCR_PC14VALUE_Pos (20U)
	4324	#define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /!< 0x00100000 /
	4325	#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
	4326	#define RTC_TAFCR_PC13MODE_Pos (19U)
	4327	#define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /!< 0x00080000 /
	4328	#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
	4329	#define RTC_TAFCR_PC13VALUE_Pos (18U)
	4330	#define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /!< 0x00040000 /
	4331	#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
	4332	#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
	4333	#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /!< 0x00008000 /
	4334	#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
	4335	#define RTC_TAFCR_TAMPPRCH_Pos (13U)
	4336	#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /!< 0x00006000 /
	4337	#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
	4338	#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /!< 0x00002000 /
	4339	#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /!< 0x00004000 /
	4340	#define RTC_TAFCR_TAMPFLT_Pos (11U)
	4341	#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /!< 0x00001800 /
	4342	#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
	4343	#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /!< 0x00000800 /
	4344	#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /!< 0x00001000 /
	4345	#define RTC_TAFCR_TAMPFREQ_Pos (8U)
	4346	#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /!< 0x00000700 /
	4347	#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
	4348	#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /!< 0x00000100 /
	4349	#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /!< 0x00000200 /
	4350	#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /!< 0x00000400 /
	4351	#define RTC_TAFCR_TAMPTS_Pos (7U)
	4352	#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /!< 0x00000080 /
	4353	#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
	4354	#define RTC_TAFCR_TAMP2TRG_Pos (4U)
	4355	#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /!< 0x00000010 /
	4356	#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
	4357	#define RTC_TAFCR_TAMP2E_Pos (3U)
	4358	#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /!< 0x00000008 /
	4359	#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
	4360	#define RTC_TAFCR_TAMPIE_Pos (2U)
	4361	#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /!< 0x00000004 /
	4362	#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
	4363	#define RTC_TAFCR_TAMP1TRG_Pos (1U)
	4364	#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /!< 0x00000002 /
	4365	#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
	4366	#define RTC_TAFCR_TAMP1E_Pos (0U)
	4367	#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /!< 0x00000001 /
	4368	#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
	4369
	4370	/* Reference defines */
	4371	#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
	4372
	4373	/****************** Bits definition for RTC_ALRMASSR register **********/
	4374	#define RTC_ALRMASSR_MASKSS_Pos (24U)
	4375	#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /!< 0x0F000000 /
	4376	#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
	4377	#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /!< 0x01000000 /
	4378	#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /!< 0x02000000 /
	4379	#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /!< 0x04000000 /
	4380	#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /!< 0x08000000 /
	4381	#define RTC_ALRMASSR_SS_Pos (0U)
	4382	#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /!< 0x00007FFF /
	4383	#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
	4384
	4385	/****************** Bits definition for RTC_BKP0R register *************/
	4386	#define RTC_BKP0R_Pos (0U)
	4387	#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /!< 0xFFFFFFFF /
	4388	#define RTC_BKP0R RTC_BKP0R_Msk
	4389
	4390	/****************** Bits definition for RTC_BKP1R register *************/
	4391	#define RTC_BKP1R_Pos (0U)
	4392	#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /!< 0xFFFFFFFF /
	4393	#define RTC_BKP1R RTC_BKP1R_Msk
	4394
	4395	/****************** Bits definition for RTC_BKP2R register *************/
	4396	#define RTC_BKP2R_Pos (0U)
	4397	#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /!< 0xFFFFFFFF /
	4398	#define RTC_BKP2R RTC_BKP2R_Msk
	4399
	4400	/****************** Bits definition for RTC_BKP3R register *************/
	4401	#define RTC_BKP3R_Pos (0U)
	4402	#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /!< 0xFFFFFFFF /
	4403	#define RTC_BKP3R RTC_BKP3R_Msk
	4404
	4405	/****************** Bits definition for RTC_BKP4R register *************/
	4406	#define RTC_BKP4R_Pos (0U)
	4407	#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /!< 0xFFFFFFFF /
	4408	#define RTC_BKP4R RTC_BKP4R_Msk
	4409
	4410	/****************** Number of backup registers ****************************/
	4411	#define RTC_BKP_NUMBER 0x00000005U
	4412
	4413	/*****************************************************************************/
	4414	/* */
	4415	/* Serial Peripheral Interface (SPI) */
	4416	/* */
	4417	/*****************************************************************************/
	4418
	4419	/*
	4420	* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
	4421	*/
	4422	#define SPI_I2S_SUPPORT /!< I2S support /
	4423
	4424	/***************** Bit definition for SPI_CR1 register *****************/
	4425	#define SPI_CR1_CPHA_Pos (0U)
	4426	#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /!< 0x00000001 /
	4427	#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /!< Clock Phase /
	4428	#define SPI_CR1_CPOL_Pos (1U)
	4429	#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /!< 0x00000002 /
	4430	#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /!< Clock Polarity /
	4431	#define SPI_CR1_MSTR_Pos (2U)
	4432	#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /!< 0x00000004 /
	4433	#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /!< Master Selection /
	4434	#define SPI_CR1_BR_Pos (3U)
	4435	#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /!< 0x00000038 /
	4436	#define SPI_CR1_BR SPI_CR1_BR_Msk /!< BR[2:0] bits (Baud Rate Control) /
	4437	#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /!< 0x00000008 /
	4438	#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /!< 0x00000010 /
	4439	#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /!< 0x00000020 /
	4440	#define SPI_CR1_SPE_Pos (6U)
	4441	#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /!< 0x00000040 /
	4442	#define SPI_CR1_SPE SPI_CR1_SPE_Msk /!< SPI Enable /
	4443	#define SPI_CR1_LSBFIRST_Pos (7U)
	4444	#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /!< 0x00000080 /
	4445	#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /!< Frame Format /
	4446	#define SPI_CR1_SSI_Pos (8U)
	4447	#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /!< 0x00000100 /
	4448	#define SPI_CR1_SSI SPI_CR1_SSI_Msk /!< Internal slave select /
	4449	#define SPI_CR1_SSM_Pos (9U)
	4450	#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /!< 0x00000200 /
	4451	#define SPI_CR1_SSM SPI_CR1_SSM_Msk /!< Software slave management /
	4452	#define SPI_CR1_RXONLY_Pos (10U)
	4453	#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /!< 0x00000400 /
	4454	#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /!< Receive only /
	4455	#define SPI_CR1_CRCL_Pos (11U)
	4456	#define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /!< 0x00000800 /
	4457	#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /!< CRC Length /
	4458	#define SPI_CR1_CRCNEXT_Pos (12U)
	4459	#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /!< 0x00001000 /
	4460	#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /!< Transmit CRC next /
	4461	#define SPI_CR1_CRCEN_Pos (13U)
	4462	#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /!< 0x00002000 /
	4463	#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /!< Hardware CRC calculation enable /
	4464	#define SPI_CR1_BIDIOE_Pos (14U)
	4465	#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /!< 0x00004000 /
	4466	#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /!< Output enable in bidirectional mode /
	4467	#define SPI_CR1_BIDIMODE_Pos (15U)
	4468	#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /!< 0x00008000 /
	4469	#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /!< Bidirectional data mode enable /
	4470
	4471	/***************** Bit definition for SPI_CR2 register *****************/
	4472	#define SPI_CR2_RXDMAEN_Pos (0U)
	4473	#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /!< 0x00000001 /
	4474	#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /!< Rx Buffer DMA Enable /
	4475	#define SPI_CR2_TXDMAEN_Pos (1U)
	4476	#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /!< 0x00000002 /
	4477	#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /!< Tx Buffer DMA Enable /
	4478	#define SPI_CR2_SSOE_Pos (2U)
	4479	#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /!< 0x00000004 /
	4480	#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /!< SS Output Enable /
	4481	#define SPI_CR2_NSSP_Pos (3U)
	4482	#define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /!< 0x00000008 /
	4483	#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /!< NSS pulse management Enable /
	4484	#define SPI_CR2_FRF_Pos (4U)
	4485	#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /!< 0x00000010 /
	4486	#define SPI_CR2_FRF SPI_CR2_FRF_Msk /!< Frame Format Enable /
	4487	#define SPI_CR2_ERRIE_Pos (5U)
	4488	#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /!< 0x00000020 /
	4489	#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /!< Error Interrupt Enable /
	4490	#define SPI_CR2_RXNEIE_Pos (6U)
	4491	#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /!< 0x00000040 /
	4492	#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /!< RX buffer Not Empty Interrupt Enable /
	4493	#define SPI_CR2_TXEIE_Pos (7U)
	4494	#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /!< 0x00000080 /
	4495	#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /!< Tx buffer Empty Interrupt Enable /
	4496	#define SPI_CR2_DS_Pos (8U)
	4497	#define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /!< 0x00000F00 /
	4498	#define SPI_CR2_DS SPI_CR2_DS_Msk /!< DS[3:0] Data Size /
	4499	#define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /!< 0x00000100 /
	4500	#define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /!< 0x00000200 /
	4501	#define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /!< 0x00000400 /
	4502	#define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /!< 0x00000800 /
	4503	#define SPI_CR2_FRXTH_Pos (12U)
	4504	#define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /!< 0x00001000 /
	4505	#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /!< FIFO reception Threshold /
	4506	#define SPI_CR2_LDMARX_Pos (13U)
	4507	#define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /!< 0x00002000 /
	4508	#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /!< Last DMA transfer for reception /
	4509	#define SPI_CR2_LDMATX_Pos (14U)
	4510	#define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /!< 0x00004000 /
	4511	#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /!< Last DMA transfer for transmission /
	4512
	4513	/****************** Bit definition for SPI_SR register *****************/
	4514	#define SPI_SR_RXNE_Pos (0U)
	4515	#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /!< 0x00000001 /
	4516	#define SPI_SR_RXNE SPI_SR_RXNE_Msk /!< Receive buffer Not Empty /
	4517	#define SPI_SR_TXE_Pos (1U)
	4518	#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /!< 0x00000002 /
	4519	#define SPI_SR_TXE SPI_SR_TXE_Msk /!< Transmit buffer Empty /
	4520	#define SPI_SR_CHSIDE_Pos (2U)
	4521	#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /!< 0x00000004 /
	4522	#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /!< Channel side /
	4523	#define SPI_SR_UDR_Pos (3U)
	4524	#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /!< 0x00000008 /
	4525	#define SPI_SR_UDR SPI_SR_UDR_Msk /!< Underrun flag /
	4526	#define SPI_SR_CRCERR_Pos (4U)
	4527	#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /!< 0x00000010 /
	4528	#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /!< CRC Error flag /
	4529	#define SPI_SR_MODF_Pos (5U)
	4530	#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /!< 0x00000020 /
	4531	#define SPI_SR_MODF SPI_SR_MODF_Msk /!< Mode fault /
	4532	#define SPI_SR_OVR_Pos (6U)
	4533	#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /!< 0x00000040 /
	4534	#define SPI_SR_OVR SPI_SR_OVR_Msk /!< Overrun flag /
	4535	#define SPI_SR_BSY_Pos (7U)
	4536	#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /!< 0x00000080 /
	4537	#define SPI_SR_BSY SPI_SR_BSY_Msk /!< Busy flag /
	4538	#define SPI_SR_FRE_Pos (8U)
	4539	#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /!< 0x00000100 /
	4540	#define SPI_SR_FRE SPI_SR_FRE_Msk /!< TI frame format error /
	4541	#define SPI_SR_FRLVL_Pos (9U)
	4542	#define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /!< 0x00000600 /
	4543	#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /!< FIFO Reception Level /
	4544	#define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /!< 0x00000200 /
	4545	#define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /!< 0x00000400 /
	4546	#define SPI_SR_FTLVL_Pos (11U)
	4547	#define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /!< 0x00001800 /
	4548	#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /!< FIFO Transmission Level /
	4549	#define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /!< 0x00000800 /
	4550	#define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /!< 0x00001000 /
	4551
	4552	/****************** Bit definition for SPI_DR register *****************/
	4553	#define SPI_DR_DR_Pos (0U)
	4554	#define SPI_DR_DR_Msk (0xFFFFFFFFU << SPI_DR_DR_Pos) /!< 0xFFFFFFFF /
	4555	#define SPI_DR_DR SPI_DR_DR_Msk /!< Data Register /
	4556
	4557	/***************** Bit definition for SPI_CRCPR register ***************/
	4558	#define SPI_CRCPR_CRCPOLY_Pos (0U)
	4559	#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPR_CRCPOLY_Pos) /!< 0xFFFFFFFF /
	4560	#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /!< CRC polynomial register /
	4561
	4562	/**************** Bit definition for SPI_RXCRCR register ***************/
	4563	#define SPI_RXCRCR_RXCRC_Pos (0U)
	4564	#define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRCR_RXCRC_Pos) /!< 0xFFFFFFFF /
	4565	#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /!< Rx CRC Register /
	4566
	4567	/**************** Bit definition for SPI_TXCRCR register ***************/
	4568	#define SPI_TXCRCR_TXCRC_Pos (0U)
	4569	#define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRCR_TXCRC_Pos) /!< 0xFFFFFFFF /
	4570	#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /!< Tx CRC Register /
	4571
	4572	/**************** Bit definition for SPI_I2SCFGR register **************/
	4573	#define SPI_I2SCFGR_CHLEN_Pos (0U)
	4574	#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /!< 0x00000001 /
	4575	#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /!<Channel length (number of bits per audio channel) /
	4576	#define SPI_I2SCFGR_DATLEN_Pos (1U)
	4577	#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /!< 0x00000006 /
	4578	#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /!<DATLEN[1:0] bits (Data length to be transferred) /
	4579	#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /!< 0x00000002 /
	4580	#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /!< 0x00000004 /
	4581	#define SPI_I2SCFGR_CKPOL_Pos (3U)
	4582	#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /!< 0x00000008 /
	4583	#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /!<steady state clock polarity /
	4584	#define SPI_I2SCFGR_I2SSTD_Pos (4U)
	4585	#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /!< 0x00000030 /
	4586	#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /!<I2SSTD[1:0] bits (I2S standard selection) /
	4587	#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /!< 0x00000010 /
	4588	#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /!< 0x00000020 /
	4589	#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
	4590	#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /!< 0x00000080 /
	4591	#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /!<PCM frame synchronization /
	4592	#define SPI_I2SCFGR_I2SCFG_Pos (8U)
	4593	#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /!< 0x00000300 /
	4594	#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /!<I2SCFG[1:0] bits (I2S configuration mode) /
	4595	#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /!< 0x00000100 /
	4596	#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /!< 0x00000200 /
	4597	#define SPI_I2SCFGR_I2SE_Pos (10U)
	4598	#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /!< 0x00000400 /
	4599	#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /!<I2S Enable /
	4600	#define SPI_I2SCFGR_I2SMOD_Pos (11U)
	4601	#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /!< 0x00000800 /
	4602	#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /!<I2S mode selection /
	4603
	4604	/**************** Bit definition for SPI_I2SPR register ****************/
	4605	#define SPI_I2SPR_I2SDIV_Pos (0U)
	4606	#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /!< 0x000000FF /
	4607	#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /!<I2S Linear prescaler /
	4608	#define SPI_I2SPR_ODD_Pos (8U)
	4609	#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /!< 0x00000100 /
	4610	#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /!<Odd factor for the prescaler /
	4611	#define SPI_I2SPR_MCKOE_Pos (9U)
	4612	#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /!< 0x00000200 /
	4613	#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /!<Master Clock Output Enable /
	4614
	4615	/*****************************************************************************/
	4616	/* */
	4617	/* System Configuration (SYSCFG) */
	4618	/* */
	4619	/*****************************************************************************/
	4620	/*************** Bit definition for SYSCFG_CFGR1 register **************/
	4621	#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
	4622	#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /!< 0x00000003 /
	4623	#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /!< SYSCFG_Memory Remap Config /
	4624	#define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /!< 0x00000001 /
	4625	#define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /!< 0x00000002 /
	4626
	4627	#define SYSCFG_CFGR1_DMA_RMP_Pos (8U)
	4628	#define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FU << SYSCFG_CFGR1_DMA_RMP_Pos) /!< 0x00001F00 /
	4629	#define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /!< DMA remap mask /
	4630	#define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U)
	4631	#define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /!< 0x00000100 /
	4632	#define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk /!< ADC DMA remap /
	4633	#define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U)
	4634	#define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /!< 0x00000200 /
	4635	#define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /!< USART1 TX DMA remap /
	4636	#define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U)
	4637	#define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /!< 0x00000400 /
	4638	#define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /!< USART1 RX DMA remap /
	4639	#define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
	4640	#define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /!< 0x00000800 /
	4641	#define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /!< Timer 16 DMA remap /
	4642	#define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
	4643	#define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /!< 0x00001000 /
	4644	#define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /!< Timer 17 DMA remap /
	4645
	4646	#define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U)
	4647	#define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /!< 0x00010000 /
	4648	#define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /!< I2C PB6 Fast mode plus /
	4649	#define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U)
	4650	#define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /!< 0x00020000 /
	4651	#define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /!< I2C PB7 Fast mode plus /
	4652	#define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U)
	4653	#define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /!< 0x00040000 /
	4654	#define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /!< I2C PB8 Fast mode plus /
	4655	#define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U)
	4656	#define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /!< 0x00080000 /
	4657	#define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /!< I2C PB9 Fast mode plus /
	4658
	4659	/*************** Bit definition for SYSCFG_EXTICR1 register ************/
	4660	#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
	4661	#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /!< 0x0000000F /
	4662	#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /!< EXTI 0 configuration /
	4663	#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
	4664	#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /!< 0x000000F0 /
	4665	#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /!< EXTI 1 configuration /
	4666	#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
	4667	#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /!< 0x00000F00 /
	4668	#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /!< EXTI 2 configuration /
	4669	#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
	4670	#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /!< 0x0000F000 /
	4671	#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /!< EXTI 3 configuration /
	4672
	4673	/**
	4674	* @brief EXTI0 configuration
	4675	*/
	4676	#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /!< PA[0] pin /
	4677	#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /!< PB[0] pin /
	4678	#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /!< PC[0] pin /
	4679	#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /!< PD[0] pin /
	4680	#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /!< PF[0] pin /
	4681
	4682	/**
	4683	* @brief EXTI1 configuration
	4684	*/
	4685	#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /!< PA[1] pin /
	4686	#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /!< PB[1] pin /
	4687	#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /!< PC[1] pin /
	4688	#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /!< PD[1] pin /
	4689	#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /!< PF[1] pin /
	4690
	4691	/**
	4692	* @brief EXTI2 configuration
	4693	*/
	4694	#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /!< PA[2] pin /
	4695	#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /!< PB[2] pin /
	4696	#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /!< PC[2] pin /
	4697	#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /!< PD[2] pin /
	4698	#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /!< PF[2] pin /
	4699
	4700	/**
	4701	* @brief EXTI3 configuration
	4702	*/
	4703	#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /!< PA[3] pin /
	4704	#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /!< PB[3] pin /
	4705	#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /!< PC[3] pin /
	4706	#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /!< PD[3] pin /
	4707	#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /!< PF[3] pin /
	4708
	4709	/*************** Bit definition for SYSCFG_EXTICR2 register ************/
	4710	#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
	4711	#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /!< 0x0000000F /
	4712	#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /!< EXTI 4 configuration /
	4713	#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
	4714	#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /!< 0x000000F0 /
	4715	#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /!< EXTI 5 configuration /
	4716	#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
	4717	#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /!< 0x00000F00 /
	4718	#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /!< EXTI 6 configuration /
	4719	#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
	4720	#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /!< 0x0000F000 /
	4721	#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /!< EXTI 7 configuration /
	4722
	4723	/**
	4724	* @brief EXTI4 configuration
	4725	*/
	4726	#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /!< PA[4] pin /
	4727	#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /!< PB[4] pin /
	4728	#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /!< PC[4] pin /
	4729	#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /!< PD[4] pin /
	4730	#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /!< PF[4] pin /
	4731
	4732	/**
	4733	* @brief EXTI5 configuration
	4734	*/
	4735	#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /!< PA[5] pin /
	4736	#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /!< PB[5] pin /
	4737	#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /!< PC[5] pin /
	4738	#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /!< PD[5] pin /
	4739	#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /!< PF[5] pin /
	4740
	4741	/**
	4742	* @brief EXTI6 configuration
	4743	*/
	4744	#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /!< PA[6] pin /
	4745	#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /!< PB[6] pin /
	4746	#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /!< PC[6] pin /
	4747	#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /!< PD[6] pin /
	4748	#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /!< PF[6] pin /
	4749
	4750	/**
	4751	* @brief EXTI7 configuration
	4752	*/
	4753	#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /!< PA[7] pin /
	4754	#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /!< PB[7] pin /
	4755	#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /!< PC[7] pin /
	4756	#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /!< PD[7] pin /
	4757	#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /!< PF[7] pin /
	4758
	4759	/*************** Bit definition for SYSCFG_EXTICR3 register ************/
	4760	#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
	4761	#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /!< 0x0000000F /
	4762	#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /!< EXTI 8 configuration /
	4763	#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
	4764	#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /!< 0x000000F0 /
	4765	#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /!< EXTI 9 configuration /
	4766	#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
	4767	#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /!< 0x00000F00 /
	4768	#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /!< EXTI 10 configuration /
	4769	#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
	4770	#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /!< 0x0000F000 /
	4771	#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /!< EXTI 11 configuration /
	4772
	4773	/**
	4774	* @brief EXTI8 configuration
	4775	*/
	4776	#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /!< PA[8] pin /
	4777	#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /!< PB[8] pin /
	4778	#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /!< PC[8] pin /
	4779	#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /!< PD[8] pin /
	4780	#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /!< PF[8] pin /
	4781
	4782
	4783	/**
	4784	* @brief EXTI9 configuration
	4785	*/
	4786	#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /!< PA[9] pin /
	4787	#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /!< PB[9] pin /
	4788	#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /!< PC[9] pin /
	4789	#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /!< PD[9] pin /
	4790	#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /!< PF[9] pin /
	4791
	4792	/**
	4793	* @brief EXTI10 configuration
	4794	*/
	4795	#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /!< PA[10] pin /
	4796	#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /!< PB[10] pin /
	4797	#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /!< PC[10] pin /
	4798	#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /!< PD[10] pin /
	4799	#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /!< PF[10] pin /
	4800
	4801	/**
	4802	* @brief EXTI11 configuration
	4803	*/
	4804	#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /!< PA[11] pin /
	4805	#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /!< PB[11] pin /
	4806	#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /!< PC[11] pin /
	4807	#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /!< PD[11] pin /
	4808	#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /!< PF[11] pin /
	4809
	4810	/*************** Bit definition for SYSCFG_EXTICR4 register ************/
	4811	#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
	4812	#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /!< 0x0000000F /
	4813	#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /!< EXTI 12 configuration /
	4814	#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
	4815	#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /!< 0x000000F0 /
	4816	#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /!< EXTI 13 configuration /
	4817	#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
	4818	#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /!< 0x00000F00 /
	4819	#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /!< EXTI 14 configuration /
	4820	#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
	4821	#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /!< 0x0000F000 /
	4822	#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /!< EXTI 15 configuration /
	4823
	4824	/**
	4825	* @brief EXTI12 configuration
	4826	*/
	4827	#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /!< PA[12] pin /
	4828	#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /!< PB[12] pin /
	4829	#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /!< PC[12] pin /
	4830	#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /!< PD[12] pin /
	4831	#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /!< PF[12] pin /
	4832
	4833	/**
	4834	* @brief EXTI13 configuration
	4835	*/
	4836	#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /!< PA[13] pin /
	4837	#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /!< PB[13] pin /
	4838	#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /!< PC[13] pin /
	4839	#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /!< PD[13] pin /
	4840	#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /!< PF[13] pin /
	4841
	4842	/**
	4843	* @brief EXTI14 configuration
	4844	*/
	4845	#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /!< PA[14] pin /
	4846	#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /!< PB[14] pin /
	4847	#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /!< PC[14] pin /
	4848	#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /!< PD[14] pin /
	4849	#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /!< PF[14] pin /
	4850
	4851	/**
	4852	* @brief EXTI15 configuration
	4853	*/
	4854	#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /!< PA[15] pin /
	4855	#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /!< PB[15] pin /
	4856	#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /!< PC[15] pin /
	4857	#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /!< PD[15] pin /
	4858	#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /!< PF[15] pin /
	4859
	4860	/*************** Bit definition for SYSCFG_CFGR2 register **************/
	4861	#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
	4862	#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /!< 0x00000001 /
	4863	#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 /
	4864	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
	4865	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /!< 0x00000002 /
	4866	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 /
	4867	#define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
	4868	#define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /!< 0x00000004 /
	4869	#define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface /
	4870	#define SYSCFG_CFGR2_SRAM_PEF_Pos (8U)
	4871	#define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1U << SYSCFG_CFGR2_SRAM_PEF_Pos) /!< 0x00000100 /
	4872	#define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /!< SRAM Parity error flag /
	4873	#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /!< SRAM Parity error flag (define maintained for legacy purpose) /
	4874
	4875	/*****************************************************************************/
	4876	/* */
	4877	/* Timers (TIM) */
	4878	/* */
	4879	/*****************************************************************************/
	4880	/***************** Bit definition for TIM_CR1 register *****************/
	4881	#define TIM_CR1_CEN_Pos (0U)
	4882	#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /!< 0x00000001 /
	4883	#define TIM_CR1_CEN TIM_CR1_CEN_Msk /!<Counter enable /
	4884	#define TIM_CR1_UDIS_Pos (1U)
	4885	#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /!< 0x00000002 /
	4886	#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /!<Update disable /
	4887	#define TIM_CR1_URS_Pos (2U)
	4888	#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /!< 0x00000004 /
	4889	#define TIM_CR1_URS TIM_CR1_URS_Msk /!<Update request source /
	4890	#define TIM_CR1_OPM_Pos (3U)
	4891	#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /!< 0x00000008 /
	4892	#define TIM_CR1_OPM TIM_CR1_OPM_Msk /!<One pulse mode /
	4893	#define TIM_CR1_DIR_Pos (4U)
	4894	#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /!< 0x00000010 /
	4895	#define TIM_CR1_DIR TIM_CR1_DIR_Msk /!<Direction /
	4896
	4897	#define TIM_CR1_CMS_Pos (5U)
	4898	#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /!< 0x00000060 /
	4899	#define TIM_CR1_CMS TIM_CR1_CMS_Msk /!<CMS[1:0] bits (Center-aligned mode selection) /
	4900	#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /!< 0x00000020 /
	4901	#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /!< 0x00000040 /
	4902
	4903	#define TIM_CR1_ARPE_Pos (7U)
	4904	#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /!< 0x00000080 /
	4905	#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /!<Auto-reload preload enable /
	4906
	4907	#define TIM_CR1_CKD_Pos (8U)
	4908	#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /!< 0x00000300 /
	4909	#define TIM_CR1_CKD TIM_CR1_CKD_Msk /!<CKD[1:0] bits (clock division) /
	4910	#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /!< 0x00000100 /
	4911	#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /!< 0x00000200 /
	4912
	4913	/***************** Bit definition for TIM_CR2 register *****************/
	4914	#define TIM_CR2_CCPC_Pos (0U)
	4915	#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /!< 0x00000001 /
	4916	#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /!<Capture/Compare Preloaded Control /
	4917	#define TIM_CR2_CCUS_Pos (2U)
	4918	#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /!< 0x00000004 /
	4919	#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /!<Capture/Compare Control Update Selection /
	4920	#define TIM_CR2_CCDS_Pos (3U)
	4921	#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /!< 0x00000008 /
	4922	#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /!<Capture/Compare DMA Selection /
	4923
	4924	#define TIM_CR2_MMS_Pos (4U)
	4925	#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /!< 0x00000070 /
	4926	#define TIM_CR2_MMS TIM_CR2_MMS_Msk /!<MMS[2:0] bits (Master Mode Selection) /
	4927	#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /!< 0x00000010 /
	4928	#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /!< 0x00000020 /
	4929	#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /!< 0x00000040 /
	4930
	4931	#define TIM_CR2_TI1S_Pos (7U)
	4932	#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /!< 0x00000080 /
	4933	#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /!<TI1 Selection /
	4934	#define TIM_CR2_OIS1_Pos (8U)
	4935	#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /!< 0x00000100 /
	4936	#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /!<Output Idle state 1 (OC1 output) /
	4937	#define TIM_CR2_OIS1N_Pos (9U)
	4938	#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /!< 0x00000200 /
	4939	#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /!<Output Idle state 1 (OC1N output) /
	4940	#define TIM_CR2_OIS2_Pos (10U)
	4941	#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /!< 0x00000400 /
	4942	#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /!<Output Idle state 2 (OC2 output) /
	4943	#define TIM_CR2_OIS2N_Pos (11U)
	4944	#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /!< 0x00000800 /
	4945	#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /!<Output Idle state 2 (OC2N output) /
	4946	#define TIM_CR2_OIS3_Pos (12U)
	4947	#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /!< 0x00001000 /
	4948	#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /!<Output Idle state 3 (OC3 output) /
	4949	#define TIM_CR2_OIS3N_Pos (13U)
	4950	#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /!< 0x00002000 /
	4951	#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /!<Output Idle state 3 (OC3N output) /
	4952	#define TIM_CR2_OIS4_Pos (14U)
	4953	#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /!< 0x00004000 /
	4954	#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /!<Output Idle state 4 (OC4 output) /
	4955
	4956	/***************** Bit definition for TIM_SMCR register ****************/
	4957	#define TIM_SMCR_SMS_Pos (0U)
	4958	#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /!< 0x00000007 /
	4959	#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /!<SMS[2:0] bits (Slave mode selection) /
	4960	#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /!< 0x00000001 /
	4961	#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /!< 0x00000002 /
	4962	#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /!< 0x00000004 /
	4963
	4964	#define TIM_SMCR_OCCS_Pos (3U)
	4965	#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /!< 0x00000008 /
	4966	#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /!< OCREF clear selection /
	4967
	4968	#define TIM_SMCR_TS_Pos (4U)
	4969	#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /!< 0x00000070 /
	4970	#define TIM_SMCR_TS TIM_SMCR_TS_Msk /!<TS[2:0] bits (Trigger selection) /
	4971	#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /!< 0x00000010 /
	4972	#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /!< 0x00000020 /
	4973	#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /!< 0x00000040 /
	4974
	4975	#define TIM_SMCR_MSM_Pos (7U)
	4976	#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /!< 0x00000080 /
	4977	#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /!<Master/slave mode /
	4978
	4979	#define TIM_SMCR_ETF_Pos (8U)
	4980	#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /!< 0x00000F00 /
	4981	#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /!<ETF[3:0] bits (External trigger filter) /
	4982	#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /!< 0x00000100 /
	4983	#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /!< 0x00000200 /
	4984	#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /!< 0x00000400 /
	4985	#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /!< 0x00000800 /
	4986
	4987	#define TIM_SMCR_ETPS_Pos (12U)
	4988	#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /!< 0x00003000 /
	4989	#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /!<ETPS[1:0] bits (External trigger prescaler) /
	4990	#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /!< 0x00001000 /
	4991	#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /!< 0x00002000 /
	4992
	4993	#define TIM_SMCR_ECE_Pos (14U)
	4994	#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /!< 0x00004000 /
	4995	#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /!<External clock enable /
	4996	#define TIM_SMCR_ETP_Pos (15U)
	4997	#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /!< 0x00008000 /
	4998	#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /!<External trigger polarity /
	4999
	5000	/***************** Bit definition for TIM_DIER register ****************/
	5001	#define TIM_DIER_UIE_Pos (0U)
	5002	#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /!< 0x00000001 /
	5003	#define TIM_DIER_UIE TIM_DIER_UIE_Msk /!<Update interrupt enable /
	5004	#define TIM_DIER_CC1IE_Pos (1U)
	5005	#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /!< 0x00000002 /
	5006	#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /!<Capture/Compare 1 interrupt enable /
	5007	#define TIM_DIER_CC2IE_Pos (2U)
	5008	#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /!< 0x00000004 /
	5009	#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /!<Capture/Compare 2 interrupt enable /
	5010	#define TIM_DIER_CC3IE_Pos (3U)
	5011	#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /!< 0x00000008 /
	5012	#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /!<Capture/Compare 3 interrupt enable /
	5013	#define TIM_DIER_CC4IE_Pos (4U)
	5014	#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /!< 0x00000010 /
	5015	#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /!<Capture/Compare 4 interrupt enable /
	5016	#define TIM_DIER_COMIE_Pos (5U)
	5017	#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /!< 0x00000020 /
	5018	#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /!<COM interrupt enable /
	5019	#define TIM_DIER_TIE_Pos (6U)
	5020	#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /!< 0x00000040 /
	5021	#define TIM_DIER_TIE TIM_DIER_TIE_Msk /!<Trigger interrupt enable /
	5022	#define TIM_DIER_BIE_Pos (7U)
	5023	#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /!< 0x00000080 /
	5024	#define TIM_DIER_BIE TIM_DIER_BIE_Msk /!<Break interrupt enable /
	5025	#define TIM_DIER_UDE_Pos (8U)
	5026	#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /!< 0x00000100 /
	5027	#define TIM_DIER_UDE TIM_DIER_UDE_Msk /!<Update DMA request enable /
	5028	#define TIM_DIER_CC1DE_Pos (9U)
	5029	#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /!< 0x00000200 /
	5030	#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /!<Capture/Compare 1 DMA request enable /
	5031	#define TIM_DIER_CC2DE_Pos (10U)
	5032	#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /!< 0x00000400 /
	5033	#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /!<Capture/Compare 2 DMA request enable /
	5034	#define TIM_DIER_CC3DE_Pos (11U)
	5035	#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /!< 0x00000800 /
	5036	#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /!<Capture/Compare 3 DMA request enable /
	5037	#define TIM_DIER_CC4DE_Pos (12U)
	5038	#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /!< 0x00001000 /
	5039	#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /!<Capture/Compare 4 DMA request enable /
	5040	#define TIM_DIER_COMDE_Pos (13U)
	5041	#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /!< 0x00002000 /
	5042	#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /!<COM DMA request enable /
	5043	#define TIM_DIER_TDE_Pos (14U)
	5044	#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /!< 0x00004000 /
	5045	#define TIM_DIER_TDE TIM_DIER_TDE_Msk /!<Trigger DMA request enable /
	5046
	5047	/****************** Bit definition for TIM_SR register *****************/
	5048	#define TIM_SR_UIF_Pos (0U)
	5049	#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /!< 0x00000001 /
	5050	#define TIM_SR_UIF TIM_SR_UIF_Msk /!<Update interrupt Flag /
	5051	#define TIM_SR_CC1IF_Pos (1U)
	5052	#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /!< 0x00000002 /
	5053	#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /!<Capture/Compare 1 interrupt Flag /
	5054	#define TIM_SR_CC2IF_Pos (2U)
	5055	#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /!< 0x00000004 /
	5056	#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /!<Capture/Compare 2 interrupt Flag /
	5057	#define TIM_SR_CC3IF_Pos (3U)
	5058	#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /!< 0x00000008 /
	5059	#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /!<Capture/Compare 3 interrupt Flag /
	5060	#define TIM_SR_CC4IF_Pos (4U)
	5061	#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /!< 0x00000010 /
	5062	#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /!<Capture/Compare 4 interrupt Flag /
	5063	#define TIM_SR_COMIF_Pos (5U)
	5064	#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /!< 0x00000020 /
	5065	#define TIM_SR_COMIF TIM_SR_COMIF_Msk /!<COM interrupt Flag /
	5066	#define TIM_SR_TIF_Pos (6U)
	5067	#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /!< 0x00000040 /
	5068	#define TIM_SR_TIF TIM_SR_TIF_Msk /!<Trigger interrupt Flag /
	5069	#define TIM_SR_BIF_Pos (7U)
	5070	#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /!< 0x00000080 /
	5071	#define TIM_SR_BIF TIM_SR_BIF_Msk /!<Break interrupt Flag /
	5072	#define TIM_SR_CC1OF_Pos (9U)
	5073	#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /!< 0x00000200 /
	5074	#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /!<Capture/Compare 1 Overcapture Flag /
	5075	#define TIM_SR_CC2OF_Pos (10U)
	5076	#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /!< 0x00000400 /
	5077	#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /!<Capture/Compare 2 Overcapture Flag /
	5078	#define TIM_SR_CC3OF_Pos (11U)
	5079	#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /!< 0x00000800 /
	5080	#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /!<Capture/Compare 3 Overcapture Flag /
	5081	#define TIM_SR_CC4OF_Pos (12U)
	5082	#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /!< 0x00001000 /
	5083	#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /!<Capture/Compare 4 Overcapture Flag /
	5084
	5085	/***************** Bit definition for TIM_EGR register *****************/
	5086	#define TIM_EGR_UG_Pos (0U)
	5087	#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /!< 0x00000001 /
	5088	#define TIM_EGR_UG TIM_EGR_UG_Msk /!<Update Generation /
	5089	#define TIM_EGR_CC1G_Pos (1U)
	5090	#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /!< 0x00000002 /
	5091	#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /!<Capture/Compare 1 Generation /
	5092	#define TIM_EGR_CC2G_Pos (2U)
	5093	#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /!< 0x00000004 /
	5094	#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /!<Capture/Compare 2 Generation /
	5095	#define TIM_EGR_CC3G_Pos (3U)
	5096	#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /!< 0x00000008 /
	5097	#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /!<Capture/Compare 3 Generation /
	5098	#define TIM_EGR_CC4G_Pos (4U)
	5099	#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /!< 0x00000010 /
	5100	#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /!<Capture/Compare 4 Generation /
	5101	#define TIM_EGR_COMG_Pos (5U)
	5102	#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /!< 0x00000020 /
	5103	#define TIM_EGR_COMG TIM_EGR_COMG_Msk /!<Capture/Compare Control Update Generation /
	5104	#define TIM_EGR_TG_Pos (6U)
	5105	#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /!< 0x00000040 /
	5106	#define TIM_EGR_TG TIM_EGR_TG_Msk /!<Trigger Generation /
	5107	#define TIM_EGR_BG_Pos (7U)
	5108	#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /!< 0x00000080 /
	5109	#define TIM_EGR_BG TIM_EGR_BG_Msk /!<Break Generation /
	5110
	5111	/**************** Bit definition for TIM_CCMR1 register ****************/
	5112	#define TIM_CCMR1_CC1S_Pos (0U)
	5113	#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /!< 0x00000003 /
	5114	#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
	5115	#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /!< 0x00000001 /
	5116	#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /!< 0x00000002 /
	5117
	5118	#define TIM_CCMR1_OC1FE_Pos (2U)
	5119	#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /!< 0x00000004 /
	5120	#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /!<Output Compare 1 Fast enable /
	5121	#define TIM_CCMR1_OC1PE_Pos (3U)
	5122	#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /!< 0x00000008 /
	5123	#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /!<Output Compare 1 Preload enable /
	5124
	5125	#define TIM_CCMR1_OC1M_Pos (4U)
	5126	#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /!< 0x00000070 /
	5127	#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /!<OC1M[2:0] bits (Output Compare 1 Mode) /
	5128	#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /!< 0x00000010 /
	5129	#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /!< 0x00000020 /
	5130	#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /!< 0x00000040 /
	5131
	5132	#define TIM_CCMR1_OC1CE_Pos (7U)
	5133	#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /!< 0x00000080 /
	5134	#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /!<Output Compare 1Clear Enable /
	5135
	5136	#define TIM_CCMR1_CC2S_Pos (8U)
	5137	#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /!< 0x00000300 /
	5138	#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
	5139	#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /!< 0x00000100 /
	5140	#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /!< 0x00000200 /
	5141
	5142	#define TIM_CCMR1_OC2FE_Pos (10U)
	5143	#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /!< 0x00000400 /
	5144	#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /!<Output Compare 2 Fast enable /
	5145	#define TIM_CCMR1_OC2PE_Pos (11U)
	5146	#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /!< 0x00000800 /
	5147	#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /!<Output Compare 2 Preload enable /
	5148
	5149	#define TIM_CCMR1_OC2M_Pos (12U)
	5150	#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /!< 0x00007000 /
	5151	#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /!<OC2M[2:0] bits (Output Compare 2 Mode) /
	5152	#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /!< 0x00001000 /
	5153	#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /!< 0x00002000 /
	5154	#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /!< 0x00004000 /
	5155
	5156	#define TIM_CCMR1_OC2CE_Pos (15U)
	5157	#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /!< 0x00008000 /
	5158	#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /!<Output Compare 2 Clear Enable /
	5159
	5160	/---------------------------------------------------------------------------/
	5161
	5162	#define TIM_CCMR1_IC1PSC_Pos (2U)
	5163	#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /!< 0x0000000C /
	5164	#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
	5165	#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000004 /
	5166	#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000008 /
	5167
	5168	#define TIM_CCMR1_IC1F_Pos (4U)
	5169	#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /!< 0x000000F0 /
	5170	#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /!<IC1F[3:0] bits (Input Capture 1 Filter) /
	5171	#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /!< 0x00000010 /
	5172	#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /!< 0x00000020 /
	5173	#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /!< 0x00000040 /
	5174	#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /!< 0x00000080 /
	5175
	5176	#define TIM_CCMR1_IC2PSC_Pos (10U)
	5177	#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000C00 /
	5178	#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
	5179	#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000400 /
	5180	#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000800 /
	5181
	5182	#define TIM_CCMR1_IC2F_Pos (12U)
	5183	#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /!< 0x0000F000 /
	5184	#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /!<IC2F[3:0] bits (Input Capture 2 Filter) /
	5185	#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /!< 0x00001000 /
	5186	#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /!< 0x00002000 /
	5187	#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /!< 0x00004000 /
	5188	#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /!< 0x00008000 /
	5189
	5190	/**************** Bit definition for TIM_CCMR2 register ****************/
	5191	#define TIM_CCMR2_CC3S_Pos (0U)
	5192	#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /!< 0x00000003 /
	5193	#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
	5194	#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /!< 0x00000001 /
	5195	#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /!< 0x00000002 /
	5196
	5197	#define TIM_CCMR2_OC3FE_Pos (2U)
	5198	#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /!< 0x00000004 /
	5199	#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /!<Output Compare 3 Fast enable /
	5200	#define TIM_CCMR2_OC3PE_Pos (3U)
	5201	#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /!< 0x00000008 /
	5202	#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /!<Output Compare 3 Preload enable /
	5203
	5204	#define TIM_CCMR2_OC3M_Pos (4U)
	5205	#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /!< 0x00000070 /
	5206	#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /!<OC3M[2:0] bits (Output Compare 3 Mode) /
	5207	#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /!< 0x00000010 /
	5208	#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /!< 0x00000020 /
	5209	#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /!< 0x00000040 /
	5210
	5211	#define TIM_CCMR2_OC3CE_Pos (7U)
	5212	#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /!< 0x00000080 /
	5213	#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /!<Output Compare 3 Clear Enable /
	5214
	5215	#define TIM_CCMR2_CC4S_Pos (8U)
	5216	#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /!< 0x00000300 /
	5217	#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
	5218	#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /!< 0x00000100 /
	5219	#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /!< 0x00000200 /
	5220
	5221	#define TIM_CCMR2_OC4FE_Pos (10U)
	5222	#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /!< 0x00000400 /
	5223	#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /!<Output Compare 4 Fast enable /
	5224	#define TIM_CCMR2_OC4PE_Pos (11U)
	5225	#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /!< 0x00000800 /
	5226	#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /!<Output Compare 4 Preload enable /
	5227
	5228	#define TIM_CCMR2_OC4M_Pos (12U)
	5229	#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /!< 0x00007000 /
	5230	#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /!<OC4M[2:0] bits (Output Compare 4 Mode) /
	5231	#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /!< 0x00001000 /
	5232	#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /!< 0x00002000 /
	5233	#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /!< 0x00004000 /
	5234
	5235	#define TIM_CCMR2_OC4CE_Pos (15U)
	5236	#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /!< 0x00008000 /
	5237	#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /!<Output Compare 4 Clear Enable /
	5238
	5239	/---------------------------------------------------------------------------/
	5240
	5241	#define TIM_CCMR2_IC3PSC_Pos (2U)
	5242	#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /!< 0x0000000C /
	5243	#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
	5244	#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000004 /
	5245	#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000008 /
	5246
	5247	#define TIM_CCMR2_IC3F_Pos (4U)
	5248	#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /!< 0x000000F0 /
	5249	#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /!<IC3F[3:0] bits (Input Capture 3 Filter) /
	5250	#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /!< 0x00000010 /
	5251	#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /!< 0x00000020 /
	5252	#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /!< 0x00000040 /
	5253	#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /!< 0x00000080 /
	5254
	5255	#define TIM_CCMR2_IC4PSC_Pos (10U)
	5256	#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000C00 /
	5257	#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
	5258	#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000400 /
	5259	#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000800 /
	5260
	5261	#define TIM_CCMR2_IC4F_Pos (12U)
	5262	#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /!< 0x0000F000 /
	5263	#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /!<IC4F[3:0] bits (Input Capture 4 Filter) /
	5264	#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /!< 0x00001000 /
	5265	#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /!< 0x00002000 /
	5266	#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /!< 0x00004000 /
	5267	#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /!< 0x00008000 /
	5268
	5269	/***************** Bit definition for TIM_CCER register ****************/
	5270	#define TIM_CCER_CC1E_Pos (0U)
	5271	#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /!< 0x00000001 /
	5272	#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /!<Capture/Compare 1 output enable /
	5273	#define TIM_CCER_CC1P_Pos (1U)
	5274	#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /!< 0x00000002 /
	5275	#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /!<Capture/Compare 1 output Polarity /
	5276	#define TIM_CCER_CC1NE_Pos (2U)
	5277	#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /!< 0x00000004 /
	5278	#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /!<Capture/Compare 1 Complementary output enable /
	5279	#define TIM_CCER_CC1NP_Pos (3U)
	5280	#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /!< 0x00000008 /
	5281	#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /!<Capture/Compare 1 Complementary output Polarity /
	5282	#define TIM_CCER_CC2E_Pos (4U)
	5283	#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /!< 0x00000010 /
	5284	#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /!<Capture/Compare 2 output enable /
	5285	#define TIM_CCER_CC2P_Pos (5U)
	5286	#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /!< 0x00000020 /
	5287	#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /!<Capture/Compare 2 output Polarity /
	5288	#define TIM_CCER_CC2NE_Pos (6U)
	5289	#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /!< 0x00000040 /
	5290	#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /!<Capture/Compare 2 Complementary output enable /
	5291	#define TIM_CCER_CC2NP_Pos (7U)
	5292	#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /!< 0x00000080 /
	5293	#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /!<Capture/Compare 2 Complementary output Polarity /
	5294	#define TIM_CCER_CC3E_Pos (8U)
	5295	#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /!< 0x00000100 /
	5296	#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /!<Capture/Compare 3 output enable /
	5297	#define TIM_CCER_CC3P_Pos (9U)
	5298	#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /!< 0x00000200 /
	5299	#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /!<Capture/Compare 3 output Polarity /
	5300	#define TIM_CCER_CC3NE_Pos (10U)
	5301	#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /!< 0x00000400 /
	5302	#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /!<Capture/Compare 3 Complementary output enable /
	5303	#define TIM_CCER_CC3NP_Pos (11U)
	5304	#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /!< 0x00000800 /
	5305	#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /!<Capture/Compare 3 Complementary output Polarity /
	5306	#define TIM_CCER_CC4E_Pos (12U)
	5307	#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /!< 0x00001000 /
	5308	#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /!<Capture/Compare 4 output enable /
	5309	#define TIM_CCER_CC4P_Pos (13U)
	5310	#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /!< 0x00002000 /
	5311	#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /!<Capture/Compare 4 output Polarity /
	5312	#define TIM_CCER_CC4NP_Pos (15U)
	5313	#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /!< 0x00008000 /
	5314	#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /!<Capture/Compare 4 Complementary output Polarity /
	5315
	5316	/***************** Bit definition for TIM_CNT register *****************/
	5317	#define TIM_CNT_CNT_Pos (0U)
	5318	#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /!< 0xFFFFFFFF /
	5319	#define TIM_CNT_CNT TIM_CNT_CNT_Msk /!<Counter Value /
	5320
	5321	/***************** Bit definition for TIM_PSC register *****************/
	5322	#define TIM_PSC_PSC_Pos (0U)
	5323	#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /!< 0x0000FFFF /
	5324	#define TIM_PSC_PSC TIM_PSC_PSC_Msk /!<Prescaler Value /
	5325
	5326	/***************** Bit definition for TIM_ARR register *****************/
	5327	#define TIM_ARR_ARR_Pos (0U)
	5328	#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /!< 0xFFFFFFFF /
	5329	#define TIM_ARR_ARR TIM_ARR_ARR_Msk /!<actual auto-reload Value /
	5330
	5331	/***************** Bit definition for TIM_RCR register *****************/
	5332	#define TIM_RCR_REP_Pos (0U)
	5333	#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /!< 0x000000FF /
	5334	#define TIM_RCR_REP TIM_RCR_REP_Msk /!<Repetition Counter Value /
	5335
	5336	/***************** Bit definition for TIM_CCR1 register ****************/
	5337	#define TIM_CCR1_CCR1_Pos (0U)
	5338	#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /!< 0x0000FFFF /
	5339	#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /!<Capture/Compare 1 Value /
	5340
	5341	/***************** Bit definition for TIM_CCR2 register ****************/
	5342	#define TIM_CCR2_CCR2_Pos (0U)
	5343	#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /!< 0x0000FFFF /
	5344	#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /!<Capture/Compare 2 Value /
	5345
	5346	/***************** Bit definition for TIM_CCR3 register ****************/
	5347	#define TIM_CCR3_CCR3_Pos (0U)
	5348	#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /!< 0x0000FFFF /
	5349	#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /!<Capture/Compare 3 Value /
	5350
	5351	/***************** Bit definition for TIM_CCR4 register ****************/
	5352	#define TIM_CCR4_CCR4_Pos (0U)
	5353	#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /!< 0x0000FFFF /
	5354	#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /!<Capture/Compare 4 Value /
	5355
	5356	/***************** Bit definition for TIM_BDTR register ****************/
	5357	#define TIM_BDTR_DTG_Pos (0U)
	5358	#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /!< 0x000000FF /
	5359	#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /!<DTG[0:7] bits (Dead-Time Generator set-up) /
	5360	#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /!< 0x00000001 /
	5361	#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /!< 0x00000002 /
	5362	#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /!< 0x00000004 /
	5363	#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /!< 0x00000008 /
	5364	#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /!< 0x00000010 /
	5365	#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /!< 0x00000020 /
	5366	#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /!< 0x00000040 /
	5367	#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /!< 0x00000080 /
	5368
	5369	#define TIM_BDTR_LOCK_Pos (8U)
	5370	#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /!< 0x00000300 /
	5371	#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /!<LOCK[1:0] bits (Lock Configuration) /
	5372	#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /!< 0x00000100 /
	5373	#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /!< 0x00000200 /
	5374
	5375	#define TIM_BDTR_OSSI_Pos (10U)
	5376	#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /!< 0x00000400 /
	5377	#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /!<Off-State Selection for Idle mode /
	5378	#define TIM_BDTR_OSSR_Pos (11U)
	5379	#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /!< 0x00000800 /
	5380	#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /!<Off-State Selection for Run mode /
	5381	#define TIM_BDTR_BKE_Pos (12U)
	5382	#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /!< 0x00001000 /
	5383	#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /!<Break enable /
	5384	#define TIM_BDTR_BKP_Pos (13U)
	5385	#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /!< 0x00002000 /
	5386	#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /!<Break Polarity /
	5387	#define TIM_BDTR_AOE_Pos (14U)
	5388	#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /!< 0x00004000 /
	5389	#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /!<Automatic Output enable /
	5390	#define TIM_BDTR_MOE_Pos (15U)
	5391	#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /!< 0x00008000 /
	5392	#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /!<Main Output enable /
	5393
	5394	/***************** Bit definition for TIM_DCR register *****************/
	5395	#define TIM_DCR_DBA_Pos (0U)
	5396	#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /!< 0x0000001F /
	5397	#define TIM_DCR_DBA TIM_DCR_DBA_Msk /!<DBA[4:0] bits (DMA Base Address) /
	5398	#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /!< 0x00000001 /
	5399	#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /!< 0x00000002 /
	5400	#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /!< 0x00000004 /
	5401	#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /!< 0x00000008 /
	5402	#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /!< 0x00000010 /
	5403
	5404	#define TIM_DCR_DBL_Pos (8U)
	5405	#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /!< 0x00001F00 /
	5406	#define TIM_DCR_DBL TIM_DCR_DBL_Msk /!<DBL[4:0] bits (DMA Burst Length) /
	5407	#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /!< 0x00000100 /
	5408	#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /!< 0x00000200 /
	5409	#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /!< 0x00000400 /
	5410	#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /!< 0x00000800 /
	5411	#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /!< 0x00001000 /
	5412
	5413	/***************** Bit definition for TIM_DMAR register ****************/
	5414	#define TIM_DMAR_DMAB_Pos (0U)
	5415	#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /!< 0x0000FFFF /
	5416	#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /!<DMA register for burst accesses /
	5417
	5418	/***************** Bit definition for TIM14_OR register ******************/
	5419	#define TIM14_OR_TI1_RMP_Pos (0U)
	5420	#define TIM14_OR_TI1_RMP_Msk (0x3U << TIM14_OR_TI1_RMP_Pos) /!< 0x00000003 /
	5421	#define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) /
	5422	#define TIM14_OR_TI1_RMP_0 (0x1U << TIM14_OR_TI1_RMP_Pos) /!< 0x00000001 /
	5423	#define TIM14_OR_TI1_RMP_1 (0x2U << TIM14_OR_TI1_RMP_Pos) /!< 0x00000002 /
	5424
	5425	/******************************************************************************/
	5426	/* */
	5427	/* Touch Sensing Controller (TSC) */
	5428	/* */
	5429	/******************************************************************************/
	5430	/***************** Bit definition for TSC_CR register *******************/
	5431	#define TSC_CR_TSCE_Pos (0U)
	5432	#define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /!< 0x00000001 /
	5433	#define TSC_CR_TSCE TSC_CR_TSCE_Msk /!<Touch sensing controller enable /
	5434	#define TSC_CR_START_Pos (1U)
	5435	#define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /!< 0x00000002 /
	5436	#define TSC_CR_START TSC_CR_START_Msk /!<Start acquisition /
	5437	#define TSC_CR_AM_Pos (2U)
	5438	#define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /!< 0x00000004 /
	5439	#define TSC_CR_AM TSC_CR_AM_Msk /!<Acquisition mode /
	5440	#define TSC_CR_SYNCPOL_Pos (3U)
	5441	#define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /!< 0x00000008 /
	5442	#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /!<Synchronization pin polarity /
	5443	#define TSC_CR_IODEF_Pos (4U)
	5444	#define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /!< 0x00000010 /
	5445	#define TSC_CR_IODEF TSC_CR_IODEF_Msk /!<IO default mode /
	5446
	5447	#define TSC_CR_MCV_Pos (5U)
	5448	#define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /!< 0x000000E0 /
	5449	#define TSC_CR_MCV TSC_CR_MCV_Msk /!<MCV[2:0] bits (Max Count Value) /
	5450	#define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /!< 0x00000020 /
	5451	#define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /!< 0x00000040 /
	5452	#define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /!< 0x00000080 /
	5453
	5454	#define TSC_CR_PGPSC_Pos (12U)
	5455	#define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /!< 0x00007000 /
	5456	#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /!<PGPSC[2:0] bits (Pulse Generator Prescaler) /
	5457	#define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /!< 0x00001000 /
	5458	#define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /!< 0x00002000 /
	5459	#define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /!< 0x00004000 /
	5460
	5461	#define TSC_CR_SSPSC_Pos (15U)
	5462	#define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /!< 0x00008000 /
	5463	#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /!<Spread Spectrum Prescaler /
	5464	#define TSC_CR_SSE_Pos (16U)
	5465	#define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /!< 0x00010000 /
	5466	#define TSC_CR_SSE TSC_CR_SSE_Msk /!<Spread Spectrum Enable /
	5467
	5468	#define TSC_CR_SSD_Pos (17U)
	5469	#define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /!< 0x00FE0000 /
	5470	#define TSC_CR_SSD TSC_CR_SSD_Msk /!<SSD[6:0] bits (Spread Spectrum Deviation) /
	5471	#define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /!< 0x00020000 /
	5472	#define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /!< 0x00040000 /
	5473	#define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /!< 0x00080000 /
	5474	#define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /!< 0x00100000 /
	5475	#define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /!< 0x00200000 /
	5476	#define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /!< 0x00400000 /
	5477	#define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /!< 0x00800000 /
	5478
	5479	#define TSC_CR_CTPL_Pos (24U)
	5480	#define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /!< 0x0F000000 /
	5481	#define TSC_CR_CTPL TSC_CR_CTPL_Msk /!<CTPL[3:0] bits (Charge Transfer pulse low) /
	5482	#define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /!< 0x01000000 /
	5483	#define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /!< 0x02000000 /
	5484	#define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /!< 0x04000000 /
	5485	#define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /!< 0x08000000 /
	5486
	5487	#define TSC_CR_CTPH_Pos (28U)
	5488	#define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /!< 0xF0000000 /
	5489	#define TSC_CR_CTPH TSC_CR_CTPH_Msk /!<CTPH[3:0] bits (Charge Transfer pulse high) /
	5490	#define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /!< 0x10000000 /
	5491	#define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /!< 0x20000000 /
	5492	#define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /!< 0x40000000 /
	5493	#define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /!< 0x80000000 /
	5494
	5495	/***************** Bit definition for TSC_IER register ******************/
	5496	#define TSC_IER_EOAIE_Pos (0U)
	5497	#define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /!< 0x00000001 /
	5498	#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /!<End of acquisition interrupt enable /
	5499	#define TSC_IER_MCEIE_Pos (1U)
	5500	#define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /!< 0x00000002 /
	5501	#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /!<Max count error interrupt enable /
	5502
	5503	/***************** Bit definition for TSC_ICR register ******************/
	5504	#define TSC_ICR_EOAIC_Pos (0U)
	5505	#define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /!< 0x00000001 /
	5506	#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /!<End of acquisition interrupt clear /
	5507	#define TSC_ICR_MCEIC_Pos (1U)
	5508	#define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /!< 0x00000002 /
	5509	#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /!<Max count error interrupt clear /
	5510
	5511	/***************** Bit definition for TSC_ISR register ******************/
	5512	#define TSC_ISR_EOAF_Pos (0U)
	5513	#define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /!< 0x00000001 /
	5514	#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /!<End of acquisition flag /
	5515	#define TSC_ISR_MCEF_Pos (1U)
	5516	#define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /!< 0x00000002 /
	5517	#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /!<Max count error flag /
	5518
	5519	/***************** Bit definition for TSC_IOHCR register ****************/
	5520	#define TSC_IOHCR_G1_IO1_Pos (0U)
	5521	#define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /!< 0x00000001 /
	5522	#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /!<GROUP1_IO1 schmitt trigger hysteresis mode /
	5523	#define TSC_IOHCR_G1_IO2_Pos (1U)
	5524	#define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /!< 0x00000002 /
	5525	#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /!<GROUP1_IO2 schmitt trigger hysteresis mode /
	5526	#define TSC_IOHCR_G1_IO3_Pos (2U)
	5527	#define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /!< 0x00000004 /
	5528	#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /!<GROUP1_IO3 schmitt trigger hysteresis mode /
	5529	#define TSC_IOHCR_G1_IO4_Pos (3U)
	5530	#define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /!< 0x00000008 /
	5531	#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /!<GROUP1_IO4 schmitt trigger hysteresis mode /
	5532	#define TSC_IOHCR_G2_IO1_Pos (4U)
	5533	#define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /!< 0x00000010 /
	5534	#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /!<GROUP2_IO1 schmitt trigger hysteresis mode /
	5535	#define TSC_IOHCR_G2_IO2_Pos (5U)
	5536	#define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /!< 0x00000020 /
	5537	#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /!<GROUP2_IO2 schmitt trigger hysteresis mode /
	5538	#define TSC_IOHCR_G2_IO3_Pos (6U)
	5539	#define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /!< 0x00000040 /
	5540	#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /!<GROUP2_IO3 schmitt trigger hysteresis mode /
	5541	#define TSC_IOHCR_G2_IO4_Pos (7U)
	5542	#define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /!< 0x00000080 /
	5543	#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /!<GROUP2_IO4 schmitt trigger hysteresis mode /
	5544	#define TSC_IOHCR_G3_IO1_Pos (8U)
	5545	#define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /!< 0x00000100 /
	5546	#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /!<GROUP3_IO1 schmitt trigger hysteresis mode /
	5547	#define TSC_IOHCR_G3_IO2_Pos (9U)
	5548	#define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /!< 0x00000200 /
	5549	#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /!<GROUP3_IO2 schmitt trigger hysteresis mode /
	5550	#define TSC_IOHCR_G3_IO3_Pos (10U)
	5551	#define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /!< 0x00000400 /
	5552	#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /!<GROUP3_IO3 schmitt trigger hysteresis mode /
	5553	#define TSC_IOHCR_G3_IO4_Pos (11U)
	5554	#define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /!< 0x00000800 /
	5555	#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /!<GROUP3_IO4 schmitt trigger hysteresis mode /
	5556	#define TSC_IOHCR_G4_IO1_Pos (12U)
	5557	#define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /!< 0x00001000 /
	5558	#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /!<GROUP4_IO1 schmitt trigger hysteresis mode /
	5559	#define TSC_IOHCR_G4_IO2_Pos (13U)
	5560	#define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /!< 0x00002000 /
	5561	#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /!<GROUP4_IO2 schmitt trigger hysteresis mode /
	5562	#define TSC_IOHCR_G4_IO3_Pos (14U)
	5563	#define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /!< 0x00004000 /
	5564	#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /!<GROUP4_IO3 schmitt trigger hysteresis mode /
	5565	#define TSC_IOHCR_G4_IO4_Pos (15U)
	5566	#define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /!< 0x00008000 /
	5567	#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /!<GROUP4_IO4 schmitt trigger hysteresis mode /
	5568	#define TSC_IOHCR_G5_IO1_Pos (16U)
	5569	#define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /!< 0x00010000 /
	5570	#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /!<GROUP5_IO1 schmitt trigger hysteresis mode /
	5571	#define TSC_IOHCR_G5_IO2_Pos (17U)
	5572	#define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /!< 0x00020000 /
	5573	#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /!<GROUP5_IO2 schmitt trigger hysteresis mode /
	5574	#define TSC_IOHCR_G5_IO3_Pos (18U)
	5575	#define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /!< 0x00040000 /
	5576	#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /!<GROUP5_IO3 schmitt trigger hysteresis mode /
	5577	#define TSC_IOHCR_G5_IO4_Pos (19U)
	5578	#define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /!< 0x00080000 /
	5579	#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /!<GROUP5_IO4 schmitt trigger hysteresis mode /
	5580	#define TSC_IOHCR_G6_IO1_Pos (20U)
	5581	#define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /!< 0x00100000 /
	5582	#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /!<GROUP6_IO1 schmitt trigger hysteresis mode /
	5583	#define TSC_IOHCR_G6_IO2_Pos (21U)
	5584	#define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /!< 0x00200000 /
	5585	#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /!<GROUP6_IO2 schmitt trigger hysteresis mode /
	5586	#define TSC_IOHCR_G6_IO3_Pos (22U)
	5587	#define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /!< 0x00400000 /
	5588	#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /!<GROUP6_IO3 schmitt trigger hysteresis mode /
	5589	#define TSC_IOHCR_G6_IO4_Pos (23U)
	5590	#define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /!< 0x00800000 /
	5591	#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /!<GROUP6_IO4 schmitt trigger hysteresis mode /
	5592	#define TSC_IOHCR_G7_IO1_Pos (24U)
	5593	#define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /!< 0x01000000 /
	5594	#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /!<GROUP7_IO1 schmitt trigger hysteresis mode /
	5595	#define TSC_IOHCR_G7_IO2_Pos (25U)
	5596	#define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /!< 0x02000000 /
	5597	#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /!<GROUP7_IO2 schmitt trigger hysteresis mode /
	5598	#define TSC_IOHCR_G7_IO3_Pos (26U)
	5599	#define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /!< 0x04000000 /
	5600	#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /!<GROUP7_IO3 schmitt trigger hysteresis mode /
	5601	#define TSC_IOHCR_G7_IO4_Pos (27U)
	5602	#define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /!< 0x08000000 /
	5603	#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /!<GROUP7_IO4 schmitt trigger hysteresis mode /
	5604	#define TSC_IOHCR_G8_IO1_Pos (28U)
	5605	#define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /!< 0x10000000 /
	5606	#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /!<GROUP8_IO1 schmitt trigger hysteresis mode /
	5607	#define TSC_IOHCR_G8_IO2_Pos (29U)
	5608	#define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /!< 0x20000000 /
	5609	#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /!<GROUP8_IO2 schmitt trigger hysteresis mode /
	5610	#define TSC_IOHCR_G8_IO3_Pos (30U)
	5611	#define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /!< 0x40000000 /
	5612	#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /!<GROUP8_IO3 schmitt trigger hysteresis mode /
	5613	#define TSC_IOHCR_G8_IO4_Pos (31U)
	5614	#define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /!< 0x80000000 /
	5615	#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /!<GROUP8_IO4 schmitt trigger hysteresis mode /
	5616
	5617	/***************** Bit definition for TSC_IOASCR register ***************/
	5618	#define TSC_IOASCR_G1_IO1_Pos (0U)
	5619	#define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /!< 0x00000001 /
	5620	#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /!<GROUP1_IO1 analog switch enable /
	5621	#define TSC_IOASCR_G1_IO2_Pos (1U)
	5622	#define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /!< 0x00000002 /
	5623	#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /!<GROUP1_IO2 analog switch enable /
	5624	#define TSC_IOASCR_G1_IO3_Pos (2U)
	5625	#define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /!< 0x00000004 /
	5626	#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /!<GROUP1_IO3 analog switch enable /
	5627	#define TSC_IOASCR_G1_IO4_Pos (3U)
	5628	#define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /!< 0x00000008 /
	5629	#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /!<GROUP1_IO4 analog switch enable /
	5630	#define TSC_IOASCR_G2_IO1_Pos (4U)
	5631	#define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /!< 0x00000010 /
	5632	#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /!<GROUP2_IO1 analog switch enable /
	5633	#define TSC_IOASCR_G2_IO2_Pos (5U)
	5634	#define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /!< 0x00000020 /
	5635	#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /!<GROUP2_IO2 analog switch enable /
	5636	#define TSC_IOASCR_G2_IO3_Pos (6U)
	5637	#define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /!< 0x00000040 /
	5638	#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /!<GROUP2_IO3 analog switch enable /
	5639	#define TSC_IOASCR_G2_IO4_Pos (7U)
	5640	#define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /!< 0x00000080 /
	5641	#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /!<GROUP2_IO4 analog switch enable /
	5642	#define TSC_IOASCR_G3_IO1_Pos (8U)
	5643	#define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /!< 0x00000100 /
	5644	#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /!<GROUP3_IO1 analog switch enable /
	5645	#define TSC_IOASCR_G3_IO2_Pos (9U)
	5646	#define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /!< 0x00000200 /
	5647	#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /!<GROUP3_IO2 analog switch enable /
	5648	#define TSC_IOASCR_G3_IO3_Pos (10U)
	5649	#define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /!< 0x00000400 /
	5650	#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /!<GROUP3_IO3 analog switch enable /
	5651	#define TSC_IOASCR_G3_IO4_Pos (11U)
	5652	#define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /!< 0x00000800 /
	5653	#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /!<GROUP3_IO4 analog switch enable /
	5654	#define TSC_IOASCR_G4_IO1_Pos (12U)
	5655	#define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /!< 0x00001000 /
	5656	#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /!<GROUP4_IO1 analog switch enable /
	5657	#define TSC_IOASCR_G4_IO2_Pos (13U)
	5658	#define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /!< 0x00002000 /
	5659	#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /!<GROUP4_IO2 analog switch enable /
	5660	#define TSC_IOASCR_G4_IO3_Pos (14U)
	5661	#define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /!< 0x00004000 /
	5662	#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /!<GROUP4_IO3 analog switch enable /
	5663	#define TSC_IOASCR_G4_IO4_Pos (15U)
	5664	#define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /!< 0x00008000 /
	5665	#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /!<GROUP4_IO4 analog switch enable /
	5666	#define TSC_IOASCR_G5_IO1_Pos (16U)
	5667	#define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /!< 0x00010000 /
	5668	#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /!<GROUP5_IO1 analog switch enable /
	5669	#define TSC_IOASCR_G5_IO2_Pos (17U)
	5670	#define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /!< 0x00020000 /
	5671	#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /!<GROUP5_IO2 analog switch enable /
	5672	#define TSC_IOASCR_G5_IO3_Pos (18U)
	5673	#define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /!< 0x00040000 /
	5674	#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /!<GROUP5_IO3 analog switch enable /
	5675	#define TSC_IOASCR_G5_IO4_Pos (19U)
	5676	#define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /!< 0x00080000 /
	5677	#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /!<GROUP5_IO4 analog switch enable /
	5678	#define TSC_IOASCR_G6_IO1_Pos (20U)
	5679	#define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /!< 0x00100000 /
	5680	#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /!<GROUP6_IO1 analog switch enable /
	5681	#define TSC_IOASCR_G6_IO2_Pos (21U)
	5682	#define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /!< 0x00200000 /
	5683	#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /!<GROUP6_IO2 analog switch enable /
	5684	#define TSC_IOASCR_G6_IO3_Pos (22U)
	5685	#define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /!< 0x00400000 /
	5686	#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /!<GROUP6_IO3 analog switch enable /
	5687	#define TSC_IOASCR_G6_IO4_Pos (23U)
	5688	#define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /!< 0x00800000 /
	5689	#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /!<GROUP6_IO4 analog switch enable /
	5690	#define TSC_IOASCR_G7_IO1_Pos (24U)
	5691	#define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /!< 0x01000000 /
	5692	#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /!<GROUP7_IO1 analog switch enable /
	5693	#define TSC_IOASCR_G7_IO2_Pos (25U)
	5694	#define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /!< 0x02000000 /
	5695	#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /!<GROUP7_IO2 analog switch enable /
	5696	#define TSC_IOASCR_G7_IO3_Pos (26U)
	5697	#define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /!< 0x04000000 /
	5698	#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /!<GROUP7_IO3 analog switch enable /
	5699	#define TSC_IOASCR_G7_IO4_Pos (27U)
	5700	#define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /!< 0x08000000 /
	5701	#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /!<GROUP7_IO4 analog switch enable /
	5702	#define TSC_IOASCR_G8_IO1_Pos (28U)
	5703	#define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /!< 0x10000000 /
	5704	#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /!<GROUP8_IO1 analog switch enable /
	5705	#define TSC_IOASCR_G8_IO2_Pos (29U)
	5706	#define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /!< 0x20000000 /
	5707	#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /!<GROUP8_IO2 analog switch enable /
	5708	#define TSC_IOASCR_G8_IO3_Pos (30U)
	5709	#define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /!< 0x40000000 /
	5710	#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /!<GROUP8_IO3 analog switch enable /
	5711	#define TSC_IOASCR_G8_IO4_Pos (31U)
	5712	#define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /!< 0x80000000 /
	5713	#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /!<GROUP8_IO4 analog switch enable /
	5714
	5715	/***************** Bit definition for TSC_IOSCR register ****************/
	5716	#define TSC_IOSCR_G1_IO1_Pos (0U)
	5717	#define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /!< 0x00000001 /
	5718	#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /!<GROUP1_IO1 sampling mode /
	5719	#define TSC_IOSCR_G1_IO2_Pos (1U)
	5720	#define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /!< 0x00000002 /
	5721	#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /!<GROUP1_IO2 sampling mode /
	5722	#define TSC_IOSCR_G1_IO3_Pos (2U)
	5723	#define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /!< 0x00000004 /
	5724	#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /!<GROUP1_IO3 sampling mode /
	5725	#define TSC_IOSCR_G1_IO4_Pos (3U)
	5726	#define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /!< 0x00000008 /
	5727	#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /!<GROUP1_IO4 sampling mode /
	5728	#define TSC_IOSCR_G2_IO1_Pos (4U)
	5729	#define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /!< 0x00000010 /
	5730	#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /!<GROUP2_IO1 sampling mode /
	5731	#define TSC_IOSCR_G2_IO2_Pos (5U)
	5732	#define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /!< 0x00000020 /
	5733	#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /!<GROUP2_IO2 sampling mode /
	5734	#define TSC_IOSCR_G2_IO3_Pos (6U)
	5735	#define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /!< 0x00000040 /
	5736	#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /!<GROUP2_IO3 sampling mode /
	5737	#define TSC_IOSCR_G2_IO4_Pos (7U)
	5738	#define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /!< 0x00000080 /
	5739	#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /!<GROUP2_IO4 sampling mode /
	5740	#define TSC_IOSCR_G3_IO1_Pos (8U)
	5741	#define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /!< 0x00000100 /
	5742	#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /!<GROUP3_IO1 sampling mode /
	5743	#define TSC_IOSCR_G3_IO2_Pos (9U)
	5744	#define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /!< 0x00000200 /
	5745	#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /!<GROUP3_IO2 sampling mode /
	5746	#define TSC_IOSCR_G3_IO3_Pos (10U)
	5747	#define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /!< 0x00000400 /
	5748	#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /!<GROUP3_IO3 sampling mode /
	5749	#define TSC_IOSCR_G3_IO4_Pos (11U)
	5750	#define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /!< 0x00000800 /
	5751	#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /!<GROUP3_IO4 sampling mode /
	5752	#define TSC_IOSCR_G4_IO1_Pos (12U)
	5753	#define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /!< 0x00001000 /
	5754	#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /!<GROUP4_IO1 sampling mode /
	5755	#define TSC_IOSCR_G4_IO2_Pos (13U)
	5756	#define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /!< 0x00002000 /
	5757	#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /!<GROUP4_IO2 sampling mode /
	5758	#define TSC_IOSCR_G4_IO3_Pos (14U)
	5759	#define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /!< 0x00004000 /
	5760	#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /!<GROUP4_IO3 sampling mode /
	5761	#define TSC_IOSCR_G4_IO4_Pos (15U)
	5762	#define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /!< 0x00008000 /
	5763	#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /!<GROUP4_IO4 sampling mode /
	5764	#define TSC_IOSCR_G5_IO1_Pos (16U)
	5765	#define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /!< 0x00010000 /
	5766	#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /!<GROUP5_IO1 sampling mode /
	5767	#define TSC_IOSCR_G5_IO2_Pos (17U)
	5768	#define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /!< 0x00020000 /
	5769	#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /!<GROUP5_IO2 sampling mode /
	5770	#define TSC_IOSCR_G5_IO3_Pos (18U)
	5771	#define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /!< 0x00040000 /
	5772	#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /!<GROUP5_IO3 sampling mode /
	5773	#define TSC_IOSCR_G5_IO4_Pos (19U)
	5774	#define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /!< 0x00080000 /
	5775	#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /!<GROUP5_IO4 sampling mode /
	5776	#define TSC_IOSCR_G6_IO1_Pos (20U)
	5777	#define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /!< 0x00100000 /
	5778	#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /!<GROUP6_IO1 sampling mode /
	5779	#define TSC_IOSCR_G6_IO2_Pos (21U)
	5780	#define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /!< 0x00200000 /
	5781	#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /!<GROUP6_IO2 sampling mode /
	5782	#define TSC_IOSCR_G6_IO3_Pos (22U)
	5783	#define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /!< 0x00400000 /
	5784	#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /!<GROUP6_IO3 sampling mode /
	5785	#define TSC_IOSCR_G6_IO4_Pos (23U)
	5786	#define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /!< 0x00800000 /
	5787	#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /!<GROUP6_IO4 sampling mode /
	5788	#define TSC_IOSCR_G7_IO1_Pos (24U)
	5789	#define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /!< 0x01000000 /
	5790	#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /!<GROUP7_IO1 sampling mode /
	5791	#define TSC_IOSCR_G7_IO2_Pos (25U)
	5792	#define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /!< 0x02000000 /
	5793	#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /!<GROUP7_IO2 sampling mode /
	5794	#define TSC_IOSCR_G7_IO3_Pos (26U)
	5795	#define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /!< 0x04000000 /
	5796	#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /!<GROUP7_IO3 sampling mode /
	5797	#define TSC_IOSCR_G7_IO4_Pos (27U)
	5798	#define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /!< 0x08000000 /
	5799	#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /!<GROUP7_IO4 sampling mode /
	5800	#define TSC_IOSCR_G8_IO1_Pos (28U)
	5801	#define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /!< 0x10000000 /
	5802	#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /!<GROUP8_IO1 sampling mode /
	5803	#define TSC_IOSCR_G8_IO2_Pos (29U)
	5804	#define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /!< 0x20000000 /
	5805	#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /!<GROUP8_IO2 sampling mode /
	5806	#define TSC_IOSCR_G8_IO3_Pos (30U)
	5807	#define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /!< 0x40000000 /
	5808	#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /!<GROUP8_IO3 sampling mode /
	5809	#define TSC_IOSCR_G8_IO4_Pos (31U)
	5810	#define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /!< 0x80000000 /
	5811	#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /!<GROUP8_IO4 sampling mode /
	5812
	5813	/***************** Bit definition for TSC_IOCCR register ****************/
	5814	#define TSC_IOCCR_G1_IO1_Pos (0U)
	5815	#define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /!< 0x00000001 /
	5816	#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /!<GROUP1_IO1 channel mode /
	5817	#define TSC_IOCCR_G1_IO2_Pos (1U)
	5818	#define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /!< 0x00000002 /
	5819	#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /!<GROUP1_IO2 channel mode /
	5820	#define TSC_IOCCR_G1_IO3_Pos (2U)
	5821	#define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /!< 0x00000004 /
	5822	#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /!<GROUP1_IO3 channel mode /
	5823	#define TSC_IOCCR_G1_IO4_Pos (3U)
	5824	#define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /!< 0x00000008 /
	5825	#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /!<GROUP1_IO4 channel mode /
	5826	#define TSC_IOCCR_G2_IO1_Pos (4U)
	5827	#define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /!< 0x00000010 /
	5828	#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /!<GROUP2_IO1 channel mode /
	5829	#define TSC_IOCCR_G2_IO2_Pos (5U)
	5830	#define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /!< 0x00000020 /
	5831	#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /!<GROUP2_IO2 channel mode /
	5832	#define TSC_IOCCR_G2_IO3_Pos (6U)
	5833	#define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /!< 0x00000040 /
	5834	#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /!<GROUP2_IO3 channel mode /
	5835	#define TSC_IOCCR_G2_IO4_Pos (7U)
	5836	#define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /!< 0x00000080 /
	5837	#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /!<GROUP2_IO4 channel mode /
	5838	#define TSC_IOCCR_G3_IO1_Pos (8U)
	5839	#define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /!< 0x00000100 /
	5840	#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /!<GROUP3_IO1 channel mode /
	5841	#define TSC_IOCCR_G3_IO2_Pos (9U)
	5842	#define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /!< 0x00000200 /
	5843	#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /!<GROUP3_IO2 channel mode /
	5844	#define TSC_IOCCR_G3_IO3_Pos (10U)
	5845	#define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /!< 0x00000400 /
	5846	#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /!<GROUP3_IO3 channel mode /
	5847	#define TSC_IOCCR_G3_IO4_Pos (11U)
	5848	#define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /!< 0x00000800 /
	5849	#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /!<GROUP3_IO4 channel mode /
	5850	#define TSC_IOCCR_G4_IO1_Pos (12U)
	5851	#define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /!< 0x00001000 /
	5852	#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /!<GROUP4_IO1 channel mode /
	5853	#define TSC_IOCCR_G4_IO2_Pos (13U)
	5854	#define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /!< 0x00002000 /
	5855	#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /!<GROUP4_IO2 channel mode /
	5856	#define TSC_IOCCR_G4_IO3_Pos (14U)
	5857	#define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /!< 0x00004000 /
	5858	#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /!<GROUP4_IO3 channel mode /
	5859	#define TSC_IOCCR_G4_IO4_Pos (15U)
	5860	#define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /!< 0x00008000 /
	5861	#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /!<GROUP4_IO4 channel mode /
	5862	#define TSC_IOCCR_G5_IO1_Pos (16U)
	5863	#define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /!< 0x00010000 /
	5864	#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /!<GROUP5_IO1 channel mode /
	5865	#define TSC_IOCCR_G5_IO2_Pos (17U)
	5866	#define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /!< 0x00020000 /
	5867	#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /!<GROUP5_IO2 channel mode /
	5868	#define TSC_IOCCR_G5_IO3_Pos (18U)
	5869	#define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /!< 0x00040000 /
	5870	#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /!<GROUP5_IO3 channel mode /
	5871	#define TSC_IOCCR_G5_IO4_Pos (19U)
	5872	#define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /!< 0x00080000 /
	5873	#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /!<GROUP5_IO4 channel mode /
	5874	#define TSC_IOCCR_G6_IO1_Pos (20U)
	5875	#define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /!< 0x00100000 /
	5876	#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /!<GROUP6_IO1 channel mode /
	5877	#define TSC_IOCCR_G6_IO2_Pos (21U)
	5878	#define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /!< 0x00200000 /
	5879	#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /!<GROUP6_IO2 channel mode /
	5880	#define TSC_IOCCR_G6_IO3_Pos (22U)
	5881	#define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /!< 0x00400000 /
	5882	#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /!<GROUP6_IO3 channel mode /
	5883	#define TSC_IOCCR_G6_IO4_Pos (23U)
	5884	#define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /!< 0x00800000 /
	5885	#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /!<GROUP6_IO4 channel mode /
	5886	#define TSC_IOCCR_G7_IO1_Pos (24U)
	5887	#define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /!< 0x01000000 /
	5888	#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /!<GROUP7_IO1 channel mode /
	5889	#define TSC_IOCCR_G7_IO2_Pos (25U)
	5890	#define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /!< 0x02000000 /
	5891	#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /!<GROUP7_IO2 channel mode /
	5892	#define TSC_IOCCR_G7_IO3_Pos (26U)
	5893	#define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /!< 0x04000000 /
	5894	#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /!<GROUP7_IO3 channel mode /
	5895	#define TSC_IOCCR_G7_IO4_Pos (27U)
	5896	#define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /!< 0x08000000 /
	5897	#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /!<GROUP7_IO4 channel mode /
	5898	#define TSC_IOCCR_G8_IO1_Pos (28U)
	5899	#define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /!< 0x10000000 /
	5900	#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /!<GROUP8_IO1 channel mode /
	5901	#define TSC_IOCCR_G8_IO2_Pos (29U)
	5902	#define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /!< 0x20000000 /
	5903	#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /!<GROUP8_IO2 channel mode /
	5904	#define TSC_IOCCR_G8_IO3_Pos (30U)
	5905	#define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /!< 0x40000000 /
	5906	#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /!<GROUP8_IO3 channel mode /
	5907	#define TSC_IOCCR_G8_IO4_Pos (31U)
	5908	#define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /!< 0x80000000 /
	5909	#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /!<GROUP8_IO4 channel mode /
	5910
	5911	/***************** Bit definition for TSC_IOGCSR register ***************/
	5912	#define TSC_IOGCSR_G1E_Pos (0U)
	5913	#define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /!< 0x00000001 /
	5914	#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /!<Analog IO GROUP1 enable /
	5915	#define TSC_IOGCSR_G2E_Pos (1U)
	5916	#define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /!< 0x00000002 /
	5917	#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /!<Analog IO GROUP2 enable /
	5918	#define TSC_IOGCSR_G3E_Pos (2U)
	5919	#define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /!< 0x00000004 /
	5920	#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /!<Analog IO GROUP3 enable /
	5921	#define TSC_IOGCSR_G4E_Pos (3U)
	5922	#define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /!< 0x00000008 /
	5923	#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /!<Analog IO GROUP4 enable /
	5924	#define TSC_IOGCSR_G5E_Pos (4U)
	5925	#define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /!< 0x00000010 /
	5926	#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /!<Analog IO GROUP5 enable /
	5927	#define TSC_IOGCSR_G6E_Pos (5U)
	5928	#define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /!< 0x00000020 /
	5929	#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /!<Analog IO GROUP6 enable /
	5930	#define TSC_IOGCSR_G7E_Pos (6U)
	5931	#define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /!< 0x00000040 /
	5932	#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /!<Analog IO GROUP7 enable /
	5933	#define TSC_IOGCSR_G8E_Pos (7U)
	5934	#define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /!< 0x00000080 /
	5935	#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /!<Analog IO GROUP8 enable /
	5936	#define TSC_IOGCSR_G1S_Pos (16U)
	5937	#define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /!< 0x00010000 /
	5938	#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /!<Analog IO GROUP1 status /
	5939	#define TSC_IOGCSR_G2S_Pos (17U)
	5940	#define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /!< 0x00020000 /
	5941	#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /!<Analog IO GROUP2 status /
	5942	#define TSC_IOGCSR_G3S_Pos (18U)
	5943	#define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /!< 0x00040000 /
	5944	#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /!<Analog IO GROUP3 status /
	5945	#define TSC_IOGCSR_G4S_Pos (19U)
	5946	#define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /!< 0x00080000 /
	5947	#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /!<Analog IO GROUP4 status /
	5948	#define TSC_IOGCSR_G5S_Pos (20U)
	5949	#define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /!< 0x00100000 /
	5950	#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /!<Analog IO GROUP5 status /
	5951	#define TSC_IOGCSR_G6S_Pos (21U)
	5952	#define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /!< 0x00200000 /
	5953	#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /!<Analog IO GROUP6 status /
	5954	#define TSC_IOGCSR_G7S_Pos (22U)
	5955	#define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /!< 0x00400000 /
	5956	#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /!<Analog IO GROUP7 status /
	5957	#define TSC_IOGCSR_G8S_Pos (23U)
	5958	#define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /!< 0x00800000 /
	5959	#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /!<Analog IO GROUP8 status /
	5960
	5961	/***************** Bit definition for TSC_IOGXCR register ***************/
	5962	#define TSC_IOGXCR_CNT_Pos (0U)
	5963	#define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /!< 0x00003FFF /
	5964	#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /!<CNT[13:0] bits (Counter value) /
	5965
	5966	/******************************************************************************/
	5967	/* */
	5968	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
	5969	/* */
	5970	/******************************************************************************/
	5971
	5972	/*
	5973	* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
	5974	*/
	5975
	5976	/* Support of LIN feature */
	5977	#define USART_LIN_SUPPORT
	5978
	5979	/* Support of Smartcard feature */
	5980	#define USART_SMARTCARD_SUPPORT
	5981
	5982	/* Support of Irda feature */
	5983	#define USART_IRDA_SUPPORT
	5984
	5985	/* Support of Wake Up from Stop Mode feature */
	5986	#define USART_WUSM_SUPPORT
	5987
	5988	/**************** Bit definition for USART_CR1 register *****************/
	5989	#define USART_CR1_UE_Pos (0U)
	5990	#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /!< 0x00000001 /
	5991	#define USART_CR1_UE USART_CR1_UE_Msk /!< USART Enable /
	5992	#define USART_CR1_UESM_Pos (1U)
	5993	#define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /!< 0x00000002 /
	5994	#define USART_CR1_UESM USART_CR1_UESM_Msk /!< USART Enable in STOP Mode /
	5995	#define USART_CR1_RE_Pos (2U)
	5996	#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /!< 0x00000004 /
	5997	#define USART_CR1_RE USART_CR1_RE_Msk /!< Receiver Enable /
	5998	#define USART_CR1_TE_Pos (3U)
	5999	#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /!< 0x00000008 /
	6000	#define USART_CR1_TE USART_CR1_TE_Msk /!< Transmitter Enable /
	6001	#define USART_CR1_IDLEIE_Pos (4U)
	6002	#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /!< 0x00000010 /
	6003	#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /!< IDLE Interrupt Enable /
	6004	#define USART_CR1_RXNEIE_Pos (5U)
	6005	#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /!< 0x00000020 /
	6006	#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /!< RXNE Interrupt Enable /
	6007	#define USART_CR1_TCIE_Pos (6U)
	6008	#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /!< 0x00000040 /
	6009	#define USART_CR1_TCIE USART_CR1_TCIE_Msk /!< Transmission Complete Interrupt Enable /
	6010	#define USART_CR1_TXEIE_Pos (7U)
	6011	#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /!< 0x00000080 /
	6012	#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /!< TXE Interrupt Enable /
	6013	#define USART_CR1_PEIE_Pos (8U)
	6014	#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /!< 0x00000100 /
	6015	#define USART_CR1_PEIE USART_CR1_PEIE_Msk /!< PE Interrupt Enable /
	6016	#define USART_CR1_PS_Pos (9U)
	6017	#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /!< 0x00000200 /
	6018	#define USART_CR1_PS USART_CR1_PS_Msk /!< Parity Selection /
	6019	#define USART_CR1_PCE_Pos (10U)
	6020	#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /!< 0x00000400 /
	6021	#define USART_CR1_PCE USART_CR1_PCE_Msk /!< Parity Control Enable /
	6022	#define USART_CR1_WAKE_Pos (11U)
	6023	#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /!< 0x00000800 /
	6024	#define USART_CR1_WAKE USART_CR1_WAKE_Msk /!< Receiver Wakeup method /
	6025	#define USART_CR1_M_Pos (12U)
	6026	#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /!< 0x00001000 /
	6027	#define USART_CR1_M USART_CR1_M_Msk /!< Word Length /
	6028	#define USART_CR1_MME_Pos (13U)
	6029	#define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /!< 0x00002000 /
	6030	#define USART_CR1_MME USART_CR1_MME_Msk /!< Mute Mode Enable /
	6031	#define USART_CR1_CMIE_Pos (14U)
	6032	#define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /!< 0x00004000 /
	6033	#define USART_CR1_CMIE USART_CR1_CMIE_Msk /!< Character match interrupt enable /
	6034	#define USART_CR1_OVER8_Pos (15U)
	6035	#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /!< 0x00008000 /
	6036	#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /!< Oversampling by 8-bit or 16-bit mode /
	6037	#define USART_CR1_DEDT_Pos (16U)
	6038	#define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /!< 0x001F0000 /
	6039	#define USART_CR1_DEDT USART_CR1_DEDT_Msk /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
	6040	#define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /!< 0x00010000 /
	6041	#define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /!< 0x00020000 /
	6042	#define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /!< 0x00040000 /
	6043	#define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /!< 0x00080000 /
	6044	#define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /!< 0x00100000 /
	6045	#define USART_CR1_DEAT_Pos (21U)
	6046	#define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /!< 0x03E00000 /
	6047	#define USART_CR1_DEAT USART_CR1_DEAT_Msk /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
	6048	#define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /!< 0x00200000 /
	6049	#define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /!< 0x00400000 /
	6050	#define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /!< 0x00800000 /
	6051	#define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /!< 0x01000000 /
	6052	#define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /!< 0x02000000 /
	6053	#define USART_CR1_RTOIE_Pos (26U)
	6054	#define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /!< 0x04000000 /
	6055	#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /!< Receive Time Out interrupt enable /
	6056	#define USART_CR1_EOBIE_Pos (27U)
	6057	#define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /!< 0x08000000 /
	6058	#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /!< End of Block interrupt enable /
	6059
	6060	/**************** Bit definition for USART_CR2 register *****************/
	6061	#define USART_CR2_ADDM7_Pos (4U)
	6062	#define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /!< 0x00000010 /
	6063	#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /!< 7-bit or 4-bit Address Detection /
	6064	#define USART_CR2_LBDL_Pos (5U)
	6065	#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /!< 0x00000020 /
	6066	#define USART_CR2_LBDL USART_CR2_LBDL_Msk /!< LIN Break Detection Length /
	6067	#define USART_CR2_LBDIE_Pos (6U)
	6068	#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /!< 0x00000040 /
	6069	#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /!< LIN Break Detection Interrupt Enable /
	6070	#define USART_CR2_LBCL_Pos (8U)
	6071	#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /!< 0x00000100 /
	6072	#define USART_CR2_LBCL USART_CR2_LBCL_Msk /!< Last Bit Clock pulse /
	6073	#define USART_CR2_CPHA_Pos (9U)
	6074	#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /!< 0x00000200 /
	6075	#define USART_CR2_CPHA USART_CR2_CPHA_Msk /!< Clock Phase /
	6076	#define USART_CR2_CPOL_Pos (10U)
	6077	#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /!< 0x00000400 /
	6078	#define USART_CR2_CPOL USART_CR2_CPOL_Msk /!< Clock Polarity /
	6079	#define USART_CR2_CLKEN_Pos (11U)
	6080	#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /!< 0x00000800 /
	6081	#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /!< Clock Enable /
	6082	#define USART_CR2_STOP_Pos (12U)
	6083	#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /!< 0x00003000 /
	6084	#define USART_CR2_STOP USART_CR2_STOP_Msk /!< STOP[1:0] bits (STOP bits) /
	6085	#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /!< 0x00001000 /
	6086	#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /!< 0x00002000 /
	6087	#define USART_CR2_LINEN_Pos (14U)
	6088	#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /!< 0x00004000 /
	6089	#define USART_CR2_LINEN USART_CR2_LINEN_Msk /!< LIN mode enable /
	6090	#define USART_CR2_SWAP_Pos (15U)
	6091	#define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /!< 0x00008000 /
	6092	#define USART_CR2_SWAP USART_CR2_SWAP_Msk /!< SWAP TX/RX pins /
	6093	#define USART_CR2_RXINV_Pos (16U)
	6094	#define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /!< 0x00010000 /
	6095	#define USART_CR2_RXINV USART_CR2_RXINV_Msk /!< RX pin active level inversion /
	6096	#define USART_CR2_TXINV_Pos (17U)
	6097	#define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /!< 0x00020000 /
	6098	#define USART_CR2_TXINV USART_CR2_TXINV_Msk /!< TX pin active level inversion /
	6099	#define USART_CR2_DATAINV_Pos (18U)
	6100	#define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /!< 0x00040000 /
	6101	#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /!< Binary data inversion /
	6102	#define USART_CR2_MSBFIRST_Pos (19U)
	6103	#define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /!< 0x00080000 /
	6104	#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /!< Most Significant Bit First /
	6105	#define USART_CR2_ABREN_Pos (20U)
	6106	#define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /!< 0x00100000 /
	6107	#define USART_CR2_ABREN USART_CR2_ABREN_Msk /!< Auto Baud-Rate Enable/
	6108	#define USART_CR2_ABRMODE_Pos (21U)
	6109	#define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /!< 0x00600000 /
	6110	#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
	6111	#define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /!< 0x00200000 /
	6112	#define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /!< 0x00400000 /
	6113	#define USART_CR2_RTOEN_Pos (23U)
	6114	#define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /!< 0x00800000 /
	6115	#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /!< Receiver Time-Out enable /
	6116	#define USART_CR2_ADD_Pos (24U)
	6117	#define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /!< 0xFF000000 /
	6118	#define USART_CR2_ADD USART_CR2_ADD_Msk /!< Address of the USART node /
	6119
	6120	/**************** Bit definition for USART_CR3 register *****************/
	6121	#define USART_CR3_EIE_Pos (0U)
	6122	#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /!< 0x00000001 /
	6123	#define USART_CR3_EIE USART_CR3_EIE_Msk /!< Error Interrupt Enable /
	6124	#define USART_CR3_IREN_Pos (1U)
	6125	#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /!< 0x00000002 /
	6126	#define USART_CR3_IREN USART_CR3_IREN_Msk /!< IrDA mode Enable /
	6127	#define USART_CR3_IRLP_Pos (2U)
	6128	#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /!< 0x00000004 /
	6129	#define USART_CR3_IRLP USART_CR3_IRLP_Msk /!< IrDA Low-Power /
	6130	#define USART_CR3_HDSEL_Pos (3U)
	6131	#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /!< 0x00000008 /
	6132	#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /!< Half-Duplex Selection /
	6133	#define USART_CR3_NACK_Pos (4U)
	6134	#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /!< 0x00000010 /
	6135	#define USART_CR3_NACK USART_CR3_NACK_Msk /!< SmartCard NACK enable /
	6136	#define USART_CR3_SCEN_Pos (5U)
	6137	#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /!< 0x00000020 /
	6138	#define USART_CR3_SCEN USART_CR3_SCEN_Msk /!< SmartCard mode enable /
	6139	#define USART_CR3_DMAR_Pos (6U)
	6140	#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /!< 0x00000040 /
	6141	#define USART_CR3_DMAR USART_CR3_DMAR_Msk /!< DMA Enable Receiver /
	6142	#define USART_CR3_DMAT_Pos (7U)
	6143	#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /!< 0x00000080 /
	6144	#define USART_CR3_DMAT USART_CR3_DMAT_Msk /!< DMA Enable Transmitter /
	6145	#define USART_CR3_RTSE_Pos (8U)
	6146	#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /!< 0x00000100 /
	6147	#define USART_CR3_RTSE USART_CR3_RTSE_Msk /!< RTS Enable /
	6148	#define USART_CR3_CTSE_Pos (9U)
	6149	#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /!< 0x00000200 /
	6150	#define USART_CR3_CTSE USART_CR3_CTSE_Msk /!< CTS Enable /
	6151	#define USART_CR3_CTSIE_Pos (10U)
	6152	#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /!< 0x00000400 /
	6153	#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /!< CTS Interrupt Enable /
	6154	#define USART_CR3_ONEBIT_Pos (11U)
	6155	#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /!< 0x00000800 /
	6156	#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /!< One sample bit method enable /
	6157	#define USART_CR3_OVRDIS_Pos (12U)
	6158	#define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /!< 0x00001000 /
	6159	#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /!< Overrun Disable /
	6160	#define USART_CR3_DDRE_Pos (13U)
	6161	#define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /!< 0x00002000 /
	6162	#define USART_CR3_DDRE USART_CR3_DDRE_Msk /!< DMA Disable on Reception Error /
	6163	#define USART_CR3_DEM_Pos (14U)
	6164	#define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /!< 0x00004000 /
	6165	#define USART_CR3_DEM USART_CR3_DEM_Msk /!< Driver Enable Mode /
	6166	#define USART_CR3_DEP_Pos (15U)
	6167	#define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /!< 0x00008000 /
	6168	#define USART_CR3_DEP USART_CR3_DEP_Msk /!< Driver Enable Polarity Selection /
	6169	#define USART_CR3_SCARCNT_Pos (17U)
	6170	#define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /!< 0x000E0000 /
	6171	#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
	6172	#define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /!< 0x00020000 /
	6173	#define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /!< 0x00040000 /
	6174	#define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /!< 0x00080000 /
	6175	#define USART_CR3_WUS_Pos (20U)
	6176	#define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /!< 0x00300000 /
	6177	#define USART_CR3_WUS USART_CR3_WUS_Msk /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
	6178	#define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /!< 0x00100000 /
	6179	#define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /!< 0x00200000 /
	6180	#define USART_CR3_WUFIE_Pos (22U)
	6181	#define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /!< 0x00400000 /
	6182	#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /!< Wake Up Interrupt Enable /
	6183
	6184	/**************** Bit definition for USART_BRR register *****************/
	6185	#define USART_BRR_DIV_FRACTION_Pos (0U)
	6186	#define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /!< 0x0000000F /
	6187	#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /!< Fraction of USARTDIV /
	6188	#define USART_BRR_DIV_MANTISSA_Pos (4U)
	6189	#define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /!< 0x0000FFF0 /
	6190	#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /!< Mantissa of USARTDIV /
	6191
	6192	/**************** Bit definition for USART_GTPR register ****************/
	6193	#define USART_GTPR_PSC_Pos (0U)
	6194	#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /!< 0x000000FF /
	6195	#define USART_GTPR_PSC USART_GTPR_PSC_Msk /!< PSC[7:0] bits (Prescaler value) /
	6196	#define USART_GTPR_GT_Pos (8U)
	6197	#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /!< 0x0000FF00 /
	6198	#define USART_GTPR_GT USART_GTPR_GT_Msk /!< GT[7:0] bits (Guard time value) /
	6199
	6200
	6201	/***************** Bit definition for USART_RTOR register ***************/
	6202	#define USART_RTOR_RTO_Pos (0U)
	6203	#define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /!< 0x00FFFFFF /
	6204	#define USART_RTOR_RTO USART_RTOR_RTO_Msk /!< Receiver Time Out Value /
	6205	#define USART_RTOR_BLEN_Pos (24U)
	6206	#define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /!< 0xFF000000 /
	6207	#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /!< Block Length /
	6208
	6209	/***************** Bit definition for USART_RQR register ****************/
	6210	#define USART_RQR_ABRRQ_Pos (0U)
	6211	#define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /!< 0x00000001 /
	6212	#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /!< Auto-Baud Rate Request /
	6213	#define USART_RQR_SBKRQ_Pos (1U)
	6214	#define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /!< 0x00000002 /
	6215	#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /!< Send Break Request /
	6216	#define USART_RQR_MMRQ_Pos (2U)
	6217	#define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /!< 0x00000004 /
	6218	#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /!< Mute Mode Request /
	6219	#define USART_RQR_RXFRQ_Pos (3U)
	6220	#define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /!< 0x00000008 /
	6221	#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /!< Receive Data flush Request /
	6222	#define USART_RQR_TXFRQ_Pos (4U)
	6223	#define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /!< 0x00000010 /
	6224	#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /!< Transmit data flush Request /
	6225
	6226	/***************** Bit definition for USART_ISR register ****************/
	6227	#define USART_ISR_PE_Pos (0U)
	6228	#define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /!< 0x00000001 /
	6229	#define USART_ISR_PE USART_ISR_PE_Msk /!< Parity Error /
	6230	#define USART_ISR_FE_Pos (1U)
	6231	#define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /!< 0x00000002 /
	6232	#define USART_ISR_FE USART_ISR_FE_Msk /!< Framing Error /
	6233	#define USART_ISR_NE_Pos (2U)
	6234	#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /!< 0x00000004 /
	6235	#define USART_ISR_NE USART_ISR_NE_Msk /!< Noise detected Flag /
	6236	#define USART_ISR_ORE_Pos (3U)
	6237	#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /!< 0x00000008 /
	6238	#define USART_ISR_ORE USART_ISR_ORE_Msk /!< OverRun Error /
	6239	#define USART_ISR_IDLE_Pos (4U)
	6240	#define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /!< 0x00000010 /
	6241	#define USART_ISR_IDLE USART_ISR_IDLE_Msk /!< IDLE line detected /
	6242	#define USART_ISR_RXNE_Pos (5U)
	6243	#define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /!< 0x00000020 /
	6244	#define USART_ISR_RXNE USART_ISR_RXNE_Msk /!< Read Data Register Not Empty /
	6245	#define USART_ISR_TC_Pos (6U)
	6246	#define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /!< 0x00000040 /
	6247	#define USART_ISR_TC USART_ISR_TC_Msk /!< Transmission Complete /
	6248	#define USART_ISR_TXE_Pos (7U)
	6249	#define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /!< 0x00000080 /
	6250	#define USART_ISR_TXE USART_ISR_TXE_Msk /!< Transmit Data Register Empty /
	6251	#define USART_ISR_LBDF_Pos (8U)
	6252	#define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /!< 0x00000100 /
	6253	#define USART_ISR_LBDF USART_ISR_LBDF_Msk /!< LIN Break Detection Flag /
	6254	#define USART_ISR_CTSIF_Pos (9U)
	6255	#define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /!< 0x00000200 /
	6256	#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /!< CTS interrupt flag /
	6257	#define USART_ISR_CTS_Pos (10U)
	6258	#define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /!< 0x00000400 /
	6259	#define USART_ISR_CTS USART_ISR_CTS_Msk /!< CTS flag /
	6260	#define USART_ISR_RTOF_Pos (11U)
	6261	#define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /!< 0x00000800 /
	6262	#define USART_ISR_RTOF USART_ISR_RTOF_Msk /!< Receiver Time Out /
	6263	#define USART_ISR_EOBF_Pos (12U)
	6264	#define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /!< 0x00001000 /
	6265	#define USART_ISR_EOBF USART_ISR_EOBF_Msk /!< End Of Block Flag /
	6266	#define USART_ISR_ABRE_Pos (14U)
	6267	#define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /!< 0x00004000 /
	6268	#define USART_ISR_ABRE USART_ISR_ABRE_Msk /!< Auto-Baud Rate Error /
	6269	#define USART_ISR_ABRF_Pos (15U)
	6270	#define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /!< 0x00008000 /
	6271	#define USART_ISR_ABRF USART_ISR_ABRF_Msk /!< Auto-Baud Rate Flag /
	6272	#define USART_ISR_BUSY_Pos (16U)
	6273	#define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /!< 0x00010000 /
	6274	#define USART_ISR_BUSY USART_ISR_BUSY_Msk /!< Busy Flag /
	6275	#define USART_ISR_CMF_Pos (17U)
	6276	#define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /!< 0x00020000 /
	6277	#define USART_ISR_CMF USART_ISR_CMF_Msk /!< Character Match Flag /
	6278	#define USART_ISR_SBKF_Pos (18U)
	6279	#define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /!< 0x00040000 /
	6280	#define USART_ISR_SBKF USART_ISR_SBKF_Msk /!< Send Break Flag /
	6281	#define USART_ISR_RWU_Pos (19U)
	6282	#define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /!< 0x00080000 /
	6283	#define USART_ISR_RWU USART_ISR_RWU_Msk /!< Receive Wake Up from mute mode Flag /
	6284	#define USART_ISR_WUF_Pos (20U)
	6285	#define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /!< 0x00100000 /
	6286	#define USART_ISR_WUF USART_ISR_WUF_Msk /!< Wake Up from stop mode Flag /
	6287	#define USART_ISR_TEACK_Pos (21U)
	6288	#define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /!< 0x00200000 /
	6289	#define USART_ISR_TEACK USART_ISR_TEACK_Msk /!< Transmit Enable Acknowledge Flag /
	6290	#define USART_ISR_REACK_Pos (22U)
	6291	#define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /!< 0x00400000 /
	6292	#define USART_ISR_REACK USART_ISR_REACK_Msk /!< Receive Enable Acknowledge Flag /
	6293
	6294	/***************** Bit definition for USART_ICR register ****************/
	6295	#define USART_ICR_PECF_Pos (0U)
	6296	#define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /!< 0x00000001 /
	6297	#define USART_ICR_PECF USART_ICR_PECF_Msk /!< Parity Error Clear Flag /
	6298	#define USART_ICR_FECF_Pos (1U)
	6299	#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /!< 0x00000002 /
	6300	#define USART_ICR_FECF USART_ICR_FECF_Msk /!< Framing Error Clear Flag /
	6301	#define USART_ICR_NCF_Pos (2U)
	6302	#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /!< 0x00000004 /
	6303	#define USART_ICR_NCF USART_ICR_NCF_Msk /!< Noise detected Clear Flag /
	6304	#define USART_ICR_ORECF_Pos (3U)
	6305	#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /!< 0x00000008 /
	6306	#define USART_ICR_ORECF USART_ICR_ORECF_Msk /!< OverRun Error Clear Flag /
	6307	#define USART_ICR_IDLECF_Pos (4U)
	6308	#define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /!< 0x00000010 /
	6309	#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /!< IDLE line detected Clear Flag /
	6310	#define USART_ICR_TCCF_Pos (6U)
	6311	#define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /!< 0x00000040 /
	6312	#define USART_ICR_TCCF USART_ICR_TCCF_Msk /!< Transmission Complete Clear Flag /
	6313	#define USART_ICR_LBDCF_Pos (8U)
	6314	#define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /!< 0x00000100 /
	6315	#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /!< LIN Break Detection Clear Flag /
	6316	#define USART_ICR_CTSCF_Pos (9U)
	6317	#define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /!< 0x00000200 /
	6318	#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /!< CTS Interrupt Clear Flag /
	6319	#define USART_ICR_RTOCF_Pos (11U)
	6320	#define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /!< 0x00000800 /
	6321	#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /!< Receiver Time Out Clear Flag /
	6322	#define USART_ICR_EOBCF_Pos (12U)
	6323	#define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /!< 0x00001000 /
	6324	#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /!< End Of Block Clear Flag /
	6325	#define USART_ICR_CMCF_Pos (17U)
	6326	#define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /!< 0x00020000 /
	6327	#define USART_ICR_CMCF USART_ICR_CMCF_Msk /!< Character Match Clear Flag /
	6328	#define USART_ICR_WUCF_Pos (20U)
	6329	#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /!< 0x00100000 /
	6330	#define USART_ICR_WUCF USART_ICR_WUCF_Msk /!< Wake Up from stop mode Clear Flag /
	6331
	6332	/***************** Bit definition for USART_RDR register ****************/
	6333	#define USART_RDR_RDR ((uint16_t)0x01FFU) /!< RDR[8:0] bits (Receive Data value) /
	6334
	6335	/***************** Bit definition for USART_TDR register ****************/
	6336	#define USART_TDR_TDR ((uint16_t)0x01FFU) /!< TDR[8:0] bits (Transmit Data value) /
	6337
	6338	/******************************************************************************/
	6339	/* */
	6340	/* Window WATCHDOG (WWDG) */
	6341	/* */
	6342	/******************************************************************************/
	6343
	6344	/***************** Bit definition for WWDG_CR register ******************/
	6345	#define WWDG_CR_T_Pos (0U)
	6346	#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /!< 0x0000007F /
	6347	#define WWDG_CR_T WWDG_CR_T_Msk /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
	6348	#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /!< 0x00000001 /
	6349	#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /!< 0x00000002 /
	6350	#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /!< 0x00000004 /
	6351	#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /!< 0x00000008 /
	6352	#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /!< 0x00000010 /
	6353	#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /!< 0x00000020 /
	6354	#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /!< 0x00000040 /
	6355
	6356	/* Legacy defines */
	6357	#define WWDG_CR_T0 WWDG_CR_T_0
	6358	#define WWDG_CR_T1 WWDG_CR_T_1
	6359	#define WWDG_CR_T2 WWDG_CR_T_2
	6360	#define WWDG_CR_T3 WWDG_CR_T_3
	6361	#define WWDG_CR_T4 WWDG_CR_T_4
	6362	#define WWDG_CR_T5 WWDG_CR_T_5
	6363	#define WWDG_CR_T6 WWDG_CR_T_6
	6364
	6365	#define WWDG_CR_WDGA_Pos (7U)
	6366	#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /!< 0x00000080 /
	6367	#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /!< Activation bit /
	6368
	6369	/***************** Bit definition for WWDG_CFR register *****************/
	6370	#define WWDG_CFR_W_Pos (0U)
	6371	#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /!< 0x0000007F /
	6372	#define WWDG_CFR_W WWDG_CFR_W_Msk /!< W[6:0] bits (7-bit window value) /
	6373	#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /!< 0x00000001 /
	6374	#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /!< 0x00000002 /
	6375	#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /!< 0x00000004 /
	6376	#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /!< 0x00000008 /
	6377	#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /!< 0x00000010 /
	6378	#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /!< 0x00000020 /
	6379	#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /!< 0x00000040 /
	6380
	6381	/* Legacy defines */
	6382	#define WWDG_CFR_W0 WWDG_CFR_W_0
	6383	#define WWDG_CFR_W1 WWDG_CFR_W_1
	6384	#define WWDG_CFR_W2 WWDG_CFR_W_2
	6385	#define WWDG_CFR_W3 WWDG_CFR_W_3
	6386	#define WWDG_CFR_W4 WWDG_CFR_W_4
	6387	#define WWDG_CFR_W5 WWDG_CFR_W_5
	6388	#define WWDG_CFR_W6 WWDG_CFR_W_6
	6389
	6390	#define WWDG_CFR_WDGTB_Pos (7U)
	6391	#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /!< 0x00000180 /
	6392	#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /!< WDGTB[1:0] bits (Timer Base) /
	6393	#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /!< 0x00000080 /
	6394	#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /!< 0x00000100 /
	6395
	6396	/* Legacy defines */
	6397	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
	6398	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
	6399
	6400	#define WWDG_CFR_EWI_Pos (9U)
	6401	#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /!< 0x00000200 /
	6402	#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /!< Early Wakeup Interrupt /
	6403
	6404	/***************** Bit definition for WWDG_SR register ******************/
	6405	#define WWDG_SR_EWIF_Pos (0U)
	6406	#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /!< 0x00000001 /
	6407	#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /!< Early Wakeup Interrupt Flag /
	6408
	6409	/**
	6410	* @}
	6411	*/
	6412
	6413	/**
	6414	* @}
	6415	*/
	6416
	6417
	6418	/** @addtogroup Exported_macro
	6419	* @{
	6420	*/
	6421
	6422	/**************************** ADC Instances *******************************/
	6423	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
	6424
	6425	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
	6426
	6427	/**************************** COMP Instances *******************************/
	6428	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
	6429	((INSTANCE) == COMP2))
	6430
	6431	#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
	6432
	6433	#define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
	6434
	6435	#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
	6436
	6437	/**************************** CEC Instances *******************************/
	6438	#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
	6439
	6440	/**************************** CRC Instances *******************************/
	6441	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
	6442
	6443	/***************************** DAC Instances ******************************/
	6444	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
	6445
	6446	/***************************** DMA Instances ******************************/
	6447	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
	6448	((INSTANCE) == DMA1_Channel2) \|\| \
	6449	((INSTANCE) == DMA1_Channel3) \|\| \
	6450	((INSTANCE) == DMA1_Channel4) \|\| \
	6451	((INSTANCE) == DMA1_Channel5))
	6452
	6453	/**************************** GPIO Instances ******************************/
	6454	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
	6455	((INSTANCE) == GPIOB) \|\| \
	6456	((INSTANCE) == GPIOC) \|\| \
	6457	((INSTANCE) == GPIOD) \|\| \
	6458	((INSTANCE) == GPIOF))
	6459
	6460	/************************** GPIO Alternate Function Instances *************/
	6461	#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
	6462	((INSTANCE) == GPIOB))
	6463
	6464	/**************************** GPIO Lock Instances *************************/
	6465	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
	6466	((INSTANCE) == GPIOB))
	6467
	6468	/**************************** I2C Instances *******************************/
	6469	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
	6470	((INSTANCE) == I2C2))
	6471
	6472	/**************** I2C Instances : wakeup capability from stop modes *******/
	6473	#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
	6474
	6475	/**************************** I2S Instances *******************************/
	6476	#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
	6477	((INSTANCE) == SPI2))
	6478
	6479	/**************************** IWDG Instances ******************************/
	6480	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
	6481
	6482	/**************************** RTC Instances *******************************/
	6483	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
	6484
	6485	/**************************** SMBUS Instances *******************************/
	6486	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
	6487
	6488	/**************************** SPI Instances *******************************/
	6489	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
	6490	((INSTANCE) == SPI2))
	6491
	6492	/**************************** TIM Instances *******************************/
	6493	#define IS_TIM_INSTANCE(INSTANCE)\
	6494	(((INSTANCE) == TIM1) \|\| \
	6495	((INSTANCE) == TIM2) \|\| \
	6496	((INSTANCE) == TIM3) \|\| \
	6497	((INSTANCE) == TIM6) \|\| \
	6498	((INSTANCE) == TIM14) \|\| \
	6499	((INSTANCE) == TIM15) \|\| \
	6500	((INSTANCE) == TIM16) \|\| \
	6501	((INSTANCE) == TIM17))
	6502
	6503	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
	6504	(((INSTANCE) == TIM1) \|\| \
	6505	((INSTANCE) == TIM2) \|\| \
	6506	((INSTANCE) == TIM3) \|\| \
	6507	((INSTANCE) == TIM14) \|\| \
	6508	((INSTANCE) == TIM15) \|\| \
	6509	((INSTANCE) == TIM16) \|\| \
	6510	((INSTANCE) == TIM17))
	6511
	6512	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
	6513	(((INSTANCE) == TIM1) \|\| \
	6514	((INSTANCE) == TIM2) \|\| \
	6515	((INSTANCE) == TIM3) \|\| \
	6516	((INSTANCE) == TIM15))
	6517
	6518	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
	6519	(((INSTANCE) == TIM1) \|\| \
	6520	((INSTANCE) == TIM2) \|\| \
	6521	((INSTANCE) == TIM3))
	6522
	6523	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
	6524	(((INSTANCE) == TIM1) \|\| \
	6525	((INSTANCE) == TIM2) \|\| \
	6526	((INSTANCE) == TIM3))
	6527
	6528	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
	6529	(((INSTANCE) == TIM1) \|\| \
	6530	((INSTANCE) == TIM2) \|\| \
	6531	((INSTANCE) == TIM3))
	6532
	6533	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
	6534	(((INSTANCE) == TIM1) \|\| \
	6535	((INSTANCE) == TIM2) \|\| \
	6536	((INSTANCE) == TIM3))
	6537
	6538	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
	6539	(((INSTANCE) == TIM1) \|\| \
	6540	((INSTANCE) == TIM2) \|\| \
	6541	((INSTANCE) == TIM3) \|\| \
	6542	((INSTANCE) == TIM15))
	6543
	6544	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
	6545	(((INSTANCE) == TIM1) \|\| \
	6546	((INSTANCE) == TIM2) \|\| \
	6547	((INSTANCE) == TIM3) \|\| \
	6548	((INSTANCE) == TIM15))
	6549
	6550	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
	6551	(((INSTANCE) == TIM1) \|\| \
	6552	((INSTANCE) == TIM2) \|\| \
	6553	((INSTANCE) == TIM3))
	6554
	6555	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
	6556	(((INSTANCE) == TIM1) \|\| \
	6557	((INSTANCE) == TIM2) \|\| \
	6558	((INSTANCE) == TIM3))
	6559
	6560	#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
	6561	(((INSTANCE) == TIM1))
	6562
	6563	#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
	6564	(((INSTANCE) == TIM1))
	6565
	6566	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
	6567	(((INSTANCE) == TIM1) \|\| \
	6568	((INSTANCE) == TIM2) \|\| \
	6569	((INSTANCE) == TIM3))
	6570
	6571	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
	6572	(((INSTANCE) == TIM1) \|\| \
	6573	((INSTANCE) == TIM2) \|\| \
	6574	((INSTANCE) == TIM3) \|\| \
	6575	((INSTANCE) == TIM6) \|\| \
	6576	((INSTANCE) == TIM15))
	6577
	6578	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
	6579	(((INSTANCE) == TIM1) \|\| \
	6580	((INSTANCE) == TIM2) \|\| \
	6581	((INSTANCE) == TIM3) \|\| \
	6582	((INSTANCE) == TIM15))
	6583
	6584	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
	6585	((INSTANCE) == TIM2)
	6586
	6587	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
	6588	(((INSTANCE) == TIM1) \|\| \
	6589	((INSTANCE) == TIM2) \|\| \
	6590	((INSTANCE) == TIM3) \|\| \
	6591	((INSTANCE) == TIM15) \|\| \
	6592	((INSTANCE) == TIM16) \|\| \
	6593	((INSTANCE) == TIM17))
	6594
	6595	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
	6596	(((INSTANCE) == TIM1) \|\| \
	6597	((INSTANCE) == TIM15) \|\| \
	6598	((INSTANCE) == TIM16) \|\| \
	6599	((INSTANCE) == TIM17))
	6600
	6601	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
	6602	((((INSTANCE) == TIM1) && \
	6603	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
	6604	((CHANNEL) == TIM_CHANNEL_2) \|\| \
	6605	((CHANNEL) == TIM_CHANNEL_3) \|\| \
	6606	((CHANNEL) == TIM_CHANNEL_4))) \
	6607	\|\| \
	6608	(((INSTANCE) == TIM2) && \
	6609	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
	6610	((CHANNEL) == TIM_CHANNEL_2) \|\| \
	6611	((CHANNEL) == TIM_CHANNEL_3) \|\| \
	6612	((CHANNEL) == TIM_CHANNEL_4))) \
	6613	\|\| \
	6614	(((INSTANCE) == TIM3) && \
	6615	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
	6616	((CHANNEL) == TIM_CHANNEL_2) \|\| \
	6617	((CHANNEL) == TIM_CHANNEL_3) \|\| \
	6618	((CHANNEL) == TIM_CHANNEL_4))) \
	6619	\|\| \
	6620	(((INSTANCE) == TIM14) && \
	6621	(((CHANNEL) == TIM_CHANNEL_1))) \
	6622	\|\| \
	6623	(((INSTANCE) == TIM15) && \
	6624	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
	6625	((CHANNEL) == TIM_CHANNEL_2))) \
	6626	\|\| \
	6627	(((INSTANCE) == TIM16) && \
	6628	(((CHANNEL) == TIM_CHANNEL_1))) \
	6629	\|\| \
	6630	(((INSTANCE) == TIM17) && \
	6631	(((CHANNEL) == TIM_CHANNEL_1))))
	6632
	6633	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
	6634	((((INSTANCE) == TIM1) && \
	6635	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
	6636	((CHANNEL) == TIM_CHANNEL_2) \|\| \
	6637	((CHANNEL) == TIM_CHANNEL_3))) \
	6638	\|\| \
	6639	(((INSTANCE) == TIM15) && \
	6640	((CHANNEL) == TIM_CHANNEL_1)) \
	6641	\|\| \
	6642	(((INSTANCE) == TIM16) && \
	6643	((CHANNEL) == TIM_CHANNEL_1)) \
	6644	\|\| \
	6645	(((INSTANCE) == TIM17) && \
	6646	((CHANNEL) == TIM_CHANNEL_1)))
	6647
	6648	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
	6649	(((INSTANCE) == TIM1) \|\| \
	6650	((INSTANCE) == TIM2) \|\| \
	6651	((INSTANCE) == TIM3))
	6652
	6653	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
	6654	(((INSTANCE) == TIM1) \|\| \
	6655	((INSTANCE) == TIM15) \|\| \
	6656	((INSTANCE) == TIM16) \|\| \
	6657	((INSTANCE) == TIM17))
	6658
	6659	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
	6660	(((INSTANCE) == TIM1) \|\| \
	6661	((INSTANCE) == TIM2) \|\| \
	6662	((INSTANCE) == TIM3) \|\| \
	6663	((INSTANCE) == TIM14) \|\| \
	6664	((INSTANCE) == TIM15) \|\| \
	6665	((INSTANCE) == TIM16) \|\| \
	6666	((INSTANCE) == TIM17))
	6667
	6668	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
	6669	(((INSTANCE) == TIM1) \|\| \
	6670	((INSTANCE) == TIM2) \|\| \
	6671	((INSTANCE) == TIM3) \|\| \
	6672	((INSTANCE) == TIM6) \|\| \
	6673	((INSTANCE) == TIM15) \|\| \
	6674	((INSTANCE) == TIM16) \|\| \
	6675	((INSTANCE) == TIM17))
	6676
	6677	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
	6678	(((INSTANCE) == TIM1) \|\| \
	6679	((INSTANCE) == TIM2) \|\| \
	6680	((INSTANCE) == TIM3) \|\| \
	6681	((INSTANCE) == TIM15) \|\| \
	6682	((INSTANCE) == TIM16) \|\| \
	6683	((INSTANCE) == TIM17))
	6684
	6685	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
	6686	(((INSTANCE) == TIM1) \|\| \
	6687	((INSTANCE) == TIM15) \|\| \
	6688	((INSTANCE) == TIM16) \|\| \
	6689	((INSTANCE) == TIM17))
	6690
	6691	#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
	6692	((INSTANCE) == TIM14)
	6693
	6694	#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
	6695	((INSTANCE) == TIM1)
	6696
	6697	/**************************** TSC Instances *******************************/
	6698	#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
	6699
	6700	/********************* UART Instances : IRDA mode *************************/
	6701	#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
	6702
	6703	/******************* UART Instances : Smard card mode *********************/
	6704	#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
	6705
	6706	/****************** USART Instances : Synchronous mode ********************/
	6707	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
	6708	((INSTANCE) == USART2))
	6709
	6710	/****************** USART Instances : auto Baud rate detection ************/
	6711	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
	6712
	6713	/****************** UART Instances : Asynchronous mode ********************/
	6714	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
	6715	((INSTANCE) == USART2))
	6716
	6717	/****************** UART Instances : Half-Duplex mode ********************/
	6718	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
	6719	((INSTANCE) == USART2))
	6720
	6721	/**************** UART Instances : Hardware Flow control ******************/
	6722	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
	6723	((INSTANCE) == USART2))
	6724
	6725	/**************** UART Instances : LIN mode ******************/
	6726	#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
	6727
	6728	/**************** UART Instances : wakeup from stop mode ******************/
	6729	#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
	6730	/* Old macro definition maintained for legacy purpose */
	6731	#define IS_UART_WAKEUP_INSTANCE IS_UART_WAKEUP_FROMSTOP_INSTANCE
	6732
	6733	/**************** UART Instances : Driver enable detection ******************/
	6734	#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
	6735	((INSTANCE) == USART2))
	6736
	6737	/**************************** WWDG Instances ******************************/
	6738	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
	6739
	6740	/**
	6741	* @}
	6742	*/
	6743
	6744
	6745	/******************************************************************************/
	6746	/* For a painless codes migration between the STM32F0xx device product */
	6747	/* lines, the aliases defined below are put in place to overcome the */
	6748	/* differences in the interrupt handlers and IRQn definitions. */
	6749	/* No need to update developed interrupt code when moving across */
	6750	/* product lines within the same STM32F0 Family */
	6751	/******************************************************************************/
	6752
	6753	/* Aliases for __IRQn */
	6754	#define ADC1_IRQn ADC1_COMP_IRQn
	6755	#define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
	6756	#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
	6757	#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
	6758	#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
	6759	#define VDDIO2_IRQn PVD_IRQn
	6760	#define PVD_VDDIO2_IRQn PVD_IRQn
	6761	#define RCC_CRS_IRQn RCC_IRQn
	6762	#define TIM6_IRQn TIM6_DAC_IRQn
	6763
	6764
	6765	/* Aliases for __IRQHandler */
	6766	#define ADC1_IRQHandler ADC1_COMP_IRQHandler
	6767	#define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
	6768	#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
	6769	#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
	6770	#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
	6771	#define VDDIO2_IRQHandler PVD_IRQHandler
	6772	#define PVD_VDDIO2_IRQHandler PVD_IRQHandler
	6773	#define RCC_CRS_IRQHandler RCC_IRQHandler
	6774	#define TIM6_IRQHandler TIM6_DAC_IRQHandler
	6775
	6776
	6777	#ifdef __cplusplus
	6778	}
	6779	#endif /* __cplusplus */
	6780
	6781	#endif /* __STM32F051x8_H */
	6782
	6783	/**
	6784	* @}
	6785	*/
	6786
	6787	/**
	6788	* @}
	6789	*/
	6790
	6791	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/