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2024-02-24 8b51c78f1b88d94a89bb8c37ae38a54f523cb597
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8b51c7 1 /**
Q 2   ******************************************************************************
3   * @file    stm32f042x6.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
6   *          This file contains all the peripheral register's definitions, bits 
7   *          definitions and memory mapping for STM32F0xx devices.            
8   *            
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral抯 registers hardware
13   *  
14   ******************************************************************************
15   * @attention
16   *
17   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18   *
19   * Redistribution and use in source and binary forms, with or without modification,
20   * are permitted provided that the following conditions are met:
21   *   1. Redistributions of source code must retain the above copyright notice,
22   *      this list of conditions and the following disclaimer.
23   *   2. Redistributions in binary form must reproduce the above copyright notice,
24   *      this list of conditions and the following disclaimer in the documentation
25   *      and/or other materials provided with the distribution.
26   *   3. Neither the name of STMicroelectronics nor the names of its contributors
27   *      may be used to endorse or promote products derived from this software
28   *      without specific prior written permission.
29   *
30   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40   *
41   ******************************************************************************
42   */
43                                                            
44 /** @addtogroup CMSIS
45   * @{
46   */
47
48 /** @addtogroup stm32f042x6
49   * @{
50   */
51     
52 #ifndef __STM32F042x6_H
53 #define __STM32F042x6_H
54
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58
59   /** @addtogroup Configuration_section_for_CMSIS
60   * @{
61   */
62 /**
63  * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
64  */
65 #define __CM0_REV                 0 /*!< Core Revision r0p0                            */
66 #define __MPU_PRESENT             0 /*!< STM32F0xx do not provide MPU                  */
67 #define __NVIC_PRIO_BITS          2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
68 #define __Vendor_SysTickConfig    0     /*!< Set to 1 if different SysTick Config is used */
69  
70 /**
71   * @}
72   */
73    
74 /** @addtogroup Peripheral_interrupt_number_definition
75   * @{
76   */
77
78 /**
79  * @brief STM32F0xx Interrupt Number Definition, according to the selected device 
80  *        in @ref Library_configuration_section 
81  */
82
83  /*!< Interrupt Number Definition */
84 typedef enum
85 {
86 /******  Cortex-M0 Processor Exceptions Numbers **************************************************************/
87   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                        */
88   HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                                */
89   SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                                  */
90   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                                  */
91   SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                              */
92
93 /******  STM32F0 specific Interrupt Numbers ******************************************************************/
94   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
95   PVD_VDDIO2_IRQn             = 1,      /*!< PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31             */
96   RTC_IRQn                    = 2,      /*!< RTC Interrupt through EXTI Lines 17, 19 and 20                  */
97   FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                          */
98   RCC_CRS_IRQn                = 4,      /*!< RCC & CRS global Interrupt                                      */
99   EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupt                                     */
100   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupt                                     */
101   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupt                                     */
102   TSC_IRQn                    = 8,      /*!< Touch Sensing Controller Interrupts                             */
103   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                        */
104   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupt                          */
105   DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupt                          */
106   ADC1_IRQn                   = 12,     /*!< ADC1 Interrupt                                                  */
107   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupt           */
108   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                  */
109   TIM2_IRQn                   = 15,     /*!< TIM2 global Interrupt                                           */
110   TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                           */
111   TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                          */
112   TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                          */
113   TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                          */
114   I2C1_IRQn                   = 23,     /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup)      */
115   SPI1_IRQn                   = 25,     /*!< SPI1 global Interrupt                                           */
116   SPI2_IRQn                   = 26,     /*!< SPI2 global Interrupt                                           */
117   USART1_IRQn                 = 27,     /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
118   USART2_IRQn                 = 28,     /*!< USART2 global Interrupt                                         */
119   CEC_CAN_IRQn                = 30,     /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt           */
120   USB_IRQn                    = 31      /*!< USB global Interrupt  & EXTI Line18 Interrupt                   */
121 } IRQn_Type;
122
123 /**
124   * @}
125   */
126
127 #include "core_cm0.h"            /* Cortex-M0 processor and core peripherals */
128 #include "system_stm32f0xx.h"    /* STM32F0xx System Header */
129 #include <stdint.h>
130
131 /** @addtogroup Peripheral_registers_structures
132   * @{
133   */
134
135 /**
136   * @brief Analog to Digital Converter
137   */
138
139 typedef struct
140 {
141   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
142   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
143   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
144   __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
145   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
146   __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
147        uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
148        uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
149   __IO uint32_t TR;           /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
150        uint32_t RESERVED3;    /*!< Reserved,                                                      0x24 */
151   __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
152        uint32_t RESERVED4[5]; /*!< Reserved,                                                      0x2C */
153   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
154 } ADC_TypeDef;
155
156 typedef struct
157 {
158   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
159 } ADC_Common_TypeDef;
160
161 /** 
162   * @brief Controller Area Network TxMailBox
163   */
164 typedef struct
165 {
166   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
167   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
168   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
169   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
170 }CAN_TxMailBox_TypeDef;
171
172 /**
173   * @brief Controller Area Network FIFOMailBox
174   */
175 typedef struct
176 {
177   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
178   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
179   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
180   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
181 }CAN_FIFOMailBox_TypeDef;
182   
183 /**
184   * @brief Controller Area Network FilterRegister
185   */
186 typedef struct
187 {
188   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
189   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
190 }CAN_FilterRegister_TypeDef;
191
192 /**
193   * @brief Controller Area Network
194   */
195 typedef struct
196 {
197   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
198   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
199   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
200   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
201   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
202   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
203   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
204   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
205   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
206   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
207   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
208   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
209   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
210   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
211   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
212   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
213   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
214   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
215   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
216   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
217   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
218   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
219 }CAN_TypeDef;
220
221 /**
222   * @brief HDMI-CEC
223   */
224
225 typedef struct
226 {
227   __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
228   __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
229   __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
230   __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
231   __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
232   __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
233 }CEC_TypeDef;
234
235 /** 
236   * @brief CRC calculation unit
237   */
238
239 typedef struct
240 {
241   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
242   __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
243   uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
244   uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
245   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */ 
246   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
247   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
248   __IO uint32_t RESERVED3;   /*!< Reserved,                                                    0x14 */
249 } CRC_TypeDef;
250
251 /** 
252   * @brief Clock Recovery System
253   */
254 typedef struct 
255 {
256 __IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
257 __IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
258 __IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
259 __IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
260 }CRS_TypeDef;
261
262 /** 
263   * @brief Debug MCU
264   */
265
266 typedef struct
267 {
268   __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
269   __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
270   __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
271   __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
272 }DBGMCU_TypeDef;
273
274 /** 
275   * @brief DMA Controller
276   */
277
278 typedef struct
279 {
280   __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
281   __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
282   __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
283   __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
284 } DMA_Channel_TypeDef;
285
286 typedef struct
287 {
288   __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
289   __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
290 } DMA_TypeDef;
291
292 /** 
293   * @brief External Interrupt/Event Controller
294   */
295
296 typedef struct
297 {
298   __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
299   __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
300   __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
301   __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
302   __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
303   __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
304 } EXTI_TypeDef;
305
306 /** 
307   * @brief FLASH Registers
308   */
309 typedef struct
310 {
311   __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
312   __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
313   __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
314   __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
315   __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
316   __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
317   __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
318   __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
319   __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
320 } FLASH_TypeDef;
321
322 /** 
323   * @brief Option Bytes Registers
324   */
325 typedef struct
326 {
327   __IO uint16_t RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00 */
328   __IO uint16_t USER;         /*!< FLASH option byte user options,                Address offset: 0x02 */
329   __IO uint16_t DATA0;        /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
330   __IO uint16_t DATA1;        /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
331   __IO uint16_t WRP0;         /*!< FLASH option byte write protection 0,          Address offset: 0x08 */
332 } OB_TypeDef;
333
334 /** 
335   * @brief General Purpose I/O
336   */
337
338 typedef struct
339 {
340   __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
341   __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
342   __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
343   __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
344   __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
345   __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
346   __IO uint32_t BSRR;         /*!< GPIO port bit set/reset register,      Address offset: 0x1A */
347   __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
348   __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,  Address offset: 0x20-0x24 */
349   __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
350 } GPIO_TypeDef;
351
352 /** 
353   * @brief SysTem Configuration
354   */
355
356 typedef struct
357 {
358   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                           Address offset: 0x00 */
359        uint32_t RESERVED;    /*!< Reserved,                                                                  0x04 */
360   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration register,     Address offset: 0x14-0x08 */
361   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                           Address offset: 0x18 */
362 } SYSCFG_TypeDef;
363
364 /** 
365   * @brief Inter-integrated Circuit Interface
366   */
367
368 typedef struct
369 {
370   __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
371   __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
372   __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
373   __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
374   __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
375   __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
376   __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
377   __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
378   __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
379   __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
380   __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
381 } I2C_TypeDef;
382
383 /** 
384   * @brief Independent WATCHDOG
385   */
386
387 typedef struct
388 {
389   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
390   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
391   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
392   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
393   __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
394 } IWDG_TypeDef;
395
396 /** 
397   * @brief Power Control
398   */
399
400 typedef struct
401 {
402   __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
403   __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
404 } PWR_TypeDef;
405
406 /** 
407   * @brief Reset and Clock Control
408   */
409
410 typedef struct
411 {
412   __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
413   __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
414   __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
415   __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
416   __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
417   __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
418   __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
419   __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
420   __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
421   __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
422   __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
423   __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
424   __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
425   __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
426 } RCC_TypeDef;
427
428 /** 
429   * @brief Real-Time Clock
430   */
431 typedef struct
432 {
433   __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
434   __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
435   __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
436   __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
437   __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
438        uint32_t RESERVED1;  /*!< Reserved,                                                  Address offset: 0x14 */
439        uint32_t RESERVED2;  /*!< Reserved,                                                  Address offset: 0x18 */
440   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
441        uint32_t RESERVED3;  /*!< Reserved,                                                  Address offset: 0x20 */
442   __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
443   __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
444   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
445   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
446   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
447   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
448   __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
449   __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
450   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
451        uint32_t RESERVED4;  /*!< Reserved,                                                  Address offset: 0x48 */
452        uint32_t RESERVED5;  /*!< Reserved,                                                  Address offset: 0x4C */
453   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
454   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
455   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
456   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
457   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
458 } RTC_TypeDef;
459
460 /** 
461   * @brief Serial Peripheral Interface
462   */
463
464 typedef struct
465 {
466   __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
467   __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
468   __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
469   __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
470   __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
471   __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
472   __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
473   __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
474   __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
475 } SPI_TypeDef;
476
477 /** 
478   * @brief TIM
479   */
480 typedef struct
481 {
482   __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
483   __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
484   __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
485   __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
486   __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
487   __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
488   __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
489   __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
490   __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
491   __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
492   __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
493   __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
494   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
495   __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
496   __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
497   __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
498   __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
499   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
500   __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
501   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
502   __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
503 } TIM_TypeDef;
504
505 /**
506   * @brief Touch Sensing Controller (TSC)
507   */
508 typedef struct
509 {
510   __IO uint32_t CR;        /*!< TSC control register,                                     Address offset: 0x00 */
511   __IO uint32_t IER;       /*!< TSC interrupt enable register,                            Address offset: 0x04 */
512   __IO uint32_t ICR;       /*!< TSC interrupt clear register,                             Address offset: 0x08 */
513   __IO uint32_t ISR;       /*!< TSC interrupt status register,                            Address offset: 0x0C */
514   __IO uint32_t IOHCR;     /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
515        uint32_t RESERVED1; /*!< Reserved,                                                 Address offset: 0x14 */
516   __IO uint32_t IOASCR;    /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
517        uint32_t RESERVED2; /*!< Reserved,                                                 Address offset: 0x1C */
518   __IO uint32_t IOSCR;     /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
519        uint32_t RESERVED3; /*!< Reserved,                                                 Address offset: 0x24 */
520   __IO uint32_t IOCCR;     /*!< TSC I/O channel control register,                         Address offset: 0x28 */
521        uint32_t RESERVED4; /*!< Reserved,                                                 Address offset: 0x2C */
522   __IO uint32_t IOGCSR;    /*!< TSC I/O group control status register,                    Address offset: 0x30 */
523   __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
524 }TSC_TypeDef;
525
526 /** 
527   * @brief Universal Synchronous Asynchronous Receiver Transmitter
528   */
529  
530 typedef struct
531 {
532   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
533   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
534   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
535   __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
536   __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
537   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
538   __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
539   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
540   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
541   __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
542   uint16_t  RESERVED1;  /*!< Reserved, 0x26                                                 */
543   __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
544   uint16_t  RESERVED2;  /*!< Reserved, 0x2A                                                 */
545 } USART_TypeDef;
546
547 /** 
548   * @brief Universal Serial Bus Full Speed Device
549   */
550   
551 typedef struct
552 {
553   __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
554   __IO uint16_t RESERVED0;       /*!< Reserved */     
555   __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
556   __IO uint16_t RESERVED1;       /*!< Reserved */       
557   __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
558   __IO uint16_t RESERVED2;       /*!< Reserved */       
559   __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
560   __IO uint16_t RESERVED3;       /*!< Reserved */       
561   __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
562   __IO uint16_t RESERVED4;       /*!< Reserved */       
563   __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
564   __IO uint16_t RESERVED5;       /*!< Reserved */       
565   __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
566   __IO uint16_t RESERVED6;       /*!< Reserved */       
567   __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
568   __IO uint16_t RESERVED7[17];   /*!< Reserved */     
569   __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
570   __IO uint16_t RESERVED8;       /*!< Reserved */       
571   __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
572   __IO uint16_t RESERVED9;       /*!< Reserved */       
573   __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
574   __IO uint16_t RESERVEDA;       /*!< Reserved */       
575   __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
576   __IO uint16_t RESERVEDB;       /*!< Reserved */       
577   __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
578   __IO uint16_t RESERVEDC;       /*!< Reserved */       
579   __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
580   __IO uint16_t RESERVEDD;       /*!< Reserved */       
581   __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
582   __IO uint16_t RESERVEDE;       /*!< Reserved */       
583 } USB_TypeDef;
584
585 /** 
586   * @brief Window WATCHDOG
587   */
588 typedef struct
589 {
590   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
591   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
592   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
593 } WWDG_TypeDef;
594
595 /** 
596   * @}
597   */
598   
599 /** @addtogroup Peripheral_memory_map
600   * @{
601   */
602
603 #define FLASH_BASE            ((uint32_t)0x08000000U)              /*!< FLASH base address in the alias region */
604 #define FLASH_BANK1_END       ((uint32_t)0x08007FFFU) /*!< FLASH END address of bank1 */
605 #define SRAM_BASE             ((uint32_t)0x20000000U)              /*!< SRAM base address in the alias region */
606 #define PERIPH_BASE           ((uint32_t)0x40000000U)              /*!< Peripheral base address in the alias region */
607
608 /*!< Peripheral memory map */
609 #define APBPERIPH_BASE        PERIPH_BASE
610 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
611 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
612
613 /*!< APB peripherals */
614 #define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
615 #define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
616 #define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
617 #define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
618 #define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
619 #define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
620 #define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
621 #define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
622 #define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
623 #define USB_BASE              (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
624 #define USB_PMAADDR           (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
625 #define CAN_BASE              (APBPERIPH_BASE + 0x00006400)
626 #define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)
627 #define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
628 #define CEC_BASE              (APBPERIPH_BASE + 0x00007800)
629
630 #define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
631 #define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
632 #define ADC1_BASE             (APBPERIPH_BASE + 0x00012400)
633 #define ADC_BASE              (APBPERIPH_BASE + 0x00012708)
634 #define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
635 #define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
636 #define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
637 #define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
638 #define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
639 #define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
640
641 /*!< AHB peripherals */
642 #define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
643 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
644 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
645 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
646 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
647 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
648 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
649 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
650
651 #define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
652 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
653 #define OB_BASE               ((uint32_t)0x1FFFF800U)       /*!< FLASH Option Bytes base address */
654 #define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7CCU)       /*!< FLASH Size register base address */
655 #define UID_BASE              ((uint32_t)0x1FFFF7ACU)       /*!< Unique device ID register base address */
656 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
657 #define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
658
659 /*!< AHB2 peripherals */
660 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
661 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
662 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
663 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
664
665 /**
666   * @}
667   */
668   
669 /** @addtogroup Peripheral_declaration
670   * @{
671   */  
672
673 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
674 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
675 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
676 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
677 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
678 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
679 #define USART2              ((USART_TypeDef *) USART2_BASE)
680 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
681 #define CAN                 ((CAN_TypeDef *) CAN_BASE)
682 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
683 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
684 #define CEC                 ((CEC_TypeDef *) CEC_BASE)
685 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
686 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
687 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
688 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
689 #define ADC                 ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */
690 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
691 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
692 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
693 #define USART1              ((USART_TypeDef *) USART1_BASE)
694 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
695 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
696 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
697 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
698 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
699 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
700 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
701 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
702 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
703 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
704 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
705 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
706 #define OB                  ((OB_TypeDef *) OB_BASE) 
707 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
708 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
709 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
710 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
711 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
712 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
713 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
714 #define USB                 ((USB_TypeDef *) USB_BASE)
715 /**
716   * @}
717   */
718
719 /** @addtogroup Exported_constants
720   * @{
721   */
722
723   /** @addtogroup Peripheral_Registers_Bits_Definition
724   * @{
725   */
726
727 /******************************************************************************/
728 /*                         Peripheral Registers Bits Definition               */
729 /******************************************************************************/
730
731 /******************************************************************************/
732 /*                                                                            */
733 /*                      Analog to Digital Converter (ADC)                     */
734 /*                                                                            */
735 /******************************************************************************/
736
737 /*
738  * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
739  */
740 #define ADC_CHANNEL_VBAT_SUPPORT                       /*!< ADC feature available only on specific devices: ADC internal channel Vbat */
741
742 /********************  Bits definition for ADC_ISR register  ******************/
743 #define ADC_ISR_ADRDY_Pos         (0U)                                         
744 #define ADC_ISR_ADRDY_Msk         (0x1U << ADC_ISR_ADRDY_Pos)                  /*!< 0x00000001 */
745 #define ADC_ISR_ADRDY             ADC_ISR_ADRDY_Msk                            /*!< ADC ready flag */
746 #define ADC_ISR_EOSMP_Pos         (1U)                                         
747 #define ADC_ISR_EOSMP_Msk         (0x1U << ADC_ISR_EOSMP_Pos)                  /*!< 0x00000002 */
748 #define ADC_ISR_EOSMP             ADC_ISR_EOSMP_Msk                            /*!< ADC group regular end of sampling flag */
749 #define ADC_ISR_EOC_Pos           (2U)                                         
750 #define ADC_ISR_EOC_Msk           (0x1U << ADC_ISR_EOC_Pos)                    /*!< 0x00000004 */
751 #define ADC_ISR_EOC               ADC_ISR_EOC_Msk                              /*!< ADC group regular end of unitary conversion flag */
752 #define ADC_ISR_EOS_Pos           (3U)                                         
753 #define ADC_ISR_EOS_Msk           (0x1U << ADC_ISR_EOS_Pos)                    /*!< 0x00000008 */
754 #define ADC_ISR_EOS               ADC_ISR_EOS_Msk                              /*!< ADC group regular end of sequence conversions flag */
755 #define ADC_ISR_OVR_Pos           (4U)                                         
756 #define ADC_ISR_OVR_Msk           (0x1U << ADC_ISR_OVR_Pos)                    /*!< 0x00000010 */
757 #define ADC_ISR_OVR               ADC_ISR_OVR_Msk                              /*!< ADC group regular overrun flag */
758 #define ADC_ISR_AWD1_Pos          (7U)                                         
759 #define ADC_ISR_AWD1_Msk          (0x1U << ADC_ISR_AWD1_Pos)                   /*!< 0x00000080 */
760 #define ADC_ISR_AWD1              ADC_ISR_AWD1_Msk                             /*!< ADC analog watchdog 1 flag */
761
762 /* Legacy defines */
763 #define ADC_ISR_AWD             (ADC_ISR_AWD1)
764 #define ADC_ISR_EOSEQ           (ADC_ISR_EOS)
765
766 /********************  Bits definition for ADC_IER register  ******************/
767 #define ADC_IER_ADRDYIE_Pos       (0U)                                         
768 #define ADC_IER_ADRDYIE_Msk       (0x1U << ADC_IER_ADRDYIE_Pos)                /*!< 0x00000001 */
769 #define ADC_IER_ADRDYIE           ADC_IER_ADRDYIE_Msk                          /*!< ADC ready interrupt */
770 #define ADC_IER_EOSMPIE_Pos       (1U)                                         
771 #define ADC_IER_EOSMPIE_Msk       (0x1U << ADC_IER_EOSMPIE_Pos)                /*!< 0x00000002 */
772 #define ADC_IER_EOSMPIE           ADC_IER_EOSMPIE_Msk                          /*!< ADC group regular end of sampling interrupt */
773 #define ADC_IER_EOCIE_Pos         (2U)                                         
774 #define ADC_IER_EOCIE_Msk         (0x1U << ADC_IER_EOCIE_Pos)                  /*!< 0x00000004 */
775 #define ADC_IER_EOCIE             ADC_IER_EOCIE_Msk                            /*!< ADC group regular end of unitary conversion interrupt */
776 #define ADC_IER_EOSIE_Pos         (3U)                                         
777 #define ADC_IER_EOSIE_Msk         (0x1U << ADC_IER_EOSIE_Pos)                  /*!< 0x00000008 */
778 #define ADC_IER_EOSIE             ADC_IER_EOSIE_Msk                            /*!< ADC group regular end of sequence conversions interrupt */
779 #define ADC_IER_OVRIE_Pos         (4U)                                         
780 #define ADC_IER_OVRIE_Msk         (0x1U << ADC_IER_OVRIE_Pos)                  /*!< 0x00000010 */
781 #define ADC_IER_OVRIE             ADC_IER_OVRIE_Msk                            /*!< ADC group regular overrun interrupt */
782 #define ADC_IER_AWD1IE_Pos        (7U)                                         
783 #define ADC_IER_AWD1IE_Msk        (0x1U << ADC_IER_AWD1IE_Pos)                 /*!< 0x00000080 */
784 #define ADC_IER_AWD1IE            ADC_IER_AWD1IE_Msk                           /*!< ADC analog watchdog 1 interrupt */
785
786 /* Legacy defines */
787 #define ADC_IER_AWDIE           (ADC_IER_AWD1IE)
788 #define ADC_IER_EOSEQIE         (ADC_IER_EOSIE)
789
790 /********************  Bits definition for ADC_CR register  *******************/
791 #define ADC_CR_ADEN_Pos           (0U)                                         
792 #define ADC_CR_ADEN_Msk           (0x1U << ADC_CR_ADEN_Pos)                    /*!< 0x00000001 */
793 #define ADC_CR_ADEN               ADC_CR_ADEN_Msk                              /*!< ADC enable */
794 #define ADC_CR_ADDIS_Pos          (1U)                                         
795 #define ADC_CR_ADDIS_Msk          (0x1U << ADC_CR_ADDIS_Pos)                   /*!< 0x00000002 */
796 #define ADC_CR_ADDIS              ADC_CR_ADDIS_Msk                             /*!< ADC disable */
797 #define ADC_CR_ADSTART_Pos        (2U)                                         
798 #define ADC_CR_ADSTART_Msk        (0x1U << ADC_CR_ADSTART_Pos)                 /*!< 0x00000004 */
799 #define ADC_CR_ADSTART            ADC_CR_ADSTART_Msk                           /*!< ADC group regular conversion start */
800 #define ADC_CR_ADSTP_Pos          (4U)                                         
801 #define ADC_CR_ADSTP_Msk          (0x1U << ADC_CR_ADSTP_Pos)                   /*!< 0x00000010 */
802 #define ADC_CR_ADSTP              ADC_CR_ADSTP_Msk                             /*!< ADC group regular conversion stop */
803 #define ADC_CR_ADCAL_Pos          (31U)                                        
804 #define ADC_CR_ADCAL_Msk          (0x1U << ADC_CR_ADCAL_Pos)                   /*!< 0x80000000 */
805 #define ADC_CR_ADCAL              ADC_CR_ADCAL_Msk                             /*!< ADC calibration */
806
807 /*******************  Bits definition for ADC_CFGR1 register  *****************/
808 #define ADC_CFGR1_DMAEN_Pos       (0U)                                         
809 #define ADC_CFGR1_DMAEN_Msk       (0x1U << ADC_CFGR1_DMAEN_Pos)                /*!< 0x00000001 */
810 #define ADC_CFGR1_DMAEN           ADC_CFGR1_DMAEN_Msk                          /*!< ADC DMA transfer enable */
811 #define ADC_CFGR1_DMACFG_Pos      (1U)                                         
812 #define ADC_CFGR1_DMACFG_Msk      (0x1U << ADC_CFGR1_DMACFG_Pos)               /*!< 0x00000002 */
813 #define ADC_CFGR1_DMACFG          ADC_CFGR1_DMACFG_Msk                         /*!< ADC DMA transfer configuration */
814 #define ADC_CFGR1_SCANDIR_Pos     (2U)                                         
815 #define ADC_CFGR1_SCANDIR_Msk     (0x1U << ADC_CFGR1_SCANDIR_Pos)              /*!< 0x00000004 */
816 #define ADC_CFGR1_SCANDIR         ADC_CFGR1_SCANDIR_Msk                        /*!< ADC group regular sequencer scan direction */
817
818 #define ADC_CFGR1_RES_Pos         (3U)                                         
819 #define ADC_CFGR1_RES_Msk         (0x3U << ADC_CFGR1_RES_Pos)                  /*!< 0x00000018 */
820 #define ADC_CFGR1_RES             ADC_CFGR1_RES_Msk                            /*!< ADC data resolution */
821 #define ADC_CFGR1_RES_0           (0x1U << ADC_CFGR1_RES_Pos)                  /*!< 0x00000008 */
822 #define ADC_CFGR1_RES_1           (0x2U << ADC_CFGR1_RES_Pos)                  /*!< 0x00000010 */
823
824 #define ADC_CFGR1_ALIGN_Pos       (5U)                                         
825 #define ADC_CFGR1_ALIGN_Msk       (0x1U << ADC_CFGR1_ALIGN_Pos)                /*!< 0x00000020 */
826 #define ADC_CFGR1_ALIGN           ADC_CFGR1_ALIGN_Msk                          /*!< ADC data alignement */
827
828 #define ADC_CFGR1_EXTSEL_Pos      (6U)                                         
829 #define ADC_CFGR1_EXTSEL_Msk      (0x7U << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x000001C0 */
830 #define ADC_CFGR1_EXTSEL          ADC_CFGR1_EXTSEL_Msk                         /*!< ADC group regular external trigger source */
831 #define ADC_CFGR1_EXTSEL_0        (0x1U << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x00000040 */
832 #define ADC_CFGR1_EXTSEL_1        (0x2U << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x00000080 */
833 #define ADC_CFGR1_EXTSEL_2        (0x4U << ADC_CFGR1_EXTSEL_Pos)               /*!< 0x00000100 */
834
835 #define ADC_CFGR1_EXTEN_Pos       (10U)                                        
836 #define ADC_CFGR1_EXTEN_Msk       (0x3U << ADC_CFGR1_EXTEN_Pos)                /*!< 0x00000C00 */
837 #define ADC_CFGR1_EXTEN           ADC_CFGR1_EXTEN_Msk                          /*!< ADC group regular external trigger polarity */
838 #define ADC_CFGR1_EXTEN_0         (0x1U << ADC_CFGR1_EXTEN_Pos)                /*!< 0x00000400 */
839 #define ADC_CFGR1_EXTEN_1         (0x2U << ADC_CFGR1_EXTEN_Pos)                /*!< 0x00000800 */
840
841 #define ADC_CFGR1_OVRMOD_Pos      (12U)                                        
842 #define ADC_CFGR1_OVRMOD_Msk      (0x1U << ADC_CFGR1_OVRMOD_Pos)               /*!< 0x00001000 */
843 #define ADC_CFGR1_OVRMOD          ADC_CFGR1_OVRMOD_Msk                         /*!< ADC group regular overrun configuration */
844 #define ADC_CFGR1_CONT_Pos        (13U)                                        
845 #define ADC_CFGR1_CONT_Msk        (0x1U << ADC_CFGR1_CONT_Pos)                 /*!< 0x00002000 */
846 #define ADC_CFGR1_CONT            ADC_CFGR1_CONT_Msk                           /*!< ADC group regular continuous conversion mode */
847 #define ADC_CFGR1_WAIT_Pos        (14U)                                        
848 #define ADC_CFGR1_WAIT_Msk        (0x1U << ADC_CFGR1_WAIT_Pos)                 /*!< 0x00004000 */
849 #define ADC_CFGR1_WAIT            ADC_CFGR1_WAIT_Msk                           /*!< ADC low power auto wait */
850 #define ADC_CFGR1_AUTOFF_Pos      (15U)                                        
851 #define ADC_CFGR1_AUTOFF_Msk      (0x1U << ADC_CFGR1_AUTOFF_Pos)               /*!< 0x00008000 */
852 #define ADC_CFGR1_AUTOFF          ADC_CFGR1_AUTOFF_Msk                         /*!< ADC low power auto power off */
853 #define ADC_CFGR1_DISCEN_Pos      (16U)                                        
854 #define ADC_CFGR1_DISCEN_Msk      (0x1U << ADC_CFGR1_DISCEN_Pos)               /*!< 0x00010000 */
855 #define ADC_CFGR1_DISCEN          ADC_CFGR1_DISCEN_Msk                         /*!< ADC group regular sequencer discontinuous mode */
856
857 #define ADC_CFGR1_AWD1SGL_Pos     (22U)                                        
858 #define ADC_CFGR1_AWD1SGL_Msk     (0x1U << ADC_CFGR1_AWD1SGL_Pos)              /*!< 0x00400000 */
859 #define ADC_CFGR1_AWD1SGL         ADC_CFGR1_AWD1SGL_Msk                        /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
860 #define ADC_CFGR1_AWD1EN_Pos      (23U)                                        
861 #define ADC_CFGR1_AWD1EN_Msk      (0x1U << ADC_CFGR1_AWD1EN_Pos)               /*!< 0x00800000 */
862 #define ADC_CFGR1_AWD1EN          ADC_CFGR1_AWD1EN_Msk                         /*!< ADC analog watchdog 1 enable on scope ADC group regular */
863
864 #define ADC_CFGR1_AWD1CH_Pos      (26U)                                        
865 #define ADC_CFGR1_AWD1CH_Msk      (0x1FU << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x7C000000 */
866 #define ADC_CFGR1_AWD1CH          ADC_CFGR1_AWD1CH_Msk                         /*!< ADC analog watchdog 1 monitored channel selection */
867 #define ADC_CFGR1_AWD1CH_0        (0x01U << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x04000000 */
868 #define ADC_CFGR1_AWD1CH_1        (0x02U << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x08000000 */
869 #define ADC_CFGR1_AWD1CH_2        (0x04U << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x10000000 */
870 #define ADC_CFGR1_AWD1CH_3        (0x08U << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x20000000 */
871 #define ADC_CFGR1_AWD1CH_4        (0x10U << ADC_CFGR1_AWD1CH_Pos)              /*!< 0x40000000 */
872
873 /* Legacy defines */
874 #define ADC_CFGR1_AUTDLY        (ADC_CFGR1_WAIT)
875 #define ADC_CFGR1_AWDSGL        (ADC_CFGR1_AWD1SGL)
876 #define ADC_CFGR1_AWDEN         (ADC_CFGR1_AWD1EN)
877 #define ADC_CFGR1_AWDCH         (ADC_CFGR1_AWD1CH)
878 #define ADC_CFGR1_AWDCH_0       (ADC_CFGR1_AWD1CH_0)
879 #define ADC_CFGR1_AWDCH_1       (ADC_CFGR1_AWD1CH_1)
880 #define ADC_CFGR1_AWDCH_2       (ADC_CFGR1_AWD1CH_2)
881 #define ADC_CFGR1_AWDCH_3       (ADC_CFGR1_AWD1CH_3)
882 #define ADC_CFGR1_AWDCH_4       (ADC_CFGR1_AWD1CH_4)
883
884 /*******************  Bits definition for ADC_CFGR2 register  *****************/
885 #define ADC_CFGR2_CKMODE_Pos      (30U)                                        
886 #define ADC_CFGR2_CKMODE_Msk      (0x3U << ADC_CFGR2_CKMODE_Pos)               /*!< 0xC0000000 */
887 #define ADC_CFGR2_CKMODE          ADC_CFGR2_CKMODE_Msk                         /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
888 #define ADC_CFGR2_CKMODE_1        (0x2U << ADC_CFGR2_CKMODE_Pos)               /*!< 0x80000000 */
889 #define ADC_CFGR2_CKMODE_0        (0x1U << ADC_CFGR2_CKMODE_Pos)               /*!< 0x40000000 */
890
891 /* Legacy defines */
892 #define  ADC_CFGR2_JITOFFDIV4   (ADC_CFGR2_CKMODE_1)   /*!< ADC clocked by PCLK div4 */
893 #define  ADC_CFGR2_JITOFFDIV2   (ADC_CFGR2_CKMODE_0)   /*!< ADC clocked by PCLK div2 */
894
895 /******************  Bit definition for ADC_SMPR register  ********************/
896 #define ADC_SMPR_SMP_Pos          (0U)                                         
897 #define ADC_SMPR_SMP_Msk          (0x7U << ADC_SMPR_SMP_Pos)                   /*!< 0x00000007 */
898 #define ADC_SMPR_SMP              ADC_SMPR_SMP_Msk                             /*!< ADC group of channels sampling time 2 */
899 #define ADC_SMPR_SMP_0            (0x1U << ADC_SMPR_SMP_Pos)                   /*!< 0x00000001 */
900 #define ADC_SMPR_SMP_1            (0x2U << ADC_SMPR_SMP_Pos)                   /*!< 0x00000002 */
901 #define ADC_SMPR_SMP_2            (0x4U << ADC_SMPR_SMP_Pos)                   /*!< 0x00000004 */
902
903 /* Legacy defines */
904 #define  ADC_SMPR1_SMPR         (ADC_SMPR_SMP)         /*!< SMP[2:0] bits (Sampling time selection) */
905 #define  ADC_SMPR1_SMPR_0       (ADC_SMPR_SMP_0)       /*!< bit 0 */
906 #define  ADC_SMPR1_SMPR_1       (ADC_SMPR_SMP_1)       /*!< bit 1 */
907 #define  ADC_SMPR1_SMPR_2       (ADC_SMPR_SMP_2)       /*!< bit 2 */
908
909 /*******************  Bit definition for ADC_TR register  ********************/
910 #define ADC_TR1_LT1_Pos           (0U)                                         
911 #define ADC_TR1_LT1_Msk           (0xFFFU << ADC_TR1_LT1_Pos)                  /*!< 0x00000FFF */
912 #define ADC_TR1_LT1               ADC_TR1_LT1_Msk                              /*!< ADC analog watchdog 1 threshold low */
913 #define ADC_TR1_LT1_0             (0x001U << ADC_TR1_LT1_Pos)                  /*!< 0x00000001 */
914 #define ADC_TR1_LT1_1             (0x002U << ADC_TR1_LT1_Pos)                  /*!< 0x00000002 */
915 #define ADC_TR1_LT1_2             (0x004U << ADC_TR1_LT1_Pos)                  /*!< 0x00000004 */
916 #define ADC_TR1_LT1_3             (0x008U << ADC_TR1_LT1_Pos)                  /*!< 0x00000008 */
917 #define ADC_TR1_LT1_4             (0x010U << ADC_TR1_LT1_Pos)                  /*!< 0x00000010 */
918 #define ADC_TR1_LT1_5             (0x020U << ADC_TR1_LT1_Pos)                  /*!< 0x00000020 */
919 #define ADC_TR1_LT1_6             (0x040U << ADC_TR1_LT1_Pos)                  /*!< 0x00000040 */
920 #define ADC_TR1_LT1_7             (0x080U << ADC_TR1_LT1_Pos)                  /*!< 0x00000080 */
921 #define ADC_TR1_LT1_8             (0x100U << ADC_TR1_LT1_Pos)                  /*!< 0x00000100 */
922 #define ADC_TR1_LT1_9             (0x200U << ADC_TR1_LT1_Pos)                  /*!< 0x00000200 */
923 #define ADC_TR1_LT1_10            (0x400U << ADC_TR1_LT1_Pos)                  /*!< 0x00000400 */
924 #define ADC_TR1_LT1_11            (0x800U << ADC_TR1_LT1_Pos)                  /*!< 0x00000800 */
925
926 #define ADC_TR1_HT1_Pos           (16U)                                        
927 #define ADC_TR1_HT1_Msk           (0xFFFU << ADC_TR1_HT1_Pos)                  /*!< 0x0FFF0000 */
928 #define ADC_TR1_HT1               ADC_TR1_HT1_Msk                              /*!< ADC Analog watchdog 1 threshold high */
929 #define ADC_TR1_HT1_0             (0x001U << ADC_TR1_HT1_Pos)                  /*!< 0x00010000 */
930 #define ADC_TR1_HT1_1             (0x002U << ADC_TR1_HT1_Pos)                  /*!< 0x00020000 */
931 #define ADC_TR1_HT1_2             (0x004U << ADC_TR1_HT1_Pos)                  /*!< 0x00040000 */
932 #define ADC_TR1_HT1_3             (0x008U << ADC_TR1_HT1_Pos)                  /*!< 0x00080000 */
933 #define ADC_TR1_HT1_4             (0x010U << ADC_TR1_HT1_Pos)                  /*!< 0x00100000 */
934 #define ADC_TR1_HT1_5             (0x020U << ADC_TR1_HT1_Pos)                  /*!< 0x00200000 */
935 #define ADC_TR1_HT1_6             (0x040U << ADC_TR1_HT1_Pos)                  /*!< 0x00400000 */
936 #define ADC_TR1_HT1_7             (0x080U << ADC_TR1_HT1_Pos)                  /*!< 0x00800000 */
937 #define ADC_TR1_HT1_8             (0x100U << ADC_TR1_HT1_Pos)                  /*!< 0x01000000 */
938 #define ADC_TR1_HT1_9             (0x200U << ADC_TR1_HT1_Pos)                  /*!< 0x02000000 */
939 #define ADC_TR1_HT1_10            (0x400U << ADC_TR1_HT1_Pos)                  /*!< 0x04000000 */
940 #define ADC_TR1_HT1_11            (0x800U << ADC_TR1_HT1_Pos)                  /*!< 0x08000000 */
941
942 /* Legacy defines */
943 #define  ADC_TR_HT              (ADC_TR1_HT1)
944 #define  ADC_TR_LT              (ADC_TR1_LT1)
945 #define  ADC_HTR_HT             (ADC_TR1_HT1)
946 #define  ADC_LTR_LT             (ADC_TR1_LT1)
947
948 /******************  Bit definition for ADC_CHSELR register  ******************/
949 #define ADC_CHSELR_CHSEL_Pos      (0U)                                         
950 #define ADC_CHSELR_CHSEL_Msk      (0x7FFFFU << ADC_CHSELR_CHSEL_Pos)           /*!< 0x0007FFFF */
951 #define ADC_CHSELR_CHSEL          ADC_CHSELR_CHSEL_Msk                         /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
952 #define ADC_CHSELR_CHSEL18_Pos    (18U)                                        
953 #define ADC_CHSELR_CHSEL18_Msk    (0x1U << ADC_CHSELR_CHSEL18_Pos)             /*!< 0x00040000 */
954 #define ADC_CHSELR_CHSEL18        ADC_CHSELR_CHSEL18_Msk                       /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
955 #define ADC_CHSELR_CHSEL17_Pos    (17U)                                        
956 #define ADC_CHSELR_CHSEL17_Msk    (0x1U << ADC_CHSELR_CHSEL17_Pos)             /*!< 0x00020000 */
957 #define ADC_CHSELR_CHSEL17        ADC_CHSELR_CHSEL17_Msk                       /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
958 #define ADC_CHSELR_CHSEL16_Pos    (16U)                                        
959 #define ADC_CHSELR_CHSEL16_Msk    (0x1U << ADC_CHSELR_CHSEL16_Pos)             /*!< 0x00010000 */
960 #define ADC_CHSELR_CHSEL16        ADC_CHSELR_CHSEL16_Msk                       /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
961 #define ADC_CHSELR_CHSEL15_Pos    (15U)                                        
962 #define ADC_CHSELR_CHSEL15_Msk    (0x1U << ADC_CHSELR_CHSEL15_Pos)             /*!< 0x00008000 */
963 #define ADC_CHSELR_CHSEL15        ADC_CHSELR_CHSEL15_Msk                       /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
964 #define ADC_CHSELR_CHSEL14_Pos    (14U)                                        
965 #define ADC_CHSELR_CHSEL14_Msk    (0x1U << ADC_CHSELR_CHSEL14_Pos)             /*!< 0x00004000 */
966 #define ADC_CHSELR_CHSEL14        ADC_CHSELR_CHSEL14_Msk                       /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
967 #define ADC_CHSELR_CHSEL13_Pos    (13U)                                        
968 #define ADC_CHSELR_CHSEL13_Msk    (0x1U << ADC_CHSELR_CHSEL13_Pos)             /*!< 0x00002000 */
969 #define ADC_CHSELR_CHSEL13        ADC_CHSELR_CHSEL13_Msk                       /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
970 #define ADC_CHSELR_CHSEL12_Pos    (12U)                                        
971 #define ADC_CHSELR_CHSEL12_Msk    (0x1U << ADC_CHSELR_CHSEL12_Pos)             /*!< 0x00001000 */
972 #define ADC_CHSELR_CHSEL12        ADC_CHSELR_CHSEL12_Msk                       /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
973 #define ADC_CHSELR_CHSEL11_Pos    (11U)                                        
974 #define ADC_CHSELR_CHSEL11_Msk    (0x1U << ADC_CHSELR_CHSEL11_Pos)             /*!< 0x00000800 */
975 #define ADC_CHSELR_CHSEL11        ADC_CHSELR_CHSEL11_Msk                       /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
976 #define ADC_CHSELR_CHSEL10_Pos    (10U)                                        
977 #define ADC_CHSELR_CHSEL10_Msk    (0x1U << ADC_CHSELR_CHSEL10_Pos)             /*!< 0x00000400 */
978 #define ADC_CHSELR_CHSEL10        ADC_CHSELR_CHSEL10_Msk                       /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
979 #define ADC_CHSELR_CHSEL9_Pos     (9U)                                         
980 #define ADC_CHSELR_CHSEL9_Msk     (0x1U << ADC_CHSELR_CHSEL9_Pos)              /*!< 0x00000200 */
981 #define ADC_CHSELR_CHSEL9         ADC_CHSELR_CHSEL9_Msk                        /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
982 #define ADC_CHSELR_CHSEL8_Pos     (8U)                                         
983 #define ADC_CHSELR_CHSEL8_Msk     (0x1U << ADC_CHSELR_CHSEL8_Pos)              /*!< 0x00000100 */
984 #define ADC_CHSELR_CHSEL8         ADC_CHSELR_CHSEL8_Msk                        /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
985 #define ADC_CHSELR_CHSEL7_Pos     (7U)                                         
986 #define ADC_CHSELR_CHSEL7_Msk     (0x1U << ADC_CHSELR_CHSEL7_Pos)              /*!< 0x00000080 */
987 #define ADC_CHSELR_CHSEL7         ADC_CHSELR_CHSEL7_Msk                        /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
988 #define ADC_CHSELR_CHSEL6_Pos     (6U)                                         
989 #define ADC_CHSELR_CHSEL6_Msk     (0x1U << ADC_CHSELR_CHSEL6_Pos)              /*!< 0x00000040 */
990 #define ADC_CHSELR_CHSEL6         ADC_CHSELR_CHSEL6_Msk                        /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
991 #define ADC_CHSELR_CHSEL5_Pos     (5U)                                         
992 #define ADC_CHSELR_CHSEL5_Msk     (0x1U << ADC_CHSELR_CHSEL5_Pos)              /*!< 0x00000020 */
993 #define ADC_CHSELR_CHSEL5         ADC_CHSELR_CHSEL5_Msk                        /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
994 #define ADC_CHSELR_CHSEL4_Pos     (4U)                                         
995 #define ADC_CHSELR_CHSEL4_Msk     (0x1U << ADC_CHSELR_CHSEL4_Pos)              /*!< 0x00000010 */
996 #define ADC_CHSELR_CHSEL4         ADC_CHSELR_CHSEL4_Msk                        /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
997 #define ADC_CHSELR_CHSEL3_Pos     (3U)                                         
998 #define ADC_CHSELR_CHSEL3_Msk     (0x1U << ADC_CHSELR_CHSEL3_Pos)              /*!< 0x00000008 */
999 #define ADC_CHSELR_CHSEL3         ADC_CHSELR_CHSEL3_Msk                        /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
1000 #define ADC_CHSELR_CHSEL2_Pos     (2U)                                         
1001 #define ADC_CHSELR_CHSEL2_Msk     (0x1U << ADC_CHSELR_CHSEL2_Pos)              /*!< 0x00000004 */
1002 #define ADC_CHSELR_CHSEL2         ADC_CHSELR_CHSEL2_Msk                        /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
1003 #define ADC_CHSELR_CHSEL1_Pos     (1U)                                         
1004 #define ADC_CHSELR_CHSEL1_Msk     (0x1U << ADC_CHSELR_CHSEL1_Pos)              /*!< 0x00000002 */
1005 #define ADC_CHSELR_CHSEL1         ADC_CHSELR_CHSEL1_Msk                        /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
1006 #define ADC_CHSELR_CHSEL0_Pos     (0U)                                         
1007 #define ADC_CHSELR_CHSEL0_Msk     (0x1U << ADC_CHSELR_CHSEL0_Pos)              /*!< 0x00000001 */
1008 #define ADC_CHSELR_CHSEL0         ADC_CHSELR_CHSEL0_Msk                        /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
1009
1010 /********************  Bit definition for ADC_DR register  ********************/
1011 #define ADC_DR_DATA_Pos           (0U)                                         
1012 #define ADC_DR_DATA_Msk           (0xFFFFU << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
1013 #define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!< ADC group regular conversion data */
1014 #define ADC_DR_DATA_0             (0x0001U << ADC_DR_DATA_Pos)                 /*!< 0x00000001 */
1015 #define ADC_DR_DATA_1             (0x0002U << ADC_DR_DATA_Pos)                 /*!< 0x00000002 */
1016 #define ADC_DR_DATA_2             (0x0004U << ADC_DR_DATA_Pos)                 /*!< 0x00000004 */
1017 #define ADC_DR_DATA_3             (0x0008U << ADC_DR_DATA_Pos)                 /*!< 0x00000008 */
1018 #define ADC_DR_DATA_4             (0x0010U << ADC_DR_DATA_Pos)                 /*!< 0x00000010 */
1019 #define ADC_DR_DATA_5             (0x0020U << ADC_DR_DATA_Pos)                 /*!< 0x00000020 */
1020 #define ADC_DR_DATA_6             (0x0040U << ADC_DR_DATA_Pos)                 /*!< 0x00000040 */
1021 #define ADC_DR_DATA_7             (0x0080U << ADC_DR_DATA_Pos)                 /*!< 0x00000080 */
1022 #define ADC_DR_DATA_8             (0x0100U << ADC_DR_DATA_Pos)                 /*!< 0x00000100 */
1023 #define ADC_DR_DATA_9             (0x0200U << ADC_DR_DATA_Pos)                 /*!< 0x00000200 */
1024 #define ADC_DR_DATA_10            (0x0400U << ADC_DR_DATA_Pos)                 /*!< 0x00000400 */
1025 #define ADC_DR_DATA_11            (0x0800U << ADC_DR_DATA_Pos)                 /*!< 0x00000800 */
1026 #define ADC_DR_DATA_12            (0x1000U << ADC_DR_DATA_Pos)                 /*!< 0x00001000 */
1027 #define ADC_DR_DATA_13            (0x2000U << ADC_DR_DATA_Pos)                 /*!< 0x00002000 */
1028 #define ADC_DR_DATA_14            (0x4000U << ADC_DR_DATA_Pos)                 /*!< 0x00004000 */
1029 #define ADC_DR_DATA_15            (0x8000U << ADC_DR_DATA_Pos)                 /*!< 0x00008000 */
1030
1031 /*************************  ADC Common registers  *****************************/
1032 /*******************  Bit definition for ADC_CCR register  ********************/
1033 #define ADC_CCR_VREFEN_Pos        (22U)                                        
1034 #define ADC_CCR_VREFEN_Msk        (0x1U << ADC_CCR_VREFEN_Pos)                 /*!< 0x00400000 */
1035 #define ADC_CCR_VREFEN            ADC_CCR_VREFEN_Msk                           /*!< ADC internal path to VrefInt enable */
1036 #define ADC_CCR_TSEN_Pos          (23U)                                        
1037 #define ADC_CCR_TSEN_Msk          (0x1U << ADC_CCR_TSEN_Pos)                   /*!< 0x00800000 */
1038 #define ADC_CCR_TSEN              ADC_CCR_TSEN_Msk                             /*!< ADC internal path to temperature sensor enable */
1039
1040 #define ADC_CCR_VBATEN_Pos        (24U)                                        
1041 #define ADC_CCR_VBATEN_Msk        (0x1U << ADC_CCR_VBATEN_Pos)                 /*!< 0x01000000 */
1042 #define ADC_CCR_VBATEN            ADC_CCR_VBATEN_Msk                           /*!< ADC internal path to battery voltage enable */
1043
1044 /******************************************************************************/
1045 /*                                                                            */
1046 /*                   Controller Area Network (CAN )                           */
1047 /*                                                                            */
1048 /******************************************************************************/
1049 /*!<CAN control and status registers */
1050 /*******************  Bit definition for CAN_MCR register  ********************/
1051 #define CAN_MCR_INRQ_Pos       (0U)                                            
1052 #define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
1053 #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
1054 #define CAN_MCR_SLEEP_Pos      (1U)                                            
1055 #define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
1056 #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
1057 #define CAN_MCR_TXFP_Pos       (2U)                                            
1058 #define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
1059 #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
1060 #define CAN_MCR_RFLM_Pos       (3U)                                            
1061 #define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
1062 #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
1063 #define CAN_MCR_NART_Pos       (4U)                                            
1064 #define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
1065 #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
1066 #define CAN_MCR_AWUM_Pos       (5U)                                            
1067 #define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
1068 #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
1069 #define CAN_MCR_ABOM_Pos       (6U)                                            
1070 #define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
1071 #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
1072 #define CAN_MCR_TTCM_Pos       (7U)                                            
1073 #define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
1074 #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
1075 #define CAN_MCR_RESET_Pos      (15U)                                           
1076 #define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
1077 #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
1078
1079 /*******************  Bit definition for CAN_MSR register  ********************/
1080 #define CAN_MSR_INAK_Pos       (0U)                                            
1081 #define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
1082 #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
1083 #define CAN_MSR_SLAK_Pos       (1U)                                            
1084 #define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
1085 #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
1086 #define CAN_MSR_ERRI_Pos       (2U)                                            
1087 #define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
1088 #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
1089 #define CAN_MSR_WKUI_Pos       (3U)                                            
1090 #define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
1091 #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
1092 #define CAN_MSR_SLAKI_Pos      (4U)                                            
1093 #define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
1094 #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
1095 #define CAN_MSR_TXM_Pos        (8U)                                            
1096 #define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
1097 #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
1098 #define CAN_MSR_RXM_Pos        (9U)                                            
1099 #define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
1100 #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
1101 #define CAN_MSR_SAMP_Pos       (10U)                                           
1102 #define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
1103 #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
1104 #define CAN_MSR_RX_Pos         (11U)                                           
1105 #define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
1106 #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
1107
1108 /*******************  Bit definition for CAN_TSR register  ********************/
1109 #define CAN_TSR_RQCP0_Pos      (0U)                                            
1110 #define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
1111 #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
1112 #define CAN_TSR_TXOK0_Pos      (1U)                                            
1113 #define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
1114 #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
1115 #define CAN_TSR_ALST0_Pos      (2U)                                            
1116 #define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
1117 #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
1118 #define CAN_TSR_TERR0_Pos      (3U)                                            
1119 #define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
1120 #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
1121 #define CAN_TSR_ABRQ0_Pos      (7U)                                            
1122 #define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
1123 #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
1124 #define CAN_TSR_RQCP1_Pos      (8U)                                            
1125 #define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
1126 #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
1127 #define CAN_TSR_TXOK1_Pos      (9U)                                            
1128 #define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
1129 #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
1130 #define CAN_TSR_ALST1_Pos      (10U)                                           
1131 #define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
1132 #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
1133 #define CAN_TSR_TERR1_Pos      (11U)                                           
1134 #define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
1135 #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
1136 #define CAN_TSR_ABRQ1_Pos      (15U)                                           
1137 #define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
1138 #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
1139 #define CAN_TSR_RQCP2_Pos      (16U)                                           
1140 #define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
1141 #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
1142 #define CAN_TSR_TXOK2_Pos      (17U)                                           
1143 #define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
1144 #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
1145 #define CAN_TSR_ALST2_Pos      (18U)                                           
1146 #define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
1147 #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
1148 #define CAN_TSR_TERR2_Pos      (19U)                                           
1149 #define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
1150 #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
1151 #define CAN_TSR_ABRQ2_Pos      (23U)                                           
1152 #define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
1153 #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
1154 #define CAN_TSR_CODE_Pos       (24U)                                           
1155 #define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
1156 #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
1157
1158 #define CAN_TSR_TME_Pos        (26U)                                           
1159 #define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
1160 #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
1161 #define CAN_TSR_TME0_Pos       (26U)                                           
1162 #define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
1163 #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
1164 #define CAN_TSR_TME1_Pos       (27U)                                           
1165 #define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
1166 #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
1167 #define CAN_TSR_TME2_Pos       (28U)                                           
1168 #define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
1169 #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
1170
1171 #define CAN_TSR_LOW_Pos        (29U)                                           
1172 #define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
1173 #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
1174 #define CAN_TSR_LOW0_Pos       (29U)                                           
1175 #define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
1176 #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
1177 #define CAN_TSR_LOW1_Pos       (30U)                                           
1178 #define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
1179 #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
1180 #define CAN_TSR_LOW2_Pos       (31U)                                           
1181 #define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
1182 #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
1183
1184 /*******************  Bit definition for CAN_RF0R register  *******************/
1185 #define CAN_RF0R_FMP0_Pos      (0U)                                            
1186 #define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
1187 #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
1188 #define CAN_RF0R_FULL0_Pos     (3U)                                            
1189 #define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
1190 #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
1191 #define CAN_RF0R_FOVR0_Pos     (4U)                                            
1192 #define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
1193 #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
1194 #define CAN_RF0R_RFOM0_Pos     (5U)                                            
1195 #define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
1196 #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
1197
1198 /*******************  Bit definition for CAN_RF1R register  *******************/
1199 #define CAN_RF1R_FMP1_Pos      (0U)                                            
1200 #define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
1201 #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
1202 #define CAN_RF1R_FULL1_Pos     (3U)                                            
1203 #define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
1204 #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
1205 #define CAN_RF1R_FOVR1_Pos     (4U)                                            
1206 #define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
1207 #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
1208 #define CAN_RF1R_RFOM1_Pos     (5U)                                            
1209 #define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
1210 #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
1211
1212 /********************  Bit definition for CAN_IER register  *******************/
1213 #define CAN_IER_TMEIE_Pos      (0U)                                            
1214 #define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
1215 #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
1216 #define CAN_IER_FMPIE0_Pos     (1U)                                            
1217 #define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
1218 #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
1219 #define CAN_IER_FFIE0_Pos      (2U)                                            
1220 #define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
1221 #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
1222 #define CAN_IER_FOVIE0_Pos     (3U)                                            
1223 #define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
1224 #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
1225 #define CAN_IER_FMPIE1_Pos     (4U)                                            
1226 #define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
1227 #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
1228 #define CAN_IER_FFIE1_Pos      (5U)                                            
1229 #define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
1230 #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
1231 #define CAN_IER_FOVIE1_Pos     (6U)                                            
1232 #define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
1233 #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
1234 #define CAN_IER_EWGIE_Pos      (8U)                                            
1235 #define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
1236 #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
1237 #define CAN_IER_EPVIE_Pos      (9U)                                            
1238 #define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
1239 #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
1240 #define CAN_IER_BOFIE_Pos      (10U)                                           
1241 #define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
1242 #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
1243 #define CAN_IER_LECIE_Pos      (11U)                                           
1244 #define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
1245 #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
1246 #define CAN_IER_ERRIE_Pos      (15U)                                           
1247 #define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
1248 #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
1249 #define CAN_IER_WKUIE_Pos      (16U)                                           
1250 #define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
1251 #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
1252 #define CAN_IER_SLKIE_Pos      (17U)                                           
1253 #define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
1254 #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
1255
1256 /********************  Bit definition for CAN_ESR register  *******************/
1257 #define CAN_ESR_EWGF_Pos       (0U)                                            
1258 #define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
1259 #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
1260 #define CAN_ESR_EPVF_Pos       (1U)                                            
1261 #define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
1262 #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
1263 #define CAN_ESR_BOFF_Pos       (2U)                                            
1264 #define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
1265 #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
1266
1267 #define CAN_ESR_LEC_Pos        (4U)                                            
1268 #define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
1269 #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
1270 #define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
1271 #define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
1272 #define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
1273
1274 #define CAN_ESR_TEC_Pos        (16U)                                           
1275 #define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
1276 #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
1277 #define CAN_ESR_REC_Pos        (24U)                                           
1278 #define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
1279 #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
1280
1281 /*******************  Bit definition for CAN_BTR register  ********************/
1282 #define CAN_BTR_BRP_Pos        (0U)                                            
1283 #define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
1284 #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
1285 #define CAN_BTR_TS1_Pos        (16U)                                           
1286 #define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
1287 #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
1288 #define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
1289 #define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
1290 #define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
1291 #define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
1292 #define CAN_BTR_TS2_Pos        (20U)                                           
1293 #define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
1294 #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
1295 #define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
1296 #define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
1297 #define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
1298 #define CAN_BTR_SJW_Pos        (24U)                                           
1299 #define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
1300 #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
1301 #define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
1302 #define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
1303 #define CAN_BTR_LBKM_Pos       (30U)                                           
1304 #define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
1305 #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
1306 #define CAN_BTR_SILM_Pos       (31U)                                           
1307 #define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
1308 #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
1309
1310 /*!<Mailbox registers */
1311 /******************  Bit definition for CAN_TI0R register  ********************/
1312 #define CAN_TI0R_TXRQ_Pos      (0U)                                            
1313 #define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
1314 #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
1315 #define CAN_TI0R_RTR_Pos       (1U)                                            
1316 #define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
1317 #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
1318 #define CAN_TI0R_IDE_Pos       (2U)                                            
1319 #define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
1320 #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
1321 #define CAN_TI0R_EXID_Pos      (3U)                                            
1322 #define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
1323 #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
1324 #define CAN_TI0R_STID_Pos      (21U)                                           
1325 #define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
1326 #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
1327
1328 /******************  Bit definition for CAN_TDT0R register  *******************/
1329 #define CAN_TDT0R_DLC_Pos      (0U)                                            
1330 #define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
1331 #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
1332 #define CAN_TDT0R_TGT_Pos      (8U)                                            
1333 #define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
1334 #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
1335 #define CAN_TDT0R_TIME_Pos     (16U)                                           
1336 #define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
1337 #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
1338
1339 /******************  Bit definition for CAN_TDL0R register  *******************/
1340 #define CAN_TDL0R_DATA0_Pos    (0U)                                            
1341 #define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
1342 #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
1343 #define CAN_TDL0R_DATA1_Pos    (8U)                                            
1344 #define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
1345 #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
1346 #define CAN_TDL0R_DATA2_Pos    (16U)                                           
1347 #define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
1348 #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
1349 #define CAN_TDL0R_DATA3_Pos    (24U)                                           
1350 #define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
1351 #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
1352
1353 /******************  Bit definition for CAN_TDH0R register  *******************/
1354 #define CAN_TDH0R_DATA4_Pos    (0U)                                            
1355 #define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
1356 #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
1357 #define CAN_TDH0R_DATA5_Pos    (8U)                                            
1358 #define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
1359 #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
1360 #define CAN_TDH0R_DATA6_Pos    (16U)                                           
1361 #define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
1362 #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
1363 #define CAN_TDH0R_DATA7_Pos    (24U)                                           
1364 #define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
1365 #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
1366
1367 /*******************  Bit definition for CAN_TI1R register  *******************/
1368 #define CAN_TI1R_TXRQ_Pos      (0U)                                            
1369 #define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
1370 #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
1371 #define CAN_TI1R_RTR_Pos       (1U)                                            
1372 #define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
1373 #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
1374 #define CAN_TI1R_IDE_Pos       (2U)                                            
1375 #define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
1376 #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
1377 #define CAN_TI1R_EXID_Pos      (3U)                                            
1378 #define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
1379 #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
1380 #define CAN_TI1R_STID_Pos      (21U)                                           
1381 #define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
1382 #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
1383
1384 /*******************  Bit definition for CAN_TDT1R register  ******************/
1385 #define CAN_TDT1R_DLC_Pos      (0U)                                            
1386 #define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
1387 #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
1388 #define CAN_TDT1R_TGT_Pos      (8U)                                            
1389 #define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
1390 #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
1391 #define CAN_TDT1R_TIME_Pos     (16U)                                           
1392 #define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
1393 #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
1394
1395 /*******************  Bit definition for CAN_TDL1R register  ******************/
1396 #define CAN_TDL1R_DATA0_Pos    (0U)                                            
1397 #define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
1398 #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
1399 #define CAN_TDL1R_DATA1_Pos    (8U)                                            
1400 #define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
1401 #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
1402 #define CAN_TDL1R_DATA2_Pos    (16U)                                           
1403 #define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
1404 #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
1405 #define CAN_TDL1R_DATA3_Pos    (24U)                                           
1406 #define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
1407 #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
1408
1409 /*******************  Bit definition for CAN_TDH1R register  ******************/
1410 #define CAN_TDH1R_DATA4_Pos    (0U)                                            
1411 #define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
1412 #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
1413 #define CAN_TDH1R_DATA5_Pos    (8U)                                            
1414 #define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
1415 #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
1416 #define CAN_TDH1R_DATA6_Pos    (16U)                                           
1417 #define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
1418 #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
1419 #define CAN_TDH1R_DATA7_Pos    (24U)                                           
1420 #define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
1421 #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
1422
1423 /*******************  Bit definition for CAN_TI2R register  *******************/
1424 #define CAN_TI2R_TXRQ_Pos      (0U)                                            
1425 #define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
1426 #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
1427 #define CAN_TI2R_RTR_Pos       (1U)                                            
1428 #define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
1429 #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
1430 #define CAN_TI2R_IDE_Pos       (2U)                                            
1431 #define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
1432 #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
1433 #define CAN_TI2R_EXID_Pos      (3U)                                            
1434 #define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
1435 #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
1436 #define CAN_TI2R_STID_Pos      (21U)                                           
1437 #define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
1438 #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
1439
1440 /*******************  Bit definition for CAN_TDT2R register  ******************/
1441 #define CAN_TDT2R_DLC_Pos      (0U)                                            
1442 #define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
1443 #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
1444 #define CAN_TDT2R_TGT_Pos      (8U)                                            
1445 #define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
1446 #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
1447 #define CAN_TDT2R_TIME_Pos     (16U)                                           
1448 #define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
1449 #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
1450
1451 /*******************  Bit definition for CAN_TDL2R register  ******************/
1452 #define CAN_TDL2R_DATA0_Pos    (0U)                                            
1453 #define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
1454 #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
1455 #define CAN_TDL2R_DATA1_Pos    (8U)                                            
1456 #define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
1457 #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
1458 #define CAN_TDL2R_DATA2_Pos    (16U)                                           
1459 #define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
1460 #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
1461 #define CAN_TDL2R_DATA3_Pos    (24U)                                           
1462 #define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
1463 #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
1464
1465 /*******************  Bit definition for CAN_TDH2R register  ******************/
1466 #define CAN_TDH2R_DATA4_Pos    (0U)                                            
1467 #define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
1468 #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
1469 #define CAN_TDH2R_DATA5_Pos    (8U)                                            
1470 #define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
1471 #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
1472 #define CAN_TDH2R_DATA6_Pos    (16U)                                           
1473 #define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
1474 #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
1475 #define CAN_TDH2R_DATA7_Pos    (24U)                                           
1476 #define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
1477 #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
1478
1479 /*******************  Bit definition for CAN_RI0R register  *******************/
1480 #define CAN_RI0R_RTR_Pos       (1U)                                            
1481 #define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
1482 #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
1483 #define CAN_RI0R_IDE_Pos       (2U)                                            
1484 #define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
1485 #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
1486 #define CAN_RI0R_EXID_Pos      (3U)                                            
1487 #define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
1488 #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
1489 #define CAN_RI0R_STID_Pos      (21U)                                           
1490 #define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
1491 #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
1492
1493 /*******************  Bit definition for CAN_RDT0R register  ******************/
1494 #define CAN_RDT0R_DLC_Pos      (0U)                                            
1495 #define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
1496 #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
1497 #define CAN_RDT0R_FMI_Pos      (8U)                                            
1498 #define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
1499 #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
1500 #define CAN_RDT0R_TIME_Pos     (16U)                                           
1501 #define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
1502 #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
1503
1504 /*******************  Bit definition for CAN_RDL0R register  ******************/
1505 #define CAN_RDL0R_DATA0_Pos    (0U)                                            
1506 #define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
1507 #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
1508 #define CAN_RDL0R_DATA1_Pos    (8U)                                            
1509 #define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
1510 #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
1511 #define CAN_RDL0R_DATA2_Pos    (16U)                                           
1512 #define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
1513 #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
1514 #define CAN_RDL0R_DATA3_Pos    (24U)                                           
1515 #define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
1516 #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
1517
1518 /*******************  Bit definition for CAN_RDH0R register  ******************/
1519 #define CAN_RDH0R_DATA4_Pos    (0U)                                            
1520 #define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
1521 #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
1522 #define CAN_RDH0R_DATA5_Pos    (8U)                                            
1523 #define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
1524 #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
1525 #define CAN_RDH0R_DATA6_Pos    (16U)                                           
1526 #define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
1527 #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
1528 #define CAN_RDH0R_DATA7_Pos    (24U)                                           
1529 #define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
1530 #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
1531
1532 /*******************  Bit definition for CAN_RI1R register  *******************/
1533 #define CAN_RI1R_RTR_Pos       (1U)                                            
1534 #define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
1535 #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
1536 #define CAN_RI1R_IDE_Pos       (2U)                                            
1537 #define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
1538 #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
1539 #define CAN_RI1R_EXID_Pos      (3U)                                            
1540 #define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
1541 #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
1542 #define CAN_RI1R_STID_Pos      (21U)                                           
1543 #define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
1544 #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
1545
1546 /*******************  Bit definition for CAN_RDT1R register  ******************/
1547 #define CAN_RDT1R_DLC_Pos      (0U)                                            
1548 #define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
1549 #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
1550 #define CAN_RDT1R_FMI_Pos      (8U)                                            
1551 #define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
1552 #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
1553 #define CAN_RDT1R_TIME_Pos     (16U)                                           
1554 #define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
1555 #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
1556
1557 /*******************  Bit definition for CAN_RDL1R register  ******************/
1558 #define CAN_RDL1R_DATA0_Pos    (0U)                                            
1559 #define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
1560 #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
1561 #define CAN_RDL1R_DATA1_Pos    (8U)                                            
1562 #define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
1563 #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
1564 #define CAN_RDL1R_DATA2_Pos    (16U)                                           
1565 #define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
1566 #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
1567 #define CAN_RDL1R_DATA3_Pos    (24U)                                           
1568 #define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
1569 #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
1570
1571 /*******************  Bit definition for CAN_RDH1R register  ******************/
1572 #define CAN_RDH1R_DATA4_Pos    (0U)                                            
1573 #define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
1574 #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
1575 #define CAN_RDH1R_DATA5_Pos    (8U)                                            
1576 #define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
1577 #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
1578 #define CAN_RDH1R_DATA6_Pos    (16U)                                           
1579 #define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
1580 #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
1581 #define CAN_RDH1R_DATA7_Pos    (24U)                                           
1582 #define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
1583 #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
1584
1585 /*!<CAN filter registers */
1586 /*******************  Bit definition for CAN_FMR register  ********************/
1587 #define CAN_FMR_FINIT_Pos      (0U)                                            
1588 #define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
1589 #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
1590 #define CAN_FMR_CAN2SB_Pos     (8U)                                            
1591 #define CAN_FMR_CAN2SB_Msk     (0x3FU << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
1592 #define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
1593
1594 /*******************  Bit definition for CAN_FM1R register  *******************/
1595 #define CAN_FM1R_FBM_Pos       (0U)                                            
1596 #define CAN_FM1R_FBM_Msk       (0xFFFFFFFU << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
1597 #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
1598 #define CAN_FM1R_FBM0_Pos      (0U)                                            
1599 #define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
1600 #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
1601 #define CAN_FM1R_FBM1_Pos      (1U)                                            
1602 #define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
1603 #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
1604 #define CAN_FM1R_FBM2_Pos      (2U)                                            
1605 #define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
1606 #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
1607 #define CAN_FM1R_FBM3_Pos      (3U)                                            
1608 #define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
1609 #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
1610 #define CAN_FM1R_FBM4_Pos      (4U)                                            
1611 #define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
1612 #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
1613 #define CAN_FM1R_FBM5_Pos      (5U)                                            
1614 #define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
1615 #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
1616 #define CAN_FM1R_FBM6_Pos      (6U)                                            
1617 #define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
1618 #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
1619 #define CAN_FM1R_FBM7_Pos      (7U)                                            
1620 #define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
1621 #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
1622 #define CAN_FM1R_FBM8_Pos      (8U)                                            
1623 #define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
1624 #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
1625 #define CAN_FM1R_FBM9_Pos      (9U)                                            
1626 #define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
1627 #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
1628 #define CAN_FM1R_FBM10_Pos     (10U)                                           
1629 #define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
1630 #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
1631 #define CAN_FM1R_FBM11_Pos     (11U)                                           
1632 #define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
1633 #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
1634 #define CAN_FM1R_FBM12_Pos     (12U)                                           
1635 #define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
1636 #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
1637 #define CAN_FM1R_FBM13_Pos     (13U)                                           
1638 #define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
1639 #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
1640 #define CAN_FM1R_FBM14_Pos     (14U)                                           
1641 #define CAN_FM1R_FBM14_Msk     (0x1U << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
1642 #define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
1643 #define CAN_FM1R_FBM15_Pos     (15U)                                           
1644 #define CAN_FM1R_FBM15_Msk     (0x1U << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
1645 #define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
1646 #define CAN_FM1R_FBM16_Pos     (16U)                                           
1647 #define CAN_FM1R_FBM16_Msk     (0x1U << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
1648 #define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
1649 #define CAN_FM1R_FBM17_Pos     (17U)                                           
1650 #define CAN_FM1R_FBM17_Msk     (0x1U << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
1651 #define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
1652 #define CAN_FM1R_FBM18_Pos     (18U)                                           
1653 #define CAN_FM1R_FBM18_Msk     (0x1U << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
1654 #define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
1655 #define CAN_FM1R_FBM19_Pos     (19U)                                           
1656 #define CAN_FM1R_FBM19_Msk     (0x1U << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
1657 #define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
1658 #define CAN_FM1R_FBM20_Pos     (20U)                                           
1659 #define CAN_FM1R_FBM20_Msk     (0x1U << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
1660 #define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
1661 #define CAN_FM1R_FBM21_Pos     (21U)                                           
1662 #define CAN_FM1R_FBM21_Msk     (0x1U << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
1663 #define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
1664 #define CAN_FM1R_FBM22_Pos     (22U)                                           
1665 #define CAN_FM1R_FBM22_Msk     (0x1U << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
1666 #define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
1667 #define CAN_FM1R_FBM23_Pos     (23U)                                           
1668 #define CAN_FM1R_FBM23_Msk     (0x1U << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
1669 #define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
1670 #define CAN_FM1R_FBM24_Pos     (24U)                                           
1671 #define CAN_FM1R_FBM24_Msk     (0x1U << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
1672 #define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
1673 #define CAN_FM1R_FBM25_Pos     (25U)                                           
1674 #define CAN_FM1R_FBM25_Msk     (0x1U << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
1675 #define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
1676 #define CAN_FM1R_FBM26_Pos     (26U)                                           
1677 #define CAN_FM1R_FBM26_Msk     (0x1U << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
1678 #define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
1679 #define CAN_FM1R_FBM27_Pos     (27U)                                           
1680 #define CAN_FM1R_FBM27_Msk     (0x1U << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
1681 #define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
1682
1683 /*******************  Bit definition for CAN_FS1R register  *******************/
1684 #define CAN_FS1R_FSC_Pos       (0U)                                            
1685 #define CAN_FS1R_FSC_Msk       (0xFFFFFFFU << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
1686 #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
1687 #define CAN_FS1R_FSC0_Pos      (0U)                                            
1688 #define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
1689 #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
1690 #define CAN_FS1R_FSC1_Pos      (1U)                                            
1691 #define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
1692 #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
1693 #define CAN_FS1R_FSC2_Pos      (2U)                                            
1694 #define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
1695 #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
1696 #define CAN_FS1R_FSC3_Pos      (3U)                                            
1697 #define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
1698 #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
1699 #define CAN_FS1R_FSC4_Pos      (4U)                                            
1700 #define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
1701 #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
1702 #define CAN_FS1R_FSC5_Pos      (5U)                                            
1703 #define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
1704 #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
1705 #define CAN_FS1R_FSC6_Pos      (6U)                                            
1706 #define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
1707 #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
1708 #define CAN_FS1R_FSC7_Pos      (7U)                                            
1709 #define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
1710 #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
1711 #define CAN_FS1R_FSC8_Pos      (8U)                                            
1712 #define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
1713 #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
1714 #define CAN_FS1R_FSC9_Pos      (9U)                                            
1715 #define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
1716 #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
1717 #define CAN_FS1R_FSC10_Pos     (10U)                                           
1718 #define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
1719 #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
1720 #define CAN_FS1R_FSC11_Pos     (11U)                                           
1721 #define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
1722 #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
1723 #define CAN_FS1R_FSC12_Pos     (12U)                                           
1724 #define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
1725 #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
1726 #define CAN_FS1R_FSC13_Pos     (13U)                                           
1727 #define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
1728 #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
1729 #define CAN_FS1R_FSC14_Pos     (14U)                                           
1730 #define CAN_FS1R_FSC14_Msk     (0x1U << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
1731 #define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
1732 #define CAN_FS1R_FSC15_Pos     (15U)                                           
1733 #define CAN_FS1R_FSC15_Msk     (0x1U << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
1734 #define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
1735 #define CAN_FS1R_FSC16_Pos     (16U)                                           
1736 #define CAN_FS1R_FSC16_Msk     (0x1U << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
1737 #define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
1738 #define CAN_FS1R_FSC17_Pos     (17U)                                           
1739 #define CAN_FS1R_FSC17_Msk     (0x1U << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
1740 #define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
1741 #define CAN_FS1R_FSC18_Pos     (18U)                                           
1742 #define CAN_FS1R_FSC18_Msk     (0x1U << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
1743 #define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
1744 #define CAN_FS1R_FSC19_Pos     (19U)                                           
1745 #define CAN_FS1R_FSC19_Msk     (0x1U << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
1746 #define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
1747 #define CAN_FS1R_FSC20_Pos     (20U)                                           
1748 #define CAN_FS1R_FSC20_Msk     (0x1U << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
1749 #define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
1750 #define CAN_FS1R_FSC21_Pos     (21U)                                           
1751 #define CAN_FS1R_FSC21_Msk     (0x1U << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
1752 #define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
1753 #define CAN_FS1R_FSC22_Pos     (22U)                                           
1754 #define CAN_FS1R_FSC22_Msk     (0x1U << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
1755 #define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
1756 #define CAN_FS1R_FSC23_Pos     (23U)                                           
1757 #define CAN_FS1R_FSC23_Msk     (0x1U << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
1758 #define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
1759 #define CAN_FS1R_FSC24_Pos     (24U)                                           
1760 #define CAN_FS1R_FSC24_Msk     (0x1U << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
1761 #define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
1762 #define CAN_FS1R_FSC25_Pos     (25U)                                           
1763 #define CAN_FS1R_FSC25_Msk     (0x1U << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
1764 #define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
1765 #define CAN_FS1R_FSC26_Pos     (26U)                                           
1766 #define CAN_FS1R_FSC26_Msk     (0x1U << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
1767 #define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
1768 #define CAN_FS1R_FSC27_Pos     (27U)                                           
1769 #define CAN_FS1R_FSC27_Msk     (0x1U << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
1770 #define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
1771
1772 /******************  Bit definition for CAN_FFA1R register  *******************/
1773 #define CAN_FFA1R_FFA_Pos      (0U)                                            
1774 #define CAN_FFA1R_FFA_Msk      (0xFFFFFFFU << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
1775 #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
1776 #define CAN_FFA1R_FFA0_Pos     (0U)                                            
1777 #define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
1778 #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
1779 #define CAN_FFA1R_FFA1_Pos     (1U)                                            
1780 #define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
1781 #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
1782 #define CAN_FFA1R_FFA2_Pos     (2U)                                            
1783 #define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
1784 #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
1785 #define CAN_FFA1R_FFA3_Pos     (3U)                                            
1786 #define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
1787 #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
1788 #define CAN_FFA1R_FFA4_Pos     (4U)                                            
1789 #define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
1790 #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
1791 #define CAN_FFA1R_FFA5_Pos     (5U)                                            
1792 #define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
1793 #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
1794 #define CAN_FFA1R_FFA6_Pos     (6U)                                            
1795 #define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
1796 #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
1797 #define CAN_FFA1R_FFA7_Pos     (7U)                                            
1798 #define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
1799 #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
1800 #define CAN_FFA1R_FFA8_Pos     (8U)                                            
1801 #define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
1802 #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
1803 #define CAN_FFA1R_FFA9_Pos     (9U)                                            
1804 #define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
1805 #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
1806 #define CAN_FFA1R_FFA10_Pos    (10U)                                           
1807 #define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
1808 #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
1809 #define CAN_FFA1R_FFA11_Pos    (11U)                                           
1810 #define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
1811 #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
1812 #define CAN_FFA1R_FFA12_Pos    (12U)                                           
1813 #define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
1814 #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
1815 #define CAN_FFA1R_FFA13_Pos    (13U)                                           
1816 #define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
1817 #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
1818 #define CAN_FFA1R_FFA14_Pos    (14U)                                           
1819 #define CAN_FFA1R_FFA14_Msk    (0x1U << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
1820 #define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
1821 #define CAN_FFA1R_FFA15_Pos    (15U)                                           
1822 #define CAN_FFA1R_FFA15_Msk    (0x1U << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
1823 #define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
1824 #define CAN_FFA1R_FFA16_Pos    (16U)                                           
1825 #define CAN_FFA1R_FFA16_Msk    (0x1U << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
1826 #define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
1827 #define CAN_FFA1R_FFA17_Pos    (17U)                                           
1828 #define CAN_FFA1R_FFA17_Msk    (0x1U << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
1829 #define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
1830 #define CAN_FFA1R_FFA18_Pos    (18U)                                           
1831 #define CAN_FFA1R_FFA18_Msk    (0x1U << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
1832 #define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
1833 #define CAN_FFA1R_FFA19_Pos    (19U)                                           
1834 #define CAN_FFA1R_FFA19_Msk    (0x1U << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
1835 #define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
1836 #define CAN_FFA1R_FFA20_Pos    (20U)                                           
1837 #define CAN_FFA1R_FFA20_Msk    (0x1U << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
1838 #define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
1839 #define CAN_FFA1R_FFA21_Pos    (21U)                                           
1840 #define CAN_FFA1R_FFA21_Msk    (0x1U << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
1841 #define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
1842 #define CAN_FFA1R_FFA22_Pos    (22U)                                           
1843 #define CAN_FFA1R_FFA22_Msk    (0x1U << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
1844 #define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
1845 #define CAN_FFA1R_FFA23_Pos    (23U)                                           
1846 #define CAN_FFA1R_FFA23_Msk    (0x1U << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
1847 #define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
1848 #define CAN_FFA1R_FFA24_Pos    (24U)                                           
1849 #define CAN_FFA1R_FFA24_Msk    (0x1U << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
1850 #define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
1851 #define CAN_FFA1R_FFA25_Pos    (25U)                                           
1852 #define CAN_FFA1R_FFA25_Msk    (0x1U << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
1853 #define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
1854 #define CAN_FFA1R_FFA26_Pos    (26U)                                           
1855 #define CAN_FFA1R_FFA26_Msk    (0x1U << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
1856 #define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
1857 #define CAN_FFA1R_FFA27_Pos    (27U)                                           
1858 #define CAN_FFA1R_FFA27_Msk    (0x1U << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
1859 #define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
1860
1861 /*******************  Bit definition for CAN_FA1R register  *******************/
1862 #define CAN_FA1R_FACT_Pos      (0U)                                            
1863 #define CAN_FA1R_FACT_Msk      (0xFFFFFFFU << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
1864 #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
1865 #define CAN_FA1R_FACT0_Pos     (0U)                                            
1866 #define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
1867 #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
1868 #define CAN_FA1R_FACT1_Pos     (1U)                                            
1869 #define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
1870 #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
1871 #define CAN_FA1R_FACT2_Pos     (2U)                                            
1872 #define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
1873 #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
1874 #define CAN_FA1R_FACT3_Pos     (3U)                                            
1875 #define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
1876 #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
1877 #define CAN_FA1R_FACT4_Pos     (4U)                                            
1878 #define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
1879 #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
1880 #define CAN_FA1R_FACT5_Pos     (5U)                                            
1881 #define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
1882 #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
1883 #define CAN_FA1R_FACT6_Pos     (6U)                                            
1884 #define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
1885 #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
1886 #define CAN_FA1R_FACT7_Pos     (7U)                                            
1887 #define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
1888 #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
1889 #define CAN_FA1R_FACT8_Pos     (8U)                                            
1890 #define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
1891 #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
1892 #define CAN_FA1R_FACT9_Pos     (9U)                                            
1893 #define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
1894 #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
1895 #define CAN_FA1R_FACT10_Pos    (10U)                                           
1896 #define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
1897 #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
1898 #define CAN_FA1R_FACT11_Pos    (11U)                                           
1899 #define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
1900 #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
1901 #define CAN_FA1R_FACT12_Pos    (12U)                                           
1902 #define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
1903 #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
1904 #define CAN_FA1R_FACT13_Pos    (13U)                                           
1905 #define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
1906 #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
1907 #define CAN_FA1R_FACT14_Pos    (14U)                                           
1908 #define CAN_FA1R_FACT14_Msk    (0x1U << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
1909 #define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
1910 #define CAN_FA1R_FACT15_Pos    (15U)                                           
1911 #define CAN_FA1R_FACT15_Msk    (0x1U << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
1912 #define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
1913 #define CAN_FA1R_FACT16_Pos    (16U)                                           
1914 #define CAN_FA1R_FACT16_Msk    (0x1U << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
1915 #define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
1916 #define CAN_FA1R_FACT17_Pos    (17U)                                           
1917 #define CAN_FA1R_FACT17_Msk    (0x1U << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
1918 #define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
1919 #define CAN_FA1R_FACT18_Pos    (18U)                                           
1920 #define CAN_FA1R_FACT18_Msk    (0x1U << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
1921 #define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
1922 #define CAN_FA1R_FACT19_Pos    (19U)                                           
1923 #define CAN_FA1R_FACT19_Msk    (0x1U << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
1924 #define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
1925 #define CAN_FA1R_FACT20_Pos    (20U)                                           
1926 #define CAN_FA1R_FACT20_Msk    (0x1U << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
1927 #define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
1928 #define CAN_FA1R_FACT21_Pos    (21U)                                           
1929 #define CAN_FA1R_FACT21_Msk    (0x1U << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
1930 #define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
1931 #define CAN_FA1R_FACT22_Pos    (22U)                                           
1932 #define CAN_FA1R_FACT22_Msk    (0x1U << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
1933 #define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
1934 #define CAN_FA1R_FACT23_Pos    (23U)                                           
1935 #define CAN_FA1R_FACT23_Msk    (0x1U << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
1936 #define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
1937 #define CAN_FA1R_FACT24_Pos    (24U)                                           
1938 #define CAN_FA1R_FACT24_Msk    (0x1U << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
1939 #define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
1940 #define CAN_FA1R_FACT25_Pos    (25U)                                           
1941 #define CAN_FA1R_FACT25_Msk    (0x1U << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
1942 #define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
1943 #define CAN_FA1R_FACT26_Pos    (26U)                                           
1944 #define CAN_FA1R_FACT26_Msk    (0x1U << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
1945 #define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
1946 #define CAN_FA1R_FACT27_Pos    (27U)                                           
1947 #define CAN_FA1R_FACT27_Msk    (0x1U << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
1948 #define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
1949
1950 /*******************  Bit definition for CAN_F0R1 register  *******************/
1951 #define CAN_F0R1_FB0_Pos       (0U)                                            
1952 #define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
1953 #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
1954 #define CAN_F0R1_FB1_Pos       (1U)                                            
1955 #define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
1956 #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
1957 #define CAN_F0R1_FB2_Pos       (2U)                                            
1958 #define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
1959 #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
1960 #define CAN_F0R1_FB3_Pos       (3U)                                            
1961 #define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
1962 #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
1963 #define CAN_F0R1_FB4_Pos       (4U)                                            
1964 #define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
1965 #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
1966 #define CAN_F0R1_FB5_Pos       (5U)                                            
1967 #define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
1968 #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
1969 #define CAN_F0R1_FB6_Pos       (6U)                                            
1970 #define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
1971 #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
1972 #define CAN_F0R1_FB7_Pos       (7U)                                            
1973 #define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
1974 #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
1975 #define CAN_F0R1_FB8_Pos       (8U)                                            
1976 #define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
1977 #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
1978 #define CAN_F0R1_FB9_Pos       (9U)                                            
1979 #define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
1980 #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
1981 #define CAN_F0R1_FB10_Pos      (10U)                                           
1982 #define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
1983 #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
1984 #define CAN_F0R1_FB11_Pos      (11U)                                           
1985 #define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
1986 #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
1987 #define CAN_F0R1_FB12_Pos      (12U)                                           
1988 #define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
1989 #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
1990 #define CAN_F0R1_FB13_Pos      (13U)                                           
1991 #define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
1992 #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
1993 #define CAN_F0R1_FB14_Pos      (14U)                                           
1994 #define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
1995 #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
1996 #define CAN_F0R1_FB15_Pos      (15U)                                           
1997 #define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
1998 #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
1999 #define CAN_F0R1_FB16_Pos      (16U)                                           
2000 #define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
2001 #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
2002 #define CAN_F0R1_FB17_Pos      (17U)                                           
2003 #define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
2004 #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
2005 #define CAN_F0R1_FB18_Pos      (18U)                                           
2006 #define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
2007 #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
2008 #define CAN_F0R1_FB19_Pos      (19U)                                           
2009 #define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
2010 #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
2011 #define CAN_F0R1_FB20_Pos      (20U)                                           
2012 #define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
2013 #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
2014 #define CAN_F0R1_FB21_Pos      (21U)                                           
2015 #define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
2016 #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
2017 #define CAN_F0R1_FB22_Pos      (22U)                                           
2018 #define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
2019 #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
2020 #define CAN_F0R1_FB23_Pos      (23U)                                           
2021 #define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
2022 #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
2023 #define CAN_F0R1_FB24_Pos      (24U)                                           
2024 #define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
2025 #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
2026 #define CAN_F0R1_FB25_Pos      (25U)                                           
2027 #define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
2028 #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
2029 #define CAN_F0R1_FB26_Pos      (26U)                                           
2030 #define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
2031 #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
2032 #define CAN_F0R1_FB27_Pos      (27U)                                           
2033 #define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
2034 #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
2035 #define CAN_F0R1_FB28_Pos      (28U)                                           
2036 #define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
2037 #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
2038 #define CAN_F0R1_FB29_Pos      (29U)                                           
2039 #define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
2040 #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
2041 #define CAN_F0R1_FB30_Pos      (30U)                                           
2042 #define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
2043 #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
2044 #define CAN_F0R1_FB31_Pos      (31U)                                           
2045 #define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
2046 #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
2047
2048 /*******************  Bit definition for CAN_F1R1 register  *******************/
2049 #define CAN_F1R1_FB0_Pos       (0U)                                            
2050 #define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
2051 #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
2052 #define CAN_F1R1_FB1_Pos       (1U)                                            
2053 #define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
2054 #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
2055 #define CAN_F1R1_FB2_Pos       (2U)                                            
2056 #define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
2057 #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
2058 #define CAN_F1R1_FB3_Pos       (3U)                                            
2059 #define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
2060 #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
2061 #define CAN_F1R1_FB4_Pos       (4U)                                            
2062 #define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
2063 #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
2064 #define CAN_F1R1_FB5_Pos       (5U)                                            
2065 #define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
2066 #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
2067 #define CAN_F1R1_FB6_Pos       (6U)                                            
2068 #define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
2069 #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
2070 #define CAN_F1R1_FB7_Pos       (7U)                                            
2071 #define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
2072 #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
2073 #define CAN_F1R1_FB8_Pos       (8U)                                            
2074 #define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
2075 #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
2076 #define CAN_F1R1_FB9_Pos       (9U)                                            
2077 #define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
2078 #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
2079 #define CAN_F1R1_FB10_Pos      (10U)                                           
2080 #define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
2081 #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
2082 #define CAN_F1R1_FB11_Pos      (11U)                                           
2083 #define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
2084 #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
2085 #define CAN_F1R1_FB12_Pos      (12U)                                           
2086 #define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
2087 #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
2088 #define CAN_F1R1_FB13_Pos      (13U)                                           
2089 #define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
2090 #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
2091 #define CAN_F1R1_FB14_Pos      (14U)                                           
2092 #define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
2093 #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
2094 #define CAN_F1R1_FB15_Pos      (15U)                                           
2095 #define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
2096 #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
2097 #define CAN_F1R1_FB16_Pos      (16U)                                           
2098 #define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
2099 #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
2100 #define CAN_F1R1_FB17_Pos      (17U)                                           
2101 #define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
2102 #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
2103 #define CAN_F1R1_FB18_Pos      (18U)                                           
2104 #define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
2105 #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
2106 #define CAN_F1R1_FB19_Pos      (19U)                                           
2107 #define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
2108 #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
2109 #define CAN_F1R1_FB20_Pos      (20U)                                           
2110 #define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
2111 #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
2112 #define CAN_F1R1_FB21_Pos      (21U)                                           
2113 #define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
2114 #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
2115 #define CAN_F1R1_FB22_Pos      (22U)                                           
2116 #define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
2117 #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
2118 #define CAN_F1R1_FB23_Pos      (23U)                                           
2119 #define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
2120 #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
2121 #define CAN_F1R1_FB24_Pos      (24U)                                           
2122 #define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
2123 #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
2124 #define CAN_F1R1_FB25_Pos      (25U)                                           
2125 #define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
2126 #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
2127 #define CAN_F1R1_FB26_Pos      (26U)                                           
2128 #define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
2129 #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
2130 #define CAN_F1R1_FB27_Pos      (27U)                                           
2131 #define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
2132 #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
2133 #define CAN_F1R1_FB28_Pos      (28U)                                           
2134 #define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
2135 #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
2136 #define CAN_F1R1_FB29_Pos      (29U)                                           
2137 #define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
2138 #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
2139 #define CAN_F1R1_FB30_Pos      (30U)                                           
2140 #define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
2141 #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
2142 #define CAN_F1R1_FB31_Pos      (31U)                                           
2143 #define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
2144 #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
2145
2146 /*******************  Bit definition for CAN_F2R1 register  *******************/
2147 #define CAN_F2R1_FB0_Pos       (0U)                                            
2148 #define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
2149 #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
2150 #define CAN_F2R1_FB1_Pos       (1U)                                            
2151 #define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
2152 #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
2153 #define CAN_F2R1_FB2_Pos       (2U)                                            
2154 #define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
2155 #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
2156 #define CAN_F2R1_FB3_Pos       (3U)                                            
2157 #define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
2158 #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
2159 #define CAN_F2R1_FB4_Pos       (4U)                                            
2160 #define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
2161 #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
2162 #define CAN_F2R1_FB5_Pos       (5U)                                            
2163 #define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
2164 #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
2165 #define CAN_F2R1_FB6_Pos       (6U)                                            
2166 #define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
2167 #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
2168 #define CAN_F2R1_FB7_Pos       (7U)                                            
2169 #define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
2170 #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
2171 #define CAN_F2R1_FB8_Pos       (8U)                                            
2172 #define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
2173 #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
2174 #define CAN_F2R1_FB9_Pos       (9U)                                            
2175 #define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
2176 #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
2177 #define CAN_F2R1_FB10_Pos      (10U)                                           
2178 #define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
2179 #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
2180 #define CAN_F2R1_FB11_Pos      (11U)                                           
2181 #define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
2182 #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
2183 #define CAN_F2R1_FB12_Pos      (12U)                                           
2184 #define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
2185 #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
2186 #define CAN_F2R1_FB13_Pos      (13U)                                           
2187 #define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
2188 #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
2189 #define CAN_F2R1_FB14_Pos      (14U)                                           
2190 #define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
2191 #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
2192 #define CAN_F2R1_FB15_Pos      (15U)                                           
2193 #define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
2194 #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
2195 #define CAN_F2R1_FB16_Pos      (16U)                                           
2196 #define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
2197 #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
2198 #define CAN_F2R1_FB17_Pos      (17U)                                           
2199 #define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
2200 #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
2201 #define CAN_F2R1_FB18_Pos      (18U)                                           
2202 #define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
2203 #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
2204 #define CAN_F2R1_FB19_Pos      (19U)                                           
2205 #define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
2206 #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
2207 #define CAN_F2R1_FB20_Pos      (20U)                                           
2208 #define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
2209 #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
2210 #define CAN_F2R1_FB21_Pos      (21U)                                           
2211 #define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
2212 #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
2213 #define CAN_F2R1_FB22_Pos      (22U)                                           
2214 #define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
2215 #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
2216 #define CAN_F2R1_FB23_Pos      (23U)                                           
2217 #define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
2218 #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
2219 #define CAN_F2R1_FB24_Pos      (24U)                                           
2220 #define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
2221 #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
2222 #define CAN_F2R1_FB25_Pos      (25U)                                           
2223 #define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
2224 #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
2225 #define CAN_F2R1_FB26_Pos      (26U)                                           
2226 #define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
2227 #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
2228 #define CAN_F2R1_FB27_Pos      (27U)                                           
2229 #define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
2230 #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
2231 #define CAN_F2R1_FB28_Pos      (28U)                                           
2232 #define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
2233 #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
2234 #define CAN_F2R1_FB29_Pos      (29U)                                           
2235 #define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
2236 #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
2237 #define CAN_F2R1_FB30_Pos      (30U)                                           
2238 #define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
2239 #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
2240 #define CAN_F2R1_FB31_Pos      (31U)                                           
2241 #define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
2242 #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
2243
2244 /*******************  Bit definition for CAN_F3R1 register  *******************/
2245 #define CAN_F3R1_FB0_Pos       (0U)                                            
2246 #define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
2247 #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
2248 #define CAN_F3R1_FB1_Pos       (1U)                                            
2249 #define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
2250 #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
2251 #define CAN_F3R1_FB2_Pos       (2U)                                            
2252 #define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
2253 #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
2254 #define CAN_F3R1_FB3_Pos       (3U)                                            
2255 #define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
2256 #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
2257 #define CAN_F3R1_FB4_Pos       (4U)                                            
2258 #define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
2259 #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
2260 #define CAN_F3R1_FB5_Pos       (5U)                                            
2261 #define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
2262 #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
2263 #define CAN_F3R1_FB6_Pos       (6U)                                            
2264 #define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
2265 #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
2266 #define CAN_F3R1_FB7_Pos       (7U)                                            
2267 #define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
2268 #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
2269 #define CAN_F3R1_FB8_Pos       (8U)                                            
2270 #define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
2271 #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
2272 #define CAN_F3R1_FB9_Pos       (9U)                                            
2273 #define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
2274 #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
2275 #define CAN_F3R1_FB10_Pos      (10U)                                           
2276 #define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
2277 #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
2278 #define CAN_F3R1_FB11_Pos      (11U)                                           
2279 #define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
2280 #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
2281 #define CAN_F3R1_FB12_Pos      (12U)                                           
2282 #define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
2283 #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
2284 #define CAN_F3R1_FB13_Pos      (13U)                                           
2285 #define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
2286 #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
2287 #define CAN_F3R1_FB14_Pos      (14U)                                           
2288 #define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
2289 #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
2290 #define CAN_F3R1_FB15_Pos      (15U)                                           
2291 #define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
2292 #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
2293 #define CAN_F3R1_FB16_Pos      (16U)                                           
2294 #define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
2295 #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
2296 #define CAN_F3R1_FB17_Pos      (17U)                                           
2297 #define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
2298 #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
2299 #define CAN_F3R1_FB18_Pos      (18U)                                           
2300 #define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
2301 #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
2302 #define CAN_F3R1_FB19_Pos      (19U)                                           
2303 #define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
2304 #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
2305 #define CAN_F3R1_FB20_Pos      (20U)                                           
2306 #define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
2307 #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
2308 #define CAN_F3R1_FB21_Pos      (21U)                                           
2309 #define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
2310 #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
2311 #define CAN_F3R1_FB22_Pos      (22U)                                           
2312 #define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
2313 #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
2314 #define CAN_F3R1_FB23_Pos      (23U)                                           
2315 #define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
2316 #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
2317 #define CAN_F3R1_FB24_Pos      (24U)                                           
2318 #define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
2319 #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
2320 #define CAN_F3R1_FB25_Pos      (25U)                                           
2321 #define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
2322 #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
2323 #define CAN_F3R1_FB26_Pos      (26U)                                           
2324 #define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
2325 #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
2326 #define CAN_F3R1_FB27_Pos      (27U)                                           
2327 #define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
2328 #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
2329 #define CAN_F3R1_FB28_Pos      (28U)                                           
2330 #define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
2331 #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
2332 #define CAN_F3R1_FB29_Pos      (29U)                                           
2333 #define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
2334 #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
2335 #define CAN_F3R1_FB30_Pos      (30U)                                           
2336 #define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
2337 #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
2338 #define CAN_F3R1_FB31_Pos      (31U)                                           
2339 #define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
2340 #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
2341
2342 /*******************  Bit definition for CAN_F4R1 register  *******************/
2343 #define CAN_F4R1_FB0_Pos       (0U)                                            
2344 #define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
2345 #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
2346 #define CAN_F4R1_FB1_Pos       (1U)                                            
2347 #define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
2348 #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
2349 #define CAN_F4R1_FB2_Pos       (2U)                                            
2350 #define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
2351 #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
2352 #define CAN_F4R1_FB3_Pos       (3U)                                            
2353 #define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
2354 #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
2355 #define CAN_F4R1_FB4_Pos       (4U)                                            
2356 #define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
2357 #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
2358 #define CAN_F4R1_FB5_Pos       (5U)                                            
2359 #define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
2360 #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
2361 #define CAN_F4R1_FB6_Pos       (6U)                                            
2362 #define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
2363 #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
2364 #define CAN_F4R1_FB7_Pos       (7U)                                            
2365 #define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
2366 #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
2367 #define CAN_F4R1_FB8_Pos       (8U)                                            
2368 #define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
2369 #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
2370 #define CAN_F4R1_FB9_Pos       (9U)                                            
2371 #define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
2372 #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
2373 #define CAN_F4R1_FB10_Pos      (10U)                                           
2374 #define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
2375 #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
2376 #define CAN_F4R1_FB11_Pos      (11U)                                           
2377 #define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
2378 #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
2379 #define CAN_F4R1_FB12_Pos      (12U)                                           
2380 #define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
2381 #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
2382 #define CAN_F4R1_FB13_Pos      (13U)                                           
2383 #define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
2384 #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
2385 #define CAN_F4R1_FB14_Pos      (14U)                                           
2386 #define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
2387 #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
2388 #define CAN_F4R1_FB15_Pos      (15U)                                           
2389 #define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
2390 #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
2391 #define CAN_F4R1_FB16_Pos      (16U)                                           
2392 #define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
2393 #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
2394 #define CAN_F4R1_FB17_Pos      (17U)                                           
2395 #define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
2396 #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
2397 #define CAN_F4R1_FB18_Pos      (18U)                                           
2398 #define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
2399 #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
2400 #define CAN_F4R1_FB19_Pos      (19U)                                           
2401 #define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
2402 #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
2403 #define CAN_F4R1_FB20_Pos      (20U)                                           
2404 #define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
2405 #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
2406 #define CAN_F4R1_FB21_Pos      (21U)                                           
2407 #define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
2408 #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
2409 #define CAN_F4R1_FB22_Pos      (22U)                                           
2410 #define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
2411 #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
2412 #define CAN_F4R1_FB23_Pos      (23U)                                           
2413 #define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
2414 #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
2415 #define CAN_F4R1_FB24_Pos      (24U)                                           
2416 #define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
2417 #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
2418 #define CAN_F4R1_FB25_Pos      (25U)                                           
2419 #define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
2420 #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
2421 #define CAN_F4R1_FB26_Pos      (26U)                                           
2422 #define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
2423 #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
2424 #define CAN_F4R1_FB27_Pos      (27U)                                           
2425 #define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
2426 #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
2427 #define CAN_F4R1_FB28_Pos      (28U)                                           
2428 #define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
2429 #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
2430 #define CAN_F4R1_FB29_Pos      (29U)                                           
2431 #define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
2432 #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
2433 #define CAN_F4R1_FB30_Pos      (30U)                                           
2434 #define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
2435 #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
2436 #define CAN_F4R1_FB31_Pos      (31U)                                           
2437 #define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
2438 #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
2439
2440 /*******************  Bit definition for CAN_F5R1 register  *******************/
2441 #define CAN_F5R1_FB0_Pos       (0U)                                            
2442 #define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
2443 #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
2444 #define CAN_F5R1_FB1_Pos       (1U)                                            
2445 #define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
2446 #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
2447 #define CAN_F5R1_FB2_Pos       (2U)                                            
2448 #define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
2449 #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
2450 #define CAN_F5R1_FB3_Pos       (3U)                                            
2451 #define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
2452 #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
2453 #define CAN_F5R1_FB4_Pos       (4U)                                            
2454 #define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
2455 #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
2456 #define CAN_F5R1_FB5_Pos       (5U)                                            
2457 #define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
2458 #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
2459 #define CAN_F5R1_FB6_Pos       (6U)                                            
2460 #define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
2461 #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
2462 #define CAN_F5R1_FB7_Pos       (7U)                                            
2463 #define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
2464 #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
2465 #define CAN_F5R1_FB8_Pos       (8U)                                            
2466 #define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
2467 #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
2468 #define CAN_F5R1_FB9_Pos       (9U)                                            
2469 #define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
2470 #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
2471 #define CAN_F5R1_FB10_Pos      (10U)                                           
2472 #define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
2473 #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
2474 #define CAN_F5R1_FB11_Pos      (11U)                                           
2475 #define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
2476 #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
2477 #define CAN_F5R1_FB12_Pos      (12U)                                           
2478 #define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
2479 #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
2480 #define CAN_F5R1_FB13_Pos      (13U)                                           
2481 #define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
2482 #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
2483 #define CAN_F5R1_FB14_Pos      (14U)                                           
2484 #define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
2485 #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
2486 #define CAN_F5R1_FB15_Pos      (15U)                                           
2487 #define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
2488 #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
2489 #define CAN_F5R1_FB16_Pos      (16U)                                           
2490 #define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
2491 #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
2492 #define CAN_F5R1_FB17_Pos      (17U)                                           
2493 #define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
2494 #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
2495 #define CAN_F5R1_FB18_Pos      (18U)                                           
2496 #define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
2497 #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
2498 #define CAN_F5R1_FB19_Pos      (19U)                                           
2499 #define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
2500 #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
2501 #define CAN_F5R1_FB20_Pos      (20U)                                           
2502 #define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
2503 #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
2504 #define CAN_F5R1_FB21_Pos      (21U)                                           
2505 #define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
2506 #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
2507 #define CAN_F5R1_FB22_Pos      (22U)                                           
2508 #define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
2509 #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
2510 #define CAN_F5R1_FB23_Pos      (23U)                                           
2511 #define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
2512 #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
2513 #define CAN_F5R1_FB24_Pos      (24U)                                           
2514 #define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
2515 #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
2516 #define CAN_F5R1_FB25_Pos      (25U)                                           
2517 #define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
2518 #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
2519 #define CAN_F5R1_FB26_Pos      (26U)                                           
2520 #define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
2521 #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
2522 #define CAN_F5R1_FB27_Pos      (27U)                                           
2523 #define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
2524 #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
2525 #define CAN_F5R1_FB28_Pos      (28U)                                           
2526 #define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
2527 #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
2528 #define CAN_F5R1_FB29_Pos      (29U)                                           
2529 #define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
2530 #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
2531 #define CAN_F5R1_FB30_Pos      (30U)                                           
2532 #define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
2533 #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
2534 #define CAN_F5R1_FB31_Pos      (31U)                                           
2535 #define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
2536 #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
2537
2538 /*******************  Bit definition for CAN_F6R1 register  *******************/
2539 #define CAN_F6R1_FB0_Pos       (0U)                                            
2540 #define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
2541 #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
2542 #define CAN_F6R1_FB1_Pos       (1U)                                            
2543 #define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
2544 #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
2545 #define CAN_F6R1_FB2_Pos       (2U)                                            
2546 #define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
2547 #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
2548 #define CAN_F6R1_FB3_Pos       (3U)                                            
2549 #define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
2550 #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
2551 #define CAN_F6R1_FB4_Pos       (4U)                                            
2552 #define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
2553 #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
2554 #define CAN_F6R1_FB5_Pos       (5U)                                            
2555 #define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
2556 #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
2557 #define CAN_F6R1_FB6_Pos       (6U)                                            
2558 #define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
2559 #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
2560 #define CAN_F6R1_FB7_Pos       (7U)                                            
2561 #define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
2562 #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
2563 #define CAN_F6R1_FB8_Pos       (8U)                                            
2564 #define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
2565 #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
2566 #define CAN_F6R1_FB9_Pos       (9U)                                            
2567 #define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
2568 #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
2569 #define CAN_F6R1_FB10_Pos      (10U)                                           
2570 #define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
2571 #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
2572 #define CAN_F6R1_FB11_Pos      (11U)                                           
2573 #define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
2574 #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
2575 #define CAN_F6R1_FB12_Pos      (12U)                                           
2576 #define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
2577 #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
2578 #define CAN_F6R1_FB13_Pos      (13U)                                           
2579 #define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
2580 #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
2581 #define CAN_F6R1_FB14_Pos      (14U)                                           
2582 #define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
2583 #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
2584 #define CAN_F6R1_FB15_Pos      (15U)                                           
2585 #define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
2586 #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
2587 #define CAN_F6R1_FB16_Pos      (16U)                                           
2588 #define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
2589 #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
2590 #define CAN_F6R1_FB17_Pos      (17U)                                           
2591 #define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
2592 #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
2593 #define CAN_F6R1_FB18_Pos      (18U)                                           
2594 #define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
2595 #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
2596 #define CAN_F6R1_FB19_Pos      (19U)                                           
2597 #define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
2598 #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
2599 #define CAN_F6R1_FB20_Pos      (20U)                                           
2600 #define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
2601 #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
2602 #define CAN_F6R1_FB21_Pos      (21U)                                           
2603 #define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
2604 #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
2605 #define CAN_F6R1_FB22_Pos      (22U)                                           
2606 #define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
2607 #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
2608 #define CAN_F6R1_FB23_Pos      (23U)                                           
2609 #define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
2610 #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
2611 #define CAN_F6R1_FB24_Pos      (24U)                                           
2612 #define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
2613 #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
2614 #define CAN_F6R1_FB25_Pos      (25U)                                           
2615 #define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
2616 #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
2617 #define CAN_F6R1_FB26_Pos      (26U)                                           
2618 #define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
2619 #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
2620 #define CAN_F6R1_FB27_Pos      (27U)                                           
2621 #define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
2622 #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
2623 #define CAN_F6R1_FB28_Pos      (28U)                                           
2624 #define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
2625 #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
2626 #define CAN_F6R1_FB29_Pos      (29U)                                           
2627 #define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
2628 #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
2629 #define CAN_F6R1_FB30_Pos      (30U)                                           
2630 #define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
2631 #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
2632 #define CAN_F6R1_FB31_Pos      (31U)                                           
2633 #define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
2634 #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
2635
2636 /*******************  Bit definition for CAN_F7R1 register  *******************/
2637 #define CAN_F7R1_FB0_Pos       (0U)                                            
2638 #define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
2639 #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
2640 #define CAN_F7R1_FB1_Pos       (1U)                                            
2641 #define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
2642 #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
2643 #define CAN_F7R1_FB2_Pos       (2U)                                            
2644 #define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
2645 #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
2646 #define CAN_F7R1_FB3_Pos       (3U)                                            
2647 #define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
2648 #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
2649 #define CAN_F7R1_FB4_Pos       (4U)                                            
2650 #define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
2651 #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
2652 #define CAN_F7R1_FB5_Pos       (5U)                                            
2653 #define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
2654 #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
2655 #define CAN_F7R1_FB6_Pos       (6U)                                            
2656 #define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
2657 #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
2658 #define CAN_F7R1_FB7_Pos       (7U)                                            
2659 #define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
2660 #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
2661 #define CAN_F7R1_FB8_Pos       (8U)                                            
2662 #define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
2663 #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
2664 #define CAN_F7R1_FB9_Pos       (9U)                                            
2665 #define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
2666 #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
2667 #define CAN_F7R1_FB10_Pos      (10U)                                           
2668 #define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
2669 #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
2670 #define CAN_F7R1_FB11_Pos      (11U)                                           
2671 #define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
2672 #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
2673 #define CAN_F7R1_FB12_Pos      (12U)                                           
2674 #define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
2675 #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
2676 #define CAN_F7R1_FB13_Pos      (13U)                                           
2677 #define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
2678 #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
2679 #define CAN_F7R1_FB14_Pos      (14U)                                           
2680 #define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
2681 #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
2682 #define CAN_F7R1_FB15_Pos      (15U)                                           
2683 #define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
2684 #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
2685 #define CAN_F7R1_FB16_Pos      (16U)                                           
2686 #define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
2687 #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
2688 #define CAN_F7R1_FB17_Pos      (17U)                                           
2689 #define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
2690 #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
2691 #define CAN_F7R1_FB18_Pos      (18U)                                           
2692 #define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
2693 #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
2694 #define CAN_F7R1_FB19_Pos      (19U)                                           
2695 #define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
2696 #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
2697 #define CAN_F7R1_FB20_Pos      (20U)                                           
2698 #define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
2699 #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
2700 #define CAN_F7R1_FB21_Pos      (21U)                                           
2701 #define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
2702 #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
2703 #define CAN_F7R1_FB22_Pos      (22U)                                           
2704 #define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
2705 #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
2706 #define CAN_F7R1_FB23_Pos      (23U)                                           
2707 #define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
2708 #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
2709 #define CAN_F7R1_FB24_Pos      (24U)                                           
2710 #define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
2711 #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
2712 #define CAN_F7R1_FB25_Pos      (25U)                                           
2713 #define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
2714 #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
2715 #define CAN_F7R1_FB26_Pos      (26U)                                           
2716 #define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
2717 #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
2718 #define CAN_F7R1_FB27_Pos      (27U)                                           
2719 #define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
2720 #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
2721 #define CAN_F7R1_FB28_Pos      (28U)                                           
2722 #define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
2723 #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
2724 #define CAN_F7R1_FB29_Pos      (29U)                                           
2725 #define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
2726 #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
2727 #define CAN_F7R1_FB30_Pos      (30U)                                           
2728 #define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
2729 #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
2730 #define CAN_F7R1_FB31_Pos      (31U)                                           
2731 #define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
2732 #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
2733
2734 /*******************  Bit definition for CAN_F8R1 register  *******************/
2735 #define CAN_F8R1_FB0_Pos       (0U)                                            
2736 #define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
2737 #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
2738 #define CAN_F8R1_FB1_Pos       (1U)                                            
2739 #define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
2740 #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
2741 #define CAN_F8R1_FB2_Pos       (2U)                                            
2742 #define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
2743 #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
2744 #define CAN_F8R1_FB3_Pos       (3U)                                            
2745 #define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
2746 #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
2747 #define CAN_F8R1_FB4_Pos       (4U)                                            
2748 #define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
2749 #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
2750 #define CAN_F8R1_FB5_Pos       (5U)                                            
2751 #define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
2752 #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
2753 #define CAN_F8R1_FB6_Pos       (6U)                                            
2754 #define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
2755 #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
2756 #define CAN_F8R1_FB7_Pos       (7U)                                            
2757 #define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
2758 #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
2759 #define CAN_F8R1_FB8_Pos       (8U)                                            
2760 #define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
2761 #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
2762 #define CAN_F8R1_FB9_Pos       (9U)                                            
2763 #define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
2764 #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
2765 #define CAN_F8R1_FB10_Pos      (10U)                                           
2766 #define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
2767 #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
2768 #define CAN_F8R1_FB11_Pos      (11U)                                           
2769 #define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
2770 #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
2771 #define CAN_F8R1_FB12_Pos      (12U)                                           
2772 #define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
2773 #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
2774 #define CAN_F8R1_FB13_Pos      (13U)                                           
2775 #define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
2776 #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
2777 #define CAN_F8R1_FB14_Pos      (14U)                                           
2778 #define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
2779 #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
2780 #define CAN_F8R1_FB15_Pos      (15U)                                           
2781 #define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
2782 #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
2783 #define CAN_F8R1_FB16_Pos      (16U)                                           
2784 #define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
2785 #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
2786 #define CAN_F8R1_FB17_Pos      (17U)                                           
2787 #define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
2788 #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
2789 #define CAN_F8R1_FB18_Pos      (18U)                                           
2790 #define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
2791 #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
2792 #define CAN_F8R1_FB19_Pos      (19U)                                           
2793 #define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
2794 #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
2795 #define CAN_F8R1_FB20_Pos      (20U)                                           
2796 #define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
2797 #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
2798 #define CAN_F8R1_FB21_Pos      (21U)                                           
2799 #define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
2800 #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
2801 #define CAN_F8R1_FB22_Pos      (22U)                                           
2802 #define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
2803 #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
2804 #define CAN_F8R1_FB23_Pos      (23U)                                           
2805 #define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
2806 #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
2807 #define CAN_F8R1_FB24_Pos      (24U)                                           
2808 #define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
2809 #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
2810 #define CAN_F8R1_FB25_Pos      (25U)                                           
2811 #define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
2812 #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
2813 #define CAN_F8R1_FB26_Pos      (26U)                                           
2814 #define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
2815 #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
2816 #define CAN_F8R1_FB27_Pos      (27U)                                           
2817 #define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
2818 #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
2819 #define CAN_F8R1_FB28_Pos      (28U)                                           
2820 #define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
2821 #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
2822 #define CAN_F8R1_FB29_Pos      (29U)                                           
2823 #define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
2824 #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
2825 #define CAN_F8R1_FB30_Pos      (30U)                                           
2826 #define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
2827 #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
2828 #define CAN_F8R1_FB31_Pos      (31U)                                           
2829 #define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
2830 #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
2831
2832 /*******************  Bit definition for CAN_F9R1 register  *******************/
2833 #define CAN_F9R1_FB0_Pos       (0U)                                            
2834 #define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
2835 #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
2836 #define CAN_F9R1_FB1_Pos       (1U)                                            
2837 #define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
2838 #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
2839 #define CAN_F9R1_FB2_Pos       (2U)                                            
2840 #define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
2841 #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
2842 #define CAN_F9R1_FB3_Pos       (3U)                                            
2843 #define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
2844 #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
2845 #define CAN_F9R1_FB4_Pos       (4U)                                            
2846 #define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
2847 #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
2848 #define CAN_F9R1_FB5_Pos       (5U)                                            
2849 #define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
2850 #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
2851 #define CAN_F9R1_FB6_Pos       (6U)                                            
2852 #define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
2853 #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
2854 #define CAN_F9R1_FB7_Pos       (7U)                                            
2855 #define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
2856 #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
2857 #define CAN_F9R1_FB8_Pos       (8U)                                            
2858 #define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
2859 #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
2860 #define CAN_F9R1_FB9_Pos       (9U)                                            
2861 #define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
2862 #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
2863 #define CAN_F9R1_FB10_Pos      (10U)                                           
2864 #define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
2865 #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
2866 #define CAN_F9R1_FB11_Pos      (11U)                                           
2867 #define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
2868 #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
2869 #define CAN_F9R1_FB12_Pos      (12U)                                           
2870 #define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
2871 #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
2872 #define CAN_F9R1_FB13_Pos      (13U)                                           
2873 #define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
2874 #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
2875 #define CAN_F9R1_FB14_Pos      (14U)                                           
2876 #define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
2877 #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
2878 #define CAN_F9R1_FB15_Pos      (15U)                                           
2879 #define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
2880 #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
2881 #define CAN_F9R1_FB16_Pos      (16U)                                           
2882 #define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
2883 #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
2884 #define CAN_F9R1_FB17_Pos      (17U)                                           
2885 #define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
2886 #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
2887 #define CAN_F9R1_FB18_Pos      (18U)                                           
2888 #define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
2889 #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
2890 #define CAN_F9R1_FB19_Pos      (19U)                                           
2891 #define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
2892 #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
2893 #define CAN_F9R1_FB20_Pos      (20U)                                           
2894 #define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
2895 #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
2896 #define CAN_F9R1_FB21_Pos      (21U)                                           
2897 #define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
2898 #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
2899 #define CAN_F9R1_FB22_Pos      (22U)                                           
2900 #define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
2901 #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
2902 #define CAN_F9R1_FB23_Pos      (23U)                                           
2903 #define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
2904 #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
2905 #define CAN_F9R1_FB24_Pos      (24U)                                           
2906 #define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
2907 #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
2908 #define CAN_F9R1_FB25_Pos      (25U)                                           
2909 #define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
2910 #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
2911 #define CAN_F9R1_FB26_Pos      (26U)                                           
2912 #define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
2913 #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
2914 #define CAN_F9R1_FB27_Pos      (27U)                                           
2915 #define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
2916 #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
2917 #define CAN_F9R1_FB28_Pos      (28U)                                           
2918 #define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
2919 #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
2920 #define CAN_F9R1_FB29_Pos      (29U)                                           
2921 #define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
2922 #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
2923 #define CAN_F9R1_FB30_Pos      (30U)                                           
2924 #define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
2925 #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
2926 #define CAN_F9R1_FB31_Pos      (31U)                                           
2927 #define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
2928 #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
2929
2930 /*******************  Bit definition for CAN_F10R1 register  ******************/
2931 #define CAN_F10R1_FB0_Pos      (0U)                                            
2932 #define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
2933 #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
2934 #define CAN_F10R1_FB1_Pos      (1U)                                            
2935 #define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
2936 #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
2937 #define CAN_F10R1_FB2_Pos      (2U)                                            
2938 #define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
2939 #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
2940 #define CAN_F10R1_FB3_Pos      (3U)                                            
2941 #define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
2942 #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
2943 #define CAN_F10R1_FB4_Pos      (4U)                                            
2944 #define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
2945 #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
2946 #define CAN_F10R1_FB5_Pos      (5U)                                            
2947 #define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
2948 #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
2949 #define CAN_F10R1_FB6_Pos      (6U)                                            
2950 #define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
2951 #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
2952 #define CAN_F10R1_FB7_Pos      (7U)                                            
2953 #define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
2954 #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
2955 #define CAN_F10R1_FB8_Pos      (8U)                                            
2956 #define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
2957 #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
2958 #define CAN_F10R1_FB9_Pos      (9U)                                            
2959 #define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
2960 #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
2961 #define CAN_F10R1_FB10_Pos     (10U)                                           
2962 #define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
2963 #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
2964 #define CAN_F10R1_FB11_Pos     (11U)                                           
2965 #define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
2966 #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
2967 #define CAN_F10R1_FB12_Pos     (12U)                                           
2968 #define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
2969 #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
2970 #define CAN_F10R1_FB13_Pos     (13U)                                           
2971 #define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
2972 #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
2973 #define CAN_F10R1_FB14_Pos     (14U)                                           
2974 #define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
2975 #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
2976 #define CAN_F10R1_FB15_Pos     (15U)                                           
2977 #define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
2978 #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
2979 #define CAN_F10R1_FB16_Pos     (16U)                                           
2980 #define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
2981 #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
2982 #define CAN_F10R1_FB17_Pos     (17U)                                           
2983 #define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
2984 #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
2985 #define CAN_F10R1_FB18_Pos     (18U)                                           
2986 #define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
2987 #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
2988 #define CAN_F10R1_FB19_Pos     (19U)                                           
2989 #define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
2990 #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
2991 #define CAN_F10R1_FB20_Pos     (20U)                                           
2992 #define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
2993 #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
2994 #define CAN_F10R1_FB21_Pos     (21U)                                           
2995 #define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
2996 #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
2997 #define CAN_F10R1_FB22_Pos     (22U)                                           
2998 #define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
2999 #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
3000 #define CAN_F10R1_FB23_Pos     (23U)                                           
3001 #define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
3002 #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
3003 #define CAN_F10R1_FB24_Pos     (24U)                                           
3004 #define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
3005 #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
3006 #define CAN_F10R1_FB25_Pos     (25U)                                           
3007 #define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
3008 #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
3009 #define CAN_F10R1_FB26_Pos     (26U)                                           
3010 #define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
3011 #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
3012 #define CAN_F10R1_FB27_Pos     (27U)                                           
3013 #define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
3014 #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
3015 #define CAN_F10R1_FB28_Pos     (28U)                                           
3016 #define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
3017 #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
3018 #define CAN_F10R1_FB29_Pos     (29U)                                           
3019 #define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
3020 #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
3021 #define CAN_F10R1_FB30_Pos     (30U)                                           
3022 #define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
3023 #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
3024 #define CAN_F10R1_FB31_Pos     (31U)                                           
3025 #define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
3026 #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
3027
3028 /*******************  Bit definition for CAN_F11R1 register  ******************/
3029 #define CAN_F11R1_FB0_Pos      (0U)                                            
3030 #define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
3031 #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
3032 #define CAN_F11R1_FB1_Pos      (1U)                                            
3033 #define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
3034 #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
3035 #define CAN_F11R1_FB2_Pos      (2U)                                            
3036 #define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
3037 #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
3038 #define CAN_F11R1_FB3_Pos      (3U)                                            
3039 #define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
3040 #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
3041 #define CAN_F11R1_FB4_Pos      (4U)                                            
3042 #define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
3043 #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
3044 #define CAN_F11R1_FB5_Pos      (5U)                                            
3045 #define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
3046 #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
3047 #define CAN_F11R1_FB6_Pos      (6U)                                            
3048 #define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
3049 #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
3050 #define CAN_F11R1_FB7_Pos      (7U)                                            
3051 #define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
3052 #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
3053 #define CAN_F11R1_FB8_Pos      (8U)                                            
3054 #define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
3055 #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
3056 #define CAN_F11R1_FB9_Pos      (9U)                                            
3057 #define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
3058 #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
3059 #define CAN_F11R1_FB10_Pos     (10U)                                           
3060 #define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
3061 #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
3062 #define CAN_F11R1_FB11_Pos     (11U)                                           
3063 #define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
3064 #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
3065 #define CAN_F11R1_FB12_Pos     (12U)                                           
3066 #define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
3067 #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
3068 #define CAN_F11R1_FB13_Pos     (13U)                                           
3069 #define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
3070 #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
3071 #define CAN_F11R1_FB14_Pos     (14U)                                           
3072 #define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
3073 #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
3074 #define CAN_F11R1_FB15_Pos     (15U)                                           
3075 #define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
3076 #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
3077 #define CAN_F11R1_FB16_Pos     (16U)                                           
3078 #define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
3079 #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
3080 #define CAN_F11R1_FB17_Pos     (17U)                                           
3081 #define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
3082 #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
3083 #define CAN_F11R1_FB18_Pos     (18U)                                           
3084 #define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
3085 #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
3086 #define CAN_F11R1_FB19_Pos     (19U)                                           
3087 #define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
3088 #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
3089 #define CAN_F11R1_FB20_Pos     (20U)                                           
3090 #define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
3091 #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
3092 #define CAN_F11R1_FB21_Pos     (21U)                                           
3093 #define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
3094 #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
3095 #define CAN_F11R1_FB22_Pos     (22U)                                           
3096 #define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
3097 #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
3098 #define CAN_F11R1_FB23_Pos     (23U)                                           
3099 #define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
3100 #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
3101 #define CAN_F11R1_FB24_Pos     (24U)                                           
3102 #define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
3103 #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
3104 #define CAN_F11R1_FB25_Pos     (25U)                                           
3105 #define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
3106 #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
3107 #define CAN_F11R1_FB26_Pos     (26U)                                           
3108 #define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
3109 #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
3110 #define CAN_F11R1_FB27_Pos     (27U)                                           
3111 #define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
3112 #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
3113 #define CAN_F11R1_FB28_Pos     (28U)                                           
3114 #define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
3115 #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
3116 #define CAN_F11R1_FB29_Pos     (29U)                                           
3117 #define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
3118 #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
3119 #define CAN_F11R1_FB30_Pos     (30U)                                           
3120 #define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
3121 #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
3122 #define CAN_F11R1_FB31_Pos     (31U)                                           
3123 #define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
3124 #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
3125
3126 /*******************  Bit definition for CAN_F12R1 register  ******************/
3127 #define CAN_F12R1_FB0_Pos      (0U)                                            
3128 #define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
3129 #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
3130 #define CAN_F12R1_FB1_Pos      (1U)                                            
3131 #define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
3132 #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
3133 #define CAN_F12R1_FB2_Pos      (2U)                                            
3134 #define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
3135 #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
3136 #define CAN_F12R1_FB3_Pos      (3U)                                            
3137 #define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
3138 #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
3139 #define CAN_F12R1_FB4_Pos      (4U)                                            
3140 #define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
3141 #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
3142 #define CAN_F12R1_FB5_Pos      (5U)                                            
3143 #define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
3144 #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
3145 #define CAN_F12R1_FB6_Pos      (6U)                                            
3146 #define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
3147 #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
3148 #define CAN_F12R1_FB7_Pos      (7U)                                            
3149 #define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
3150 #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
3151 #define CAN_F12R1_FB8_Pos      (8U)                                            
3152 #define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
3153 #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
3154 #define CAN_F12R1_FB9_Pos      (9U)                                            
3155 #define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
3156 #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
3157 #define CAN_F12R1_FB10_Pos     (10U)                                           
3158 #define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
3159 #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
3160 #define CAN_F12R1_FB11_Pos     (11U)                                           
3161 #define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
3162 #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
3163 #define CAN_F12R1_FB12_Pos     (12U)                                           
3164 #define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
3165 #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
3166 #define CAN_F12R1_FB13_Pos     (13U)                                           
3167 #define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
3168 #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
3169 #define CAN_F12R1_FB14_Pos     (14U)                                           
3170 #define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
3171 #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
3172 #define CAN_F12R1_FB15_Pos     (15U)                                           
3173 #define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
3174 #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
3175 #define CAN_F12R1_FB16_Pos     (16U)                                           
3176 #define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
3177 #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
3178 #define CAN_F12R1_FB17_Pos     (17U)                                           
3179 #define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
3180 #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
3181 #define CAN_F12R1_FB18_Pos     (18U)                                           
3182 #define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
3183 #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
3184 #define CAN_F12R1_FB19_Pos     (19U)                                           
3185 #define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
3186 #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
3187 #define CAN_F12R1_FB20_Pos     (20U)                                           
3188 #define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
3189 #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
3190 #define CAN_F12R1_FB21_Pos     (21U)                                           
3191 #define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
3192 #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
3193 #define CAN_F12R1_FB22_Pos     (22U)                                           
3194 #define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
3195 #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
3196 #define CAN_F12R1_FB23_Pos     (23U)                                           
3197 #define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
3198 #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
3199 #define CAN_F12R1_FB24_Pos     (24U)                                           
3200 #define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
3201 #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
3202 #define CAN_F12R1_FB25_Pos     (25U)                                           
3203 #define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
3204 #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
3205 #define CAN_F12R1_FB26_Pos     (26U)                                           
3206 #define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
3207 #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
3208 #define CAN_F12R1_FB27_Pos     (27U)                                           
3209 #define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
3210 #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
3211 #define CAN_F12R1_FB28_Pos     (28U)                                           
3212 #define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
3213 #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
3214 #define CAN_F12R1_FB29_Pos     (29U)                                           
3215 #define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
3216 #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
3217 #define CAN_F12R1_FB30_Pos     (30U)                                           
3218 #define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
3219 #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
3220 #define CAN_F12R1_FB31_Pos     (31U)                                           
3221 #define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
3222 #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
3223
3224 /*******************  Bit definition for CAN_F13R1 register  ******************/
3225 #define CAN_F13R1_FB0_Pos      (0U)                                            
3226 #define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
3227 #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
3228 #define CAN_F13R1_FB1_Pos      (1U)                                            
3229 #define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
3230 #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
3231 #define CAN_F13R1_FB2_Pos      (2U)                                            
3232 #define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
3233 #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
3234 #define CAN_F13R1_FB3_Pos      (3U)                                            
3235 #define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
3236 #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
3237 #define CAN_F13R1_FB4_Pos      (4U)                                            
3238 #define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
3239 #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
3240 #define CAN_F13R1_FB5_Pos      (5U)                                            
3241 #define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
3242 #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
3243 #define CAN_F13R1_FB6_Pos      (6U)                                            
3244 #define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
3245 #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
3246 #define CAN_F13R1_FB7_Pos      (7U)                                            
3247 #define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
3248 #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
3249 #define CAN_F13R1_FB8_Pos      (8U)                                            
3250 #define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
3251 #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
3252 #define CAN_F13R1_FB9_Pos      (9U)                                            
3253 #define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
3254 #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
3255 #define CAN_F13R1_FB10_Pos     (10U)                                           
3256 #define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
3257 #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
3258 #define CAN_F13R1_FB11_Pos     (11U)                                           
3259 #define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
3260 #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
3261 #define CAN_F13R1_FB12_Pos     (12U)                                           
3262 #define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
3263 #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
3264 #define CAN_F13R1_FB13_Pos     (13U)                                           
3265 #define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
3266 #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
3267 #define CAN_F13R1_FB14_Pos     (14U)                                           
3268 #define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
3269 #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
3270 #define CAN_F13R1_FB15_Pos     (15U)                                           
3271 #define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
3272 #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
3273 #define CAN_F13R1_FB16_Pos     (16U)                                           
3274 #define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
3275 #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
3276 #define CAN_F13R1_FB17_Pos     (17U)                                           
3277 #define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
3278 #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
3279 #define CAN_F13R1_FB18_Pos     (18U)                                           
3280 #define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
3281 #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
3282 #define CAN_F13R1_FB19_Pos     (19U)                                           
3283 #define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
3284 #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
3285 #define CAN_F13R1_FB20_Pos     (20U)                                           
3286 #define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
3287 #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
3288 #define CAN_F13R1_FB21_Pos     (21U)                                           
3289 #define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
3290 #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
3291 #define CAN_F13R1_FB22_Pos     (22U)                                           
3292 #define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
3293 #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
3294 #define CAN_F13R1_FB23_Pos     (23U)                                           
3295 #define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
3296 #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
3297 #define CAN_F13R1_FB24_Pos     (24U)                                           
3298 #define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
3299 #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
3300 #define CAN_F13R1_FB25_Pos     (25U)                                           
3301 #define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
3302 #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
3303 #define CAN_F13R1_FB26_Pos     (26U)                                           
3304 #define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
3305 #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
3306 #define CAN_F13R1_FB27_Pos     (27U)                                           
3307 #define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
3308 #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
3309 #define CAN_F13R1_FB28_Pos     (28U)                                           
3310 #define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
3311 #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
3312 #define CAN_F13R1_FB29_Pos     (29U)                                           
3313 #define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
3314 #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
3315 #define CAN_F13R1_FB30_Pos     (30U)                                           
3316 #define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
3317 #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
3318 #define CAN_F13R1_FB31_Pos     (31U)                                           
3319 #define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
3320 #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
3321
3322 /*******************  Bit definition for CAN_F0R2 register  *******************/
3323 #define CAN_F0R2_FB0_Pos       (0U)                                            
3324 #define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
3325 #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
3326 #define CAN_F0R2_FB1_Pos       (1U)                                            
3327 #define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
3328 #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
3329 #define CAN_F0R2_FB2_Pos       (2U)                                            
3330 #define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
3331 #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
3332 #define CAN_F0R2_FB3_Pos       (3U)                                            
3333 #define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
3334 #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
3335 #define CAN_F0R2_FB4_Pos       (4U)                                            
3336 #define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
3337 #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
3338 #define CAN_F0R2_FB5_Pos       (5U)                                            
3339 #define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
3340 #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
3341 #define CAN_F0R2_FB6_Pos       (6U)                                            
3342 #define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
3343 #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
3344 #define CAN_F0R2_FB7_Pos       (7U)                                            
3345 #define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
3346 #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
3347 #define CAN_F0R2_FB8_Pos       (8U)                                            
3348 #define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
3349 #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
3350 #define CAN_F0R2_FB9_Pos       (9U)                                            
3351 #define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
3352 #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
3353 #define CAN_F0R2_FB10_Pos      (10U)                                           
3354 #define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
3355 #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
3356 #define CAN_F0R2_FB11_Pos      (11U)                                           
3357 #define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
3358 #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
3359 #define CAN_F0R2_FB12_Pos      (12U)                                           
3360 #define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
3361 #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
3362 #define CAN_F0R2_FB13_Pos      (13U)                                           
3363 #define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
3364 #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
3365 #define CAN_F0R2_FB14_Pos      (14U)                                           
3366 #define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
3367 #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
3368 #define CAN_F0R2_FB15_Pos      (15U)                                           
3369 #define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
3370 #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
3371 #define CAN_F0R2_FB16_Pos      (16U)                                           
3372 #define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
3373 #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
3374 #define CAN_F0R2_FB17_Pos      (17U)                                           
3375 #define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
3376 #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
3377 #define CAN_F0R2_FB18_Pos      (18U)                                           
3378 #define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
3379 #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
3380 #define CAN_F0R2_FB19_Pos      (19U)                                           
3381 #define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
3382 #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
3383 #define CAN_F0R2_FB20_Pos      (20U)                                           
3384 #define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
3385 #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
3386 #define CAN_F0R2_FB21_Pos      (21U)                                           
3387 #define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
3388 #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
3389 #define CAN_F0R2_FB22_Pos      (22U)                                           
3390 #define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
3391 #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
3392 #define CAN_F0R2_FB23_Pos      (23U)                                           
3393 #define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
3394 #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
3395 #define CAN_F0R2_FB24_Pos      (24U)                                           
3396 #define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
3397 #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
3398 #define CAN_F0R2_FB25_Pos      (25U)                                           
3399 #define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
3400 #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
3401 #define CAN_F0R2_FB26_Pos      (26U)                                           
3402 #define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
3403 #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
3404 #define CAN_F0R2_FB27_Pos      (27U)                                           
3405 #define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
3406 #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
3407 #define CAN_F0R2_FB28_Pos      (28U)                                           
3408 #define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
3409 #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
3410 #define CAN_F0R2_FB29_Pos      (29U)                                           
3411 #define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
3412 #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
3413 #define CAN_F0R2_FB30_Pos      (30U)                                           
3414 #define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
3415 #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
3416 #define CAN_F0R2_FB31_Pos      (31U)                                           
3417 #define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
3418 #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
3419
3420 /*******************  Bit definition for CAN_F1R2 register  *******************/
3421 #define CAN_F1R2_FB0_Pos       (0U)                                            
3422 #define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
3423 #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
3424 #define CAN_F1R2_FB1_Pos       (1U)                                            
3425 #define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
3426 #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
3427 #define CAN_F1R2_FB2_Pos       (2U)                                            
3428 #define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
3429 #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
3430 #define CAN_F1R2_FB3_Pos       (3U)                                            
3431 #define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
3432 #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
3433 #define CAN_F1R2_FB4_Pos       (4U)                                            
3434 #define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
3435 #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
3436 #define CAN_F1R2_FB5_Pos       (5U)                                            
3437 #define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
3438 #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
3439 #define CAN_F1R2_FB6_Pos       (6U)                                            
3440 #define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
3441 #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
3442 #define CAN_F1R2_FB7_Pos       (7U)                                            
3443 #define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
3444 #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
3445 #define CAN_F1R2_FB8_Pos       (8U)                                            
3446 #define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
3447 #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
3448 #define CAN_F1R2_FB9_Pos       (9U)                                            
3449 #define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
3450 #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
3451 #define CAN_F1R2_FB10_Pos      (10U)                                           
3452 #define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
3453 #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
3454 #define CAN_F1R2_FB11_Pos      (11U)                                           
3455 #define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
3456 #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
3457 #define CAN_F1R2_FB12_Pos      (12U)                                           
3458 #define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
3459 #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
3460 #define CAN_F1R2_FB13_Pos      (13U)                                           
3461 #define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
3462 #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
3463 #define CAN_F1R2_FB14_Pos      (14U)                                           
3464 #define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
3465 #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
3466 #define CAN_F1R2_FB15_Pos      (15U)                                           
3467 #define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
3468 #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
3469 #define CAN_F1R2_FB16_Pos      (16U)                                           
3470 #define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
3471 #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
3472 #define CAN_F1R2_FB17_Pos      (17U)                                           
3473 #define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
3474 #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
3475 #define CAN_F1R2_FB18_Pos      (18U)                                           
3476 #define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
3477 #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
3478 #define CAN_F1R2_FB19_Pos      (19U)                                           
3479 #define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
3480 #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
3481 #define CAN_F1R2_FB20_Pos      (20U)                                           
3482 #define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
3483 #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
3484 #define CAN_F1R2_FB21_Pos      (21U)                                           
3485 #define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
3486 #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
3487 #define CAN_F1R2_FB22_Pos      (22U)                                           
3488 #define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
3489 #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
3490 #define CAN_F1R2_FB23_Pos      (23U)                                           
3491 #define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
3492 #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
3493 #define CAN_F1R2_FB24_Pos      (24U)                                           
3494 #define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
3495 #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
3496 #define CAN_F1R2_FB25_Pos      (25U)                                           
3497 #define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
3498 #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
3499 #define CAN_F1R2_FB26_Pos      (26U)                                           
3500 #define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
3501 #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
3502 #define CAN_F1R2_FB27_Pos      (27U)                                           
3503 #define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
3504 #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
3505 #define CAN_F1R2_FB28_Pos      (28U)                                           
3506 #define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
3507 #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
3508 #define CAN_F1R2_FB29_Pos      (29U)                                           
3509 #define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
3510 #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
3511 #define CAN_F1R2_FB30_Pos      (30U)                                           
3512 #define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
3513 #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
3514 #define CAN_F1R2_FB31_Pos      (31U)                                           
3515 #define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
3516 #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
3517
3518 /*******************  Bit definition for CAN_F2R2 register  *******************/
3519 #define CAN_F2R2_FB0_Pos       (0U)                                            
3520 #define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
3521 #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
3522 #define CAN_F2R2_FB1_Pos       (1U)                                            
3523 #define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
3524 #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
3525 #define CAN_F2R2_FB2_Pos       (2U)                                            
3526 #define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
3527 #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
3528 #define CAN_F2R2_FB3_Pos       (3U)                                            
3529 #define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
3530 #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
3531 #define CAN_F2R2_FB4_Pos       (4U)                                            
3532 #define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
3533 #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
3534 #define CAN_F2R2_FB5_Pos       (5U)                                            
3535 #define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
3536 #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
3537 #define CAN_F2R2_FB6_Pos       (6U)                                            
3538 #define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
3539 #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
3540 #define CAN_F2R2_FB7_Pos       (7U)                                            
3541 #define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
3542 #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
3543 #define CAN_F2R2_FB8_Pos       (8U)                                            
3544 #define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
3545 #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
3546 #define CAN_F2R2_FB9_Pos       (9U)                                            
3547 #define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
3548 #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
3549 #define CAN_F2R2_FB10_Pos      (10U)                                           
3550 #define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
3551 #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
3552 #define CAN_F2R2_FB11_Pos      (11U)                                           
3553 #define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
3554 #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
3555 #define CAN_F2R2_FB12_Pos      (12U)                                           
3556 #define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
3557 #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
3558 #define CAN_F2R2_FB13_Pos      (13U)                                           
3559 #define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
3560 #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
3561 #define CAN_F2R2_FB14_Pos      (14U)                                           
3562 #define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
3563 #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
3564 #define CAN_F2R2_FB15_Pos      (15U)                                           
3565 #define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
3566 #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
3567 #define CAN_F2R2_FB16_Pos      (16U)                                           
3568 #define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
3569 #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
3570 #define CAN_F2R2_FB17_Pos      (17U)                                           
3571 #define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
3572 #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
3573 #define CAN_F2R2_FB18_Pos      (18U)                                           
3574 #define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
3575 #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
3576 #define CAN_F2R2_FB19_Pos      (19U)                                           
3577 #define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
3578 #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
3579 #define CAN_F2R2_FB20_Pos      (20U)                                           
3580 #define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
3581 #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
3582 #define CAN_F2R2_FB21_Pos      (21U)                                           
3583 #define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
3584 #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
3585 #define CAN_F2R2_FB22_Pos      (22U)                                           
3586 #define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
3587 #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
3588 #define CAN_F2R2_FB23_Pos      (23U)                                           
3589 #define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
3590 #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
3591 #define CAN_F2R2_FB24_Pos      (24U)                                           
3592 #define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
3593 #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
3594 #define CAN_F2R2_FB25_Pos      (25U)                                           
3595 #define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
3596 #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
3597 #define CAN_F2R2_FB26_Pos      (26U)                                           
3598 #define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
3599 #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
3600 #define CAN_F2R2_FB27_Pos      (27U)                                           
3601 #define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
3602 #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
3603 #define CAN_F2R2_FB28_Pos      (28U)                                           
3604 #define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
3605 #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
3606 #define CAN_F2R2_FB29_Pos      (29U)                                           
3607 #define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
3608 #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
3609 #define CAN_F2R2_FB30_Pos      (30U)                                           
3610 #define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
3611 #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
3612 #define CAN_F2R2_FB31_Pos      (31U)                                           
3613 #define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
3614 #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
3615
3616 /*******************  Bit definition for CAN_F3R2 register  *******************/
3617 #define CAN_F3R2_FB0_Pos       (0U)                                            
3618 #define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
3619 #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
3620 #define CAN_F3R2_FB1_Pos       (1U)                                            
3621 #define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
3622 #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
3623 #define CAN_F3R2_FB2_Pos       (2U)                                            
3624 #define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
3625 #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
3626 #define CAN_F3R2_FB3_Pos       (3U)                                            
3627 #define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
3628 #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
3629 #define CAN_F3R2_FB4_Pos       (4U)                                            
3630 #define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
3631 #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
3632 #define CAN_F3R2_FB5_Pos       (5U)                                            
3633 #define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
3634 #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
3635 #define CAN_F3R2_FB6_Pos       (6U)                                            
3636 #define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
3637 #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
3638 #define CAN_F3R2_FB7_Pos       (7U)                                            
3639 #define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
3640 #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
3641 #define CAN_F3R2_FB8_Pos       (8U)                                            
3642 #define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
3643 #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
3644 #define CAN_F3R2_FB9_Pos       (9U)                                            
3645 #define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
3646 #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
3647 #define CAN_F3R2_FB10_Pos      (10U)                                           
3648 #define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
3649 #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
3650 #define CAN_F3R2_FB11_Pos      (11U)                                           
3651 #define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
3652 #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
3653 #define CAN_F3R2_FB12_Pos      (12U)                                           
3654 #define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
3655 #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
3656 #define CAN_F3R2_FB13_Pos      (13U)                                           
3657 #define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
3658 #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
3659 #define CAN_F3R2_FB14_Pos      (14U)                                           
3660 #define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
3661 #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
3662 #define CAN_F3R2_FB15_Pos      (15U)                                           
3663 #define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
3664 #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
3665 #define CAN_F3R2_FB16_Pos      (16U)                                           
3666 #define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
3667 #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
3668 #define CAN_F3R2_FB17_Pos      (17U)                                           
3669 #define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
3670 #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
3671 #define CAN_F3R2_FB18_Pos      (18U)                                           
3672 #define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
3673 #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
3674 #define CAN_F3R2_FB19_Pos      (19U)                                           
3675 #define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
3676 #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
3677 #define CAN_F3R2_FB20_Pos      (20U)                                           
3678 #define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
3679 #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
3680 #define CAN_F3R2_FB21_Pos      (21U)                                           
3681 #define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
3682 #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
3683 #define CAN_F3R2_FB22_Pos      (22U)                                           
3684 #define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
3685 #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
3686 #define CAN_F3R2_FB23_Pos      (23U)                                           
3687 #define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
3688 #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
3689 #define CAN_F3R2_FB24_Pos      (24U)                                           
3690 #define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
3691 #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
3692 #define CAN_F3R2_FB25_Pos      (25U)                                           
3693 #define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
3694 #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
3695 #define CAN_F3R2_FB26_Pos      (26U)                                           
3696 #define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
3697 #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
3698 #define CAN_F3R2_FB27_Pos      (27U)                                           
3699 #define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
3700 #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
3701 #define CAN_F3R2_FB28_Pos      (28U)                                           
3702 #define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
3703 #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
3704 #define CAN_F3R2_FB29_Pos      (29U)                                           
3705 #define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
3706 #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
3707 #define CAN_F3R2_FB30_Pos      (30U)                                           
3708 #define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
3709 #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
3710 #define CAN_F3R2_FB31_Pos      (31U)                                           
3711 #define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
3712 #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
3713
3714 /*******************  Bit definition for CAN_F4R2 register  *******************/
3715 #define CAN_F4R2_FB0_Pos       (0U)                                            
3716 #define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
3717 #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
3718 #define CAN_F4R2_FB1_Pos       (1U)                                            
3719 #define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
3720 #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
3721 #define CAN_F4R2_FB2_Pos       (2U)                                            
3722 #define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
3723 #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
3724 #define CAN_F4R2_FB3_Pos       (3U)                                            
3725 #define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
3726 #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
3727 #define CAN_F4R2_FB4_Pos       (4U)                                            
3728 #define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
3729 #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
3730 #define CAN_F4R2_FB5_Pos       (5U)                                            
3731 #define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
3732 #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
3733 #define CAN_F4R2_FB6_Pos       (6U)                                            
3734 #define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
3735 #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
3736 #define CAN_F4R2_FB7_Pos       (7U)                                            
3737 #define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
3738 #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
3739 #define CAN_F4R2_FB8_Pos       (8U)                                            
3740 #define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
3741 #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
3742 #define CAN_F4R2_FB9_Pos       (9U)                                            
3743 #define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
3744 #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
3745 #define CAN_F4R2_FB10_Pos      (10U)                                           
3746 #define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
3747 #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
3748 #define CAN_F4R2_FB11_Pos      (11U)                                           
3749 #define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
3750 #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
3751 #define CAN_F4R2_FB12_Pos      (12U)                                           
3752 #define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
3753 #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
3754 #define CAN_F4R2_FB13_Pos      (13U)                                           
3755 #define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
3756 #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
3757 #define CAN_F4R2_FB14_Pos      (14U)                                           
3758 #define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
3759 #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
3760 #define CAN_F4R2_FB15_Pos      (15U)                                           
3761 #define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
3762 #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
3763 #define CAN_F4R2_FB16_Pos      (16U)                                           
3764 #define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
3765 #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
3766 #define CAN_F4R2_FB17_Pos      (17U)                                           
3767 #define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
3768 #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
3769 #define CAN_F4R2_FB18_Pos      (18U)                                           
3770 #define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
3771 #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
3772 #define CAN_F4R2_FB19_Pos      (19U)                                           
3773 #define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
3774 #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
3775 #define CAN_F4R2_FB20_Pos      (20U)                                           
3776 #define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
3777 #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
3778 #define CAN_F4R2_FB21_Pos      (21U)                                           
3779 #define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
3780 #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
3781 #define CAN_F4R2_FB22_Pos      (22U)                                           
3782 #define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
3783 #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
3784 #define CAN_F4R2_FB23_Pos      (23U)                                           
3785 #define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
3786 #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
3787 #define CAN_F4R2_FB24_Pos      (24U)                                           
3788 #define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
3789 #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
3790 #define CAN_F4R2_FB25_Pos      (25U)                                           
3791 #define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
3792 #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
3793 #define CAN_F4R2_FB26_Pos      (26U)                                           
3794 #define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
3795 #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
3796 #define CAN_F4R2_FB27_Pos      (27U)                                           
3797 #define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
3798 #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
3799 #define CAN_F4R2_FB28_Pos      (28U)                                           
3800 #define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
3801 #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
3802 #define CAN_F4R2_FB29_Pos      (29U)                                           
3803 #define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
3804 #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
3805 #define CAN_F4R2_FB30_Pos      (30U)                                           
3806 #define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
3807 #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
3808 #define CAN_F4R2_FB31_Pos      (31U)                                           
3809 #define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
3810 #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
3811
3812 /*******************  Bit definition for CAN_F5R2 register  *******************/
3813 #define CAN_F5R2_FB0_Pos       (0U)                                            
3814 #define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
3815 #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
3816 #define CAN_F5R2_FB1_Pos       (1U)                                            
3817 #define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
3818 #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
3819 #define CAN_F5R2_FB2_Pos       (2U)                                            
3820 #define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
3821 #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
3822 #define CAN_F5R2_FB3_Pos       (3U)                                            
3823 #define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
3824 #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
3825 #define CAN_F5R2_FB4_Pos       (4U)                                            
3826 #define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
3827 #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
3828 #define CAN_F5R2_FB5_Pos       (5U)                                            
3829 #define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
3830 #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
3831 #define CAN_F5R2_FB6_Pos       (6U)                                            
3832 #define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
3833 #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
3834 #define CAN_F5R2_FB7_Pos       (7U)                                            
3835 #define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
3836 #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
3837 #define CAN_F5R2_FB8_Pos       (8U)                                            
3838 #define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
3839 #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
3840 #define CAN_F5R2_FB9_Pos       (9U)                                            
3841 #define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
3842 #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
3843 #define CAN_F5R2_FB10_Pos      (10U)                                           
3844 #define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
3845 #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
3846 #define CAN_F5R2_FB11_Pos      (11U)                                           
3847 #define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
3848 #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
3849 #define CAN_F5R2_FB12_Pos      (12U)                                           
3850 #define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
3851 #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
3852 #define CAN_F5R2_FB13_Pos      (13U)                                           
3853 #define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
3854 #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
3855 #define CAN_F5R2_FB14_Pos      (14U)                                           
3856 #define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
3857 #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
3858 #define CAN_F5R2_FB15_Pos      (15U)                                           
3859 #define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
3860 #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
3861 #define CAN_F5R2_FB16_Pos      (16U)                                           
3862 #define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
3863 #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
3864 #define CAN_F5R2_FB17_Pos      (17U)                                           
3865 #define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
3866 #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
3867 #define CAN_F5R2_FB18_Pos      (18U)                                           
3868 #define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
3869 #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
3870 #define CAN_F5R2_FB19_Pos      (19U)                                           
3871 #define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
3872 #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
3873 #define CAN_F5R2_FB20_Pos      (20U)                                           
3874 #define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
3875 #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
3876 #define CAN_F5R2_FB21_Pos      (21U)                                           
3877 #define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
3878 #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
3879 #define CAN_F5R2_FB22_Pos      (22U)                                           
3880 #define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
3881 #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
3882 #define CAN_F5R2_FB23_Pos      (23U)                                           
3883 #define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
3884 #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
3885 #define CAN_F5R2_FB24_Pos      (24U)                                           
3886 #define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
3887 #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
3888 #define CAN_F5R2_FB25_Pos      (25U)                                           
3889 #define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
3890 #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
3891 #define CAN_F5R2_FB26_Pos      (26U)                                           
3892 #define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
3893 #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
3894 #define CAN_F5R2_FB27_Pos      (27U)                                           
3895 #define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
3896 #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
3897 #define CAN_F5R2_FB28_Pos      (28U)                                           
3898 #define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
3899 #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
3900 #define CAN_F5R2_FB29_Pos      (29U)                                           
3901 #define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
3902 #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
3903 #define CAN_F5R2_FB30_Pos      (30U)                                           
3904 #define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
3905 #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
3906 #define CAN_F5R2_FB31_Pos      (31U)                                           
3907 #define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
3908 #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
3909
3910 /*******************  Bit definition for CAN_F6R2 register  *******************/
3911 #define CAN_F6R2_FB0_Pos       (0U)                                            
3912 #define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
3913 #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
3914 #define CAN_F6R2_FB1_Pos       (1U)                                            
3915 #define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
3916 #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
3917 #define CAN_F6R2_FB2_Pos       (2U)                                            
3918 #define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
3919 #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
3920 #define CAN_F6R2_FB3_Pos       (3U)                                            
3921 #define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
3922 #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
3923 #define CAN_F6R2_FB4_Pos       (4U)                                            
3924 #define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
3925 #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
3926 #define CAN_F6R2_FB5_Pos       (5U)                                            
3927 #define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
3928 #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
3929 #define CAN_F6R2_FB6_Pos       (6U)                                            
3930 #define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
3931 #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
3932 #define CAN_F6R2_FB7_Pos       (7U)                                            
3933 #define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
3934 #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
3935 #define CAN_F6R2_FB8_Pos       (8U)                                            
3936 #define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
3937 #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
3938 #define CAN_F6R2_FB9_Pos       (9U)                                            
3939 #define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
3940 #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
3941 #define CAN_F6R2_FB10_Pos      (10U)                                           
3942 #define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
3943 #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
3944 #define CAN_F6R2_FB11_Pos      (11U)                                           
3945 #define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
3946 #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
3947 #define CAN_F6R2_FB12_Pos      (12U)                                           
3948 #define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
3949 #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
3950 #define CAN_F6R2_FB13_Pos      (13U)                                           
3951 #define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
3952 #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
3953 #define CAN_F6R2_FB14_Pos      (14U)                                           
3954 #define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
3955 #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
3956 #define CAN_F6R2_FB15_Pos      (15U)                                           
3957 #define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
3958 #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
3959 #define CAN_F6R2_FB16_Pos      (16U)                                           
3960 #define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
3961 #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
3962 #define CAN_F6R2_FB17_Pos      (17U)                                           
3963 #define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
3964 #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
3965 #define CAN_F6R2_FB18_Pos      (18U)                                           
3966 #define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
3967 #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
3968 #define CAN_F6R2_FB19_Pos      (19U)                                           
3969 #define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
3970 #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
3971 #define CAN_F6R2_FB20_Pos      (20U)                                           
3972 #define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
3973 #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
3974 #define CAN_F6R2_FB21_Pos      (21U)                                           
3975 #define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
3976 #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
3977 #define CAN_F6R2_FB22_Pos      (22U)                                           
3978 #define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
3979 #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
3980 #define CAN_F6R2_FB23_Pos      (23U)                                           
3981 #define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
3982 #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
3983 #define CAN_F6R2_FB24_Pos      (24U)                                           
3984 #define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
3985 #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
3986 #define CAN_F6R2_FB25_Pos      (25U)                                           
3987 #define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
3988 #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
3989 #define CAN_F6R2_FB26_Pos      (26U)                                           
3990 #define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
3991 #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
3992 #define CAN_F6R2_FB27_Pos      (27U)                                           
3993 #define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
3994 #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
3995 #define CAN_F6R2_FB28_Pos      (28U)                                           
3996 #define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
3997 #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
3998 #define CAN_F6R2_FB29_Pos      (29U)                                           
3999 #define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
4000 #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
4001 #define CAN_F6R2_FB30_Pos      (30U)                                           
4002 #define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
4003 #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
4004 #define CAN_F6R2_FB31_Pos      (31U)                                           
4005 #define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
4006 #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
4007
4008 /*******************  Bit definition for CAN_F7R2 register  *******************/
4009 #define CAN_F7R2_FB0_Pos       (0U)                                            
4010 #define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
4011 #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
4012 #define CAN_F7R2_FB1_Pos       (1U)                                            
4013 #define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
4014 #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
4015 #define CAN_F7R2_FB2_Pos       (2U)                                            
4016 #define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
4017 #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
4018 #define CAN_F7R2_FB3_Pos       (3U)                                            
4019 #define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
4020 #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
4021 #define CAN_F7R2_FB4_Pos       (4U)                                            
4022 #define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
4023 #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
4024 #define CAN_F7R2_FB5_Pos       (5U)                                            
4025 #define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
4026 #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
4027 #define CAN_F7R2_FB6_Pos       (6U)                                            
4028 #define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
4029 #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
4030 #define CAN_F7R2_FB7_Pos       (7U)                                            
4031 #define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
4032 #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
4033 #define CAN_F7R2_FB8_Pos       (8U)                                            
4034 #define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
4035 #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
4036 #define CAN_F7R2_FB9_Pos       (9U)                                            
4037 #define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
4038 #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
4039 #define CAN_F7R2_FB10_Pos      (10U)                                           
4040 #define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
4041 #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
4042 #define CAN_F7R2_FB11_Pos      (11U)                                           
4043 #define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
4044 #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
4045 #define CAN_F7R2_FB12_Pos      (12U)                                           
4046 #define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
4047 #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
4048 #define CAN_F7R2_FB13_Pos      (13U)                                           
4049 #define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
4050 #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
4051 #define CAN_F7R2_FB14_Pos      (14U)                                           
4052 #define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
4053 #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
4054 #define CAN_F7R2_FB15_Pos      (15U)                                           
4055 #define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
4056 #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
4057 #define CAN_F7R2_FB16_Pos      (16U)                                           
4058 #define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
4059 #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
4060 #define CAN_F7R2_FB17_Pos      (17U)                                           
4061 #define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
4062 #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
4063 #define CAN_F7R2_FB18_Pos      (18U)                                           
4064 #define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
4065 #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
4066 #define CAN_F7R2_FB19_Pos      (19U)                                           
4067 #define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
4068 #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
4069 #define CAN_F7R2_FB20_Pos      (20U)                                           
4070 #define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
4071 #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
4072 #define CAN_F7R2_FB21_Pos      (21U)                                           
4073 #define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
4074 #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
4075 #define CAN_F7R2_FB22_Pos      (22U)                                           
4076 #define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
4077 #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
4078 #define CAN_F7R2_FB23_Pos      (23U)                                           
4079 #define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
4080 #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
4081 #define CAN_F7R2_FB24_Pos      (24U)                                           
4082 #define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
4083 #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
4084 #define CAN_F7R2_FB25_Pos      (25U)                                           
4085 #define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
4086 #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
4087 #define CAN_F7R2_FB26_Pos      (26U)                                           
4088 #define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
4089 #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
4090 #define CAN_F7R2_FB27_Pos      (27U)                                           
4091 #define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
4092 #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
4093 #define CAN_F7R2_FB28_Pos      (28U)                                           
4094 #define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
4095 #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
4096 #define CAN_F7R2_FB29_Pos      (29U)                                           
4097 #define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
4098 #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
4099 #define CAN_F7R2_FB30_Pos      (30U)                                           
4100 #define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
4101 #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
4102 #define CAN_F7R2_FB31_Pos      (31U)                                           
4103 #define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
4104 #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
4105
4106 /*******************  Bit definition for CAN_F8R2 register  *******************/
4107 #define CAN_F8R2_FB0_Pos       (0U)                                            
4108 #define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
4109 #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
4110 #define CAN_F8R2_FB1_Pos       (1U)                                            
4111 #define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
4112 #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
4113 #define CAN_F8R2_FB2_Pos       (2U)                                            
4114 #define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
4115 #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
4116 #define CAN_F8R2_FB3_Pos       (3U)                                            
4117 #define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
4118 #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
4119 #define CAN_F8R2_FB4_Pos       (4U)                                            
4120 #define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
4121 #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
4122 #define CAN_F8R2_FB5_Pos       (5U)                                            
4123 #define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
4124 #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
4125 #define CAN_F8R2_FB6_Pos       (6U)                                            
4126 #define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
4127 #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
4128 #define CAN_F8R2_FB7_Pos       (7U)                                            
4129 #define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
4130 #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
4131 #define CAN_F8R2_FB8_Pos       (8U)                                            
4132 #define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
4133 #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
4134 #define CAN_F8R2_FB9_Pos       (9U)                                            
4135 #define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
4136 #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
4137 #define CAN_F8R2_FB10_Pos      (10U)                                           
4138 #define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
4139 #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
4140 #define CAN_F8R2_FB11_Pos      (11U)                                           
4141 #define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
4142 #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
4143 #define CAN_F8R2_FB12_Pos      (12U)                                           
4144 #define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
4145 #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
4146 #define CAN_F8R2_FB13_Pos      (13U)                                           
4147 #define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
4148 #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
4149 #define CAN_F8R2_FB14_Pos      (14U)                                           
4150 #define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
4151 #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
4152 #define CAN_F8R2_FB15_Pos      (15U)                                           
4153 #define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
4154 #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
4155 #define CAN_F8R2_FB16_Pos      (16U)                                           
4156 #define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
4157 #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
4158 #define CAN_F8R2_FB17_Pos      (17U)                                           
4159 #define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
4160 #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
4161 #define CAN_F8R2_FB18_Pos      (18U)                                           
4162 #define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
4163 #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
4164 #define CAN_F8R2_FB19_Pos      (19U)                                           
4165 #define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
4166 #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
4167 #define CAN_F8R2_FB20_Pos      (20U)                                           
4168 #define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
4169 #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
4170 #define CAN_F8R2_FB21_Pos      (21U)                                           
4171 #define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
4172 #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
4173 #define CAN_F8R2_FB22_Pos      (22U)                                           
4174 #define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
4175 #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
4176 #define CAN_F8R2_FB23_Pos      (23U)                                           
4177 #define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
4178 #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
4179 #define CAN_F8R2_FB24_Pos      (24U)                                           
4180 #define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
4181 #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
4182 #define CAN_F8R2_FB25_Pos      (25U)                                           
4183 #define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
4184 #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
4185 #define CAN_F8R2_FB26_Pos      (26U)                                           
4186 #define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
4187 #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
4188 #define CAN_F8R2_FB27_Pos      (27U)                                           
4189 #define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
4190 #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
4191 #define CAN_F8R2_FB28_Pos      (28U)                                           
4192 #define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
4193 #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
4194 #define CAN_F8R2_FB29_Pos      (29U)                                           
4195 #define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
4196 #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
4197 #define CAN_F8R2_FB30_Pos      (30U)                                           
4198 #define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
4199 #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
4200 #define CAN_F8R2_FB31_Pos      (31U)                                           
4201 #define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
4202 #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
4203
4204 /*******************  Bit definition for CAN_F9R2 register  *******************/
4205 #define CAN_F9R2_FB0_Pos       (0U)                                            
4206 #define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
4207 #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
4208 #define CAN_F9R2_FB1_Pos       (1U)                                            
4209 #define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
4210 #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
4211 #define CAN_F9R2_FB2_Pos       (2U)                                            
4212 #define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
4213 #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
4214 #define CAN_F9R2_FB3_Pos       (3U)                                            
4215 #define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
4216 #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
4217 #define CAN_F9R2_FB4_Pos       (4U)                                            
4218 #define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
4219 #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
4220 #define CAN_F9R2_FB5_Pos       (5U)                                            
4221 #define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
4222 #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
4223 #define CAN_F9R2_FB6_Pos       (6U)                                            
4224 #define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
4225 #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
4226 #define CAN_F9R2_FB7_Pos       (7U)                                            
4227 #define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
4228 #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
4229 #define CAN_F9R2_FB8_Pos       (8U)                                            
4230 #define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
4231 #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
4232 #define CAN_F9R2_FB9_Pos       (9U)                                            
4233 #define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
4234 #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
4235 #define CAN_F9R2_FB10_Pos      (10U)                                           
4236 #define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
4237 #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
4238 #define CAN_F9R2_FB11_Pos      (11U)                                           
4239 #define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
4240 #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
4241 #define CAN_F9R2_FB12_Pos      (12U)                                           
4242 #define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
4243 #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
4244 #define CAN_F9R2_FB13_Pos      (13U)                                           
4245 #define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
4246 #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
4247 #define CAN_F9R2_FB14_Pos      (14U)                                           
4248 #define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
4249 #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
4250 #define CAN_F9R2_FB15_Pos      (15U)                                           
4251 #define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
4252 #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
4253 #define CAN_F9R2_FB16_Pos      (16U)                                           
4254 #define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
4255 #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
4256 #define CAN_F9R2_FB17_Pos      (17U)                                           
4257 #define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
4258 #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
4259 #define CAN_F9R2_FB18_Pos      (18U)                                           
4260 #define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
4261 #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
4262 #define CAN_F9R2_FB19_Pos      (19U)                                           
4263 #define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
4264 #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
4265 #define CAN_F9R2_FB20_Pos      (20U)                                           
4266 #define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
4267 #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
4268 #define CAN_F9R2_FB21_Pos      (21U)                                           
4269 #define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
4270 #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
4271 #define CAN_F9R2_FB22_Pos      (22U)                                           
4272 #define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
4273 #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
4274 #define CAN_F9R2_FB23_Pos      (23U)                                           
4275 #define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
4276 #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
4277 #define CAN_F9R2_FB24_Pos      (24U)                                           
4278 #define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
4279 #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
4280 #define CAN_F9R2_FB25_Pos      (25U)                                           
4281 #define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
4282 #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
4283 #define CAN_F9R2_FB26_Pos      (26U)                                           
4284 #define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
4285 #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
4286 #define CAN_F9R2_FB27_Pos      (27U)                                           
4287 #define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
4288 #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
4289 #define CAN_F9R2_FB28_Pos      (28U)                                           
4290 #define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
4291 #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
4292 #define CAN_F9R2_FB29_Pos      (29U)                                           
4293 #define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
4294 #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
4295 #define CAN_F9R2_FB30_Pos      (30U)                                           
4296 #define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
4297 #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
4298 #define CAN_F9R2_FB31_Pos      (31U)                                           
4299 #define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
4300 #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
4301
4302 /*******************  Bit definition for CAN_F10R2 register  ******************/
4303 #define CAN_F10R2_FB0_Pos      (0U)                                            
4304 #define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
4305 #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
4306 #define CAN_F10R2_FB1_Pos      (1U)                                            
4307 #define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
4308 #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
4309 #define CAN_F10R2_FB2_Pos      (2U)                                            
4310 #define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
4311 #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
4312 #define CAN_F10R2_FB3_Pos      (3U)                                            
4313 #define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
4314 #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
4315 #define CAN_F10R2_FB4_Pos      (4U)                                            
4316 #define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
4317 #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
4318 #define CAN_F10R2_FB5_Pos      (5U)                                            
4319 #define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
4320 #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
4321 #define CAN_F10R2_FB6_Pos      (6U)                                            
4322 #define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
4323 #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
4324 #define CAN_F10R2_FB7_Pos      (7U)                                            
4325 #define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
4326 #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
4327 #define CAN_F10R2_FB8_Pos      (8U)                                            
4328 #define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
4329 #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
4330 #define CAN_F10R2_FB9_Pos      (9U)                                            
4331 #define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
4332 #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
4333 #define CAN_F10R2_FB10_Pos     (10U)                                           
4334 #define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
4335 #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
4336 #define CAN_F10R2_FB11_Pos     (11U)                                           
4337 #define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
4338 #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
4339 #define CAN_F10R2_FB12_Pos     (12U)                                           
4340 #define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
4341 #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
4342 #define CAN_F10R2_FB13_Pos     (13U)                                           
4343 #define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
4344 #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
4345 #define CAN_F10R2_FB14_Pos     (14U)                                           
4346 #define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
4347 #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
4348 #define CAN_F10R2_FB15_Pos     (15U)                                           
4349 #define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
4350 #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
4351 #define CAN_F10R2_FB16_Pos     (16U)                                           
4352 #define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
4353 #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
4354 #define CAN_F10R2_FB17_Pos     (17U)                                           
4355 #define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
4356 #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
4357 #define CAN_F10R2_FB18_Pos     (18U)                                           
4358 #define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
4359 #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
4360 #define CAN_F10R2_FB19_Pos     (19U)                                           
4361 #define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
4362 #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
4363 #define CAN_F10R2_FB20_Pos     (20U)                                           
4364 #define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
4365 #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
4366 #define CAN_F10R2_FB21_Pos     (21U)                                           
4367 #define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
4368 #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
4369 #define CAN_F10R2_FB22_Pos     (22U)                                           
4370 #define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
4371 #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
4372 #define CAN_F10R2_FB23_Pos     (23U)                                           
4373 #define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
4374 #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
4375 #define CAN_F10R2_FB24_Pos     (24U)                                           
4376 #define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
4377 #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
4378 #define CAN_F10R2_FB25_Pos     (25U)                                           
4379 #define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
4380 #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
4381 #define CAN_F10R2_FB26_Pos     (26U)                                           
4382 #define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
4383 #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
4384 #define CAN_F10R2_FB27_Pos     (27U)                                           
4385 #define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
4386 #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
4387 #define CAN_F10R2_FB28_Pos     (28U)                                           
4388 #define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
4389 #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
4390 #define CAN_F10R2_FB29_Pos     (29U)                                           
4391 #define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
4392 #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
4393 #define CAN_F10R2_FB30_Pos     (30U)                                           
4394 #define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
4395 #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
4396 #define CAN_F10R2_FB31_Pos     (31U)                                           
4397 #define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
4398 #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
4399
4400 /*******************  Bit definition for CAN_F11R2 register  ******************/
4401 #define CAN_F11R2_FB0_Pos      (0U)                                            
4402 #define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
4403 #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
4404 #define CAN_F11R2_FB1_Pos      (1U)                                            
4405 #define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
4406 #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
4407 #define CAN_F11R2_FB2_Pos      (2U)                                            
4408 #define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
4409 #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
4410 #define CAN_F11R2_FB3_Pos      (3U)                                            
4411 #define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
4412 #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
4413 #define CAN_F11R2_FB4_Pos      (4U)                                            
4414 #define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
4415 #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
4416 #define CAN_F11R2_FB5_Pos      (5U)                                            
4417 #define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
4418 #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
4419 #define CAN_F11R2_FB6_Pos      (6U)                                            
4420 #define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
4421 #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
4422 #define CAN_F11R2_FB7_Pos      (7U)                                            
4423 #define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
4424 #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
4425 #define CAN_F11R2_FB8_Pos      (8U)                                            
4426 #define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
4427 #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
4428 #define CAN_F11R2_FB9_Pos      (9U)                                            
4429 #define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
4430 #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
4431 #define CAN_F11R2_FB10_Pos     (10U)                                           
4432 #define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
4433 #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
4434 #define CAN_F11R2_FB11_Pos     (11U)                                           
4435 #define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
4436 #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
4437 #define CAN_F11R2_FB12_Pos     (12U)                                           
4438 #define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
4439 #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
4440 #define CAN_F11R2_FB13_Pos     (13U)                                           
4441 #define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
4442 #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
4443 #define CAN_F11R2_FB14_Pos     (14U)                                           
4444 #define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
4445 #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
4446 #define CAN_F11R2_FB15_Pos     (15U)                                           
4447 #define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
4448 #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
4449 #define CAN_F11R2_FB16_Pos     (16U)                                           
4450 #define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
4451 #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
4452 #define CAN_F11R2_FB17_Pos     (17U)                                           
4453 #define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
4454 #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
4455 #define CAN_F11R2_FB18_Pos     (18U)                                           
4456 #define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
4457 #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
4458 #define CAN_F11R2_FB19_Pos     (19U)                                           
4459 #define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
4460 #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
4461 #define CAN_F11R2_FB20_Pos     (20U)                                           
4462 #define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
4463 #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
4464 #define CAN_F11R2_FB21_Pos     (21U)                                           
4465 #define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
4466 #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
4467 #define CAN_F11R2_FB22_Pos     (22U)                                           
4468 #define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
4469 #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
4470 #define CAN_F11R2_FB23_Pos     (23U)                                           
4471 #define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
4472 #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
4473 #define CAN_F11R2_FB24_Pos     (24U)                                           
4474 #define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
4475 #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
4476 #define CAN_F11R2_FB25_Pos     (25U)                                           
4477 #define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
4478 #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
4479 #define CAN_F11R2_FB26_Pos     (26U)                                           
4480 #define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
4481 #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
4482 #define CAN_F11R2_FB27_Pos     (27U)                                           
4483 #define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
4484 #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
4485 #define CAN_F11R2_FB28_Pos     (28U)                                           
4486 #define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
4487 #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
4488 #define CAN_F11R2_FB29_Pos     (29U)                                           
4489 #define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
4490 #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
4491 #define CAN_F11R2_FB30_Pos     (30U)                                           
4492 #define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
4493 #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
4494 #define CAN_F11R2_FB31_Pos     (31U)                                           
4495 #define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
4496 #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
4497
4498 /*******************  Bit definition for CAN_F12R2 register  ******************/
4499 #define CAN_F12R2_FB0_Pos      (0U)                                            
4500 #define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
4501 #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
4502 #define CAN_F12R2_FB1_Pos      (1U)                                            
4503 #define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
4504 #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
4505 #define CAN_F12R2_FB2_Pos      (2U)                                            
4506 #define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
4507 #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
4508 #define CAN_F12R2_FB3_Pos      (3U)                                            
4509 #define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
4510 #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
4511 #define CAN_F12R2_FB4_Pos      (4U)                                            
4512 #define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
4513 #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
4514 #define CAN_F12R2_FB5_Pos      (5U)                                            
4515 #define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
4516 #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
4517 #define CAN_F12R2_FB6_Pos      (6U)                                            
4518 #define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
4519 #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
4520 #define CAN_F12R2_FB7_Pos      (7U)                                            
4521 #define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
4522 #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
4523 #define CAN_F12R2_FB8_Pos      (8U)                                            
4524 #define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
4525 #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
4526 #define CAN_F12R2_FB9_Pos      (9U)                                            
4527 #define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
4528 #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
4529 #define CAN_F12R2_FB10_Pos     (10U)                                           
4530 #define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
4531 #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
4532 #define CAN_F12R2_FB11_Pos     (11U)                                           
4533 #define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
4534 #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
4535 #define CAN_F12R2_FB12_Pos     (12U)                                           
4536 #define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
4537 #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
4538 #define CAN_F12R2_FB13_Pos     (13U)                                           
4539 #define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
4540 #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
4541 #define CAN_F12R2_FB14_Pos     (14U)                                           
4542 #define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
4543 #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
4544 #define CAN_F12R2_FB15_Pos     (15U)                                           
4545 #define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
4546 #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
4547 #define CAN_F12R2_FB16_Pos     (16U)                                           
4548 #define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
4549 #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
4550 #define CAN_F12R2_FB17_Pos     (17U)                                           
4551 #define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
4552 #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
4553 #define CAN_F12R2_FB18_Pos     (18U)                                           
4554 #define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
4555 #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
4556 #define CAN_F12R2_FB19_Pos     (19U)                                           
4557 #define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
4558 #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
4559 #define CAN_F12R2_FB20_Pos     (20U)                                           
4560 #define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
4561 #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
4562 #define CAN_F12R2_FB21_Pos     (21U)                                           
4563 #define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
4564 #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
4565 #define CAN_F12R2_FB22_Pos     (22U)                                           
4566 #define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
4567 #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
4568 #define CAN_F12R2_FB23_Pos     (23U)                                           
4569 #define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
4570 #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
4571 #define CAN_F12R2_FB24_Pos     (24U)                                           
4572 #define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
4573 #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
4574 #define CAN_F12R2_FB25_Pos     (25U)                                           
4575 #define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
4576 #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
4577 #define CAN_F12R2_FB26_Pos     (26U)                                           
4578 #define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
4579 #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
4580 #define CAN_F12R2_FB27_Pos     (27U)                                           
4581 #define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
4582 #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
4583 #define CAN_F12R2_FB28_Pos     (28U)                                           
4584 #define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
4585 #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
4586 #define CAN_F12R2_FB29_Pos     (29U)                                           
4587 #define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
4588 #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
4589 #define CAN_F12R2_FB30_Pos     (30U)                                           
4590 #define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
4591 #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
4592 #define CAN_F12R2_FB31_Pos     (31U)                                           
4593 #define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
4594 #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
4595
4596 /*******************  Bit definition for CAN_F13R2 register  ******************/
4597 #define CAN_F13R2_FB0_Pos      (0U)                                            
4598 #define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
4599 #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
4600 #define CAN_F13R2_FB1_Pos      (1U)                                            
4601 #define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
4602 #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
4603 #define CAN_F13R2_FB2_Pos      (2U)                                            
4604 #define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
4605 #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
4606 #define CAN_F13R2_FB3_Pos      (3U)                                            
4607 #define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
4608 #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
4609 #define CAN_F13R2_FB4_Pos      (4U)                                            
4610 #define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
4611 #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
4612 #define CAN_F13R2_FB5_Pos      (5U)                                            
4613 #define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
4614 #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
4615 #define CAN_F13R2_FB6_Pos      (6U)                                            
4616 #define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
4617 #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
4618 #define CAN_F13R2_FB7_Pos      (7U)                                            
4619 #define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
4620 #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
4621 #define CAN_F13R2_FB8_Pos      (8U)                                            
4622 #define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
4623 #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
4624 #define CAN_F13R2_FB9_Pos      (9U)                                            
4625 #define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
4626 #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
4627 #define CAN_F13R2_FB10_Pos     (10U)                                           
4628 #define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
4629 #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
4630 #define CAN_F13R2_FB11_Pos     (11U)                                           
4631 #define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
4632 #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
4633 #define CAN_F13R2_FB12_Pos     (12U)                                           
4634 #define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
4635 #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
4636 #define CAN_F13R2_FB13_Pos     (13U)                                           
4637 #define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
4638 #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
4639 #define CAN_F13R2_FB14_Pos     (14U)                                           
4640 #define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
4641 #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
4642 #define CAN_F13R2_FB15_Pos     (15U)                                           
4643 #define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
4644 #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
4645 #define CAN_F13R2_FB16_Pos     (16U)                                           
4646 #define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
4647 #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
4648 #define CAN_F13R2_FB17_Pos     (17U)                                           
4649 #define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
4650 #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
4651 #define CAN_F13R2_FB18_Pos     (18U)                                           
4652 #define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
4653 #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
4654 #define CAN_F13R2_FB19_Pos     (19U)                                           
4655 #define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
4656 #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
4657 #define CAN_F13R2_FB20_Pos     (20U)                                           
4658 #define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
4659 #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
4660 #define CAN_F13R2_FB21_Pos     (21U)                                           
4661 #define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
4662 #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
4663 #define CAN_F13R2_FB22_Pos     (22U)                                           
4664 #define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
4665 #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
4666 #define CAN_F13R2_FB23_Pos     (23U)                                           
4667 #define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
4668 #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
4669 #define CAN_F13R2_FB24_Pos     (24U)                                           
4670 #define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
4671 #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
4672 #define CAN_F13R2_FB25_Pos     (25U)                                           
4673 #define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
4674 #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
4675 #define CAN_F13R2_FB26_Pos     (26U)                                           
4676 #define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
4677 #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
4678 #define CAN_F13R2_FB27_Pos     (27U)                                           
4679 #define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
4680 #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
4681 #define CAN_F13R2_FB28_Pos     (28U)                                           
4682 #define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
4683 #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
4684 #define CAN_F13R2_FB29_Pos     (29U)                                           
4685 #define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
4686 #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
4687 #define CAN_F13R2_FB30_Pos     (30U)                                           
4688 #define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
4689 #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
4690 #define CAN_F13R2_FB31_Pos     (31U)                                           
4691 #define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
4692 #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
4693
4694 /******************************************************************************/
4695 /*                                                                            */
4696 /*                                 HDMI-CEC (CEC)                             */
4697 /*                                                                            */
4698 /******************************************************************************/
4699
4700 /*******************  Bit definition for CEC_CR register  *********************/
4701 #define CEC_CR_CECEN_Pos         (0U)                                          
4702 #define CEC_CR_CECEN_Msk         (0x1U << CEC_CR_CECEN_Pos)                    /*!< 0x00000001 */
4703 #define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                         */
4704 #define CEC_CR_TXSOM_Pos         (1U)                                          
4705 #define CEC_CR_TXSOM_Msk         (0x1U << CEC_CR_TXSOM_Pos)                    /*!< 0x00000002 */
4706 #define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message            */
4707 #define CEC_CR_TXEOM_Pos         (2U)                                          
4708 #define CEC_CR_TXEOM_Msk         (0x1U << CEC_CR_TXEOM_Pos)                    /*!< 0x00000004 */
4709 #define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message              */
4710
4711 /*******************  Bit definition for CEC_CFGR register  *******************/
4712 #define CEC_CFGR_SFT_Pos         (0U)                                          
4713 #define CEC_CFGR_SFT_Msk         (0x7U << CEC_CFGR_SFT_Pos)                    /*!< 0x00000007 */
4714 #define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time               */
4715 #define CEC_CFGR_RXTOL_Pos       (3U)                                          
4716 #define CEC_CFGR_RXTOL_Msk       (0x1U << CEC_CFGR_RXTOL_Pos)                  /*!< 0x00000008 */
4717 #define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                      */
4718 #define CEC_CFGR_BRESTP_Pos      (4U)                                          
4719 #define CEC_CFGR_BRESTP_Msk      (0x1U << CEC_CFGR_BRESTP_Pos)                 /*!< 0x00000010 */
4720 #define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                        */
4721 #define CEC_CFGR_BREGEN_Pos      (5U)                                          
4722 #define CEC_CFGR_BREGEN_Msk      (0x1U << CEC_CFGR_BREGEN_Pos)                 /*!< 0x00000020 */
4723 #define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation    */
4724 #define CEC_CFGR_LBPEGEN_Pos     (6U)                                          
4725 #define CEC_CFGR_LBPEGEN_Msk     (0x1U << CEC_CFGR_LBPEGEN_Pos)                /*!< 0x00000040 */
4726 #define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error gener.   */
4727 #define CEC_CFGR_BRDNOGEN_Pos    (7U)                                          
4728 #define CEC_CFGR_BRDNOGEN_Msk    (0x1U << CEC_CFGR_BRDNOGEN_Pos)               /*!< 0x00000080 */
4729 #define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No Error generation  */
4730 #define CEC_CFGR_SFTOPT_Pos      (8U)                                          
4731 #define CEC_CFGR_SFTOPT_Msk      (0x1U << CEC_CFGR_SFTOPT_Pos)                 /*!< 0x00000100 */
4732 #define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional      */
4733 #define CEC_CFGR_OAR_Pos         (16U)                                         
4734 #define CEC_CFGR_OAR_Msk         (0x7FFFU << CEC_CFGR_OAR_Pos)                 /*!< 0x7FFF0000 */
4735 #define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                    */
4736 #define CEC_CFGR_LSTN_Pos        (31U)                                         
4737 #define CEC_CFGR_LSTN_Msk        (0x1U << CEC_CFGR_LSTN_Pos)                   /*!< 0x80000000 */
4738 #define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                    */
4739
4740 /*******************  Bit definition for CEC_TXDR register  *******************/
4741 #define CEC_TXDR_TXD_Pos         (0U)                                          
4742 #define CEC_TXDR_TXD_Msk         (0xFFU << CEC_TXDR_TXD_Pos)                   /*!< 0x000000FF */
4743 #define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                        */
4744
4745 /*******************  Bit definition for CEC_RXDR register  *******************/
4746 #define CEC_TXDR_RXD_Pos         (0U)                                          
4747 #define CEC_TXDR_RXD_Msk         (0xFFU << CEC_TXDR_RXD_Pos)                   /*!< 0x000000FF */
4748 #define CEC_TXDR_RXD             CEC_TXDR_RXD_Msk                              /*!< CEC Rx Data                        */
4749
4750 /*******************  Bit definition for CEC_ISR register  ********************/
4751 #define CEC_ISR_RXBR_Pos         (0U)                                          
4752 #define CEC_ISR_RXBR_Msk         (0x1U << CEC_ISR_RXBR_Pos)                    /*!< 0x00000001 */
4753 #define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                   */
4754 #define CEC_ISR_RXEND_Pos        (1U)                                          
4755 #define CEC_ISR_RXEND_Msk        (0x1U << CEC_ISR_RXEND_Pos)                   /*!< 0x00000002 */
4756 #define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                   */
4757 #define CEC_ISR_RXOVR_Pos        (2U)                                          
4758 #define CEC_ISR_RXOVR_Msk        (0x1U << CEC_ISR_RXOVR_Pos)                   /*!< 0x00000004 */
4759 #define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                         */
4760 #define CEC_ISR_BRE_Pos          (3U)                                          
4761 #define CEC_ISR_BRE_Msk          (0x1U << CEC_ISR_BRE_Pos)                     /*!< 0x00000008 */
4762 #define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                */
4763 #define CEC_ISR_SBPE_Pos         (4U)                                          
4764 #define CEC_ISR_SBPE_Msk         (0x1U << CEC_ISR_SBPE_Pos)                    /*!< 0x00000010 */
4765 #define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error          */
4766 #define CEC_ISR_LBPE_Pos         (5U)                                          
4767 #define CEC_ISR_LBPE_Msk         (0x1U << CEC_ISR_LBPE_Pos)                    /*!< 0x00000020 */
4768 #define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error           */
4769 #define CEC_ISR_RXACKE_Pos       (6U)                                          
4770 #define CEC_ISR_RXACKE_Msk       (0x1U << CEC_ISR_RXACKE_Pos)                  /*!< 0x00000040 */
4771 #define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge             */
4772 #define CEC_ISR_ARBLST_Pos       (7U)                                          
4773 #define CEC_ISR_ARBLST_Msk       (0x1U << CEC_ISR_ARBLST_Pos)                  /*!< 0x00000080 */
4774 #define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                   */
4775 #define CEC_ISR_TXBR_Pos         (8U)                                          
4776 #define CEC_ISR_TXBR_Msk         (0x1U << CEC_ISR_TXBR_Pos)                    /*!< 0x00000100 */
4777 #define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                    */
4778 #define CEC_ISR_TXEND_Pos        (9U)                                          
4779 #define CEC_ISR_TXEND_Msk        (0x1U << CEC_ISR_TXEND_Pos)                   /*!< 0x00000200 */
4780 #define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                */
4781 #define CEC_ISR_TXUDR_Pos        (10U)                                         
4782 #define CEC_ISR_TXUDR_Msk        (0x1U << CEC_ISR_TXUDR_Pos)                   /*!< 0x00000400 */
4783 #define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                 */
4784 #define CEC_ISR_TXERR_Pos        (11U)                                         
4785 #define CEC_ISR_TXERR_Msk        (0x1U << CEC_ISR_TXERR_Pos)                   /*!< 0x00000800 */
4786 #define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                           */
4787 #define CEC_ISR_TXACKE_Pos       (12U)                                         
4788 #define CEC_ISR_TXACKE_Msk       (0x1U << CEC_ISR_TXACKE_Pos)                  /*!< 0x00001000 */
4789 #define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge             */
4790
4791 /*******************  Bit definition for CEC_IER register  ********************/
4792 #define CEC_IER_RXBRIE_Pos       (0U)                                          
4793 #define CEC_IER_RXBRIE_Msk       (0x1U << CEC_IER_RXBRIE_Pos)                  /*!< 0x00000001 */
4794 #define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable         */
4795 #define CEC_IER_RXENDIE_Pos      (1U)                                          
4796 #define CEC_IER_RXENDIE_Msk      (0x1U << CEC_IER_RXENDIE_Pos)                 /*!< 0x00000002 */
4797 #define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable         */
4798 #define CEC_IER_RXOVRIE_Pos      (2U)                                          
4799 #define CEC_IER_RXOVRIE_Msk      (0x1U << CEC_IER_RXOVRIE_Pos)                 /*!< 0x00000004 */
4800 #define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable               */
4801 #define CEC_IER_BREIE_Pos        (3U)                                          
4802 #define CEC_IER_BREIE_Msk        (0x1U << CEC_IER_BREIE_Pos)                   /*!< 0x00000008 */
4803 #define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable      */
4804 #define CEC_IER_SBPEIE_Pos       (4U)                                          
4805 #define CEC_IER_SBPEIE_Msk       (0x1U << CEC_IER_SBPEIE_Pos)                  /*!< 0x00000010 */
4806 #define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable*/
4807 #define CEC_IER_LBPEIE_Pos       (5U)                                          
4808 #define CEC_IER_LBPEIE_Msk       (0x1U << CEC_IER_LBPEIE_Pos)                  /*!< 0x00000020 */
4809 #define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable */
4810 #define CEC_IER_RXACKEIE_Pos     (6U)                                          
4811 #define CEC_IER_RXACKEIE_Msk     (0x1U << CEC_IER_RXACKEIE_Pos)                /*!< 0x00000040 */
4812 #define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable   */
4813 #define CEC_IER_ARBLSTIE_Pos     (7U)                                          
4814 #define CEC_IER_ARBLSTIE_Msk     (0x1U << CEC_IER_ARBLSTIE_Pos)                /*!< 0x00000080 */
4815 #define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable         */
4816 #define CEC_IER_TXBRIE_Pos       (8U)                                          
4817 #define CEC_IER_TXBRIE_Msk       (0x1U << CEC_IER_TXBRIE_Pos)                  /*!< 0x00000100 */
4818 #define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable         */
4819 #define CEC_IER_TXENDIE_Pos      (9U)                                          
4820 #define CEC_IER_TXENDIE_Msk      (0x1U << CEC_IER_TXENDIE_Pos)                 /*!< 0x00000200 */
4821 #define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable      */
4822 #define CEC_IER_TXUDRIE_Pos      (10U)                                         
4823 #define CEC_IER_TXUDRIE_Msk      (0x1U << CEC_IER_TXUDRIE_Pos)                 /*!< 0x00000400 */
4824 #define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable       */
4825 #define CEC_IER_TXERRIE_Pos      (11U)                                         
4826 #define CEC_IER_TXERRIE_Msk      (0x1U << CEC_IER_TXERRIE_Pos)                 /*!< 0x00000800 */
4827 #define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                 */
4828 #define CEC_IER_TXACKEIE_Pos     (12U)                                         
4829 #define CEC_IER_TXACKEIE_Msk     (0x1U << CEC_IER_TXACKEIE_Pos)                /*!< 0x00001000 */
4830 #define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable   */
4831
4832 /******************************************************************************/
4833 /*                                                                            */
4834 /*                       CRC calculation unit (CRC)                           */
4835 /*                                                                            */
4836 /******************************************************************************/
4837 /*******************  Bit definition for CRC_DR register  *********************/
4838 #define CRC_DR_DR_Pos            (0U)                                          
4839 #define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
4840 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
4841
4842 /*******************  Bit definition for CRC_IDR register  ********************/
4843 #define CRC_IDR_IDR              ((uint8_t)0xFFU)                              /*!< General-purpose 8-bit data register bits */
4844
4845 /********************  Bit definition for CRC_CR register  ********************/
4846 #define CRC_CR_RESET_Pos         (0U)                                          
4847 #define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
4848 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
4849 #define CRC_CR_REV_IN_Pos        (5U)                                          
4850 #define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
4851 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
4852 #define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
4853 #define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
4854 #define CRC_CR_REV_OUT_Pos       (7U)                                          
4855 #define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
4856 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
4857
4858 /*******************  Bit definition for CRC_INIT register  *******************/
4859 #define CRC_INIT_INIT_Pos        (0U)                                          
4860 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
4861 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
4862
4863 /******************************************************************************/
4864 /*                                                                            */
4865 /*                          CRS Clock Recovery System                         */
4866 /******************************************************************************/
4867
4868 /*******************  Bit definition for CRS_CR register  *********************/
4869 #define CRS_CR_SYNCOKIE_Pos       (0U)                                         
4870 #define CRS_CR_SYNCOKIE_Msk       (0x1U << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
4871 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
4872 #define CRS_CR_SYNCWARNIE_Pos     (1U)                                         
4873 #define CRS_CR_SYNCWARNIE_Msk     (0x1U << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
4874 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
4875 #define CRS_CR_ERRIE_Pos          (2U)                                         
4876 #define CRS_CR_ERRIE_Msk          (0x1U << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
4877 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
4878 #define CRS_CR_ESYNCIE_Pos        (3U)                                         
4879 #define CRS_CR_ESYNCIE_Msk        (0x1U << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
4880 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
4881 #define CRS_CR_CEN_Pos            (5U)                                         
4882 #define CRS_CR_CEN_Msk            (0x1U << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
4883 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
4884 #define CRS_CR_AUTOTRIMEN_Pos     (6U)                                         
4885 #define CRS_CR_AUTOTRIMEN_Msk     (0x1U << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
4886 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
4887 #define CRS_CR_SWSYNC_Pos         (7U)                                         
4888 #define CRS_CR_SWSYNC_Msk         (0x1U << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
4889 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
4890 #define CRS_CR_TRIM_Pos           (8U)                                         
4891 #define CRS_CR_TRIM_Msk           (0x3FU << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
4892 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
4893
4894 /*******************  Bit definition for CRS_CFGR register  *********************/
4895 #define CRS_CFGR_RELOAD_Pos       (0U)                                         
4896 #define CRS_CFGR_RELOAD_Msk       (0xFFFFU << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
4897 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
4898 #define CRS_CFGR_FELIM_Pos        (16U)                                        
4899 #define CRS_CFGR_FELIM_Msk        (0xFFU << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
4900 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
4901
4902 #define CRS_CFGR_SYNCDIV_Pos      (24U)                                        
4903 #define CRS_CFGR_SYNCDIV_Msk      (0x7U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
4904 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
4905 #define CRS_CFGR_SYNCDIV_0        (0x1U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
4906 #define CRS_CFGR_SYNCDIV_1        (0x2U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
4907 #define CRS_CFGR_SYNCDIV_2        (0x4U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
4908
4909 #define CRS_CFGR_SYNCSRC_Pos      (28U)                                        
4910 #define CRS_CFGR_SYNCSRC_Msk      (0x3U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
4911 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
4912 #define CRS_CFGR_SYNCSRC_0        (0x1U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
4913 #define CRS_CFGR_SYNCSRC_1        (0x2U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
4914
4915 #define CRS_CFGR_SYNCPOL_Pos      (31U)                                        
4916 #define CRS_CFGR_SYNCPOL_Msk      (0x1U << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
4917 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
4918   
4919 /*******************  Bit definition for CRS_ISR register  *********************/
4920 #define CRS_ISR_SYNCOKF_Pos       (0U)                                         
4921 #define CRS_ISR_SYNCOKF_Msk       (0x1U << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
4922 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
4923 #define CRS_ISR_SYNCWARNF_Pos     (1U)                                         
4924 #define CRS_ISR_SYNCWARNF_Msk     (0x1U << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
4925 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
4926 #define CRS_ISR_ERRF_Pos          (2U)                                         
4927 #define CRS_ISR_ERRF_Msk          (0x1U << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
4928 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
4929 #define CRS_ISR_ESYNCF_Pos        (3U)                                         
4930 #define CRS_ISR_ESYNCF_Msk        (0x1U << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
4931 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
4932 #define CRS_ISR_SYNCERR_Pos       (8U)                                         
4933 #define CRS_ISR_SYNCERR_Msk       (0x1U << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
4934 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
4935 #define CRS_ISR_SYNCMISS_Pos      (9U)                                         
4936 #define CRS_ISR_SYNCMISS_Msk      (0x1U << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
4937 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
4938 #define CRS_ISR_TRIMOVF_Pos       (10U)                                        
4939 #define CRS_ISR_TRIMOVF_Msk       (0x1U << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
4940 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
4941 #define CRS_ISR_FEDIR_Pos         (15U)                                        
4942 #define CRS_ISR_FEDIR_Msk         (0x1U << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
4943 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
4944 #define CRS_ISR_FECAP_Pos         (16U)                                        
4945 #define CRS_ISR_FECAP_Msk         (0xFFFFU << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
4946 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
4947
4948 /*******************  Bit definition for CRS_ICR register  *********************/
4949 #define CRS_ICR_SYNCOKC_Pos       (0U)                                         
4950 #define CRS_ICR_SYNCOKC_Msk       (0x1U << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
4951 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
4952 #define CRS_ICR_SYNCWARNC_Pos     (1U)                                         
4953 #define CRS_ICR_SYNCWARNC_Msk     (0x1U << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
4954 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
4955 #define CRS_ICR_ERRC_Pos          (2U)                                         
4956 #define CRS_ICR_ERRC_Msk          (0x1U << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
4957 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag        */
4958 #define CRS_ICR_ESYNCC_Pos        (3U)                                         
4959 #define CRS_ICR_ESYNCC_Msk        (0x1U << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
4960 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
4961
4962 /******************************************************************************/
4963 /*                                                                            */
4964 /*                           Debug MCU (DBGMCU)                               */
4965 /*                                                                            */
4966 /******************************************************************************/
4967
4968 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
4969 #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)                      
4970 #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
4971 #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk  /*!< Device Identifier */
4972
4973 #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)                     
4974 #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
4975 #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk  /*!< REV_ID[15:0] bits (Revision Identifier) */
4976 #define DBGMCU_IDCODE_REV_ID_0                       (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
4977 #define DBGMCU_IDCODE_REV_ID_1                       (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
4978 #define DBGMCU_IDCODE_REV_ID_2                       (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
4979 #define DBGMCU_IDCODE_REV_ID_3                       (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
4980 #define DBGMCU_IDCODE_REV_ID_4                       (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
4981 #define DBGMCU_IDCODE_REV_ID_5                       (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
4982 #define DBGMCU_IDCODE_REV_ID_6                       (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
4983 #define DBGMCU_IDCODE_REV_ID_7                       (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
4984 #define DBGMCU_IDCODE_REV_ID_8                       (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
4985 #define DBGMCU_IDCODE_REV_ID_9                       (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
4986 #define DBGMCU_IDCODE_REV_ID_10                      (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
4987 #define DBGMCU_IDCODE_REV_ID_11                      (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
4988 #define DBGMCU_IDCODE_REV_ID_12                      (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
4989 #define DBGMCU_IDCODE_REV_ID_13                      (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
4990 #define DBGMCU_IDCODE_REV_ID_14                      (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
4991 #define DBGMCU_IDCODE_REV_ID_15                      (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
4992
4993 /******************  Bit definition for DBGMCU_CR register  *******************/
4994 #define DBGMCU_CR_DBG_STOP_Pos                       (1U)                      
4995 #define DBGMCU_CR_DBG_STOP_Msk                       (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
4996 #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk    /*!< Debug Stop Mode */
4997 #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)                      
4998 #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
4999 #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
5000
5001 /******************  Bit definition for DBGMCU_APB1_FZ register  **************/
5002 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)                      
5003 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
5004 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
5005 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)                      
5006 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
5007 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
5008 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)                      
5009 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
5010 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */
5011 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)                     
5012 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
5013 #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
5014 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)                     
5015 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
5016 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
5017 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)                     
5018 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
5019 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
5020 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)                     
5021 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
5022 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
5023 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos              (25U)                     
5024 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk              (0x1U << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
5025 #define DBGMCU_APB1_FZ_DBG_CAN_STOP                  DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk /*!< CAN debug stopped when Core is halted  */
5026
5027 /******************  Bit definition for DBGMCU_APB2_FZ register  **************/
5028 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (11U)                     
5029 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
5030 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
5031 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos            (17U)                     
5032 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
5033 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP                DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */
5034 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos            (18U)                     
5035 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
5036 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP                DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */
5037
5038 /******************************************************************************/
5039 /*                                                                            */
5040 /*                           DMA Controller (DMA)                             */
5041 /*                                                                            */
5042 /******************************************************************************/
5043 /*******************  Bit definition for DMA_ISR register  ********************/
5044 #define DMA_ISR_GIF1_Pos       (0U)                                            
5045 #define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
5046 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
5047 #define DMA_ISR_TCIF1_Pos      (1U)                                            
5048 #define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
5049 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
5050 #define DMA_ISR_HTIF1_Pos      (2U)                                            
5051 #define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
5052 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
5053 #define DMA_ISR_TEIF1_Pos      (3U)                                            
5054 #define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
5055 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
5056 #define DMA_ISR_GIF2_Pos       (4U)                                            
5057 #define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
5058 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
5059 #define DMA_ISR_TCIF2_Pos      (5U)                                            
5060 #define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
5061 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
5062 #define DMA_ISR_HTIF2_Pos      (6U)                                            
5063 #define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
5064 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
5065 #define DMA_ISR_TEIF2_Pos      (7U)                                            
5066 #define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
5067 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
5068 #define DMA_ISR_GIF3_Pos       (8U)                                            
5069 #define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
5070 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
5071 #define DMA_ISR_TCIF3_Pos      (9U)                                            
5072 #define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
5073 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
5074 #define DMA_ISR_HTIF3_Pos      (10U)                                           
5075 #define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
5076 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
5077 #define DMA_ISR_TEIF3_Pos      (11U)                                           
5078 #define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
5079 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
5080 #define DMA_ISR_GIF4_Pos       (12U)                                           
5081 #define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
5082 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
5083 #define DMA_ISR_TCIF4_Pos      (13U)                                           
5084 #define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
5085 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
5086 #define DMA_ISR_HTIF4_Pos      (14U)                                           
5087 #define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
5088 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
5089 #define DMA_ISR_TEIF4_Pos      (15U)                                           
5090 #define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
5091 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
5092 #define DMA_ISR_GIF5_Pos       (16U)                                           
5093 #define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
5094 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
5095 #define DMA_ISR_TCIF5_Pos      (17U)                                           
5096 #define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
5097 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
5098 #define DMA_ISR_HTIF5_Pos      (18U)                                           
5099 #define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
5100 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
5101 #define DMA_ISR_TEIF5_Pos      (19U)                                           
5102 #define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
5103 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
5104 #define DMA_ISR_GIF6_Pos       (20U)                                           
5105 #define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
5106 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag    */
5107 #define DMA_ISR_TCIF6_Pos      (21U)                                           
5108 #define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
5109 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag   */
5110 #define DMA_ISR_HTIF6_Pos      (22U)                                           
5111 #define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
5112 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag       */
5113 #define DMA_ISR_TEIF6_Pos      (23U)                                           
5114 #define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
5115 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag      */
5116 #define DMA_ISR_GIF7_Pos       (24U)                                           
5117 #define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
5118 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag    */
5119 #define DMA_ISR_TCIF7_Pos      (25U)                                           
5120 #define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
5121 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag   */
5122 #define DMA_ISR_HTIF7_Pos      (26U)                                           
5123 #define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
5124 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag       */
5125 #define DMA_ISR_TEIF7_Pos      (27U)                                           
5126 #define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
5127 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag      */
5128
5129 /*******************  Bit definition for DMA_IFCR register  *******************/
5130 #define DMA_IFCR_CGIF1_Pos     (0U)                                            
5131 #define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
5132 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
5133 #define DMA_IFCR_CTCIF1_Pos    (1U)                                            
5134 #define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
5135 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
5136 #define DMA_IFCR_CHTIF1_Pos    (2U)                                            
5137 #define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
5138 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
5139 #define DMA_IFCR_CTEIF1_Pos    (3U)                                            
5140 #define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
5141 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
5142 #define DMA_IFCR_CGIF2_Pos     (4U)                                            
5143 #define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
5144 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
5145 #define DMA_IFCR_CTCIF2_Pos    (5U)                                            
5146 #define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
5147 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
5148 #define DMA_IFCR_CHTIF2_Pos    (6U)                                            
5149 #define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
5150 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
5151 #define DMA_IFCR_CTEIF2_Pos    (7U)                                            
5152 #define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
5153 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
5154 #define DMA_IFCR_CGIF3_Pos     (8U)                                            
5155 #define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
5156 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
5157 #define DMA_IFCR_CTCIF3_Pos    (9U)                                            
5158 #define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
5159 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
5160 #define DMA_IFCR_CHTIF3_Pos    (10U)                                           
5161 #define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
5162 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
5163 #define DMA_IFCR_CTEIF3_Pos    (11U)                                           
5164 #define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
5165 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
5166 #define DMA_IFCR_CGIF4_Pos     (12U)                                           
5167 #define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
5168 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
5169 #define DMA_IFCR_CTCIF4_Pos    (13U)                                           
5170 #define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
5171 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
5172 #define DMA_IFCR_CHTIF4_Pos    (14U)                                           
5173 #define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
5174 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
5175 #define DMA_IFCR_CTEIF4_Pos    (15U)                                           
5176 #define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
5177 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
5178 #define DMA_IFCR_CGIF5_Pos     (16U)                                           
5179 #define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
5180 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
5181 #define DMA_IFCR_CTCIF5_Pos    (17U)                                           
5182 #define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
5183 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
5184 #define DMA_IFCR_CHTIF5_Pos    (18U)                                           
5185 #define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
5186 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
5187 #define DMA_IFCR_CTEIF5_Pos    (19U)                                           
5188 #define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
5189 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
5190 #define DMA_IFCR_CGIF6_Pos     (20U)                                           
5191 #define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
5192 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear    */
5193 #define DMA_IFCR_CTCIF6_Pos    (21U)                                           
5194 #define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
5195 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear   */
5196 #define DMA_IFCR_CHTIF6_Pos    (22U)                                           
5197 #define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
5198 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear       */
5199 #define DMA_IFCR_CTEIF6_Pos    (23U)                                           
5200 #define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
5201 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear      */
5202 #define DMA_IFCR_CGIF7_Pos     (24U)                                           
5203 #define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
5204 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear    */
5205 #define DMA_IFCR_CTCIF7_Pos    (25U)                                           
5206 #define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
5207 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear   */
5208 #define DMA_IFCR_CHTIF7_Pos    (26U)                                           
5209 #define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
5210 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear       */
5211 #define DMA_IFCR_CTEIF7_Pos    (27U)                                           
5212 #define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
5213 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear      */
5214
5215 /*******************  Bit definition for DMA_CCR register  ********************/
5216 #define DMA_CCR_EN_Pos         (0U)                                            
5217 #define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
5218 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
5219 #define DMA_CCR_TCIE_Pos       (1U)                                            
5220 #define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
5221 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
5222 #define DMA_CCR_HTIE_Pos       (2U)                                            
5223 #define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
5224 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
5225 #define DMA_CCR_TEIE_Pos       (3U)                                            
5226 #define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
5227 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
5228 #define DMA_CCR_DIR_Pos        (4U)                                            
5229 #define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
5230 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
5231 #define DMA_CCR_CIRC_Pos       (5U)                                            
5232 #define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
5233 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
5234 #define DMA_CCR_PINC_Pos       (6U)                                            
5235 #define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
5236 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
5237 #define DMA_CCR_MINC_Pos       (7U)                                            
5238 #define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
5239 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
5240
5241 #define DMA_CCR_PSIZE_Pos      (8U)                                            
5242 #define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
5243 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
5244 #define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
5245 #define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
5246
5247 #define DMA_CCR_MSIZE_Pos      (10U)                                           
5248 #define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
5249 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
5250 #define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
5251 #define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
5252
5253 #define DMA_CCR_PL_Pos         (12U)                                           
5254 #define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
5255 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
5256 #define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
5257 #define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
5258
5259 #define DMA_CCR_MEM2MEM_Pos    (14U)                                           
5260 #define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
5261 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
5262
5263 /******************  Bit definition for DMA_CNDTR register  *******************/
5264 #define DMA_CNDTR_NDT_Pos      (0U)                                            
5265 #define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
5266 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
5267
5268 /******************  Bit definition for DMA_CPAR register  ********************/
5269 #define DMA_CPAR_PA_Pos        (0U)                                            
5270 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
5271 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
5272
5273 /******************  Bit definition for DMA_CMAR register  ********************/
5274 #define DMA_CMAR_MA_Pos        (0U)                                            
5275 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
5276 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
5277
5278 /******************************************************************************/
5279 /*                                                                            */
5280 /*                 External Interrupt/Event Controller (EXTI)                 */
5281 /*                                                                            */
5282 /******************************************************************************/
5283 /*******************  Bit definition for EXTI_IMR register  *******************/
5284 #define EXTI_IMR_MR0_Pos          (0U)                                         
5285 #define EXTI_IMR_MR0_Msk          (0x1U << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
5286 #define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0  */
5287 #define EXTI_IMR_MR1_Pos          (1U)                                         
5288 #define EXTI_IMR_MR1_Msk          (0x1U << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
5289 #define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1  */
5290 #define EXTI_IMR_MR2_Pos          (2U)                                         
5291 #define EXTI_IMR_MR2_Msk          (0x1U << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
5292 #define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2  */
5293 #define EXTI_IMR_MR3_Pos          (3U)                                         
5294 #define EXTI_IMR_MR3_Msk          (0x1U << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
5295 #define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3  */
5296 #define EXTI_IMR_MR4_Pos          (4U)                                         
5297 #define EXTI_IMR_MR4_Msk          (0x1U << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
5298 #define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4  */
5299 #define EXTI_IMR_MR5_Pos          (5U)                                         
5300 #define EXTI_IMR_MR5_Msk          (0x1U << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
5301 #define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5  */
5302 #define EXTI_IMR_MR6_Pos          (6U)                                         
5303 #define EXTI_IMR_MR6_Msk          (0x1U << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
5304 #define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6  */
5305 #define EXTI_IMR_MR7_Pos          (7U)                                         
5306 #define EXTI_IMR_MR7_Msk          (0x1U << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
5307 #define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7  */
5308 #define EXTI_IMR_MR8_Pos          (8U)                                         
5309 #define EXTI_IMR_MR8_Msk          (0x1U << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
5310 #define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8  */
5311 #define EXTI_IMR_MR9_Pos          (9U)                                         
5312 #define EXTI_IMR_MR9_Msk          (0x1U << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
5313 #define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9  */
5314 #define EXTI_IMR_MR10_Pos         (10U)                                        
5315 #define EXTI_IMR_MR10_Msk         (0x1U << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
5316 #define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
5317 #define EXTI_IMR_MR11_Pos         (11U)                                        
5318 #define EXTI_IMR_MR11_Msk         (0x1U << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
5319 #define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
5320 #define EXTI_IMR_MR12_Pos         (12U)                                        
5321 #define EXTI_IMR_MR12_Msk         (0x1U << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
5322 #define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
5323 #define EXTI_IMR_MR13_Pos         (13U)                                        
5324 #define EXTI_IMR_MR13_Msk         (0x1U << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
5325 #define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
5326 #define EXTI_IMR_MR14_Pos         (14U)                                        
5327 #define EXTI_IMR_MR14_Msk         (0x1U << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
5328 #define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
5329 #define EXTI_IMR_MR15_Pos         (15U)                                        
5330 #define EXTI_IMR_MR15_Msk         (0x1U << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
5331 #define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
5332 #define EXTI_IMR_MR16_Pos         (16U)                                        
5333 #define EXTI_IMR_MR16_Msk         (0x1U << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
5334 #define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
5335 #define EXTI_IMR_MR17_Pos         (17U)                                        
5336 #define EXTI_IMR_MR17_Msk         (0x1U << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
5337 #define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
5338 #define EXTI_IMR_MR18_Pos         (18U)                                        
5339 #define EXTI_IMR_MR18_Msk         (0x1U << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
5340 #define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
5341 #define EXTI_IMR_MR19_Pos         (19U)                                        
5342 #define EXTI_IMR_MR19_Msk         (0x1U << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
5343 #define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
5344 #define EXTI_IMR_MR21_Pos         (21U)                                        
5345 #define EXTI_IMR_MR21_Msk         (0x1U << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
5346 #define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
5347 #define EXTI_IMR_MR22_Pos         (22U)                                        
5348 #define EXTI_IMR_MR22_Msk         (0x1U << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
5349 #define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
5350 #define EXTI_IMR_MR23_Pos         (23U)                                        
5351 #define EXTI_IMR_MR23_Msk         (0x1U << EXTI_IMR_MR23_Pos)                  /*!< 0x00800000 */
5352 #define EXTI_IMR_MR23             EXTI_IMR_MR23_Msk                            /*!< Interrupt Mask on line 23 */
5353 #define EXTI_IMR_MR25_Pos         (25U)                                        
5354 #define EXTI_IMR_MR25_Msk         (0x1U << EXTI_IMR_MR25_Pos)                  /*!< 0x02000000 */
5355 #define EXTI_IMR_MR25             EXTI_IMR_MR25_Msk                            /*!< Interrupt Mask on line 25 */
5356 #define EXTI_IMR_MR27_Pos         (27U)                                        
5357 #define EXTI_IMR_MR27_Msk         (0x1U << EXTI_IMR_MR27_Pos)                  /*!< 0x08000000 */
5358 #define EXTI_IMR_MR27             EXTI_IMR_MR27_Msk                            /*!< Interrupt Mask on line 27 */
5359 #define EXTI_IMR_MR31_Pos         (31U)                                        
5360 #define EXTI_IMR_MR31_Msk         (0x1U << EXTI_IMR_MR31_Pos)                  /*!< 0x80000000 */
5361 #define EXTI_IMR_MR31             EXTI_IMR_MR31_Msk                            /*!< Interrupt Mask on line 31 */
5362
5363 /* References Defines */
5364 #define  EXTI_IMR_IM0 EXTI_IMR_MR0
5365 #define  EXTI_IMR_IM1 EXTI_IMR_MR1
5366 #define  EXTI_IMR_IM2 EXTI_IMR_MR2
5367 #define  EXTI_IMR_IM3 EXTI_IMR_MR3
5368 #define  EXTI_IMR_IM4 EXTI_IMR_MR4
5369 #define  EXTI_IMR_IM5 EXTI_IMR_MR5
5370 #define  EXTI_IMR_IM6 EXTI_IMR_MR6
5371 #define  EXTI_IMR_IM7 EXTI_IMR_MR7
5372 #define  EXTI_IMR_IM8 EXTI_IMR_MR8
5373 #define  EXTI_IMR_IM9 EXTI_IMR_MR9
5374 #define  EXTI_IMR_IM10 EXTI_IMR_MR10
5375 #define  EXTI_IMR_IM11 EXTI_IMR_MR11
5376 #define  EXTI_IMR_IM12 EXTI_IMR_MR12
5377 #define  EXTI_IMR_IM13 EXTI_IMR_MR13
5378 #define  EXTI_IMR_IM14 EXTI_IMR_MR14
5379 #define  EXTI_IMR_IM15 EXTI_IMR_MR15
5380 #define  EXTI_IMR_IM16 EXTI_IMR_MR16
5381 #define  EXTI_IMR_IM17 EXTI_IMR_MR17
5382 #define  EXTI_IMR_IM18 EXTI_IMR_MR18
5383 #define  EXTI_IMR_IM19 EXTI_IMR_MR19
5384 #define  EXTI_IMR_IM21 EXTI_IMR_MR21
5385 #define  EXTI_IMR_IM22 EXTI_IMR_MR22
5386 #define  EXTI_IMR_IM23 EXTI_IMR_MR23
5387 #define  EXTI_IMR_IM25 EXTI_IMR_MR25
5388 #define  EXTI_IMR_IM27 EXTI_IMR_MR27
5389 #define  EXTI_IMR_IM31 EXTI_IMR_MR31
5390
5391 #define EXTI_IMR_IM_Pos           (0U)                                         
5392 #define EXTI_IMR_IM_Msk           (0x8AEFFFFFU << EXTI_IMR_IM_Pos)             /*!< 0x8AEFFFFF */
5393 #define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
5394
5395
5396 /******************  Bit definition for EXTI_EMR register  ********************/
5397 #define EXTI_EMR_MR0_Pos          (0U)                                         
5398 #define EXTI_EMR_MR0_Msk          (0x1U << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
5399 #define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0  */
5400 #define EXTI_EMR_MR1_Pos          (1U)                                         
5401 #define EXTI_EMR_MR1_Msk          (0x1U << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
5402 #define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1  */
5403 #define EXTI_EMR_MR2_Pos          (2U)                                         
5404 #define EXTI_EMR_MR2_Msk          (0x1U << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
5405 #define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2  */
5406 #define EXTI_EMR_MR3_Pos          (3U)                                         
5407 #define EXTI_EMR_MR3_Msk          (0x1U << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
5408 #define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3  */
5409 #define EXTI_EMR_MR4_Pos          (4U)                                         
5410 #define EXTI_EMR_MR4_Msk          (0x1U << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
5411 #define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4  */
5412 #define EXTI_EMR_MR5_Pos          (5U)                                         
5413 #define EXTI_EMR_MR5_Msk          (0x1U << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
5414 #define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5  */
5415 #define EXTI_EMR_MR6_Pos          (6U)                                         
5416 #define EXTI_EMR_MR6_Msk          (0x1U << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
5417 #define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6  */
5418 #define EXTI_EMR_MR7_Pos          (7U)                                         
5419 #define EXTI_EMR_MR7_Msk          (0x1U << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
5420 #define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7  */
5421 #define EXTI_EMR_MR8_Pos          (8U)                                         
5422 #define EXTI_EMR_MR8_Msk          (0x1U << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
5423 #define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8  */
5424 #define EXTI_EMR_MR9_Pos          (9U)                                         
5425 #define EXTI_EMR_MR9_Msk          (0x1U << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
5426 #define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9  */
5427 #define EXTI_EMR_MR10_Pos         (10U)                                        
5428 #define EXTI_EMR_MR10_Msk         (0x1U << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
5429 #define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
5430 #define EXTI_EMR_MR11_Pos         (11U)                                        
5431 #define EXTI_EMR_MR11_Msk         (0x1U << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
5432 #define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
5433 #define EXTI_EMR_MR12_Pos         (12U)                                        
5434 #define EXTI_EMR_MR12_Msk         (0x1U << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
5435 #define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
5436 #define EXTI_EMR_MR13_Pos         (13U)                                        
5437 #define EXTI_EMR_MR13_Msk         (0x1U << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
5438 #define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
5439 #define EXTI_EMR_MR14_Pos         (14U)                                        
5440 #define EXTI_EMR_MR14_Msk         (0x1U << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
5441 #define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
5442 #define EXTI_EMR_MR15_Pos         (15U)                                        
5443 #define EXTI_EMR_MR15_Msk         (0x1U << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
5444 #define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
5445 #define EXTI_EMR_MR16_Pos         (16U)                                        
5446 #define EXTI_EMR_MR16_Msk         (0x1U << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
5447 #define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
5448 #define EXTI_EMR_MR17_Pos         (17U)                                        
5449 #define EXTI_EMR_MR17_Msk         (0x1U << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
5450 #define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
5451 #define EXTI_EMR_MR18_Pos         (18U)                                        
5452 #define EXTI_EMR_MR18_Msk         (0x1U << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
5453 #define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
5454 #define EXTI_EMR_MR19_Pos         (19U)                                        
5455 #define EXTI_EMR_MR19_Msk         (0x1U << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
5456 #define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
5457 #define EXTI_EMR_MR21_Pos         (21U)                                        
5458 #define EXTI_EMR_MR21_Msk         (0x1U << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
5459 #define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
5460 #define EXTI_EMR_MR22_Pos         (22U)                                        
5461 #define EXTI_EMR_MR22_Msk         (0x1U << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
5462 #define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
5463 #define EXTI_EMR_MR23_Pos         (23U)                                        
5464 #define EXTI_EMR_MR23_Msk         (0x1U << EXTI_EMR_MR23_Pos)                  /*!< 0x00800000 */
5465 #define EXTI_EMR_MR23             EXTI_EMR_MR23_Msk                            /*!< Event Mask on line 23 */
5466 #define EXTI_EMR_MR25_Pos         (25U)                                        
5467 #define EXTI_EMR_MR25_Msk         (0x1U << EXTI_EMR_MR25_Pos)                  /*!< 0x02000000 */
5468 #define EXTI_EMR_MR25             EXTI_EMR_MR25_Msk                            /*!< Event Mask on line 25 */
5469 #define EXTI_EMR_MR27_Pos         (27U)                                        
5470 #define EXTI_EMR_MR27_Msk         (0x1U << EXTI_EMR_MR27_Pos)                  /*!< 0x08000000 */
5471 #define EXTI_EMR_MR27             EXTI_EMR_MR27_Msk                            /*!< Event Mask on line 27 */
5472 #define EXTI_EMR_MR31_Pos         (31U)                                        
5473 #define EXTI_EMR_MR31_Msk         (0x1U << EXTI_EMR_MR31_Pos)                  /*!< 0x80000000 */
5474 #define EXTI_EMR_MR31             EXTI_EMR_MR31_Msk                            /*!< Event Mask on line 31 */
5475
5476 /* References Defines */
5477 #define  EXTI_EMR_EM0 EXTI_EMR_MR0
5478 #define  EXTI_EMR_EM1 EXTI_EMR_MR1
5479 #define  EXTI_EMR_EM2 EXTI_EMR_MR2
5480 #define  EXTI_EMR_EM3 EXTI_EMR_MR3
5481 #define  EXTI_EMR_EM4 EXTI_EMR_MR4
5482 #define  EXTI_EMR_EM5 EXTI_EMR_MR5
5483 #define  EXTI_EMR_EM6 EXTI_EMR_MR6
5484 #define  EXTI_EMR_EM7 EXTI_EMR_MR7
5485 #define  EXTI_EMR_EM8 EXTI_EMR_MR8
5486 #define  EXTI_EMR_EM9 EXTI_EMR_MR9
5487 #define  EXTI_EMR_EM10 EXTI_EMR_MR10
5488 #define  EXTI_EMR_EM11 EXTI_EMR_MR11
5489 #define  EXTI_EMR_EM12 EXTI_EMR_MR12
5490 #define  EXTI_EMR_EM13 EXTI_EMR_MR13
5491 #define  EXTI_EMR_EM14 EXTI_EMR_MR14
5492 #define  EXTI_EMR_EM15 EXTI_EMR_MR15
5493 #define  EXTI_EMR_EM16 EXTI_EMR_MR16
5494 #define  EXTI_EMR_EM17 EXTI_EMR_MR17
5495 #define  EXTI_EMR_EM18 EXTI_EMR_MR18
5496 #define  EXTI_EMR_EM19 EXTI_EMR_MR19
5497 #define  EXTI_EMR_EM21 EXTI_EMR_MR21
5498 #define  EXTI_EMR_EM22 EXTI_EMR_MR22
5499 #define  EXTI_EMR_EM23 EXTI_EMR_MR23
5500 #define  EXTI_EMR_EM25 EXTI_EMR_MR25
5501 #define  EXTI_EMR_EM27 EXTI_EMR_MR27
5502 #define  EXTI_EMR_EM31 EXTI_EMR_MR31
5503
5504 /*******************  Bit definition for EXTI_RTSR register  ******************/
5505 #define EXTI_RTSR_TR0_Pos         (0U)                                         
5506 #define EXTI_RTSR_TR0_Msk         (0x1U << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
5507 #define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
5508 #define EXTI_RTSR_TR1_Pos         (1U)                                         
5509 #define EXTI_RTSR_TR1_Msk         (0x1U << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
5510 #define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
5511 #define EXTI_RTSR_TR2_Pos         (2U)                                         
5512 #define EXTI_RTSR_TR2_Msk         (0x1U << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
5513 #define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
5514 #define EXTI_RTSR_TR3_Pos         (3U)                                         
5515 #define EXTI_RTSR_TR3_Msk         (0x1U << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
5516 #define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
5517 #define EXTI_RTSR_TR4_Pos         (4U)                                         
5518 #define EXTI_RTSR_TR4_Msk         (0x1U << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
5519 #define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
5520 #define EXTI_RTSR_TR5_Pos         (5U)                                         
5521 #define EXTI_RTSR_TR5_Msk         (0x1U << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
5522 #define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
5523 #define EXTI_RTSR_TR6_Pos         (6U)                                         
5524 #define EXTI_RTSR_TR6_Msk         (0x1U << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
5525 #define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
5526 #define EXTI_RTSR_TR7_Pos         (7U)                                         
5527 #define EXTI_RTSR_TR7_Msk         (0x1U << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
5528 #define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
5529 #define EXTI_RTSR_TR8_Pos         (8U)                                         
5530 #define EXTI_RTSR_TR8_Msk         (0x1U << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
5531 #define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
5532 #define EXTI_RTSR_TR9_Pos         (9U)                                         
5533 #define EXTI_RTSR_TR9_Msk         (0x1U << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
5534 #define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
5535 #define EXTI_RTSR_TR10_Pos        (10U)                                        
5536 #define EXTI_RTSR_TR10_Msk        (0x1U << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
5537 #define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
5538 #define EXTI_RTSR_TR11_Pos        (11U)                                        
5539 #define EXTI_RTSR_TR11_Msk        (0x1U << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
5540 #define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
5541 #define EXTI_RTSR_TR12_Pos        (12U)                                        
5542 #define EXTI_RTSR_TR12_Msk        (0x1U << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
5543 #define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
5544 #define EXTI_RTSR_TR13_Pos        (13U)                                        
5545 #define EXTI_RTSR_TR13_Msk        (0x1U << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
5546 #define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
5547 #define EXTI_RTSR_TR14_Pos        (14U)                                        
5548 #define EXTI_RTSR_TR14_Msk        (0x1U << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
5549 #define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
5550 #define EXTI_RTSR_TR15_Pos        (15U)                                        
5551 #define EXTI_RTSR_TR15_Msk        (0x1U << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
5552 #define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
5553 #define EXTI_RTSR_TR16_Pos        (16U)                                        
5554 #define EXTI_RTSR_TR16_Msk        (0x1U << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
5555 #define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
5556 #define EXTI_RTSR_TR17_Pos        (17U)                                        
5557 #define EXTI_RTSR_TR17_Msk        (0x1U << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
5558 #define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
5559 #define EXTI_RTSR_TR19_Pos        (19U)                                        
5560 #define EXTI_RTSR_TR19_Msk        (0x1U << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
5561 #define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
5562 #define EXTI_RTSR_TR21_Pos        (21U)                                        
5563 #define EXTI_RTSR_TR21_Msk        (0x1U << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
5564 #define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
5565 #define EXTI_RTSR_TR22_Pos        (22U)                                        
5566 #define EXTI_RTSR_TR22_Msk        (0x1U << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
5567 #define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
5568 #define EXTI_RTSR_TR31_Pos        (31U)                                        
5569 #define EXTI_RTSR_TR31_Msk        (0x1U << EXTI_RTSR_TR31_Pos)                 /*!< 0x80000000 */
5570 #define EXTI_RTSR_TR31            EXTI_RTSR_TR31_Msk                           /*!< Rising trigger event configuration bit of line 31 */
5571
5572 /* References Defines */
5573 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
5574 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
5575 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
5576 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
5577 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
5578 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
5579 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
5580 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
5581 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
5582 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
5583 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
5584 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
5585 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
5586 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
5587 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
5588 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
5589 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
5590 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
5591 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
5592 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
5593 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
5594 #define  EXTI_RTSR_RT31 EXTI_RTSR_TR31
5595
5596 /*******************  Bit definition for EXTI_FTSR register *******************/
5597 #define EXTI_FTSR_TR0_Pos         (0U)                                         
5598 #define EXTI_FTSR_TR0_Msk         (0x1U << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
5599 #define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
5600 #define EXTI_FTSR_TR1_Pos         (1U)                                         
5601 #define EXTI_FTSR_TR1_Msk         (0x1U << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
5602 #define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
5603 #define EXTI_FTSR_TR2_Pos         (2U)                                         
5604 #define EXTI_FTSR_TR2_Msk         (0x1U << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
5605 #define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
5606 #define EXTI_FTSR_TR3_Pos         (3U)                                         
5607 #define EXTI_FTSR_TR3_Msk         (0x1U << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
5608 #define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
5609 #define EXTI_FTSR_TR4_Pos         (4U)                                         
5610 #define EXTI_FTSR_TR4_Msk         (0x1U << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
5611 #define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
5612 #define EXTI_FTSR_TR5_Pos         (5U)                                         
5613 #define EXTI_FTSR_TR5_Msk         (0x1U << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
5614 #define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
5615 #define EXTI_FTSR_TR6_Pos         (6U)                                         
5616 #define EXTI_FTSR_TR6_Msk         (0x1U << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
5617 #define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
5618 #define EXTI_FTSR_TR7_Pos         (7U)                                         
5619 #define EXTI_FTSR_TR7_Msk         (0x1U << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
5620 #define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
5621 #define EXTI_FTSR_TR8_Pos         (8U)                                         
5622 #define EXTI_FTSR_TR8_Msk         (0x1U << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
5623 #define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
5624 #define EXTI_FTSR_TR9_Pos         (9U)                                         
5625 #define EXTI_FTSR_TR9_Msk         (0x1U << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
5626 #define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
5627 #define EXTI_FTSR_TR10_Pos        (10U)                                        
5628 #define EXTI_FTSR_TR10_Msk        (0x1U << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
5629 #define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
5630 #define EXTI_FTSR_TR11_Pos        (11U)                                        
5631 #define EXTI_FTSR_TR11_Msk        (0x1U << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
5632 #define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
5633 #define EXTI_FTSR_TR12_Pos        (12U)                                        
5634 #define EXTI_FTSR_TR12_Msk        (0x1U << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
5635 #define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
5636 #define EXTI_FTSR_TR13_Pos        (13U)                                        
5637 #define EXTI_FTSR_TR13_Msk        (0x1U << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
5638 #define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
5639 #define EXTI_FTSR_TR14_Pos        (14U)                                        
5640 #define EXTI_FTSR_TR14_Msk        (0x1U << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
5641 #define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
5642 #define EXTI_FTSR_TR15_Pos        (15U)                                        
5643 #define EXTI_FTSR_TR15_Msk        (0x1U << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
5644 #define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
5645 #define EXTI_FTSR_TR16_Pos        (16U)                                        
5646 #define EXTI_FTSR_TR16_Msk        (0x1U << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
5647 #define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
5648 #define EXTI_FTSR_TR17_Pos        (17U)                                        
5649 #define EXTI_FTSR_TR17_Msk        (0x1U << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
5650 #define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
5651 #define EXTI_FTSR_TR19_Pos        (19U)                                        
5652 #define EXTI_FTSR_TR19_Msk        (0x1U << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
5653 #define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
5654 #define EXTI_FTSR_TR21_Pos        (21U)                                        
5655 #define EXTI_FTSR_TR21_Msk        (0x1U << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
5656 #define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
5657 #define EXTI_FTSR_TR22_Pos        (22U)                                        
5658 #define EXTI_FTSR_TR22_Msk        (0x1U << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
5659 #define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
5660 #define EXTI_FTSR_TR31_Pos        (31U)                                        
5661 #define EXTI_FTSR_TR31_Msk        (0x1U << EXTI_FTSR_TR31_Pos)                 /*!< 0x80000000 */
5662 #define EXTI_FTSR_TR31            EXTI_FTSR_TR31_Msk                           /*!< Falling trigger event configuration bit of line 31 */
5663
5664 /* References Defines */
5665 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
5666 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
5667 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
5668 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
5669 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
5670 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
5671 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
5672 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
5673 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
5674 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
5675 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
5676 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
5677 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
5678 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
5679 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
5680 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
5681 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
5682 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
5683 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
5684 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
5685 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
5686 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31
5687
5688 /******************* Bit definition for EXTI_SWIER register *******************/
5689 #define EXTI_SWIER_SWIER0_Pos     (0U)                                         
5690 #define EXTI_SWIER_SWIER0_Msk     (0x1U << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
5691 #define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0  */
5692 #define EXTI_SWIER_SWIER1_Pos     (1U)                                         
5693 #define EXTI_SWIER_SWIER1_Msk     (0x1U << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
5694 #define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1  */
5695 #define EXTI_SWIER_SWIER2_Pos     (2U)                                         
5696 #define EXTI_SWIER_SWIER2_Msk     (0x1U << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
5697 #define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2  */
5698 #define EXTI_SWIER_SWIER3_Pos     (3U)                                         
5699 #define EXTI_SWIER_SWIER3_Msk     (0x1U << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
5700 #define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3  */
5701 #define EXTI_SWIER_SWIER4_Pos     (4U)                                         
5702 #define EXTI_SWIER_SWIER4_Msk     (0x1U << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
5703 #define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4  */
5704 #define EXTI_SWIER_SWIER5_Pos     (5U)                                         
5705 #define EXTI_SWIER_SWIER5_Msk     (0x1U << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
5706 #define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5  */
5707 #define EXTI_SWIER_SWIER6_Pos     (6U)                                         
5708 #define EXTI_SWIER_SWIER6_Msk     (0x1U << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
5709 #define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6  */
5710 #define EXTI_SWIER_SWIER7_Pos     (7U)                                         
5711 #define EXTI_SWIER_SWIER7_Msk     (0x1U << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
5712 #define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7  */
5713 #define EXTI_SWIER_SWIER8_Pos     (8U)                                         
5714 #define EXTI_SWIER_SWIER8_Msk     (0x1U << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
5715 #define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8  */
5716 #define EXTI_SWIER_SWIER9_Pos     (9U)                                         
5717 #define EXTI_SWIER_SWIER9_Msk     (0x1U << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
5718 #define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9  */
5719 #define EXTI_SWIER_SWIER10_Pos    (10U)                                        
5720 #define EXTI_SWIER_SWIER10_Msk    (0x1U << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
5721 #define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
5722 #define EXTI_SWIER_SWIER11_Pos    (11U)                                        
5723 #define EXTI_SWIER_SWIER11_Msk    (0x1U << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
5724 #define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
5725 #define EXTI_SWIER_SWIER12_Pos    (12U)                                        
5726 #define EXTI_SWIER_SWIER12_Msk    (0x1U << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
5727 #define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
5728 #define EXTI_SWIER_SWIER13_Pos    (13U)                                        
5729 #define EXTI_SWIER_SWIER13_Msk    (0x1U << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
5730 #define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
5731 #define EXTI_SWIER_SWIER14_Pos    (14U)                                        
5732 #define EXTI_SWIER_SWIER14_Msk    (0x1U << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
5733 #define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
5734 #define EXTI_SWIER_SWIER15_Pos    (15U)                                        
5735 #define EXTI_SWIER_SWIER15_Msk    (0x1U << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
5736 #define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
5737 #define EXTI_SWIER_SWIER16_Pos    (16U)                                        
5738 #define EXTI_SWIER_SWIER16_Msk    (0x1U << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
5739 #define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
5740 #define EXTI_SWIER_SWIER17_Pos    (17U)                                        
5741 #define EXTI_SWIER_SWIER17_Msk    (0x1U << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
5742 #define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
5743 #define EXTI_SWIER_SWIER19_Pos    (19U)                                        
5744 #define EXTI_SWIER_SWIER19_Msk    (0x1U << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
5745 #define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
5746 #define EXTI_SWIER_SWIER21_Pos    (21U)                                        
5747 #define EXTI_SWIER_SWIER21_Msk    (0x1U << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
5748 #define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
5749 #define EXTI_SWIER_SWIER22_Pos    (22U)                                        
5750 #define EXTI_SWIER_SWIER22_Msk    (0x1U << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
5751 #define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
5752 #define EXTI_SWIER_SWIER31_Pos    (31U)                                        
5753 #define EXTI_SWIER_SWIER31_Msk    (0x1U << EXTI_SWIER_SWIER31_Pos)             /*!< 0x80000000 */
5754 #define EXTI_SWIER_SWIER31        EXTI_SWIER_SWIER31_Msk                       /*!< Software Interrupt on line 31 */
5755
5756 /* References Defines */
5757 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
5758 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
5759 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
5760 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
5761 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
5762 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
5763 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
5764 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
5765 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
5766 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
5767 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
5768 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
5769 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
5770 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
5771 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
5772 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
5773 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
5774 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
5775 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
5776 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
5777 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
5778 #define  EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
5779
5780 /******************  Bit definition for EXTI_PR register  *********************/
5781 #define EXTI_PR_PR0_Pos           (0U)                                         
5782 #define EXTI_PR_PR0_Msk           (0x1U << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
5783 #define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit 0  */
5784 #define EXTI_PR_PR1_Pos           (1U)                                         
5785 #define EXTI_PR_PR1_Msk           (0x1U << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
5786 #define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit 1  */
5787 #define EXTI_PR_PR2_Pos           (2U)                                         
5788 #define EXTI_PR_PR2_Msk           (0x1U << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
5789 #define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit 2  */
5790 #define EXTI_PR_PR3_Pos           (3U)                                         
5791 #define EXTI_PR_PR3_Msk           (0x1U << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
5792 #define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit 3  */
5793 #define EXTI_PR_PR4_Pos           (4U)                                         
5794 #define EXTI_PR_PR4_Msk           (0x1U << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
5795 #define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit 4  */
5796 #define EXTI_PR_PR5_Pos           (5U)                                         
5797 #define EXTI_PR_PR5_Msk           (0x1U << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
5798 #define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit 5  */
5799 #define EXTI_PR_PR6_Pos           (6U)                                         
5800 #define EXTI_PR_PR6_Msk           (0x1U << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
5801 #define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit 6  */
5802 #define EXTI_PR_PR7_Pos           (7U)                                         
5803 #define EXTI_PR_PR7_Msk           (0x1U << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
5804 #define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit 7  */
5805 #define EXTI_PR_PR8_Pos           (8U)                                         
5806 #define EXTI_PR_PR8_Msk           (0x1U << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
5807 #define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit 8  */
5808 #define EXTI_PR_PR9_Pos           (9U)                                         
5809 #define EXTI_PR_PR9_Msk           (0x1U << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
5810 #define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit 9  */
5811 #define EXTI_PR_PR10_Pos          (10U)                                        
5812 #define EXTI_PR_PR10_Msk          (0x1U << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
5813 #define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit 10 */
5814 #define EXTI_PR_PR11_Pos          (11U)                                        
5815 #define EXTI_PR_PR11_Msk          (0x1U << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
5816 #define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit 11 */
5817 #define EXTI_PR_PR12_Pos          (12U)                                        
5818 #define EXTI_PR_PR12_Msk          (0x1U << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
5819 #define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit 12 */
5820 #define EXTI_PR_PR13_Pos          (13U)                                        
5821 #define EXTI_PR_PR13_Msk          (0x1U << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
5822 #define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit 13 */
5823 #define EXTI_PR_PR14_Pos          (14U)                                        
5824 #define EXTI_PR_PR14_Msk          (0x1U << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
5825 #define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit 14 */
5826 #define EXTI_PR_PR15_Pos          (15U)                                        
5827 #define EXTI_PR_PR15_Msk          (0x1U << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
5828 #define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit 15 */
5829 #define EXTI_PR_PR16_Pos          (16U)                                        
5830 #define EXTI_PR_PR16_Msk          (0x1U << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
5831 #define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit 16 */
5832 #define EXTI_PR_PR17_Pos          (17U)                                        
5833 #define EXTI_PR_PR17_Msk          (0x1U << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
5834 #define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit 17 */
5835 #define EXTI_PR_PR19_Pos          (19U)                                        
5836 #define EXTI_PR_PR19_Msk          (0x1U << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
5837 #define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit 19 */
5838 #define EXTI_PR_PR21_Pos          (21U)                                        
5839 #define EXTI_PR_PR21_Msk          (0x1U << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
5840 #define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit 21 */
5841 #define EXTI_PR_PR22_Pos          (22U)                                        
5842 #define EXTI_PR_PR22_Msk          (0x1U << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
5843 #define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit 22 */
5844 #define EXTI_PR_PR31_Pos          (31U)                                        
5845 #define EXTI_PR_PR31_Msk          (0x1U << EXTI_PR_PR31_Pos)                   /*!< 0x80000000 */
5846 #define EXTI_PR_PR31              EXTI_PR_PR31_Msk                             /*!< Pending bit 31 */
5847
5848 /* References Defines */
5849 #define EXTI_PR_PIF0 EXTI_PR_PR0
5850 #define EXTI_PR_PIF1 EXTI_PR_PR1
5851 #define EXTI_PR_PIF2 EXTI_PR_PR2
5852 #define EXTI_PR_PIF3 EXTI_PR_PR3
5853 #define EXTI_PR_PIF4 EXTI_PR_PR4
5854 #define EXTI_PR_PIF5 EXTI_PR_PR5
5855 #define EXTI_PR_PIF6 EXTI_PR_PR6
5856 #define EXTI_PR_PIF7 EXTI_PR_PR7
5857 #define EXTI_PR_PIF8 EXTI_PR_PR8
5858 #define EXTI_PR_PIF9 EXTI_PR_PR9
5859 #define EXTI_PR_PIF10 EXTI_PR_PR10
5860 #define EXTI_PR_PIF11 EXTI_PR_PR11
5861 #define EXTI_PR_PIF12 EXTI_PR_PR12
5862 #define EXTI_PR_PIF13 EXTI_PR_PR13
5863 #define EXTI_PR_PIF14 EXTI_PR_PR14
5864 #define EXTI_PR_PIF15 EXTI_PR_PR15
5865 #define EXTI_PR_PIF16 EXTI_PR_PR16
5866 #define EXTI_PR_PIF17 EXTI_PR_PR17
5867 #define EXTI_PR_PIF19 EXTI_PR_PR19
5868 #define EXTI_PR_PIF21 EXTI_PR_PR21
5869 #define EXTI_PR_PIF22 EXTI_PR_PR22
5870 #define EXTI_PR_PIF31 EXTI_PR_PR31
5871
5872 /******************************************************************************/
5873 /*                                                                            */
5874 /*                      FLASH and Option Bytes Registers                      */
5875 /*                                                                            */
5876 /******************************************************************************/
5877
5878 /*******************  Bit definition for FLASH_ACR register  ******************/
5879 #define FLASH_ACR_LATENCY_Pos             (0U)                                 
5880 #define FLASH_ACR_LATENCY_Msk             (0x1U << FLASH_ACR_LATENCY_Pos)      /*!< 0x00000001 */
5881 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk                /*!< LATENCY bit (Latency) */
5882
5883 #define FLASH_ACR_PRFTBE_Pos              (4U)                                 
5884 #define FLASH_ACR_PRFTBE_Msk              (0x1U << FLASH_ACR_PRFTBE_Pos)       /*!< 0x00000010 */
5885 #define FLASH_ACR_PRFTBE                  FLASH_ACR_PRFTBE_Msk                 /*!< Prefetch Buffer Enable */
5886 #define FLASH_ACR_PRFTBS_Pos              (5U)                                 
5887 #define FLASH_ACR_PRFTBS_Msk              (0x1U << FLASH_ACR_PRFTBS_Pos)       /*!< 0x00000020 */
5888 #define FLASH_ACR_PRFTBS                  FLASH_ACR_PRFTBS_Msk                 /*!< Prefetch Buffer Status */
5889
5890 /******************  Bit definition for FLASH_KEYR register  ******************/
5891 #define FLASH_KEYR_FKEYR_Pos              (0U)                                 
5892 #define FLASH_KEYR_FKEYR_Msk              (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
5893 #define FLASH_KEYR_FKEYR                  FLASH_KEYR_FKEYR_Msk                 /*!< FPEC Key */
5894
5895 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
5896 #define FLASH_OPTKEYR_OPTKEYR_Pos         (0U)                                 
5897 #define FLASH_OPTKEYR_OPTKEYR_Msk         (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
5898 #define FLASH_OPTKEYR_OPTKEYR             FLASH_OPTKEYR_OPTKEYR_Msk            /*!< Option Byte Key */
5899
5900 /******************  FLASH Keys  **********************************************/
5901 #define FLASH_KEY1_Pos                    (0U)                                 
5902 #define FLASH_KEY1_Msk                    (0x45670123U << FLASH_KEY1_Pos)      /*!< 0x45670123 */
5903 #define FLASH_KEY1                        FLASH_KEY1_Msk                       /*!< Flash program erase key1 */
5904 #define FLASH_KEY2_Pos                    (0U)                                 
5905 #define FLASH_KEY2_Msk                    (0xCDEF89ABU << FLASH_KEY2_Pos)      /*!< 0xCDEF89AB */
5906 #define FLASH_KEY2                        FLASH_KEY2_Msk                       /*!< Flash program erase key2: used with FLASH_PEKEY1
5907                                                                                 to unlock the write access to the FPEC. */
5908                                                                
5909 #define FLASH_OPTKEY1_Pos                 (0U)                                 
5910 #define FLASH_OPTKEY1_Msk                 (0x45670123U << FLASH_OPTKEY1_Pos)   /*!< 0x45670123 */
5911 #define FLASH_OPTKEY1                     FLASH_OPTKEY1_Msk                    /*!< Flash option key1 */
5912 #define FLASH_OPTKEY2_Pos                 (0U)                                 
5913 #define FLASH_OPTKEY2_Msk                 (0xCDEF89ABU << FLASH_OPTKEY2_Pos)   /*!< 0xCDEF89AB */
5914 #define FLASH_OPTKEY2                     FLASH_OPTKEY2_Msk                    /*!< Flash option key2: used with FLASH_OPTKEY1 to
5915                                                                                 unlock the write access to the option byte block */
5916
5917 /******************  Bit definition for FLASH_SR register  *******************/
5918 #define FLASH_SR_BSY_Pos                  (0U)                                 
5919 #define FLASH_SR_BSY_Msk                  (0x1U << FLASH_SR_BSY_Pos)           /*!< 0x00000001 */
5920 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk                     /*!< Busy */
5921 #define FLASH_SR_PGERR_Pos                (2U)                                 
5922 #define FLASH_SR_PGERR_Msk                (0x1U << FLASH_SR_PGERR_Pos)         /*!< 0x00000004 */
5923 #define FLASH_SR_PGERR                    FLASH_SR_PGERR_Msk                   /*!< Programming Error */
5924 #define FLASH_SR_WRPRTERR_Pos             (4U)                                 
5925 #define FLASH_SR_WRPRTERR_Msk             (0x1U << FLASH_SR_WRPRTERR_Pos)      /*!< 0x00000010 */
5926 #define FLASH_SR_WRPRTERR                 FLASH_SR_WRPRTERR_Msk                /*!< Write Protection Error */
5927 #define FLASH_SR_EOP_Pos                  (5U)                                 
5928 #define FLASH_SR_EOP_Msk                  (0x1U << FLASH_SR_EOP_Pos)           /*!< 0x00000020 */
5929 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk                     /*!< End of operation */
5930 #define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */
5931
5932 /*******************  Bit definition for FLASH_CR register  *******************/
5933 #define FLASH_CR_PG_Pos                   (0U)                                 
5934 #define FLASH_CR_PG_Msk                   (0x1U << FLASH_CR_PG_Pos)            /*!< 0x00000001 */
5935 #define FLASH_CR_PG                       FLASH_CR_PG_Msk                      /*!< Programming */
5936 #define FLASH_CR_PER_Pos                  (1U)                                 
5937 #define FLASH_CR_PER_Msk                  (0x1U << FLASH_CR_PER_Pos)           /*!< 0x00000002 */
5938 #define FLASH_CR_PER                      FLASH_CR_PER_Msk                     /*!< Page Erase */
5939 #define FLASH_CR_MER_Pos                  (2U)                                 
5940 #define FLASH_CR_MER_Msk                  (0x1U << FLASH_CR_MER_Pos)           /*!< 0x00000004 */
5941 #define FLASH_CR_MER                      FLASH_CR_MER_Msk                     /*!< Mass Erase */
5942 #define FLASH_CR_OPTPG_Pos                (4U)                                 
5943 #define FLASH_CR_OPTPG_Msk                (0x1U << FLASH_CR_OPTPG_Pos)         /*!< 0x00000010 */
5944 #define FLASH_CR_OPTPG                    FLASH_CR_OPTPG_Msk                   /*!< Option Byte Programming */
5945 #define FLASH_CR_OPTER_Pos                (5U)                                 
5946 #define FLASH_CR_OPTER_Msk                (0x1U << FLASH_CR_OPTER_Pos)         /*!< 0x00000020 */
5947 #define FLASH_CR_OPTER                    FLASH_CR_OPTER_Msk                   /*!< Option Byte Erase */
5948 #define FLASH_CR_STRT_Pos                 (6U)                                 
5949 #define FLASH_CR_STRT_Msk                 (0x1U << FLASH_CR_STRT_Pos)          /*!< 0x00000040 */
5950 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk                    /*!< Start */
5951 #define FLASH_CR_LOCK_Pos                 (7U)                                 
5952 #define FLASH_CR_LOCK_Msk                 (0x1U << FLASH_CR_LOCK_Pos)          /*!< 0x00000080 */
5953 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk                    /*!< Lock */
5954 #define FLASH_CR_OPTWRE_Pos               (9U)                                 
5955 #define FLASH_CR_OPTWRE_Msk               (0x1U << FLASH_CR_OPTWRE_Pos)        /*!< 0x00000200 */
5956 #define FLASH_CR_OPTWRE                   FLASH_CR_OPTWRE_Msk                  /*!< Option Bytes Write Enable */
5957 #define FLASH_CR_ERRIE_Pos                (10U)                                
5958 #define FLASH_CR_ERRIE_Msk                (0x1U << FLASH_CR_ERRIE_Pos)         /*!< 0x00000400 */
5959 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk                   /*!< Error Interrupt Enable */
5960 #define FLASH_CR_EOPIE_Pos                (12U)                                
5961 #define FLASH_CR_EOPIE_Msk                (0x1U << FLASH_CR_EOPIE_Pos)         /*!< 0x00001000 */
5962 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk                   /*!< End of operation interrupt enable */
5963 #define FLASH_CR_OBL_LAUNCH_Pos           (13U)                                
5964 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1U << FLASH_CR_OBL_LAUNCH_Pos)    /*!< 0x00002000 */
5965 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk              /*!< Option Bytes Loader Launch */
5966
5967 /*******************  Bit definition for FLASH_AR register  *******************/
5968 #define FLASH_AR_FAR_Pos                  (0U)                                 
5969 #define FLASH_AR_FAR_Msk                  (0xFFFFFFFFU << FLASH_AR_FAR_Pos)    /*!< 0xFFFFFFFF */
5970 #define FLASH_AR_FAR                      FLASH_AR_FAR_Msk                     /*!< Flash Address */
5971
5972 /******************  Bit definition for FLASH_OBR register  *******************/
5973 #define FLASH_OBR_OPTERR_Pos              (0U)                                 
5974 #define FLASH_OBR_OPTERR_Msk              (0x1U << FLASH_OBR_OPTERR_Pos)       /*!< 0x00000001 */
5975 #define FLASH_OBR_OPTERR                  FLASH_OBR_OPTERR_Msk                 /*!< Option Byte Error */
5976 #define FLASH_OBR_RDPRT1_Pos              (1U)                                 
5977 #define FLASH_OBR_RDPRT1_Msk              (0x1U << FLASH_OBR_RDPRT1_Pos)       /*!< 0x00000002 */
5978 #define FLASH_OBR_RDPRT1                  FLASH_OBR_RDPRT1_Msk                 /*!< Read protection Level 1 */
5979 #define FLASH_OBR_RDPRT2_Pos              (2U)                                 
5980 #define FLASH_OBR_RDPRT2_Msk              (0x1U << FLASH_OBR_RDPRT2_Pos)       /*!< 0x00000004 */
5981 #define FLASH_OBR_RDPRT2                  FLASH_OBR_RDPRT2_Msk                 /*!< Read protection Level 2 */
5982
5983 #define FLASH_OBR_USER_Pos                (8U)                                 
5984 #define FLASH_OBR_USER_Msk                (0xFFU << FLASH_OBR_USER_Pos)        /*!< 0x0000FF00 */
5985 #define FLASH_OBR_USER                    FLASH_OBR_USER_Msk                   /*!< User Option Bytes */
5986 #define FLASH_OBR_IWDG_SW_Pos             (8U)                                 
5987 #define FLASH_OBR_IWDG_SW_Msk             (0x1U << FLASH_OBR_IWDG_SW_Pos)      /*!< 0x00000100 */
5988 #define FLASH_OBR_IWDG_SW                 FLASH_OBR_IWDG_SW_Msk                /*!< IWDG SW */
5989 #define FLASH_OBR_nRST_STOP_Pos           (9U)                                 
5990 #define FLASH_OBR_nRST_STOP_Msk           (0x1U << FLASH_OBR_nRST_STOP_Pos)    /*!< 0x00000200 */
5991 #define FLASH_OBR_nRST_STOP               FLASH_OBR_nRST_STOP_Msk              /*!< nRST_STOP */
5992 #define FLASH_OBR_nRST_STDBY_Pos          (10U)                                
5993 #define FLASH_OBR_nRST_STDBY_Msk          (0x1U << FLASH_OBR_nRST_STDBY_Pos)   /*!< 0x00000400 */
5994 #define FLASH_OBR_nRST_STDBY              FLASH_OBR_nRST_STDBY_Msk             /*!< nRST_STDBY */
5995 #define FLASH_OBR_nBOOT0_Pos              (11U)                                
5996 #define FLASH_OBR_nBOOT0_Msk              (0x1U << FLASH_OBR_nBOOT0_Pos)       /*!< 0x00000800 */
5997 #define FLASH_OBR_nBOOT0                  FLASH_OBR_nBOOT0_Msk                 /*!< nBOOT0 */
5998 #define FLASH_OBR_nBOOT1_Pos              (12U)                                
5999 #define FLASH_OBR_nBOOT1_Msk              (0x1U << FLASH_OBR_nBOOT1_Pos)       /*!< 0x00001000 */
6000 #define FLASH_OBR_nBOOT1                  FLASH_OBR_nBOOT1_Msk                 /*!< nBOOT1 */
6001 #define FLASH_OBR_VDDA_MONITOR_Pos        (13U)                                
6002 #define FLASH_OBR_VDDA_MONITOR_Msk        (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
6003 #define FLASH_OBR_VDDA_MONITOR            FLASH_OBR_VDDA_MONITOR_Msk           /*!< VDDA power supply supervisor */
6004 #define FLASH_OBR_RAM_PARITY_CHECK_Pos    (14U)                                
6005 #define FLASH_OBR_RAM_PARITY_CHECK_Msk    (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */
6006 #define FLASH_OBR_RAM_PARITY_CHECK        FLASH_OBR_RAM_PARITY_CHECK_Msk       /*!< RAM parity check */
6007 #define FLASH_OBR_BOOT_SEL_Pos            (15U)                                
6008 #define FLASH_OBR_BOOT_SEL_Msk            (0x1U << FLASH_OBR_BOOT_SEL_Pos)     /*!< 0x00008000 */
6009 #define FLASH_OBR_BOOT_SEL                FLASH_OBR_BOOT_SEL_Msk               /*!< BOOT selection */
6010 #define FLASH_OBR_DATA0_Pos               (16U)                                
6011 #define FLASH_OBR_DATA0_Msk               (0xFFU << FLASH_OBR_DATA0_Pos)       /*!< 0x00FF0000 */
6012 #define FLASH_OBR_DATA0                   FLASH_OBR_DATA0_Msk                  /*!< Data0 */
6013 #define FLASH_OBR_DATA1_Pos               (24U)                                
6014 #define FLASH_OBR_DATA1_Msk               (0xFFU << FLASH_OBR_DATA1_Pos)       /*!< 0xFF000000 */
6015 #define FLASH_OBR_DATA1                   FLASH_OBR_DATA1_Msk                  /*!< Data1 */
6016
6017 /* Old BOOT1 bit definition, maintained for legacy purpose */
6018 #define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
6019
6020 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
6021 #define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
6022
6023 /******************  Bit definition for FLASH_WRPR register  ******************/
6024 #define FLASH_WRPR_WRP_Pos                (0U)                                 
6025 #define FLASH_WRPR_WRP_Msk                (0xFFFFU << FLASH_WRPR_WRP_Pos)      /*!< 0x0000FFFF */
6026 #define FLASH_WRPR_WRP                    FLASH_WRPR_WRP_Msk                   /*!< Write Protect */
6027
6028 /*----------------------------------------------------------------------------*/
6029
6030 /******************  Bit definition for OB_RDP register  **********************/
6031 #define OB_RDP_RDP_Pos       (0U)                                              
6032 #define OB_RDP_RDP_Msk       (0xFFU << OB_RDP_RDP_Pos)                         /*!< 0x000000FF */
6033 #define OB_RDP_RDP           OB_RDP_RDP_Msk                                    /*!< Read protection option byte */
6034 #define OB_RDP_nRDP_Pos      (8U)                                              
6035 #define OB_RDP_nRDP_Msk      (0xFFU << OB_RDP_nRDP_Pos)                        /*!< 0x0000FF00 */
6036 #define OB_RDP_nRDP          OB_RDP_nRDP_Msk                                   /*!< Read protection complemented option byte */
6037
6038 /******************  Bit definition for OB_USER register  *********************/
6039 #define OB_USER_USER_Pos     (16U)                                             
6040 #define OB_USER_USER_Msk     (0xFFU << OB_USER_USER_Pos)                       /*!< 0x00FF0000 */
6041 #define OB_USER_USER         OB_USER_USER_Msk                                  /*!< User option byte */
6042 #define OB_USER_nUSER_Pos    (24U)                                             
6043 #define OB_USER_nUSER_Msk    (0xFFU << OB_USER_nUSER_Pos)                      /*!< 0xFF000000 */
6044 #define OB_USER_nUSER        OB_USER_nUSER_Msk                                 /*!< User complemented option byte */
6045
6046 /******************  Bit definition for OB_WRP0 register  *********************/
6047 #define OB_WRP0_WRP0_Pos     (0U)                                              
6048 #define OB_WRP0_WRP0_Msk     (0xFFU << OB_WRP0_WRP0_Pos)                       /*!< 0x000000FF */
6049 #define OB_WRP0_WRP0         OB_WRP0_WRP0_Msk                                  /*!< Flash memory write protection option bytes */
6050 #define OB_WRP0_nWRP0_Pos    (8U)                                              
6051 #define OB_WRP0_nWRP0_Msk    (0xFFU << OB_WRP0_nWRP0_Pos)                      /*!< 0x0000FF00 */
6052 #define OB_WRP0_nWRP0        OB_WRP0_nWRP0_Msk                                 /*!< Flash memory write protection complemented option bytes */
6053
6054 /******************************************************************************/
6055 /*                                                                            */
6056 /*                       General Purpose IOs (GPIO)                           */
6057 /*                                                                            */
6058 /******************************************************************************/
6059 /*******************  Bit definition for GPIO_MODER register  *****************/
6060 #define GPIO_MODER_MODER0_Pos           (0U)                                   
6061 #define GPIO_MODER_MODER0_Msk           (0x3U << GPIO_MODER_MODER0_Pos)        /*!< 0x00000003 */
6062 #define GPIO_MODER_MODER0               GPIO_MODER_MODER0_Msk                  
6063 #define GPIO_MODER_MODER0_0             (0x1U << GPIO_MODER_MODER0_Pos)        /*!< 0x00000001 */
6064 #define GPIO_MODER_MODER0_1             (0x2U << GPIO_MODER_MODER0_Pos)        /*!< 0x00000002 */
6065 #define GPIO_MODER_MODER1_Pos           (2U)                                   
6066 #define GPIO_MODER_MODER1_Msk           (0x3U << GPIO_MODER_MODER1_Pos)        /*!< 0x0000000C */
6067 #define GPIO_MODER_MODER1               GPIO_MODER_MODER1_Msk                  
6068 #define GPIO_MODER_MODER1_0             (0x1U << GPIO_MODER_MODER1_Pos)        /*!< 0x00000004 */
6069 #define GPIO_MODER_MODER1_1             (0x2U << GPIO_MODER_MODER1_Pos)        /*!< 0x00000008 */
6070 #define GPIO_MODER_MODER2_Pos           (4U)                                   
6071 #define GPIO_MODER_MODER2_Msk           (0x3U << GPIO_MODER_MODER2_Pos)        /*!< 0x00000030 */
6072 #define GPIO_MODER_MODER2               GPIO_MODER_MODER2_Msk                  
6073 #define GPIO_MODER_MODER2_0             (0x1U << GPIO_MODER_MODER2_Pos)        /*!< 0x00000010 */
6074 #define GPIO_MODER_MODER2_1             (0x2U << GPIO_MODER_MODER2_Pos)        /*!< 0x00000020 */
6075 #define GPIO_MODER_MODER3_Pos           (6U)                                   
6076 #define GPIO_MODER_MODER3_Msk           (0x3U << GPIO_MODER_MODER3_Pos)        /*!< 0x000000C0 */
6077 #define GPIO_MODER_MODER3               GPIO_MODER_MODER3_Msk                  
6078 #define GPIO_MODER_MODER3_0             (0x1U << GPIO_MODER_MODER3_Pos)        /*!< 0x00000040 */
6079 #define GPIO_MODER_MODER3_1             (0x2U << GPIO_MODER_MODER3_Pos)        /*!< 0x00000080 */
6080 #define GPIO_MODER_MODER4_Pos           (8U)                                   
6081 #define GPIO_MODER_MODER4_Msk           (0x3U << GPIO_MODER_MODER4_Pos)        /*!< 0x00000300 */
6082 #define GPIO_MODER_MODER4               GPIO_MODER_MODER4_Msk                  
6083 #define GPIO_MODER_MODER4_0             (0x1U << GPIO_MODER_MODER4_Pos)        /*!< 0x00000100 */
6084 #define GPIO_MODER_MODER4_1             (0x2U << GPIO_MODER_MODER4_Pos)        /*!< 0x00000200 */
6085 #define GPIO_MODER_MODER5_Pos           (10U)                                  
6086 #define GPIO_MODER_MODER5_Msk           (0x3U << GPIO_MODER_MODER5_Pos)        /*!< 0x00000C00 */
6087 #define GPIO_MODER_MODER5               GPIO_MODER_MODER5_Msk                  
6088 #define GPIO_MODER_MODER5_0             (0x1U << GPIO_MODER_MODER5_Pos)        /*!< 0x00000400 */
6089 #define GPIO_MODER_MODER5_1             (0x2U << GPIO_MODER_MODER5_Pos)        /*!< 0x00000800 */
6090 #define GPIO_MODER_MODER6_Pos           (12U)                                  
6091 #define GPIO_MODER_MODER6_Msk           (0x3U << GPIO_MODER_MODER6_Pos)        /*!< 0x00003000 */
6092 #define GPIO_MODER_MODER6               GPIO_MODER_MODER6_Msk                  
6093 #define GPIO_MODER_MODER6_0             (0x1U << GPIO_MODER_MODER6_Pos)        /*!< 0x00001000 */
6094 #define GPIO_MODER_MODER6_1             (0x2U << GPIO_MODER_MODER6_Pos)        /*!< 0x00002000 */
6095 #define GPIO_MODER_MODER7_Pos           (14U)                                  
6096 #define GPIO_MODER_MODER7_Msk           (0x3U << GPIO_MODER_MODER7_Pos)        /*!< 0x0000C000 */
6097 #define GPIO_MODER_MODER7               GPIO_MODER_MODER7_Msk                  
6098 #define GPIO_MODER_MODER7_0             (0x1U << GPIO_MODER_MODER7_Pos)        /*!< 0x00004000 */
6099 #define GPIO_MODER_MODER7_1             (0x2U << GPIO_MODER_MODER7_Pos)        /*!< 0x00008000 */
6100 #define GPIO_MODER_MODER8_Pos           (16U)                                  
6101 #define GPIO_MODER_MODER8_Msk           (0x3U << GPIO_MODER_MODER8_Pos)        /*!< 0x00030000 */
6102 #define GPIO_MODER_MODER8               GPIO_MODER_MODER8_Msk                  
6103 #define GPIO_MODER_MODER8_0             (0x1U << GPIO_MODER_MODER8_Pos)        /*!< 0x00010000 */
6104 #define GPIO_MODER_MODER8_1             (0x2U << GPIO_MODER_MODER8_Pos)        /*!< 0x00020000 */
6105 #define GPIO_MODER_MODER9_Pos           (18U)                                  
6106 #define GPIO_MODER_MODER9_Msk           (0x3U << GPIO_MODER_MODER9_Pos)        /*!< 0x000C0000 */
6107 #define GPIO_MODER_MODER9               GPIO_MODER_MODER9_Msk                  
6108 #define GPIO_MODER_MODER9_0             (0x1U << GPIO_MODER_MODER9_Pos)        /*!< 0x00040000 */
6109 #define GPIO_MODER_MODER9_1             (0x2U << GPIO_MODER_MODER9_Pos)        /*!< 0x00080000 */
6110 #define GPIO_MODER_MODER10_Pos          (20U)                                  
6111 #define GPIO_MODER_MODER10_Msk          (0x3U << GPIO_MODER_MODER10_Pos)       /*!< 0x00300000 */
6112 #define GPIO_MODER_MODER10              GPIO_MODER_MODER10_Msk                 
6113 #define GPIO_MODER_MODER10_0            (0x1U << GPIO_MODER_MODER10_Pos)       /*!< 0x00100000 */
6114 #define GPIO_MODER_MODER10_1            (0x2U << GPIO_MODER_MODER10_Pos)       /*!< 0x00200000 */
6115 #define GPIO_MODER_MODER11_Pos          (22U)                                  
6116 #define GPIO_MODER_MODER11_Msk          (0x3U << GPIO_MODER_MODER11_Pos)       /*!< 0x00C00000 */
6117 #define GPIO_MODER_MODER11              GPIO_MODER_MODER11_Msk                 
6118 #define GPIO_MODER_MODER11_0            (0x1U << GPIO_MODER_MODER11_Pos)       /*!< 0x00400000 */
6119 #define GPIO_MODER_MODER11_1            (0x2U << GPIO_MODER_MODER11_Pos)       /*!< 0x00800000 */
6120 #define GPIO_MODER_MODER12_Pos          (24U)                                  
6121 #define GPIO_MODER_MODER12_Msk          (0x3U << GPIO_MODER_MODER12_Pos)       /*!< 0x03000000 */
6122 #define GPIO_MODER_MODER12              GPIO_MODER_MODER12_Msk                 
6123 #define GPIO_MODER_MODER12_0            (0x1U << GPIO_MODER_MODER12_Pos)       /*!< 0x01000000 */
6124 #define GPIO_MODER_MODER12_1            (0x2U << GPIO_MODER_MODER12_Pos)       /*!< 0x02000000 */
6125 #define GPIO_MODER_MODER13_Pos          (26U)                                  
6126 #define GPIO_MODER_MODER13_Msk          (0x3U << GPIO_MODER_MODER13_Pos)       /*!< 0x0C000000 */
6127 #define GPIO_MODER_MODER13              GPIO_MODER_MODER13_Msk                 
6128 #define GPIO_MODER_MODER13_0            (0x1U << GPIO_MODER_MODER13_Pos)       /*!< 0x04000000 */
6129 #define GPIO_MODER_MODER13_1            (0x2U << GPIO_MODER_MODER13_Pos)       /*!< 0x08000000 */
6130 #define GPIO_MODER_MODER14_Pos          (28U)                                  
6131 #define GPIO_MODER_MODER14_Msk          (0x3U << GPIO_MODER_MODER14_Pos)       /*!< 0x30000000 */
6132 #define GPIO_MODER_MODER14              GPIO_MODER_MODER14_Msk                 
6133 #define GPIO_MODER_MODER14_0            (0x1U << GPIO_MODER_MODER14_Pos)       /*!< 0x10000000 */
6134 #define GPIO_MODER_MODER14_1            (0x2U << GPIO_MODER_MODER14_Pos)       /*!< 0x20000000 */
6135 #define GPIO_MODER_MODER15_Pos          (30U)                                  
6136 #define GPIO_MODER_MODER15_Msk          (0x3U << GPIO_MODER_MODER15_Pos)       /*!< 0xC0000000 */
6137 #define GPIO_MODER_MODER15              GPIO_MODER_MODER15_Msk                 
6138 #define GPIO_MODER_MODER15_0            (0x1U << GPIO_MODER_MODER15_Pos)       /*!< 0x40000000 */
6139 #define GPIO_MODER_MODER15_1            (0x2U << GPIO_MODER_MODER15_Pos)       /*!< 0x80000000 */
6140
6141 /******************  Bit definition for GPIO_OTYPER register  *****************/
6142 #define GPIO_OTYPER_OT_0                (0x00000001U)                          
6143 #define GPIO_OTYPER_OT_1                (0x00000002U)                          
6144 #define GPIO_OTYPER_OT_2                (0x00000004U)                          
6145 #define GPIO_OTYPER_OT_3                (0x00000008U)                          
6146 #define GPIO_OTYPER_OT_4                (0x00000010U)                          
6147 #define GPIO_OTYPER_OT_5                (0x00000020U)                          
6148 #define GPIO_OTYPER_OT_6                (0x00000040U)                          
6149 #define GPIO_OTYPER_OT_7                (0x00000080U)                          
6150 #define GPIO_OTYPER_OT_8                (0x00000100U)                          
6151 #define GPIO_OTYPER_OT_9                (0x00000200U)                          
6152 #define GPIO_OTYPER_OT_10               (0x00000400U)                          
6153 #define GPIO_OTYPER_OT_11               (0x00000800U)                          
6154 #define GPIO_OTYPER_OT_12               (0x00001000U)                          
6155 #define GPIO_OTYPER_OT_13               (0x00002000U)                          
6156 #define GPIO_OTYPER_OT_14               (0x00004000U)                          
6157 #define GPIO_OTYPER_OT_15               (0x00008000U)                          
6158
6159 /****************  Bit definition for GPIO_OSPEEDR register  ******************/
6160 #define GPIO_OSPEEDR_OSPEEDR0_Pos       (0U)                                   
6161 #define GPIO_OSPEEDR_OSPEEDR0_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos)    /*!< 0x00000003 */
6162 #define GPIO_OSPEEDR_OSPEEDR0           GPIO_OSPEEDR_OSPEEDR0_Msk              
6163 #define GPIO_OSPEEDR_OSPEEDR0_0         (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos)    /*!< 0x00000001 */
6164 #define GPIO_OSPEEDR_OSPEEDR0_1         (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos)    /*!< 0x00000002 */
6165 #define GPIO_OSPEEDR_OSPEEDR1_Pos       (2U)                                   
6166 #define GPIO_OSPEEDR_OSPEEDR1_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos)    /*!< 0x0000000C */
6167 #define GPIO_OSPEEDR_OSPEEDR1           GPIO_OSPEEDR_OSPEEDR1_Msk              
6168 #define GPIO_OSPEEDR_OSPEEDR1_0         (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos)    /*!< 0x00000004 */
6169 #define GPIO_OSPEEDR_OSPEEDR1_1         (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos)    /*!< 0x00000008 */
6170 #define GPIO_OSPEEDR_OSPEEDR2_Pos       (4U)                                   
6171 #define GPIO_OSPEEDR_OSPEEDR2_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos)    /*!< 0x00000030 */
6172 #define GPIO_OSPEEDR_OSPEEDR2           GPIO_OSPEEDR_OSPEEDR2_Msk              
6173 #define GPIO_OSPEEDR_OSPEEDR2_0         (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos)    /*!< 0x00000010 */
6174 #define GPIO_OSPEEDR_OSPEEDR2_1         (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos)    /*!< 0x00000020 */
6175 #define GPIO_OSPEEDR_OSPEEDR3_Pos       (6U)                                   
6176 #define GPIO_OSPEEDR_OSPEEDR3_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos)    /*!< 0x000000C0 */
6177 #define GPIO_OSPEEDR_OSPEEDR3           GPIO_OSPEEDR_OSPEEDR3_Msk              
6178 #define GPIO_OSPEEDR_OSPEEDR3_0         (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos)    /*!< 0x00000040 */
6179 #define GPIO_OSPEEDR_OSPEEDR3_1         (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos)    /*!< 0x00000080 */
6180 #define GPIO_OSPEEDR_OSPEEDR4_Pos       (8U)                                   
6181 #define GPIO_OSPEEDR_OSPEEDR4_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos)    /*!< 0x00000300 */
6182 #define GPIO_OSPEEDR_OSPEEDR4           GPIO_OSPEEDR_OSPEEDR4_Msk              
6183 #define GPIO_OSPEEDR_OSPEEDR4_0         (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos)    /*!< 0x00000100 */
6184 #define GPIO_OSPEEDR_OSPEEDR4_1         (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos)    /*!< 0x00000200 */
6185 #define GPIO_OSPEEDR_OSPEEDR5_Pos       (10U)                                  
6186 #define GPIO_OSPEEDR_OSPEEDR5_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos)    /*!< 0x00000C00 */
6187 #define GPIO_OSPEEDR_OSPEEDR5           GPIO_OSPEEDR_OSPEEDR5_Msk              
6188 #define GPIO_OSPEEDR_OSPEEDR5_0         (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos)    /*!< 0x00000400 */
6189 #define GPIO_OSPEEDR_OSPEEDR5_1         (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos)    /*!< 0x00000800 */
6190 #define GPIO_OSPEEDR_OSPEEDR6_Pos       (12U)                                  
6191 #define GPIO_OSPEEDR_OSPEEDR6_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos)    /*!< 0x00003000 */
6192 #define GPIO_OSPEEDR_OSPEEDR6           GPIO_OSPEEDR_OSPEEDR6_Msk              
6193 #define GPIO_OSPEEDR_OSPEEDR6_0         (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos)    /*!< 0x00001000 */
6194 #define GPIO_OSPEEDR_OSPEEDR6_1         (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos)    /*!< 0x00002000 */
6195 #define GPIO_OSPEEDR_OSPEEDR7_Pos       (14U)                                  
6196 #define GPIO_OSPEEDR_OSPEEDR7_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos)    /*!< 0x0000C000 */
6197 #define GPIO_OSPEEDR_OSPEEDR7           GPIO_OSPEEDR_OSPEEDR7_Msk              
6198 #define GPIO_OSPEEDR_OSPEEDR7_0         (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos)    /*!< 0x00004000 */
6199 #define GPIO_OSPEEDR_OSPEEDR7_1         (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos)    /*!< 0x00008000 */
6200 #define GPIO_OSPEEDR_OSPEEDR8_Pos       (16U)                                  
6201 #define GPIO_OSPEEDR_OSPEEDR8_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos)    /*!< 0x00030000 */
6202 #define GPIO_OSPEEDR_OSPEEDR8           GPIO_OSPEEDR_OSPEEDR8_Msk              
6203 #define GPIO_OSPEEDR_OSPEEDR8_0         (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos)    /*!< 0x00010000 */
6204 #define GPIO_OSPEEDR_OSPEEDR8_1         (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos)    /*!< 0x00020000 */
6205 #define GPIO_OSPEEDR_OSPEEDR9_Pos       (18U)                                  
6206 #define GPIO_OSPEEDR_OSPEEDR9_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos)    /*!< 0x000C0000 */
6207 #define GPIO_OSPEEDR_OSPEEDR9           GPIO_OSPEEDR_OSPEEDR9_Msk              
6208 #define GPIO_OSPEEDR_OSPEEDR9_0         (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos)    /*!< 0x00040000 */
6209 #define GPIO_OSPEEDR_OSPEEDR9_1         (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos)    /*!< 0x00080000 */
6210 #define GPIO_OSPEEDR_OSPEEDR10_Pos      (20U)                                  
6211 #define GPIO_OSPEEDR_OSPEEDR10_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos)   /*!< 0x00300000 */
6212 #define GPIO_OSPEEDR_OSPEEDR10          GPIO_OSPEEDR_OSPEEDR10_Msk             
6213 #define GPIO_OSPEEDR_OSPEEDR10_0        (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos)   /*!< 0x00100000 */
6214 #define GPIO_OSPEEDR_OSPEEDR10_1        (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos)   /*!< 0x00200000 */
6215 #define GPIO_OSPEEDR_OSPEEDR11_Pos      (22U)                                  
6216 #define GPIO_OSPEEDR_OSPEEDR11_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos)   /*!< 0x00C00000 */
6217 #define GPIO_OSPEEDR_OSPEEDR11          GPIO_OSPEEDR_OSPEEDR11_Msk             
6218 #define GPIO_OSPEEDR_OSPEEDR11_0        (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos)   /*!< 0x00400000 */
6219 #define GPIO_OSPEEDR_OSPEEDR11_1        (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos)   /*!< 0x00800000 */
6220 #define GPIO_OSPEEDR_OSPEEDR12_Pos      (24U)                                  
6221 #define GPIO_OSPEEDR_OSPEEDR12_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos)   /*!< 0x03000000 */
6222 #define GPIO_OSPEEDR_OSPEEDR12          GPIO_OSPEEDR_OSPEEDR12_Msk             
6223 #define GPIO_OSPEEDR_OSPEEDR12_0        (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos)   /*!< 0x01000000 */
6224 #define GPIO_OSPEEDR_OSPEEDR12_1        (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos)   /*!< 0x02000000 */
6225 #define GPIO_OSPEEDR_OSPEEDR13_Pos      (26U)                                  
6226 #define GPIO_OSPEEDR_OSPEEDR13_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos)   /*!< 0x0C000000 */
6227 #define GPIO_OSPEEDR_OSPEEDR13          GPIO_OSPEEDR_OSPEEDR13_Msk             
6228 #define GPIO_OSPEEDR_OSPEEDR13_0        (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos)   /*!< 0x04000000 */
6229 #define GPIO_OSPEEDR_OSPEEDR13_1        (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos)   /*!< 0x08000000 */
6230 #define GPIO_OSPEEDR_OSPEEDR14_Pos      (28U)                                  
6231 #define GPIO_OSPEEDR_OSPEEDR14_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos)   /*!< 0x30000000 */
6232 #define GPIO_OSPEEDR_OSPEEDR14          GPIO_OSPEEDR_OSPEEDR14_Msk             
6233 #define GPIO_OSPEEDR_OSPEEDR14_0        (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos)   /*!< 0x10000000 */
6234 #define GPIO_OSPEEDR_OSPEEDR14_1        (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos)   /*!< 0x20000000 */
6235 #define GPIO_OSPEEDR_OSPEEDR15_Pos      (30U)                                  
6236 #define GPIO_OSPEEDR_OSPEEDR15_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos)   /*!< 0xC0000000 */
6237 #define GPIO_OSPEEDR_OSPEEDR15          GPIO_OSPEEDR_OSPEEDR15_Msk             
6238 #define GPIO_OSPEEDR_OSPEEDR15_0        (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos)   /*!< 0x40000000 */
6239 #define GPIO_OSPEEDR_OSPEEDR15_1        (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos)   /*!< 0x80000000 */
6240
6241 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
6242 #define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
6243 #define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
6244 #define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
6245 #define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
6246 #define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
6247 #define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
6248 #define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
6249 #define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
6250 #define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
6251 #define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
6252 #define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
6253 #define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
6254 #define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
6255 #define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
6256 #define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
6257 #define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
6258 #define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
6259 #define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
6260 #define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
6261 #define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
6262 #define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
6263 #define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
6264 #define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
6265 #define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
6266 #define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
6267 #define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
6268 #define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
6269 #define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
6270 #define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
6271 #define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
6272 #define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
6273 #define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
6274 #define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
6275 #define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
6276 #define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
6277 #define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
6278 #define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
6279 #define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
6280 #define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
6281 #define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
6282 #define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
6283 #define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
6284 #define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
6285 #define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
6286 #define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
6287 #define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
6288 #define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
6289 #define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1
6290
6291 /*******************  Bit definition for GPIO_PUPDR register ******************/
6292 #define GPIO_PUPDR_PUPDR0_Pos           (0U)                                   
6293 #define GPIO_PUPDR_PUPDR0_Msk           (0x3U << GPIO_PUPDR_PUPDR0_Pos)        /*!< 0x00000003 */
6294 #define GPIO_PUPDR_PUPDR0               GPIO_PUPDR_PUPDR0_Msk                  
6295 #define GPIO_PUPDR_PUPDR0_0             (0x1U << GPIO_PUPDR_PUPDR0_Pos)        /*!< 0x00000001 */
6296 #define GPIO_PUPDR_PUPDR0_1             (0x2U << GPIO_PUPDR_PUPDR0_Pos)        /*!< 0x00000002 */
6297 #define GPIO_PUPDR_PUPDR1_Pos           (2U)                                   
6298 #define GPIO_PUPDR_PUPDR1_Msk           (0x3U << GPIO_PUPDR_PUPDR1_Pos)        /*!< 0x0000000C */
6299 #define GPIO_PUPDR_PUPDR1               GPIO_PUPDR_PUPDR1_Msk                  
6300 #define GPIO_PUPDR_PUPDR1_0             (0x1U << GPIO_PUPDR_PUPDR1_Pos)        /*!< 0x00000004 */
6301 #define GPIO_PUPDR_PUPDR1_1             (0x2U << GPIO_PUPDR_PUPDR1_Pos)        /*!< 0x00000008 */
6302 #define GPIO_PUPDR_PUPDR2_Pos           (4U)                                   
6303 #define GPIO_PUPDR_PUPDR2_Msk           (0x3U << GPIO_PUPDR_PUPDR2_Pos)        /*!< 0x00000030 */
6304 #define GPIO_PUPDR_PUPDR2               GPIO_PUPDR_PUPDR2_Msk                  
6305 #define GPIO_PUPDR_PUPDR2_0             (0x1U << GPIO_PUPDR_PUPDR2_Pos)        /*!< 0x00000010 */
6306 #define GPIO_PUPDR_PUPDR2_1             (0x2U << GPIO_PUPDR_PUPDR2_Pos)        /*!< 0x00000020 */
6307 #define GPIO_PUPDR_PUPDR3_Pos           (6U)                                   
6308 #define GPIO_PUPDR_PUPDR3_Msk           (0x3U << GPIO_PUPDR_PUPDR3_Pos)        /*!< 0x000000C0 */
6309 #define GPIO_PUPDR_PUPDR3               GPIO_PUPDR_PUPDR3_Msk                  
6310 #define GPIO_PUPDR_PUPDR3_0             (0x1U << GPIO_PUPDR_PUPDR3_Pos)        /*!< 0x00000040 */
6311 #define GPIO_PUPDR_PUPDR3_1             (0x2U << GPIO_PUPDR_PUPDR3_Pos)        /*!< 0x00000080 */
6312 #define GPIO_PUPDR_PUPDR4_Pos           (8U)                                   
6313 #define GPIO_PUPDR_PUPDR4_Msk           (0x3U << GPIO_PUPDR_PUPDR4_Pos)        /*!< 0x00000300 */
6314 #define GPIO_PUPDR_PUPDR4               GPIO_PUPDR_PUPDR4_Msk                  
6315 #define GPIO_PUPDR_PUPDR4_0             (0x1U << GPIO_PUPDR_PUPDR4_Pos)        /*!< 0x00000100 */
6316 #define GPIO_PUPDR_PUPDR4_1             (0x2U << GPIO_PUPDR_PUPDR4_Pos)        /*!< 0x00000200 */
6317 #define GPIO_PUPDR_PUPDR5_Pos           (10U)                                  
6318 #define GPIO_PUPDR_PUPDR5_Msk           (0x3U << GPIO_PUPDR_PUPDR5_Pos)        /*!< 0x00000C00 */
6319 #define GPIO_PUPDR_PUPDR5               GPIO_PUPDR_PUPDR5_Msk                  
6320 #define GPIO_PUPDR_PUPDR5_0             (0x1U << GPIO_PUPDR_PUPDR5_Pos)        /*!< 0x00000400 */
6321 #define GPIO_PUPDR_PUPDR5_1             (0x2U << GPIO_PUPDR_PUPDR5_Pos)        /*!< 0x00000800 */
6322 #define GPIO_PUPDR_PUPDR6_Pos           (12U)                                  
6323 #define GPIO_PUPDR_PUPDR6_Msk           (0x3U << GPIO_PUPDR_PUPDR6_Pos)        /*!< 0x00003000 */
6324 #define GPIO_PUPDR_PUPDR6               GPIO_PUPDR_PUPDR6_Msk                  
6325 #define GPIO_PUPDR_PUPDR6_0             (0x1U << GPIO_PUPDR_PUPDR6_Pos)        /*!< 0x00001000 */
6326 #define GPIO_PUPDR_PUPDR6_1             (0x2U << GPIO_PUPDR_PUPDR6_Pos)        /*!< 0x00002000 */
6327 #define GPIO_PUPDR_PUPDR7_Pos           (14U)                                  
6328 #define GPIO_PUPDR_PUPDR7_Msk           (0x3U << GPIO_PUPDR_PUPDR7_Pos)        /*!< 0x0000C000 */
6329 #define GPIO_PUPDR_PUPDR7               GPIO_PUPDR_PUPDR7_Msk                  
6330 #define GPIO_PUPDR_PUPDR7_0             (0x1U << GPIO_PUPDR_PUPDR7_Pos)        /*!< 0x00004000 */
6331 #define GPIO_PUPDR_PUPDR7_1             (0x2U << GPIO_PUPDR_PUPDR7_Pos)        /*!< 0x00008000 */
6332 #define GPIO_PUPDR_PUPDR8_Pos           (16U)                                  
6333 #define GPIO_PUPDR_PUPDR8_Msk           (0x3U << GPIO_PUPDR_PUPDR8_Pos)        /*!< 0x00030000 */
6334 #define GPIO_PUPDR_PUPDR8               GPIO_PUPDR_PUPDR8_Msk                  
6335 #define GPIO_PUPDR_PUPDR8_0             (0x1U << GPIO_PUPDR_PUPDR8_Pos)        /*!< 0x00010000 */
6336 #define GPIO_PUPDR_PUPDR8_1             (0x2U << GPIO_PUPDR_PUPDR8_Pos)        /*!< 0x00020000 */
6337 #define GPIO_PUPDR_PUPDR9_Pos           (18U)                                  
6338 #define GPIO_PUPDR_PUPDR9_Msk           (0x3U << GPIO_PUPDR_PUPDR9_Pos)        /*!< 0x000C0000 */
6339 #define GPIO_PUPDR_PUPDR9               GPIO_PUPDR_PUPDR9_Msk                  
6340 #define GPIO_PUPDR_PUPDR9_0             (0x1U << GPIO_PUPDR_PUPDR9_Pos)        /*!< 0x00040000 */
6341 #define GPIO_PUPDR_PUPDR9_1             (0x2U << GPIO_PUPDR_PUPDR9_Pos)        /*!< 0x00080000 */
6342 #define GPIO_PUPDR_PUPDR10_Pos          (20U)                                  
6343 #define GPIO_PUPDR_PUPDR10_Msk          (0x3U << GPIO_PUPDR_PUPDR10_Pos)       /*!< 0x00300000 */
6344 #define GPIO_PUPDR_PUPDR10              GPIO_PUPDR_PUPDR10_Msk                 
6345 #define GPIO_PUPDR_PUPDR10_0            (0x1U << GPIO_PUPDR_PUPDR10_Pos)       /*!< 0x00100000 */
6346 #define GPIO_PUPDR_PUPDR10_1            (0x2U << GPIO_PUPDR_PUPDR10_Pos)       /*!< 0x00200000 */
6347 #define GPIO_PUPDR_PUPDR11_Pos          (22U)                                  
6348 #define GPIO_PUPDR_PUPDR11_Msk          (0x3U << GPIO_PUPDR_PUPDR11_Pos)       /*!< 0x00C00000 */
6349 #define GPIO_PUPDR_PUPDR11              GPIO_PUPDR_PUPDR11_Msk                 
6350 #define GPIO_PUPDR_PUPDR11_0            (0x1U << GPIO_PUPDR_PUPDR11_Pos)       /*!< 0x00400000 */
6351 #define GPIO_PUPDR_PUPDR11_1            (0x2U << GPIO_PUPDR_PUPDR11_Pos)       /*!< 0x00800000 */
6352 #define GPIO_PUPDR_PUPDR12_Pos          (24U)                                  
6353 #define GPIO_PUPDR_PUPDR12_Msk          (0x3U << GPIO_PUPDR_PUPDR12_Pos)       /*!< 0x03000000 */
6354 #define GPIO_PUPDR_PUPDR12              GPIO_PUPDR_PUPDR12_Msk                 
6355 #define GPIO_PUPDR_PUPDR12_0            (0x1U << GPIO_PUPDR_PUPDR12_Pos)       /*!< 0x01000000 */
6356 #define GPIO_PUPDR_PUPDR12_1            (0x2U << GPIO_PUPDR_PUPDR12_Pos)       /*!< 0x02000000 */
6357 #define GPIO_PUPDR_PUPDR13_Pos          (26U)                                  
6358 #define GPIO_PUPDR_PUPDR13_Msk          (0x3U << GPIO_PUPDR_PUPDR13_Pos)       /*!< 0x0C000000 */
6359 #define GPIO_PUPDR_PUPDR13              GPIO_PUPDR_PUPDR13_Msk                 
6360 #define GPIO_PUPDR_PUPDR13_0            (0x1U << GPIO_PUPDR_PUPDR13_Pos)       /*!< 0x04000000 */
6361 #define GPIO_PUPDR_PUPDR13_1            (0x2U << GPIO_PUPDR_PUPDR13_Pos)       /*!< 0x08000000 */
6362 #define GPIO_PUPDR_PUPDR14_Pos          (28U)                                  
6363 #define GPIO_PUPDR_PUPDR14_Msk          (0x3U << GPIO_PUPDR_PUPDR14_Pos)       /*!< 0x30000000 */
6364 #define GPIO_PUPDR_PUPDR14              GPIO_PUPDR_PUPDR14_Msk                 
6365 #define GPIO_PUPDR_PUPDR14_0            (0x1U << GPIO_PUPDR_PUPDR14_Pos)       /*!< 0x10000000 */
6366 #define GPIO_PUPDR_PUPDR14_1            (0x2U << GPIO_PUPDR_PUPDR14_Pos)       /*!< 0x20000000 */
6367 #define GPIO_PUPDR_PUPDR15_Pos          (30U)                                  
6368 #define GPIO_PUPDR_PUPDR15_Msk          (0x3U << GPIO_PUPDR_PUPDR15_Pos)       /*!< 0xC0000000 */
6369 #define GPIO_PUPDR_PUPDR15              GPIO_PUPDR_PUPDR15_Msk                 
6370 #define GPIO_PUPDR_PUPDR15_0            (0x1U << GPIO_PUPDR_PUPDR15_Pos)       /*!< 0x40000000 */
6371 #define GPIO_PUPDR_PUPDR15_1            (0x2U << GPIO_PUPDR_PUPDR15_Pos)       /*!< 0x80000000 */
6372
6373 /*******************  Bit definition for GPIO_IDR register  *******************/
6374 #define GPIO_IDR_0                      (0x00000001U)                          
6375 #define GPIO_IDR_1                      (0x00000002U)                          
6376 #define GPIO_IDR_2                      (0x00000004U)                          
6377 #define GPIO_IDR_3                      (0x00000008U)                          
6378 #define GPIO_IDR_4                      (0x00000010U)                          
6379 #define GPIO_IDR_5                      (0x00000020U)                          
6380 #define GPIO_IDR_6                      (0x00000040U)                          
6381 #define GPIO_IDR_7                      (0x00000080U)                          
6382 #define GPIO_IDR_8                      (0x00000100U)                          
6383 #define GPIO_IDR_9                      (0x00000200U)                          
6384 #define GPIO_IDR_10                     (0x00000400U)                          
6385 #define GPIO_IDR_11                     (0x00000800U)                          
6386 #define GPIO_IDR_12                     (0x00001000U)                          
6387 #define GPIO_IDR_13                     (0x00002000U)                          
6388 #define GPIO_IDR_14                     (0x00004000U)                          
6389 #define GPIO_IDR_15                     (0x00008000U)                          
6390
6391 /******************  Bit definition for GPIO_ODR register  ********************/
6392 #define GPIO_ODR_0                      (0x00000001U)                          
6393 #define GPIO_ODR_1                      (0x00000002U)                          
6394 #define GPIO_ODR_2                      (0x00000004U)                          
6395 #define GPIO_ODR_3                      (0x00000008U)                          
6396 #define GPIO_ODR_4                      (0x00000010U)                          
6397 #define GPIO_ODR_5                      (0x00000020U)                          
6398 #define GPIO_ODR_6                      (0x00000040U)                          
6399 #define GPIO_ODR_7                      (0x00000080U)                          
6400 #define GPIO_ODR_8                      (0x00000100U)                          
6401 #define GPIO_ODR_9                      (0x00000200U)                          
6402 #define GPIO_ODR_10                     (0x00000400U)                          
6403 #define GPIO_ODR_11                     (0x00000800U)                          
6404 #define GPIO_ODR_12                     (0x00001000U)                          
6405 #define GPIO_ODR_13                     (0x00002000U)                          
6406 #define GPIO_ODR_14                     (0x00004000U)                          
6407 #define GPIO_ODR_15                     (0x00008000U)                          
6408
6409 /****************** Bit definition for GPIO_BSRR register  ********************/
6410 #define GPIO_BSRR_BS_0                  (0x00000001U)                          
6411 #define GPIO_BSRR_BS_1                  (0x00000002U)                          
6412 #define GPIO_BSRR_BS_2                  (0x00000004U)                          
6413 #define GPIO_BSRR_BS_3                  (0x00000008U)                          
6414 #define GPIO_BSRR_BS_4                  (0x00000010U)                          
6415 #define GPIO_BSRR_BS_5                  (0x00000020U)                          
6416 #define GPIO_BSRR_BS_6                  (0x00000040U)                          
6417 #define GPIO_BSRR_BS_7                  (0x00000080U)                          
6418 #define GPIO_BSRR_BS_8                  (0x00000100U)                          
6419 #define GPIO_BSRR_BS_9                  (0x00000200U)                          
6420 #define GPIO_BSRR_BS_10                 (0x00000400U)                          
6421 #define GPIO_BSRR_BS_11                 (0x00000800U)                          
6422 #define GPIO_BSRR_BS_12                 (0x00001000U)                          
6423 #define GPIO_BSRR_BS_13                 (0x00002000U)                          
6424 #define GPIO_BSRR_BS_14                 (0x00004000U)                          
6425 #define GPIO_BSRR_BS_15                 (0x00008000U)                          
6426 #define GPIO_BSRR_BR_0                  (0x00010000U)                          
6427 #define GPIO_BSRR_BR_1                  (0x00020000U)                          
6428 #define GPIO_BSRR_BR_2                  (0x00040000U)                          
6429 #define GPIO_BSRR_BR_3                  (0x00080000U)                          
6430 #define GPIO_BSRR_BR_4                  (0x00100000U)                          
6431 #define GPIO_BSRR_BR_5                  (0x00200000U)                          
6432 #define GPIO_BSRR_BR_6                  (0x00400000U)                          
6433 #define GPIO_BSRR_BR_7                  (0x00800000U)                          
6434 #define GPIO_BSRR_BR_8                  (0x01000000U)                          
6435 #define GPIO_BSRR_BR_9                  (0x02000000U)                          
6436 #define GPIO_BSRR_BR_10                 (0x04000000U)                          
6437 #define GPIO_BSRR_BR_11                 (0x08000000U)                          
6438 #define GPIO_BSRR_BR_12                 (0x10000000U)                          
6439 #define GPIO_BSRR_BR_13                 (0x20000000U)                          
6440 #define GPIO_BSRR_BR_14                 (0x40000000U)                          
6441 #define GPIO_BSRR_BR_15                 (0x80000000U)                          
6442
6443 /****************** Bit definition for GPIO_LCKR register  ********************/
6444 #define GPIO_LCKR_LCK0_Pos              (0U)                                   
6445 #define GPIO_LCKR_LCK0_Msk              (0x1U << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
6446 #define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk                     
6447 #define GPIO_LCKR_LCK1_Pos              (1U)                                   
6448 #define GPIO_LCKR_LCK1_Msk              (0x1U << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
6449 #define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk                     
6450 #define GPIO_LCKR_LCK2_Pos              (2U)                                   
6451 #define GPIO_LCKR_LCK2_Msk              (0x1U << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
6452 #define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk                     
6453 #define GPIO_LCKR_LCK3_Pos              (3U)                                   
6454 #define GPIO_LCKR_LCK3_Msk              (0x1U << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
6455 #define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk                     
6456 #define GPIO_LCKR_LCK4_Pos              (4U)                                   
6457 #define GPIO_LCKR_LCK4_Msk              (0x1U << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
6458 #define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk                     
6459 #define GPIO_LCKR_LCK5_Pos              (5U)                                   
6460 #define GPIO_LCKR_LCK5_Msk              (0x1U << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
6461 #define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk                     
6462 #define GPIO_LCKR_LCK6_Pos              (6U)                                   
6463 #define GPIO_LCKR_LCK6_Msk              (0x1U << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
6464 #define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk                     
6465 #define GPIO_LCKR_LCK7_Pos              (7U)                                   
6466 #define GPIO_LCKR_LCK7_Msk              (0x1U << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
6467 #define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk                     
6468 #define GPIO_LCKR_LCK8_Pos              (8U)                                   
6469 #define GPIO_LCKR_LCK8_Msk              (0x1U << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
6470 #define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk                     
6471 #define GPIO_LCKR_LCK9_Pos              (9U)                                   
6472 #define GPIO_LCKR_LCK9_Msk              (0x1U << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
6473 #define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk                     
6474 #define GPIO_LCKR_LCK10_Pos             (10U)                                  
6475 #define GPIO_LCKR_LCK10_Msk             (0x1U << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
6476 #define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk                    
6477 #define GPIO_LCKR_LCK11_Pos             (11U)                                  
6478 #define GPIO_LCKR_LCK11_Msk             (0x1U << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
6479 #define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk                    
6480 #define GPIO_LCKR_LCK12_Pos             (12U)                                  
6481 #define GPIO_LCKR_LCK12_Msk             (0x1U << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
6482 #define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk                    
6483 #define GPIO_LCKR_LCK13_Pos             (13U)                                  
6484 #define GPIO_LCKR_LCK13_Msk             (0x1U << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
6485 #define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk                    
6486 #define GPIO_LCKR_LCK14_Pos             (14U)                                  
6487 #define GPIO_LCKR_LCK14_Msk             (0x1U << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
6488 #define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk                    
6489 #define GPIO_LCKR_LCK15_Pos             (15U)                                  
6490 #define GPIO_LCKR_LCK15_Msk             (0x1U << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
6491 #define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk                    
6492 #define GPIO_LCKR_LCKK_Pos              (16U)                                  
6493 #define GPIO_LCKR_LCKK_Msk              (0x1U << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
6494 #define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk                     
6495
6496 /****************** Bit definition for GPIO_AFRL register  ********************/
6497 #define GPIO_AFRL_AFSEL0_Pos            (0U)                                   
6498 #define GPIO_AFRL_AFSEL0_Msk            (0xFU << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
6499 #define GPIO_AFRL_AFSEL0                GPIO_AFRL_AFSEL0_Msk                    
6500 #define GPIO_AFRL_AFSEL1_Pos            (4U)                                   
6501 #define GPIO_AFRL_AFSEL1_Msk            (0xFU << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
6502 #define GPIO_AFRL_AFSEL1                GPIO_AFRL_AFSEL1_Msk                    
6503 #define GPIO_AFRL_AFSEL2_Pos            (8U)                                   
6504 #define GPIO_AFRL_AFSEL2_Msk            (0xFU << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
6505 #define GPIO_AFRL_AFSEL2                GPIO_AFRL_AFSEL2_Msk                    
6506 #define GPIO_AFRL_AFSEL3_Pos            (12U)                                  
6507 #define GPIO_AFRL_AFSEL3_Msk            (0xFU << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
6508 #define GPIO_AFRL_AFSEL3                GPIO_AFRL_AFSEL3_Msk                    
6509 #define GPIO_AFRL_AFSEL4_Pos            (16U)                                  
6510 #define GPIO_AFRL_AFSEL4_Msk            (0xFU << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
6511 #define GPIO_AFRL_AFSEL4                GPIO_AFRL_AFSEL4_Msk                    
6512 #define GPIO_AFRL_AFSEL5_Pos            (20U)                                  
6513 #define GPIO_AFRL_AFSEL5_Msk            (0xFU << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
6514 #define GPIO_AFRL_AFSEL5                GPIO_AFRL_AFSEL5_Msk                    
6515 #define GPIO_AFRL_AFSEL6_Pos            (24U)                                  
6516 #define GPIO_AFRL_AFSEL6_Msk            (0xFU << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
6517 #define GPIO_AFRL_AFSEL6                GPIO_AFRL_AFSEL6_Msk                    
6518 #define GPIO_AFRL_AFSEL7_Pos            (28U)                                  
6519 #define GPIO_AFRL_AFSEL7_Msk            (0xFU << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
6520 #define GPIO_AFRL_AFSEL7                GPIO_AFRL_AFSEL7_Msk  
6521
6522 /* Legacy aliases */                  
6523 #define GPIO_AFRL_AFRL0_Pos             GPIO_AFRL_AFSEL0_Pos                                  
6524 #define GPIO_AFRL_AFRL0_Msk             GPIO_AFRL_AFSEL0_Msk
6525 #define GPIO_AFRL_AFRL0                 GPIO_AFRL_AFSEL0
6526 #define GPIO_AFRL_AFRL1_Pos             GPIO_AFRL_AFSEL1_Pos
6527 #define GPIO_AFRL_AFRL1_Msk             GPIO_AFRL_AFSEL1_Msk
6528 #define GPIO_AFRL_AFRL1                 GPIO_AFRL_AFSEL1
6529 #define GPIO_AFRL_AFRL2_Pos             GPIO_AFRL_AFSEL2_Pos
6530 #define GPIO_AFRL_AFRL2_Msk             GPIO_AFRL_AFSEL2_Msk
6531 #define GPIO_AFRL_AFRL2                 GPIO_AFRL_AFSEL2
6532 #define GPIO_AFRL_AFRL3_Pos             GPIO_AFRL_AFSEL3_Pos
6533 #define GPIO_AFRL_AFRL3_Msk             GPIO_AFRL_AFSEL3_Msk
6534 #define GPIO_AFRL_AFRL3                 GPIO_AFRL_AFSEL3
6535 #define GPIO_AFRL_AFRL4_Pos             GPIO_AFRL_AFSEL4_Pos
6536 #define GPIO_AFRL_AFRL4_Msk             GPIO_AFRL_AFSEL4_Msk
6537 #define GPIO_AFRL_AFRL4                 GPIO_AFRL_AFSEL4
6538 #define GPIO_AFRL_AFRL5_Pos             GPIO_AFRL_AFSEL5_Pos
6539 #define GPIO_AFRL_AFRL5_Msk             GPIO_AFRL_AFSEL5_Msk
6540 #define GPIO_AFRL_AFRL5                 GPIO_AFRL_AFSEL5
6541 #define GPIO_AFRL_AFRL6_Pos             GPIO_AFRL_AFSEL6_Pos
6542 #define GPIO_AFRL_AFRL6_Msk             GPIO_AFRL_AFSEL6_Msk
6543 #define GPIO_AFRL_AFRL6                 GPIO_AFRL_AFSEL6
6544 #define GPIO_AFRL_AFRL7_Pos             GPIO_AFRL_AFSEL7_Pos
6545 #define GPIO_AFRL_AFRL7_Msk             GPIO_AFRL_AFSEL7_Msk
6546 #define GPIO_AFRL_AFRL7                 GPIO_AFRL_AFSEL7
6547  
6548 /****************** Bit definition for GPIO_AFRH register  ********************/
6549 #define GPIO_AFRH_AFSEL8_Pos            (0U)                                   
6550 #define GPIO_AFRH_AFSEL8_Msk            (0xFU << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
6551 #define GPIO_AFRH_AFSEL8                GPIO_AFRH_AFSEL8_Msk                    
6552 #define GPIO_AFRH_AFSEL9_Pos            (4U)                                   
6553 #define GPIO_AFRH_AFSEL9_Msk            (0xFU << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
6554 #define GPIO_AFRH_AFSEL9                GPIO_AFRH_AFSEL9_Msk                    
6555 #define GPIO_AFRH_AFSEL10_Pos           (8U)                                   
6556 #define GPIO_AFRH_AFSEL10_Msk           (0xFU << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
6557 #define GPIO_AFRH_AFSEL10               GPIO_AFRH_AFSEL10_Msk                    
6558 #define GPIO_AFRH_AFSEL11_Pos           (12U)                                  
6559 #define GPIO_AFRH_AFSEL11_Msk           (0xFU << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
6560 #define GPIO_AFRH_AFSEL11               GPIO_AFRH_AFSEL11_Msk                    
6561 #define GPIO_AFRH_AFSEL12_Pos           (16U)                                  
6562 #define GPIO_AFRH_AFSEL12_Msk           (0xFU << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
6563 #define GPIO_AFRH_AFSEL12               GPIO_AFRH_AFSEL12_Msk                    
6564 #define GPIO_AFRH_AFSEL13_Pos           (20U)                                  
6565 #define GPIO_AFRH_AFSEL13_Msk           (0xFU << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
6566 #define GPIO_AFRH_AFSEL13               GPIO_AFRH_AFSEL13_Msk                    
6567 #define GPIO_AFRH_AFSEL14_Pos           (24U)                                  
6568 #define GPIO_AFRH_AFSEL14_Msk           (0xFU << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
6569 #define GPIO_AFRH_AFSEL14               GPIO_AFRH_AFSEL14_Msk                    
6570 #define GPIO_AFRH_AFSEL15_Pos           (28U)                                  
6571 #define GPIO_AFRH_AFSEL15_Msk           (0xFU << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
6572 #define GPIO_AFRH_AFSEL15               GPIO_AFRH_AFSEL15_Msk                    
6573
6574 /* Legacy aliases */                  
6575 #define GPIO_AFRH_AFRH0_Pos             GPIO_AFRH_AFSEL8_Pos
6576 #define GPIO_AFRH_AFRH0_Msk             GPIO_AFRH_AFSEL8_Msk
6577 #define GPIO_AFRH_AFRH0                 GPIO_AFRH_AFSEL8
6578 #define GPIO_AFRH_AFRH1_Pos             GPIO_AFRH_AFSEL9_Pos
6579 #define GPIO_AFRH_AFRH1_Msk             GPIO_AFRH_AFSEL9_Msk
6580 #define GPIO_AFRH_AFRH1                 GPIO_AFRH_AFSEL9
6581 #define GPIO_AFRH_AFRH2_Pos             GPIO_AFRH_AFSEL10_Pos
6582 #define GPIO_AFRH_AFRH2_Msk             GPIO_AFRH_AFSEL10_Msk
6583 #define GPIO_AFRH_AFRH2                 GPIO_AFRH_AFSEL10
6584 #define GPIO_AFRH_AFRH3_Pos             GPIO_AFRH_AFSEL11_Pos
6585 #define GPIO_AFRH_AFRH3_Msk             GPIO_AFRH_AFSEL11_Msk
6586 #define GPIO_AFRH_AFRH3                 GPIO_AFRH_AFSEL11
6587 #define GPIO_AFRH_AFRH4_Pos             GPIO_AFRH_AFSEL12_Pos
6588 #define GPIO_AFRH_AFRH4_Msk             GPIO_AFRH_AFSEL12_Msk
6589 #define GPIO_AFRH_AFRH4                 GPIO_AFRH_AFSEL12
6590 #define GPIO_AFRH_AFRH5_Pos             GPIO_AFRH_AFSEL13_Pos
6591 #define GPIO_AFRH_AFRH5_Msk             GPIO_AFRH_AFSEL13_Msk
6592 #define GPIO_AFRH_AFRH5                 GPIO_AFRH_AFSEL13
6593 #define GPIO_AFRH_AFRH6_Pos             GPIO_AFRH_AFSEL14_Pos
6594 #define GPIO_AFRH_AFRH6_Msk             GPIO_AFRH_AFSEL14_Msk
6595 #define GPIO_AFRH_AFRH6                 GPIO_AFRH_AFSEL14
6596 #define GPIO_AFRH_AFRH7_Pos             GPIO_AFRH_AFSEL15_Pos
6597 #define GPIO_AFRH_AFRH7_Msk             GPIO_AFRH_AFSEL15_Msk
6598 #define GPIO_AFRH_AFRH7                 GPIO_AFRH_AFSEL15
6599
6600 /****************** Bit definition for GPIO_BRR register  *********************/
6601 #define GPIO_BRR_BR_0                   (0x00000001U)                          
6602 #define GPIO_BRR_BR_1                   (0x00000002U)                          
6603 #define GPIO_BRR_BR_2                   (0x00000004U)                          
6604 #define GPIO_BRR_BR_3                   (0x00000008U)                          
6605 #define GPIO_BRR_BR_4                   (0x00000010U)                          
6606 #define GPIO_BRR_BR_5                   (0x00000020U)                          
6607 #define GPIO_BRR_BR_6                   (0x00000040U)                          
6608 #define GPIO_BRR_BR_7                   (0x00000080U)                          
6609 #define GPIO_BRR_BR_8                   (0x00000100U)                          
6610 #define GPIO_BRR_BR_9                   (0x00000200U)                          
6611 #define GPIO_BRR_BR_10                  (0x00000400U)                          
6612 #define GPIO_BRR_BR_11                  (0x00000800U)                          
6613 #define GPIO_BRR_BR_12                  (0x00001000U)                          
6614 #define GPIO_BRR_BR_13                  (0x00002000U)                          
6615 #define GPIO_BRR_BR_14                  (0x00004000U)                          
6616 #define GPIO_BRR_BR_15                  (0x00008000U)                          
6617
6618 /******************************************************************************/
6619 /*                                                                            */
6620 /*                   Inter-integrated Circuit Interface (I2C)                 */
6621 /*                                                                            */
6622 /******************************************************************************/
6623
6624 /*******************  Bit definition for I2C_CR1 register  *******************/
6625 #define I2C_CR1_PE_Pos               (0U)                                      
6626 #define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
6627 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
6628 #define I2C_CR1_TXIE_Pos             (1U)                                      
6629 #define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
6630 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
6631 #define I2C_CR1_RXIE_Pos             (2U)                                      
6632 #define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
6633 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
6634 #define I2C_CR1_ADDRIE_Pos           (3U)                                      
6635 #define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
6636 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
6637 #define I2C_CR1_NACKIE_Pos           (4U)                                      
6638 #define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
6639 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
6640 #define I2C_CR1_STOPIE_Pos           (5U)                                      
6641 #define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
6642 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
6643 #define I2C_CR1_TCIE_Pos             (6U)                                      
6644 #define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
6645 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
6646 #define I2C_CR1_ERRIE_Pos            (7U)                                      
6647 #define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
6648 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
6649 #define I2C_CR1_DNF_Pos              (8U)                                      
6650 #define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
6651 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
6652 #define I2C_CR1_ANFOFF_Pos           (12U)                                     
6653 #define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
6654 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
6655 #define I2C_CR1_SWRST_Pos            (13U)                                     
6656 #define I2C_CR1_SWRST_Msk            (0x1U << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
6657 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */
6658 #define I2C_CR1_TXDMAEN_Pos          (14U)                                     
6659 #define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
6660 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
6661 #define I2C_CR1_RXDMAEN_Pos          (15U)                                     
6662 #define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
6663 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
6664 #define I2C_CR1_SBC_Pos              (16U)                                     
6665 #define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
6666 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
6667 #define I2C_CR1_NOSTRETCH_Pos        (17U)                                     
6668 #define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
6669 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
6670 #define I2C_CR1_WUPEN_Pos            (18U)                                     
6671 #define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
6672 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
6673 #define I2C_CR1_GCEN_Pos             (19U)                                     
6674 #define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
6675 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
6676 #define I2C_CR1_SMBHEN_Pos           (20U)                                     
6677 #define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
6678 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
6679 #define I2C_CR1_SMBDEN_Pos           (21U)                                     
6680 #define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
6681 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
6682 #define I2C_CR1_ALERTEN_Pos          (22U)                                     
6683 #define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
6684 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
6685 #define I2C_CR1_PECEN_Pos            (23U)                                     
6686 #define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
6687 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
6688
6689 /******************  Bit definition for I2C_CR2 register  ********************/
6690 #define I2C_CR2_SADD_Pos             (0U)                                      
6691 #define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
6692 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
6693 #define I2C_CR2_RD_WRN_Pos           (10U)                                     
6694 #define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
6695 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
6696 #define I2C_CR2_ADD10_Pos            (11U)                                     
6697 #define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
6698 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
6699 #define I2C_CR2_HEAD10R_Pos          (12U)                                     
6700 #define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
6701 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
6702 #define I2C_CR2_START_Pos            (13U)                                     
6703 #define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
6704 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
6705 #define I2C_CR2_STOP_Pos             (14U)                                     
6706 #define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
6707 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
6708 #define I2C_CR2_NACK_Pos             (15U)                                     
6709 #define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
6710 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
6711 #define I2C_CR2_NBYTES_Pos           (16U)                                     
6712 #define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
6713 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
6714 #define I2C_CR2_RELOAD_Pos           (24U)                                     
6715 #define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
6716 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
6717 #define I2C_CR2_AUTOEND_Pos          (25U)                                     
6718 #define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
6719 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
6720 #define I2C_CR2_PECBYTE_Pos          (26U)                                     
6721 #define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
6722 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
6723
6724 /*******************  Bit definition for I2C_OAR1 register  ******************/
6725 #define I2C_OAR1_OA1_Pos             (0U)                                      
6726 #define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
6727 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
6728 #define I2C_OAR1_OA1MODE_Pos         (10U)                                     
6729 #define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
6730 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
6731 #define I2C_OAR1_OA1EN_Pos           (15U)                                     
6732 #define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
6733 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
6734
6735 /*******************  Bit definition for I2C_OAR2 register  ******************/
6736 #define I2C_OAR2_OA2_Pos             (1U)                                      
6737 #define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
6738 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
6739 #define I2C_OAR2_OA2MSK_Pos          (8U)                                      
6740 #define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
6741 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
6742 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
6743 #define I2C_OAR2_OA2MASK01_Pos       (8U)                                      
6744 #define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
6745 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
6746 #define I2C_OAR2_OA2MASK02_Pos       (9U)                                      
6747 #define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
6748 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
6749 #define I2C_OAR2_OA2MASK03_Pos       (8U)                                      
6750 #define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
6751 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
6752 #define I2C_OAR2_OA2MASK04_Pos       (10U)                                     
6753 #define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
6754 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
6755 #define I2C_OAR2_OA2MASK05_Pos       (8U)                                      
6756 #define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
6757 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
6758 #define I2C_OAR2_OA2MASK06_Pos       (9U)                                      
6759 #define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
6760 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
6761 #define I2C_OAR2_OA2MASK07_Pos       (8U)                                      
6762 #define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
6763 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
6764 #define I2C_OAR2_OA2EN_Pos           (15U)                                     
6765 #define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
6766 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
6767
6768 /*******************  Bit definition for I2C_TIMINGR register ****************/
6769 #define I2C_TIMINGR_SCLL_Pos         (0U)                                      
6770 #define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
6771 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
6772 #define I2C_TIMINGR_SCLH_Pos         (8U)                                      
6773 #define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
6774 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
6775 #define I2C_TIMINGR_SDADEL_Pos       (16U)                                     
6776 #define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
6777 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
6778 #define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     
6779 #define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
6780 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
6781 #define I2C_TIMINGR_PRESC_Pos        (28U)                                     
6782 #define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
6783 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
6784
6785 /******************* Bit definition for I2C_TIMEOUTR register ****************/
6786 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      
6787 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
6788 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
6789 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     
6790 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
6791 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
6792 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     
6793 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
6794 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
6795 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     
6796 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
6797 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
6798 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     
6799 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
6800 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
6801
6802 /******************  Bit definition for I2C_ISR register  ********************/
6803 #define I2C_ISR_TXE_Pos              (0U)                                      
6804 #define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
6805 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
6806 #define I2C_ISR_TXIS_Pos             (1U)                                      
6807 #define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
6808 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
6809 #define I2C_ISR_RXNE_Pos             (2U)                                      
6810 #define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
6811 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
6812 #define I2C_ISR_ADDR_Pos             (3U)                                      
6813 #define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
6814 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
6815 #define I2C_ISR_NACKF_Pos            (4U)                                      
6816 #define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
6817 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
6818 #define I2C_ISR_STOPF_Pos            (5U)                                      
6819 #define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
6820 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
6821 #define I2C_ISR_TC_Pos               (6U)                                      
6822 #define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
6823 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
6824 #define I2C_ISR_TCR_Pos              (7U)                                      
6825 #define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
6826 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
6827 #define I2C_ISR_BERR_Pos             (8U)                                      
6828 #define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
6829 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
6830 #define I2C_ISR_ARLO_Pos             (9U)                                      
6831 #define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
6832 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
6833 #define I2C_ISR_OVR_Pos              (10U)                                     
6834 #define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
6835 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
6836 #define I2C_ISR_PECERR_Pos           (11U)                                     
6837 #define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
6838 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
6839 #define I2C_ISR_TIMEOUT_Pos          (12U)                                     
6840 #define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
6841 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
6842 #define I2C_ISR_ALERT_Pos            (13U)                                     
6843 #define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
6844 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
6845 #define I2C_ISR_BUSY_Pos             (15U)                                     
6846 #define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
6847 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
6848 #define I2C_ISR_DIR_Pos              (16U)                                     
6849 #define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
6850 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
6851 #define I2C_ISR_ADDCODE_Pos          (17U)                                     
6852 #define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
6853 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
6854
6855 /******************  Bit definition for I2C_ICR register  ********************/
6856 #define I2C_ICR_ADDRCF_Pos           (3U)                                      
6857 #define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
6858 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
6859 #define I2C_ICR_NACKCF_Pos           (4U)                                      
6860 #define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
6861 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
6862 #define I2C_ICR_STOPCF_Pos           (5U)                                      
6863 #define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
6864 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
6865 #define I2C_ICR_BERRCF_Pos           (8U)                                      
6866 #define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
6867 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
6868 #define I2C_ICR_ARLOCF_Pos           (9U)                                      
6869 #define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
6870 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
6871 #define I2C_ICR_OVRCF_Pos            (10U)                                     
6872 #define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
6873 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
6874 #define I2C_ICR_PECCF_Pos            (11U)                                     
6875 #define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
6876 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
6877 #define I2C_ICR_TIMOUTCF_Pos         (12U)                                     
6878 #define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
6879 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
6880 #define I2C_ICR_ALERTCF_Pos          (13U)                                     
6881 #define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
6882 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
6883
6884 /******************  Bit definition for I2C_PECR register  *******************/
6885 #define I2C_PECR_PEC_Pos             (0U)                                      
6886 #define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
6887 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
6888
6889 /******************  Bit definition for I2C_RXDR register  *********************/
6890 #define I2C_RXDR_RXDATA_Pos          (0U)                                      
6891 #define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
6892 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
6893
6894 /******************  Bit definition for I2C_TXDR register  *******************/
6895 #define I2C_TXDR_TXDATA_Pos          (0U)                                      
6896 #define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
6897 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
6898
6899 /*****************************************************************************/
6900 /*                                                                           */
6901 /*                        Independent WATCHDOG (IWDG)                        */
6902 /*                                                                           */
6903 /*****************************************************************************/
6904 /*******************  Bit definition for IWDG_KR register  *******************/
6905 #define IWDG_KR_KEY_Pos      (0U)                                              
6906 #define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
6907 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
6908
6909 /*******************  Bit definition for IWDG_PR register  *******************/
6910 #define IWDG_PR_PR_Pos       (0U)                                              
6911 #define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
6912 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
6913 #define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x01 */
6914 #define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x02 */
6915 #define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x04 */
6916
6917 /*******************  Bit definition for IWDG_RLR register  ******************/
6918 #define IWDG_RLR_RL_Pos      (0U)                                              
6919 #define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
6920 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
6921
6922 /*******************  Bit definition for IWDG_SR register  *******************/
6923 #define IWDG_SR_PVU_Pos      (0U)                                              
6924 #define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
6925 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
6926 #define IWDG_SR_RVU_Pos      (1U)                                              
6927 #define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
6928 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
6929 #define IWDG_SR_WVU_Pos      (2U)                                              
6930 #define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
6931 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
6932
6933 /*******************  Bit definition for IWDG_KR register  *******************/
6934 #define IWDG_WINR_WIN_Pos    (0U)                                              
6935 #define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
6936 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
6937
6938 /*****************************************************************************/
6939 /*                                                                           */
6940 /*                          Power Control (PWR)                              */
6941 /*                                                                           */
6942 /*****************************************************************************/
6943
6944 #define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
6945
6946
6947 /********************  Bit definition for PWR_CR register  *******************/
6948 #define PWR_CR_LPDS_Pos            (0U)                                        
6949 #define PWR_CR_LPDS_Msk            (0x1U << PWR_CR_LPDS_Pos)                   /*!< 0x00000001 */
6950 #define PWR_CR_LPDS                PWR_CR_LPDS_Msk                             /*!< Low-power Deepsleep */
6951 #define PWR_CR_PDDS_Pos            (1U)                                        
6952 #define PWR_CR_PDDS_Msk            (0x1U << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
6953 #define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
6954 #define PWR_CR_CWUF_Pos            (2U)                                        
6955 #define PWR_CR_CWUF_Msk            (0x1U << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
6956 #define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
6957 #define PWR_CR_CSBF_Pos            (3U)                                        
6958 #define PWR_CR_CSBF_Msk            (0x1U << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
6959 #define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
6960 #define PWR_CR_PVDE_Pos            (4U)                                        
6961 #define PWR_CR_PVDE_Msk            (0x1U << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
6962 #define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
6963
6964 #define PWR_CR_PLS_Pos             (5U)                                        
6965 #define PWR_CR_PLS_Msk             (0x7U << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
6966 #define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
6967 #define PWR_CR_PLS_0               (0x1U << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
6968 #define PWR_CR_PLS_1               (0x2U << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
6969 #define PWR_CR_PLS_2               (0x4U << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
6970
6971 /*!< PVD level configuration */
6972 #define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
6973 #define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
6974 #define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
6975 #define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
6976 #define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
6977 #define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
6978 #define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
6979 #define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
6980
6981 #define PWR_CR_DBP_Pos             (8U)                                        
6982 #define PWR_CR_DBP_Msk             (0x1U << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
6983 #define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
6984
6985 /*******************  Bit definition for PWR_CSR register  *******************/
6986 #define PWR_CSR_WUF_Pos            (0U)                                        
6987 #define PWR_CSR_WUF_Msk            (0x1U << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
6988 #define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
6989 #define PWR_CSR_SBF_Pos            (1U)                                        
6990 #define PWR_CSR_SBF_Msk            (0x1U << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
6991 #define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
6992 #define PWR_CSR_PVDO_Pos           (2U)                                        
6993 #define PWR_CSR_PVDO_Msk           (0x1U << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
6994 #define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
6995 #define PWR_CSR_VREFINTRDYF_Pos    (3U)                                        
6996 #define PWR_CSR_VREFINTRDYF_Msk    (0x1U << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
6997 #define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
6998
6999 #define PWR_CSR_EWUP1_Pos          (8U)                                        
7000 #define PWR_CSR_EWUP1_Msk          (0x1U << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
7001 #define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
7002 #define PWR_CSR_EWUP2_Pos          (9U)                                        
7003 #define PWR_CSR_EWUP2_Msk          (0x1U << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
7004 #define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
7005 #define PWR_CSR_EWUP4_Pos          (11U)                                       
7006 #define PWR_CSR_EWUP4_Msk          (0x1U << PWR_CSR_EWUP4_Pos)                 /*!< 0x00000800 */
7007 #define PWR_CSR_EWUP4              PWR_CSR_EWUP4_Msk                           /*!< Enable WKUP pin 4 */
7008 #define PWR_CSR_EWUP6_Pos          (13U)                                       
7009 #define PWR_CSR_EWUP6_Msk          (0x1U << PWR_CSR_EWUP6_Pos)                 /*!< 0x00002000 */
7010 #define PWR_CSR_EWUP6              PWR_CSR_EWUP6_Msk                           /*!< Enable WKUP pin 6 */
7011 #define PWR_CSR_EWUP7_Pos          (14U)                                       
7012 #define PWR_CSR_EWUP7_Msk          (0x1U << PWR_CSR_EWUP7_Pos)                 /*!< 0x00004000 */
7013 #define PWR_CSR_EWUP7              PWR_CSR_EWUP7_Msk                           /*!< Enable WKUP pin 7 */
7014
7015 /*****************************************************************************/
7016 /*                                                                           */
7017 /*                         Reset and Clock Control                           */
7018 /*                                                                           */
7019 /*****************************************************************************/
7020 /*
7021 * @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
7022 */
7023 #define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
7024 #define RCC_PLLSRC_PREDIV1_SUPPORT  /*!< PREDIV support used as PLL source input  */
7025
7026 /********************  Bit definition for RCC_CR register  *******************/
7027 #define RCC_CR_HSION_Pos                         (0U)                          
7028 #define RCC_CR_HSION_Msk                         (0x1U << RCC_CR_HSION_Pos)    /*!< 0x00000001 */
7029 #define RCC_CR_HSION                             RCC_CR_HSION_Msk              /*!< Internal High Speed clock enable */
7030 #define RCC_CR_HSIRDY_Pos                        (1U)                          
7031 #define RCC_CR_HSIRDY_Msk                        (0x1U << RCC_CR_HSIRDY_Pos)   /*!< 0x00000002 */
7032 #define RCC_CR_HSIRDY                            RCC_CR_HSIRDY_Msk             /*!< Internal High Speed clock ready flag */
7033
7034 #define RCC_CR_HSITRIM_Pos                       (3U)                          
7035 #define RCC_CR_HSITRIM_Msk                       (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
7036 #define RCC_CR_HSITRIM                           RCC_CR_HSITRIM_Msk            /*!< Internal High Speed clock trimming */
7037 #define RCC_CR_HSITRIM_0                         (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
7038 #define RCC_CR_HSITRIM_1                         (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
7039 #define RCC_CR_HSITRIM_2                         (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
7040 #define RCC_CR_HSITRIM_3                         (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
7041 #define RCC_CR_HSITRIM_4                         (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
7042
7043 #define RCC_CR_HSICAL_Pos                        (8U)                          
7044 #define RCC_CR_HSICAL_Msk                        (0xFFU << RCC_CR_HSICAL_Pos)  /*!< 0x0000FF00 */
7045 #define RCC_CR_HSICAL                            RCC_CR_HSICAL_Msk             /*!< Internal High Speed clock Calibration */
7046 #define RCC_CR_HSICAL_0                          (0x01U << RCC_CR_HSICAL_Pos)  /*!< 0x00000100 */
7047 #define RCC_CR_HSICAL_1                          (0x02U << RCC_CR_HSICAL_Pos)  /*!< 0x00000200 */
7048 #define RCC_CR_HSICAL_2                          (0x04U << RCC_CR_HSICAL_Pos)  /*!< 0x00000400 */
7049 #define RCC_CR_HSICAL_3                          (0x08U << RCC_CR_HSICAL_Pos)  /*!< 0x00000800 */
7050 #define RCC_CR_HSICAL_4                          (0x10U << RCC_CR_HSICAL_Pos)  /*!< 0x00001000 */
7051 #define RCC_CR_HSICAL_5                          (0x20U << RCC_CR_HSICAL_Pos)  /*!< 0x00002000 */
7052 #define RCC_CR_HSICAL_6                          (0x40U << RCC_CR_HSICAL_Pos)  /*!< 0x00004000 */
7053 #define RCC_CR_HSICAL_7                          (0x80U << RCC_CR_HSICAL_Pos)  /*!< 0x00008000 */
7054
7055 #define RCC_CR_HSEON_Pos                         (16U)                         
7056 #define RCC_CR_HSEON_Msk                         (0x1U << RCC_CR_HSEON_Pos)    /*!< 0x00010000 */
7057 #define RCC_CR_HSEON                             RCC_CR_HSEON_Msk              /*!< External High Speed clock enable */
7058 #define RCC_CR_HSERDY_Pos                        (17U)                         
7059 #define RCC_CR_HSERDY_Msk                        (0x1U << RCC_CR_HSERDY_Pos)   /*!< 0x00020000 */
7060 #define RCC_CR_HSERDY                            RCC_CR_HSERDY_Msk             /*!< External High Speed clock ready flag */
7061 #define RCC_CR_HSEBYP_Pos                        (18U)                         
7062 #define RCC_CR_HSEBYP_Msk                        (0x1U << RCC_CR_HSEBYP_Pos)   /*!< 0x00040000 */
7063 #define RCC_CR_HSEBYP                            RCC_CR_HSEBYP_Msk             /*!< External High Speed clock Bypass */
7064 #define RCC_CR_CSSON_Pos                         (19U)                         
7065 #define RCC_CR_CSSON_Msk                         (0x1U << RCC_CR_CSSON_Pos)    /*!< 0x00080000 */
7066 #define RCC_CR_CSSON                             RCC_CR_CSSON_Msk              /*!< Clock Security System enable */
7067 #define RCC_CR_PLLON_Pos                         (24U)                         
7068 #define RCC_CR_PLLON_Msk                         (0x1U << RCC_CR_PLLON_Pos)    /*!< 0x01000000 */
7069 #define RCC_CR_PLLON                             RCC_CR_PLLON_Msk              /*!< PLL enable */
7070 #define RCC_CR_PLLRDY_Pos                        (25U)                         
7071 #define RCC_CR_PLLRDY_Msk                        (0x1U << RCC_CR_PLLRDY_Pos)   /*!< 0x02000000 */
7072 #define RCC_CR_PLLRDY                            RCC_CR_PLLRDY_Msk             /*!< PLL clock ready flag */
7073
7074 /********************  Bit definition for RCC_CFGR register  *****************/
7075 /*!< SW configuration */
7076 #define RCC_CFGR_SW_Pos                          (0U)                          
7077 #define RCC_CFGR_SW_Msk                          (0x3U << RCC_CFGR_SW_Pos)     /*!< 0x00000003 */
7078 #define RCC_CFGR_SW                              RCC_CFGR_SW_Msk               /*!< SW[1:0] bits (System clock Switch) */
7079 #define RCC_CFGR_SW_0                            (0x1U << RCC_CFGR_SW_Pos)     /*!< 0x00000001 */
7080 #define RCC_CFGR_SW_1                            (0x2U << RCC_CFGR_SW_Pos)     /*!< 0x00000002 */
7081
7082 #define RCC_CFGR_SW_HSI                          (0x00000000U)                 /*!< HSI selected as system clock */
7083 #define RCC_CFGR_SW_HSE                          (0x00000001U)                 /*!< HSE selected as system clock */
7084 #define RCC_CFGR_SW_PLL                          (0x00000002U)                 /*!< PLL selected as system clock */
7085 #define RCC_CFGR_SW_HSI48                        (0x00000003U)                 /*!< HSI48 selected as system clock */
7086
7087 /*!< SWS configuration */
7088 #define RCC_CFGR_SWS_Pos                         (2U)                          
7089 #define RCC_CFGR_SWS_Msk                         (0x3U << RCC_CFGR_SWS_Pos)    /*!< 0x0000000C */
7090 #define RCC_CFGR_SWS                             RCC_CFGR_SWS_Msk              /*!< SWS[1:0] bits (System Clock Switch Status) */
7091 #define RCC_CFGR_SWS_0                           (0x1U << RCC_CFGR_SWS_Pos)    /*!< 0x00000004 */
7092 #define RCC_CFGR_SWS_1                           (0x2U << RCC_CFGR_SWS_Pos)    /*!< 0x00000008 */
7093
7094 #define RCC_CFGR_SWS_HSI                         (0x00000000U)                 /*!< HSI oscillator used as system clock */
7095 #define RCC_CFGR_SWS_HSE                         (0x00000004U)                 /*!< HSE oscillator used as system clock */
7096 #define RCC_CFGR_SWS_PLL                         (0x00000008U)                 /*!< PLL used as system clock */
7097 #define RCC_CFGR_SWS_HSI48                       (0x0000000CU)                 /*!< HSI48 oscillator used as system clock */
7098
7099 /*!< HPRE configuration */
7100 #define RCC_CFGR_HPRE_Pos                        (4U)                          
7101 #define RCC_CFGR_HPRE_Msk                        (0xFU << RCC_CFGR_HPRE_Pos)   /*!< 0x000000F0 */
7102 #define RCC_CFGR_HPRE                            RCC_CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB prescaler) */
7103 #define RCC_CFGR_HPRE_0                          (0x1U << RCC_CFGR_HPRE_Pos)   /*!< 0x00000010 */
7104 #define RCC_CFGR_HPRE_1                          (0x2U << RCC_CFGR_HPRE_Pos)   /*!< 0x00000020 */
7105 #define RCC_CFGR_HPRE_2                          (0x4U << RCC_CFGR_HPRE_Pos)   /*!< 0x00000040 */
7106 #define RCC_CFGR_HPRE_3                          (0x8U << RCC_CFGR_HPRE_Pos)   /*!< 0x00000080 */
7107
7108 #define RCC_CFGR_HPRE_DIV1                       (0x00000000U)                 /*!< SYSCLK not divided */
7109 #define RCC_CFGR_HPRE_DIV2                       (0x00000080U)                 /*!< SYSCLK divided by 2 */
7110 #define RCC_CFGR_HPRE_DIV4                       (0x00000090U)                 /*!< SYSCLK divided by 4 */
7111 #define RCC_CFGR_HPRE_DIV8                       (0x000000A0U)                 /*!< SYSCLK divided by 8 */
7112 #define RCC_CFGR_HPRE_DIV16                      (0x000000B0U)                 /*!< SYSCLK divided by 16 */
7113 #define RCC_CFGR_HPRE_DIV64                      (0x000000C0U)                 /*!< SYSCLK divided by 64 */
7114 #define RCC_CFGR_HPRE_DIV128                     (0x000000D0U)                 /*!< SYSCLK divided by 128 */
7115 #define RCC_CFGR_HPRE_DIV256                     (0x000000E0U)                 /*!< SYSCLK divided by 256 */
7116 #define RCC_CFGR_HPRE_DIV512                     (0x000000F0U)                 /*!< SYSCLK divided by 512 */
7117
7118 /*!< PPRE configuration */
7119 #define RCC_CFGR_PPRE_Pos                        (8U)                          
7120 #define RCC_CFGR_PPRE_Msk                        (0x7U << RCC_CFGR_PPRE_Pos)   /*!< 0x00000700 */
7121 #define RCC_CFGR_PPRE                            RCC_CFGR_PPRE_Msk             /*!< PRE[2:0] bits (APB prescaler) */
7122 #define RCC_CFGR_PPRE_0                          (0x1U << RCC_CFGR_PPRE_Pos)   /*!< 0x00000100 */
7123 #define RCC_CFGR_PPRE_1                          (0x2U << RCC_CFGR_PPRE_Pos)   /*!< 0x00000200 */
7124 #define RCC_CFGR_PPRE_2                          (0x4U << RCC_CFGR_PPRE_Pos)   /*!< 0x00000400 */
7125
7126 #define RCC_CFGR_PPRE_DIV1                       (0x00000000U)                 /*!< HCLK not divided */
7127 #define RCC_CFGR_PPRE_DIV2_Pos                   (10U)                         
7128 #define RCC_CFGR_PPRE_DIV2_Msk                   (0x1U << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */
7129 #define RCC_CFGR_PPRE_DIV2                       RCC_CFGR_PPRE_DIV2_Msk        /*!< HCLK divided by 2 */
7130 #define RCC_CFGR_PPRE_DIV4_Pos                   (8U)                          
7131 #define RCC_CFGR_PPRE_DIV4_Msk                   (0x5U << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */
7132 #define RCC_CFGR_PPRE_DIV4                       RCC_CFGR_PPRE_DIV4_Msk        /*!< HCLK divided by 4 */
7133 #define RCC_CFGR_PPRE_DIV8_Pos                   (9U)                          
7134 #define RCC_CFGR_PPRE_DIV8_Msk                   (0x3U << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */
7135 #define RCC_CFGR_PPRE_DIV8                       RCC_CFGR_PPRE_DIV8_Msk        /*!< HCLK divided by 8 */
7136 #define RCC_CFGR_PPRE_DIV16_Pos                  (8U)                          
7137 #define RCC_CFGR_PPRE_DIV16_Msk                  (0x7U << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
7138 #define RCC_CFGR_PPRE_DIV16                      RCC_CFGR_PPRE_DIV16_Msk       /*!< HCLK divided by 16 */
7139
7140 /*!< ADCPPRE configuration */
7141 #define RCC_CFGR_ADCPRE_Pos                      (14U)                         
7142 #define RCC_CFGR_ADCPRE_Msk                      (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
7143 #define RCC_CFGR_ADCPRE                          RCC_CFGR_ADCPRE_Msk           /*!< ADCPRE bit (ADC prescaler) */
7144
7145 #define RCC_CFGR_ADCPRE_DIV2                     (0x00000000U)                 /*!< PCLK divided by 2 */
7146 #define RCC_CFGR_ADCPRE_DIV4                     (0x00004000U)                 /*!< PCLK divided by 4 */
7147
7148 #define RCC_CFGR_PLLSRC_Pos                      (15U)                         
7149 #define RCC_CFGR_PLLSRC_Msk                      (0x3U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */
7150 #define RCC_CFGR_PLLSRC                          RCC_CFGR_PLLSRC_Msk           /*!< PLL entry clock source */
7151 #define RCC_CFGR_PLLSRC_HSI_DIV2                 (0x00000000U)                 /*!< HSI clock divided by 2 selected as PLL entry clock source */
7152 #define RCC_CFGR_PLLSRC_HSI_PREDIV               (0x00008000U)                 /*!< HSI/PREDIV clock selected as PLL entry clock source */
7153 #define RCC_CFGR_PLLSRC_HSE_PREDIV               (0x00010000U)                 /*!< HSE/PREDIV clock selected as PLL entry clock source */
7154 #define RCC_CFGR_PLLSRC_HSI48_PREDIV             (0x00018000U)                 /*!< HSI48/PREDIV clock selected as PLL entry clock source */
7155
7156 #define RCC_CFGR_PLLXTPRE_Pos                    (17U)                         
7157 #define RCC_CFGR_PLLXTPRE_Msk                    (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
7158 #define RCC_CFGR_PLLXTPRE                        RCC_CFGR_PLLXTPRE_Msk         /*!< HSE divider for PLL entry */
7159 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1        (0x00000000U)                 /*!< HSE/PREDIV clock not divided for PLL entry */
7160 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2        (0x00020000U)                 /*!< HSE/PREDIV clock divided by 2 for PLL entry */
7161
7162 /*!< PLLMUL configuration */
7163 #define RCC_CFGR_PLLMUL_Pos                      (18U)                         
7164 #define RCC_CFGR_PLLMUL_Msk                      (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
7165 #define RCC_CFGR_PLLMUL                          RCC_CFGR_PLLMUL_Msk           /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
7166 #define RCC_CFGR_PLLMUL_0                        (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
7167 #define RCC_CFGR_PLLMUL_1                        (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
7168 #define RCC_CFGR_PLLMUL_2                        (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
7169 #define RCC_CFGR_PLLMUL_3                        (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
7170
7171 #define RCC_CFGR_PLLMUL2                         (0x00000000U)                 /*!< PLL input clock*2 */
7172 #define RCC_CFGR_PLLMUL3                         (0x00040000U)                 /*!< PLL input clock*3 */
7173 #define RCC_CFGR_PLLMUL4                         (0x00080000U)                 /*!< PLL input clock*4 */
7174 #define RCC_CFGR_PLLMUL5                         (0x000C0000U)                 /*!< PLL input clock*5 */
7175 #define RCC_CFGR_PLLMUL6                         (0x00100000U)                 /*!< PLL input clock*6 */
7176 #define RCC_CFGR_PLLMUL7                         (0x00140000U)                 /*!< PLL input clock*7 */
7177 #define RCC_CFGR_PLLMUL8                         (0x00180000U)                 /*!< PLL input clock*8 */
7178 #define RCC_CFGR_PLLMUL9                         (0x001C0000U)                 /*!< PLL input clock*9 */
7179 #define RCC_CFGR_PLLMUL10                        (0x00200000U)                 /*!< PLL input clock10 */
7180 #define RCC_CFGR_PLLMUL11                        (0x00240000U)                 /*!< PLL input clock*11 */
7181 #define RCC_CFGR_PLLMUL12                        (0x00280000U)                 /*!< PLL input clock*12 */
7182 #define RCC_CFGR_PLLMUL13                        (0x002C0000U)                 /*!< PLL input clock*13 */
7183 #define RCC_CFGR_PLLMUL14                        (0x00300000U)                 /*!< PLL input clock*14 */
7184 #define RCC_CFGR_PLLMUL15                        (0x00340000U)                 /*!< PLL input clock*15 */
7185 #define RCC_CFGR_PLLMUL16                        (0x00380000U)                 /*!< PLL input clock*16 */
7186
7187 /*!< USB configuration */
7188 #define RCC_CFGR_USBPRE_Pos                      (22U)                         
7189 #define RCC_CFGR_USBPRE_Msk                      (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
7190 #define RCC_CFGR_USBPRE                          RCC_CFGR_USBPRE_Msk           /*!< USB prescaler */
7191
7192 /*!< MCO configuration */
7193 #define RCC_CFGR_MCO_Pos                         (24U)                         
7194 #define RCC_CFGR_MCO_Msk                         (0xFU << RCC_CFGR_MCO_Pos)    /*!< 0x0F000000 */
7195 #define RCC_CFGR_MCO                             RCC_CFGR_MCO_Msk              /*!< MCO[3:0] bits (Microcontroller Clock Output) */
7196 #define RCC_CFGR_MCO_0                           (0x1U << RCC_CFGR_MCO_Pos)    /*!< 0x01000000 */
7197 #define RCC_CFGR_MCO_1                           (0x2U << RCC_CFGR_MCO_Pos)    /*!< 0x02000000 */
7198 #define RCC_CFGR_MCO_2                           (0x4U << RCC_CFGR_MCO_Pos)    /*!< 0x04000000 */
7199 #define RCC_CFGR_MCO_3                           (0x08000000U)                 /*!< Bit 3 */
7200
7201 #define RCC_CFGR_MCO_NOCLOCK                     (0x00000000U)                 /*!< No clock */
7202 #define RCC_CFGR_MCO_HSI14                       (0x01000000U)                 /*!< HSI14 clock selected as MCO source */
7203 #define RCC_CFGR_MCO_LSI                         (0x02000000U)                 /*!< LSI clock selected as MCO source */
7204 #define RCC_CFGR_MCO_LSE                         (0x03000000U)                 /*!< LSE clock selected as MCO source */
7205 #define RCC_CFGR_MCO_SYSCLK                      (0x04000000U)                 /*!< System clock selected as MCO source */
7206 #define RCC_CFGR_MCO_HSI                         (0x05000000U)                 /*!< HSI clock selected as MCO source */
7207 #define RCC_CFGR_MCO_HSE                         (0x06000000U)                 /*!< HSE clock selected as MCO source  */
7208 #define RCC_CFGR_MCO_PLL                         (0x07000000U)                 /*!< PLL clock divided by 2 selected as MCO source */
7209 #define RCC_CFGR_MCO_HSI48                       (0x08000000U)                 /*!< HSI48 clock selected as MCO source */
7210
7211 #define RCC_CFGR_MCOPRE_Pos                      (28U)                         
7212 #define RCC_CFGR_MCOPRE_Msk                      (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
7213 #define RCC_CFGR_MCOPRE                          RCC_CFGR_MCOPRE_Msk           /*!< MCO prescaler  */
7214 #define RCC_CFGR_MCOPRE_DIV1                     (0x00000000U)                 /*!< MCO is divided by 1  */
7215 #define RCC_CFGR_MCOPRE_DIV2                     (0x10000000U)                 /*!< MCO is divided by 2  */
7216 #define RCC_CFGR_MCOPRE_DIV4                     (0x20000000U)                 /*!< MCO is divided by 4  */
7217 #define RCC_CFGR_MCOPRE_DIV8                     (0x30000000U)                 /*!< MCO is divided by 8  */
7218 #define RCC_CFGR_MCOPRE_DIV16                    (0x40000000U)                 /*!< MCO is divided by 16  */
7219 #define RCC_CFGR_MCOPRE_DIV32                    (0x50000000U)                 /*!< MCO is divided by 32  */
7220 #define RCC_CFGR_MCOPRE_DIV64                    (0x60000000U)                 /*!< MCO is divided by 64  */
7221 #define RCC_CFGR_MCOPRE_DIV128                   (0x70000000U)                 /*!< MCO is divided by 128  */
7222
7223 #define RCC_CFGR_PLLNODIV_Pos                    (31U)                         
7224 #define RCC_CFGR_PLLNODIV_Msk                    (0x1U << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
7225 #define RCC_CFGR_PLLNODIV                        RCC_CFGR_PLLNODIV_Msk         /*!< PLL is not divided to MCO  */
7226
7227 /* Reference defines */
7228 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO
7229 #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0
7230 #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1
7231 #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2
7232 #define RCC_CFGR_MCOSEL_3                    RCC_CFGR_MCO_3
7233 #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK
7234 #define RCC_CFGR_MCOSEL_HSI14                RCC_CFGR_MCO_HSI14
7235 #define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCO_LSI
7236 #define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCO_LSE
7237 #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK
7238 #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI
7239 #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE
7240 #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLL
7241 #define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCO_HSI48
7242
7243 /*!<******************  Bit definition for RCC_CIR register  *****************/
7244 #define RCC_CIR_LSIRDYF_Pos                      (0U)                          
7245 #define RCC_CIR_LSIRDYF_Msk                      (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
7246 #define RCC_CIR_LSIRDYF                          RCC_CIR_LSIRDYF_Msk           /*!< LSI Ready Interrupt flag */
7247 #define RCC_CIR_LSERDYF_Pos                      (1U)                          
7248 #define RCC_CIR_LSERDYF_Msk                      (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
7249 #define RCC_CIR_LSERDYF                          RCC_CIR_LSERDYF_Msk           /*!< LSE Ready Interrupt flag */
7250 #define RCC_CIR_HSIRDYF_Pos                      (2U)                          
7251 #define RCC_CIR_HSIRDYF_Msk                      (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
7252 #define RCC_CIR_HSIRDYF                          RCC_CIR_HSIRDYF_Msk           /*!< HSI Ready Interrupt flag */
7253 #define RCC_CIR_HSERDYF_Pos                      (3U)                          
7254 #define RCC_CIR_HSERDYF_Msk                      (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
7255 #define RCC_CIR_HSERDYF                          RCC_CIR_HSERDYF_Msk           /*!< HSE Ready Interrupt flag */
7256 #define RCC_CIR_PLLRDYF_Pos                      (4U)                          
7257 #define RCC_CIR_PLLRDYF_Msk                      (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
7258 #define RCC_CIR_PLLRDYF                          RCC_CIR_PLLRDYF_Msk           /*!< PLL Ready Interrupt flag */
7259 #define RCC_CIR_HSI14RDYF_Pos                    (5U)                          
7260 #define RCC_CIR_HSI14RDYF_Msk                    (0x1U << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */
7261 #define RCC_CIR_HSI14RDYF                        RCC_CIR_HSI14RDYF_Msk         /*!< HSI14 Ready Interrupt flag */
7262 #define RCC_CIR_HSI48RDYF_Pos                    (6U)                          
7263 #define RCC_CIR_HSI48RDYF_Msk                    (0x1U << RCC_CIR_HSI48RDYF_Pos) /*!< 0x00000040 */
7264 #define RCC_CIR_HSI48RDYF                        RCC_CIR_HSI48RDYF_Msk         /*!< HSI48 Ready Interrupt flag */
7265 #define RCC_CIR_CSSF_Pos                         (7U)                          
7266 #define RCC_CIR_CSSF_Msk                         (0x1U << RCC_CIR_CSSF_Pos)    /*!< 0x00000080 */
7267 #define RCC_CIR_CSSF                             RCC_CIR_CSSF_Msk              /*!< Clock Security System Interrupt flag */
7268 #define RCC_CIR_LSIRDYIE_Pos                     (8U)                          
7269 #define RCC_CIR_LSIRDYIE_Msk                     (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
7270 #define RCC_CIR_LSIRDYIE                         RCC_CIR_LSIRDYIE_Msk          /*!< LSI Ready Interrupt Enable */
7271 #define RCC_CIR_LSERDYIE_Pos                     (9U)                          
7272 #define RCC_CIR_LSERDYIE_Msk                     (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
7273 #define RCC_CIR_LSERDYIE                         RCC_CIR_LSERDYIE_Msk          /*!< LSE Ready Interrupt Enable */
7274 #define RCC_CIR_HSIRDYIE_Pos                     (10U)                         
7275 #define RCC_CIR_HSIRDYIE_Msk                     (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
7276 #define RCC_CIR_HSIRDYIE                         RCC_CIR_HSIRDYIE_Msk          /*!< HSI Ready Interrupt Enable */
7277 #define RCC_CIR_HSERDYIE_Pos                     (11U)                         
7278 #define RCC_CIR_HSERDYIE_Msk                     (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
7279 #define RCC_CIR_HSERDYIE                         RCC_CIR_HSERDYIE_Msk          /*!< HSE Ready Interrupt Enable */
7280 #define RCC_CIR_PLLRDYIE_Pos                     (12U)                         
7281 #define RCC_CIR_PLLRDYIE_Msk                     (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
7282 #define RCC_CIR_PLLRDYIE                         RCC_CIR_PLLRDYIE_Msk          /*!< PLL Ready Interrupt Enable */
7283 #define RCC_CIR_HSI14RDYIE_Pos                   (13U)                         
7284 #define RCC_CIR_HSI14RDYIE_Msk                   (0x1U << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */
7285 #define RCC_CIR_HSI14RDYIE                       RCC_CIR_HSI14RDYIE_Msk        /*!< HSI14 Ready Interrupt Enable */
7286 #define RCC_CIR_HSI48RDYIE_Pos                   (14U)                         
7287 #define RCC_CIR_HSI48RDYIE_Msk                   (0x1U << RCC_CIR_HSI48RDYIE_Pos) /*!< 0x00004000 */
7288 #define RCC_CIR_HSI48RDYIE                       RCC_CIR_HSI48RDYIE_Msk        /*!< HSI48 Ready Interrupt Enable */
7289 #define RCC_CIR_LSIRDYC_Pos                      (16U)                         
7290 #define RCC_CIR_LSIRDYC_Msk                      (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
7291 #define RCC_CIR_LSIRDYC                          RCC_CIR_LSIRDYC_Msk           /*!< LSI Ready Interrupt Clear */
7292 #define RCC_CIR_LSERDYC_Pos                      (17U)                         
7293 #define RCC_CIR_LSERDYC_Msk                      (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
7294 #define RCC_CIR_LSERDYC                          RCC_CIR_LSERDYC_Msk           /*!< LSE Ready Interrupt Clear */
7295 #define RCC_CIR_HSIRDYC_Pos                      (18U)                         
7296 #define RCC_CIR_HSIRDYC_Msk                      (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
7297 #define RCC_CIR_HSIRDYC                          RCC_CIR_HSIRDYC_Msk           /*!< HSI Ready Interrupt Clear */
7298 #define RCC_CIR_HSERDYC_Pos                      (19U)                         
7299 #define RCC_CIR_HSERDYC_Msk                      (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
7300 #define RCC_CIR_HSERDYC                          RCC_CIR_HSERDYC_Msk           /*!< HSE Ready Interrupt Clear */
7301 #define RCC_CIR_PLLRDYC_Pos                      (20U)                         
7302 #define RCC_CIR_PLLRDYC_Msk                      (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
7303 #define RCC_CIR_PLLRDYC                          RCC_CIR_PLLRDYC_Msk           /*!< PLL Ready Interrupt Clear */
7304 #define RCC_CIR_HSI14RDYC_Pos                    (21U)                         
7305 #define RCC_CIR_HSI14RDYC_Msk                    (0x1U << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */
7306 #define RCC_CIR_HSI14RDYC                        RCC_CIR_HSI14RDYC_Msk         /*!< HSI14 Ready Interrupt Clear */
7307 #define RCC_CIR_HSI48RDYC_Pos                    (22U)                         
7308 #define RCC_CIR_HSI48RDYC_Msk                    (0x1U << RCC_CIR_HSI48RDYC_Pos) /*!< 0x00400000 */
7309 #define RCC_CIR_HSI48RDYC                        RCC_CIR_HSI48RDYC_Msk         /*!< HSI48 Ready Interrupt Clear */
7310 #define RCC_CIR_CSSC_Pos                         (23U)                         
7311 #define RCC_CIR_CSSC_Msk                         (0x1U << RCC_CIR_CSSC_Pos)    /*!< 0x00800000 */
7312 #define RCC_CIR_CSSC                             RCC_CIR_CSSC_Msk              /*!< Clock Security System Interrupt Clear */
7313
7314 /*****************  Bit definition for RCC_APB2RSTR register  ****************/
7315 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)                          
7316 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
7317 #define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
7318 #define RCC_APB2RSTR_ADCRST_Pos                  (9U)                          
7319 #define RCC_APB2RSTR_ADCRST_Msk                  (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
7320 #define RCC_APB2RSTR_ADCRST                      RCC_APB2RSTR_ADCRST_Msk       /*!< ADC reset */
7321 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)                         
7322 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
7323 #define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
7324 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)                         
7325 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
7326 #define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
7327 #define RCC_APB2RSTR_USART1RST_Pos               (14U)                         
7328 #define RCC_APB2RSTR_USART1RST_Msk               (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
7329 #define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
7330 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)                         
7331 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
7332 #define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
7333 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)                         
7334 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
7335 #define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
7336 #define RCC_APB2RSTR_DBGMCURST_Pos               (22U)                         
7337 #define RCC_APB2RSTR_DBGMCURST_Msk               (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
7338 #define RCC_APB2RSTR_DBGMCURST                   RCC_APB2RSTR_DBGMCURST_Msk    /*!< DBGMCU reset */
7339
7340 /*!< Old ADC1 reset bit definition maintained for legacy purpose */
7341 #define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST          
7342
7343 /*****************  Bit definition for RCC_APB1RSTR register  ****************/
7344 #define RCC_APB1RSTR_TIM2RST_Pos                 (0U)                          
7345 #define RCC_APB1RSTR_TIM2RST_Msk                 (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
7346 #define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 reset */
7347 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)                          
7348 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
7349 #define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
7350 #define RCC_APB1RSTR_TIM14RST_Pos                (8U)                          
7351 #define RCC_APB1RSTR_TIM14RST_Msk                (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
7352 #define RCC_APB1RSTR_TIM14RST                    RCC_APB1RSTR_TIM14RST_Msk     /*!< Timer 14 reset */
7353 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)                         
7354 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
7355 #define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
7356 #define RCC_APB1RSTR_SPI2RST_Pos                 (14U)                         
7357 #define RCC_APB1RSTR_SPI2RST_Msk                 (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
7358 #define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 reset */
7359 #define RCC_APB1RSTR_USART2RST_Pos               (17U)                         
7360 #define RCC_APB1RSTR_USART2RST_Msk               (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
7361 #define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
7362 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)                         
7363 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
7364 #define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
7365 #define RCC_APB1RSTR_USBRST_Pos                  (23U)                         
7366 #define RCC_APB1RSTR_USBRST_Msk                  (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
7367 #define RCC_APB1RSTR_USBRST                      RCC_APB1RSTR_USBRST_Msk       /*!< USB reset */
7368 #define RCC_APB1RSTR_CANRST_Pos                  (25U)                         
7369 #define RCC_APB1RSTR_CANRST_Msk                  (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
7370 #define RCC_APB1RSTR_CANRST                      RCC_APB1RSTR_CANRST_Msk       /*!< CAN reset */
7371 #define RCC_APB1RSTR_CRSRST_Pos                  (27U)                         
7372 #define RCC_APB1RSTR_CRSRST_Msk                  (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
7373 #define RCC_APB1RSTR_CRSRST                      RCC_APB1RSTR_CRSRST_Msk       /*!< CRS reset */
7374 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)                         
7375 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
7376 #define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
7377 #define RCC_APB1RSTR_CECRST_Pos                  (30U)                         
7378 #define RCC_APB1RSTR_CECRST_Msk                  (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
7379 #define RCC_APB1RSTR_CECRST                      RCC_APB1RSTR_CECRST_Msk       /*!< CEC reset */
7380
7381 /******************  Bit definition for RCC_AHBENR register  *****************/
7382 #define RCC_AHBENR_DMAEN_Pos                     (0U)                          
7383 #define RCC_AHBENR_DMAEN_Msk                     (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
7384 #define RCC_AHBENR_DMAEN                         RCC_AHBENR_DMAEN_Msk          /*!< DMA1 clock enable */
7385 #define RCC_AHBENR_SRAMEN_Pos                    (2U)                          
7386 #define RCC_AHBENR_SRAMEN_Msk                    (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
7387 #define RCC_AHBENR_SRAMEN                        RCC_AHBENR_SRAMEN_Msk         /*!< SRAM interface clock enable */
7388 #define RCC_AHBENR_FLITFEN_Pos                   (4U)                          
7389 #define RCC_AHBENR_FLITFEN_Msk                   (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
7390 #define RCC_AHBENR_FLITFEN                       RCC_AHBENR_FLITFEN_Msk        /*!< FLITF clock enable */
7391 #define RCC_AHBENR_CRCEN_Pos                     (6U)                          
7392 #define RCC_AHBENR_CRCEN_Msk                     (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
7393 #define RCC_AHBENR_CRCEN                         RCC_AHBENR_CRCEN_Msk          /*!< CRC clock enable */
7394 #define RCC_AHBENR_GPIOAEN_Pos                   (17U)                         
7395 #define RCC_AHBENR_GPIOAEN_Msk                   (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
7396 #define RCC_AHBENR_GPIOAEN                       RCC_AHBENR_GPIOAEN_Msk        /*!< GPIOA clock enable */
7397 #define RCC_AHBENR_GPIOBEN_Pos                   (18U)                         
7398 #define RCC_AHBENR_GPIOBEN_Msk                   (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
7399 #define RCC_AHBENR_GPIOBEN                       RCC_AHBENR_GPIOBEN_Msk        /*!< GPIOB clock enable */
7400 #define RCC_AHBENR_GPIOCEN_Pos                   (19U)                         
7401 #define RCC_AHBENR_GPIOCEN_Msk                   (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
7402 #define RCC_AHBENR_GPIOCEN                       RCC_AHBENR_GPIOCEN_Msk        /*!< GPIOC clock enable */
7403 #define RCC_AHBENR_GPIOFEN_Pos                   (22U)                         
7404 #define RCC_AHBENR_GPIOFEN_Msk                   (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
7405 #define RCC_AHBENR_GPIOFEN                       RCC_AHBENR_GPIOFEN_Msk        /*!< GPIOF clock enable */
7406 #define RCC_AHBENR_TSCEN_Pos                     (24U)                         
7407 #define RCC_AHBENR_TSCEN_Msk                     (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
7408 #define RCC_AHBENR_TSCEN                         RCC_AHBENR_TSCEN_Msk          /*!< TS controller clock enable */
7409
7410 /* Old Bit definition maintained for legacy purpose */
7411 #define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
7412 #define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */
7413
7414 /*****************  Bit definition for RCC_APB2ENR register  *****************/
7415 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos             (0U)                          
7416 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk             (0x1U << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */
7417 #define RCC_APB2ENR_SYSCFGCOMPEN                 RCC_APB2ENR_SYSCFGCOMPEN_Msk  /*!< SYSCFG and comparator clock enable */
7418 #define RCC_APB2ENR_ADCEN_Pos                    (9U)                          
7419 #define RCC_APB2ENR_ADCEN_Msk                    (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
7420 #define RCC_APB2ENR_ADCEN                        RCC_APB2ENR_ADCEN_Msk         /*!< ADC1 clock enable */
7421 #define RCC_APB2ENR_TIM1EN_Pos                   (11U)                         
7422 #define RCC_APB2ENR_TIM1EN_Msk                   (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
7423 #define RCC_APB2ENR_TIM1EN                       RCC_APB2ENR_TIM1EN_Msk        /*!< TIM1 clock enable */
7424 #define RCC_APB2ENR_SPI1EN_Pos                   (12U)                         
7425 #define RCC_APB2ENR_SPI1EN_Msk                   (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
7426 #define RCC_APB2ENR_SPI1EN                       RCC_APB2ENR_SPI1EN_Msk        /*!< SPI1 clock enable */
7427 #define RCC_APB2ENR_USART1EN_Pos                 (14U)                         
7428 #define RCC_APB2ENR_USART1EN_Msk                 (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
7429 #define RCC_APB2ENR_USART1EN                     RCC_APB2ENR_USART1EN_Msk      /*!< USART1 clock enable */
7430 #define RCC_APB2ENR_TIM16EN_Pos                  (17U)                         
7431 #define RCC_APB2ENR_TIM16EN_Msk                  (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
7432 #define RCC_APB2ENR_TIM16EN                      RCC_APB2ENR_TIM16EN_Msk       /*!< TIM16 clock enable */
7433 #define RCC_APB2ENR_TIM17EN_Pos                  (18U)                         
7434 #define RCC_APB2ENR_TIM17EN_Msk                  (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
7435 #define RCC_APB2ENR_TIM17EN                      RCC_APB2ENR_TIM17EN_Msk       /*!< TIM17 clock enable */
7436 #define RCC_APB2ENR_DBGMCUEN_Pos                 (22U)                         
7437 #define RCC_APB2ENR_DBGMCUEN_Msk                 (0x1U << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */
7438 #define RCC_APB2ENR_DBGMCUEN                     RCC_APB2ENR_DBGMCUEN_Msk      /*!< DBGMCU clock enable */
7439
7440 /* Old Bit definition maintained for legacy purpose */
7441 #define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
7442 #define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */
7443
7444 /*****************  Bit definition for RCC_APB1ENR register  *****************/
7445 #define RCC_APB1ENR_TIM2EN_Pos                   (0U)                          
7446 #define RCC_APB1ENR_TIM2EN_Msk                   (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
7447 #define RCC_APB1ENR_TIM2EN                       RCC_APB1ENR_TIM2EN_Msk        /*!< Timer 2 clock enable */
7448 #define RCC_APB1ENR_TIM3EN_Pos                   (1U)                          
7449 #define RCC_APB1ENR_TIM3EN_Msk                   (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
7450 #define RCC_APB1ENR_TIM3EN                       RCC_APB1ENR_TIM3EN_Msk        /*!< Timer 3 clock enable */
7451 #define RCC_APB1ENR_TIM14EN_Pos                  (8U)                          
7452 #define RCC_APB1ENR_TIM14EN_Msk                  (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
7453 #define RCC_APB1ENR_TIM14EN                      RCC_APB1ENR_TIM14EN_Msk       /*!< Timer 14 clock enable */
7454 #define RCC_APB1ENR_WWDGEN_Pos                   (11U)                         
7455 #define RCC_APB1ENR_WWDGEN_Msk                   (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
7456 #define RCC_APB1ENR_WWDGEN                       RCC_APB1ENR_WWDGEN_Msk        /*!< Window Watchdog clock enable */
7457 #define RCC_APB1ENR_SPI2EN_Pos                   (14U)                         
7458 #define RCC_APB1ENR_SPI2EN_Msk                   (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
7459 #define RCC_APB1ENR_SPI2EN                       RCC_APB1ENR_SPI2EN_Msk        /*!< SPI2 clock enable */
7460 #define RCC_APB1ENR_USART2EN_Pos                 (17U)                         
7461 #define RCC_APB1ENR_USART2EN_Msk                 (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
7462 #define RCC_APB1ENR_USART2EN                     RCC_APB1ENR_USART2EN_Msk      /*!< USART2 clock enable */
7463 #define RCC_APB1ENR_I2C1EN_Pos                   (21U)                         
7464 #define RCC_APB1ENR_I2C1EN_Msk                   (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
7465 #define RCC_APB1ENR_I2C1EN                       RCC_APB1ENR_I2C1EN_Msk        /*!< I2C1 clock enable */
7466 #define RCC_APB1ENR_USBEN_Pos                    (23U)                         
7467 #define RCC_APB1ENR_USBEN_Msk                    (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
7468 #define RCC_APB1ENR_USBEN                        RCC_APB1ENR_USBEN_Msk         /*!< USB clock enable */
7469 #define RCC_APB1ENR_CANEN_Pos                    (25U)                         
7470 #define RCC_APB1ENR_CANEN_Msk                    (0x1U << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */
7471 #define RCC_APB1ENR_CANEN                        RCC_APB1ENR_CANEN_Msk         /*!< CAN clock enable */
7472 #define RCC_APB1ENR_CRSEN_Pos                    (27U)                         
7473 #define RCC_APB1ENR_CRSEN_Msk                    (0x1U << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
7474 #define RCC_APB1ENR_CRSEN                        RCC_APB1ENR_CRSEN_Msk         /*!< CRS clock enable */
7475 #define RCC_APB1ENR_PWREN_Pos                    (28U)                         
7476 #define RCC_APB1ENR_PWREN_Msk                    (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
7477 #define RCC_APB1ENR_PWREN                        RCC_APB1ENR_PWREN_Msk         /*!< PWR clock enable */
7478 #define RCC_APB1ENR_CECEN_Pos                    (30U)                         
7479 #define RCC_APB1ENR_CECEN_Msk                    (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */
7480 #define RCC_APB1ENR_CECEN                        RCC_APB1ENR_CECEN_Msk         /*!< CEC clock enable */
7481
7482 /*******************  Bit definition for RCC_BDCR register  ******************/
7483 #define RCC_BDCR_LSEON_Pos                       (0U)                          
7484 #define RCC_BDCR_LSEON_Msk                       (0x1U << RCC_BDCR_LSEON_Pos)  /*!< 0x00000001 */
7485 #define RCC_BDCR_LSEON                           RCC_BDCR_LSEON_Msk            /*!< External Low Speed oscillator enable */
7486 #define RCC_BDCR_LSERDY_Pos                      (1U)                          
7487 #define RCC_BDCR_LSERDY_Msk                      (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
7488 #define RCC_BDCR_LSERDY                          RCC_BDCR_LSERDY_Msk           /*!< External Low Speed oscillator Ready */
7489 #define RCC_BDCR_LSEBYP_Pos                      (2U)                          
7490 #define RCC_BDCR_LSEBYP_Msk                      (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
7491 #define RCC_BDCR_LSEBYP                          RCC_BDCR_LSEBYP_Msk           /*!< External Low Speed oscillator Bypass */
7492
7493 #define RCC_BDCR_LSEDRV_Pos                      (3U)                          
7494 #define RCC_BDCR_LSEDRV_Msk                      (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
7495 #define RCC_BDCR_LSEDRV                          RCC_BDCR_LSEDRV_Msk           /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
7496 #define RCC_BDCR_LSEDRV_0                        (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
7497 #define RCC_BDCR_LSEDRV_1                        (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
7498
7499 #define RCC_BDCR_RTCSEL_Pos                      (8U)                          
7500 #define RCC_BDCR_RTCSEL_Msk                      (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
7501 #define RCC_BDCR_RTCSEL                          RCC_BDCR_RTCSEL_Msk           /*!< RTCSEL[1:0] bits (RTC clock source selection) */
7502 #define RCC_BDCR_RTCSEL_0                        (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
7503 #define RCC_BDCR_RTCSEL_1                        (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
7504
7505 /*!< RTC configuration */
7506 #define RCC_BDCR_RTCSEL_NOCLOCK                  (0x00000000U)                 /*!< No clock */
7507 #define RCC_BDCR_RTCSEL_LSE                      (0x00000100U)                 /*!< LSE oscillator clock used as RTC clock */
7508 #define RCC_BDCR_RTCSEL_LSI                      (0x00000200U)                 /*!< LSI oscillator clock used as RTC clock */
7509 #define RCC_BDCR_RTCSEL_HSE                      (0x00000300U)                 /*!< HSE oscillator clock divided by 128 used as RTC clock */
7510
7511 #define RCC_BDCR_RTCEN_Pos                       (15U)                         
7512 #define RCC_BDCR_RTCEN_Msk                       (0x1U << RCC_BDCR_RTCEN_Pos)  /*!< 0x00008000 */
7513 #define RCC_BDCR_RTCEN                           RCC_BDCR_RTCEN_Msk            /*!< RTC clock enable */
7514 #define RCC_BDCR_BDRST_Pos                       (16U)                         
7515 #define RCC_BDCR_BDRST_Msk                       (0x1U << RCC_BDCR_BDRST_Pos)  /*!< 0x00010000 */
7516 #define RCC_BDCR_BDRST                           RCC_BDCR_BDRST_Msk            /*!< Backup domain software reset  */
7517
7518 /*******************  Bit definition for RCC_CSR register  *******************/
7519 #define RCC_CSR_LSION_Pos                        (0U)                          
7520 #define RCC_CSR_LSION_Msk                        (0x1U << RCC_CSR_LSION_Pos)   /*!< 0x00000001 */
7521 #define RCC_CSR_LSION                            RCC_CSR_LSION_Msk             /*!< Internal Low Speed oscillator enable */
7522 #define RCC_CSR_LSIRDY_Pos                       (1U)                          
7523 #define RCC_CSR_LSIRDY_Msk                       (0x1U << RCC_CSR_LSIRDY_Pos)  /*!< 0x00000002 */
7524 #define RCC_CSR_LSIRDY                           RCC_CSR_LSIRDY_Msk            /*!< Internal Low Speed oscillator Ready */
7525 #define RCC_CSR_V18PWRRSTF_Pos                   (23U)                         
7526 #define RCC_CSR_V18PWRRSTF_Msk                   (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
7527 #define RCC_CSR_V18PWRRSTF                       RCC_CSR_V18PWRRSTF_Msk        /*!< V1.8 power domain reset flag */
7528 #define RCC_CSR_RMVF_Pos                         (24U)                         
7529 #define RCC_CSR_RMVF_Msk                         (0x1U << RCC_CSR_RMVF_Pos)    /*!< 0x01000000 */
7530 #define RCC_CSR_RMVF                             RCC_CSR_RMVF_Msk              /*!< Remove reset flag */
7531 #define RCC_CSR_OBLRSTF_Pos                      (25U)                         
7532 #define RCC_CSR_OBLRSTF_Msk                      (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
7533 #define RCC_CSR_OBLRSTF                          RCC_CSR_OBLRSTF_Msk           /*!< OBL reset flag */
7534 #define RCC_CSR_PINRSTF_Pos                      (26U)                         
7535 #define RCC_CSR_PINRSTF_Msk                      (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
7536 #define RCC_CSR_PINRSTF                          RCC_CSR_PINRSTF_Msk           /*!< PIN reset flag */
7537 #define RCC_CSR_PORRSTF_Pos                      (27U)                         
7538 #define RCC_CSR_PORRSTF_Msk                      (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
7539 #define RCC_CSR_PORRSTF                          RCC_CSR_PORRSTF_Msk           /*!< POR/PDR reset flag */
7540 #define RCC_CSR_SFTRSTF_Pos                      (28U)                         
7541 #define RCC_CSR_SFTRSTF_Msk                      (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
7542 #define RCC_CSR_SFTRSTF                          RCC_CSR_SFTRSTF_Msk           /*!< Software Reset flag */
7543 #define RCC_CSR_IWDGRSTF_Pos                     (29U)                         
7544 #define RCC_CSR_IWDGRSTF_Msk                     (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
7545 #define RCC_CSR_IWDGRSTF                         RCC_CSR_IWDGRSTF_Msk          /*!< Independent Watchdog reset flag */
7546 #define RCC_CSR_WWDGRSTF_Pos                     (30U)                         
7547 #define RCC_CSR_WWDGRSTF_Msk                     (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
7548 #define RCC_CSR_WWDGRSTF                         RCC_CSR_WWDGRSTF_Msk          /*!< Window watchdog reset flag */
7549 #define RCC_CSR_LPWRRSTF_Pos                     (31U)                         
7550 #define RCC_CSR_LPWRRSTF_Msk                     (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
7551 #define RCC_CSR_LPWRRSTF                         RCC_CSR_LPWRRSTF_Msk          /*!< Low-Power reset flag */
7552
7553 /* Old Bit definition maintained for legacy purpose */
7554 #define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */
7555
7556 /*******************  Bit definition for RCC_AHBRSTR register  ***************/
7557 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)                         
7558 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
7559 #define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
7560 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)                         
7561 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
7562 #define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
7563 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)                         
7564 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
7565 #define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
7566 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)                         
7567 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
7568 #define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
7569 #define RCC_AHBRSTR_TSCRST_Pos                   (24U)                         
7570 #define RCC_AHBRSTR_TSCRST_Msk                   (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
7571 #define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TS reset */
7572
7573 /* Old Bit definition maintained for legacy purpose */
7574 #define  RCC_AHBRSTR_TSRST                   RCC_AHBRSTR_TSCRST         /*!< TS reset */
7575
7576 /*******************  Bit definition for RCC_CFGR2 register  *****************/
7577 /*!< PREDIV configuration */
7578 #define RCC_CFGR2_PREDIV_Pos                     (0U)                          
7579 #define RCC_CFGR2_PREDIV_Msk                     (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
7580 #define RCC_CFGR2_PREDIV                         RCC_CFGR2_PREDIV_Msk          /*!< PREDIV[3:0] bits */
7581 #define RCC_CFGR2_PREDIV_0                       (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
7582 #define RCC_CFGR2_PREDIV_1                       (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
7583 #define RCC_CFGR2_PREDIV_2                       (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
7584 #define RCC_CFGR2_PREDIV_3                       (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
7585
7586 #define RCC_CFGR2_PREDIV_DIV1                    (0x00000000U)                 /*!< PREDIV input clock not divided */
7587 #define RCC_CFGR2_PREDIV_DIV2                    (0x00000001U)                 /*!< PREDIV input clock divided by 2 */
7588 #define RCC_CFGR2_PREDIV_DIV3                    (0x00000002U)                 /*!< PREDIV input clock divided by 3 */
7589 #define RCC_CFGR2_PREDIV_DIV4                    (0x00000003U)                 /*!< PREDIV input clock divided by 4 */
7590 #define RCC_CFGR2_PREDIV_DIV5                    (0x00000004U)                 /*!< PREDIV input clock divided by 5 */
7591 #define RCC_CFGR2_PREDIV_DIV6                    (0x00000005U)                 /*!< PREDIV input clock divided by 6 */
7592 #define RCC_CFGR2_PREDIV_DIV7                    (0x00000006U)                 /*!< PREDIV input clock divided by 7 */
7593 #define RCC_CFGR2_PREDIV_DIV8                    (0x00000007U)                 /*!< PREDIV input clock divided by 8 */
7594 #define RCC_CFGR2_PREDIV_DIV9                    (0x00000008U)                 /*!< PREDIV input clock divided by 9 */
7595 #define RCC_CFGR2_PREDIV_DIV10                   (0x00000009U)                 /*!< PREDIV input clock divided by 10 */
7596 #define RCC_CFGR2_PREDIV_DIV11                   (0x0000000AU)                 /*!< PREDIV input clock divided by 11 */
7597 #define RCC_CFGR2_PREDIV_DIV12                   (0x0000000BU)                 /*!< PREDIV input clock divided by 12 */
7598 #define RCC_CFGR2_PREDIV_DIV13                   (0x0000000CU)                 /*!< PREDIV input clock divided by 13 */
7599 #define RCC_CFGR2_PREDIV_DIV14                   (0x0000000DU)                 /*!< PREDIV input clock divided by 14 */
7600 #define RCC_CFGR2_PREDIV_DIV15                   (0x0000000EU)                 /*!< PREDIV input clock divided by 15 */
7601 #define RCC_CFGR2_PREDIV_DIV16                   (0x0000000FU)                 /*!< PREDIV input clock divided by 16 */
7602
7603 /*******************  Bit definition for RCC_CFGR3 register  *****************/
7604 /*!< USART1 Clock source selection */
7605 #define RCC_CFGR3_USART1SW_Pos                   (0U)                          
7606 #define RCC_CFGR3_USART1SW_Msk                   (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
7607 #define RCC_CFGR3_USART1SW                       RCC_CFGR3_USART1SW_Msk        /*!< USART1SW[1:0] bits */
7608 #define RCC_CFGR3_USART1SW_0                     (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
7609 #define RCC_CFGR3_USART1SW_1                     (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
7610
7611 #define RCC_CFGR3_USART1SW_PCLK                  (0x00000000U)                 /*!< PCLK clock used as USART1 clock source */
7612 #define RCC_CFGR3_USART1SW_SYSCLK                (0x00000001U)                 /*!< System clock selected as USART1 clock source */
7613 #define RCC_CFGR3_USART1SW_LSE                   (0x00000002U)                 /*!< LSE oscillator clock used as USART1 clock source */
7614 #define RCC_CFGR3_USART1SW_HSI                   (0x00000003U)                 /*!< HSI oscillator clock used as USART1 clock source */
7615
7616 /*!< I2C1 Clock source selection */
7617 #define RCC_CFGR3_I2C1SW_Pos                     (4U)                          
7618 #define RCC_CFGR3_I2C1SW_Msk                     (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
7619 #define RCC_CFGR3_I2C1SW                         RCC_CFGR3_I2C1SW_Msk          /*!< I2C1SW bits */ 
7620
7621 #define RCC_CFGR3_I2C1SW_HSI                     (0x00000000U)                 /*!< HSI oscillator clock used as I2C1 clock source */
7622 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos              (4U)                          
7623 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk              (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
7624 #define RCC_CFGR3_I2C1SW_SYSCLK                  RCC_CFGR3_I2C1SW_SYSCLK_Msk   /*!< System clock selected as I2C1 clock source */
7625
7626 /*!< CEC Clock source selection */
7627 #define RCC_CFGR3_CECSW_Pos                      (6U)                          
7628 #define RCC_CFGR3_CECSW_Msk                      (0x1U << RCC_CFGR3_CECSW_Pos) /*!< 0x00000040 */
7629 #define RCC_CFGR3_CECSW                          RCC_CFGR3_CECSW_Msk           /*!< CECSW bits */ 
7630
7631 #define RCC_CFGR3_CECSW_HSI_DIV244               (0x00000000U)                 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
7632 #define RCC_CFGR3_CECSW_LSE_Pos                  (6U)                          
7633 #define RCC_CFGR3_CECSW_LSE_Msk                  (0x1U << RCC_CFGR3_CECSW_LSE_Pos) /*!< 0x00000040 */
7634 #define RCC_CFGR3_CECSW_LSE                      RCC_CFGR3_CECSW_LSE_Msk       /*!< LSE clock selected as HDMI CEC entry clock source */
7635
7636 /*!< USB Clock source selection */
7637 #define RCC_CFGR3_USBSW_Pos                      (7U)                          
7638 #define RCC_CFGR3_USBSW_Msk                      (0x1U << RCC_CFGR3_USBSW_Pos) /*!< 0x00000080 */
7639 #define RCC_CFGR3_USBSW                          RCC_CFGR3_USBSW_Msk           /*!< USBSW bits */
7640
7641 #define RCC_CFGR3_USBSW_HSI48                    (0x00000000U)                 /*!< HSI48 oscillator clock used as USB clock source */
7642 #define RCC_CFGR3_USBSW_PLLCLK_Pos               (7U)                          
7643 #define RCC_CFGR3_USBSW_PLLCLK_Msk               (0x1U << RCC_CFGR3_USBSW_PLLCLK_Pos) /*!< 0x00000080 */
7644 #define RCC_CFGR3_USBSW_PLLCLK                   RCC_CFGR3_USBSW_PLLCLK_Msk    /*!< PLLCLK selected as USB clock source */
7645
7646 /*******************  Bit definition for RCC_CR2 register  *******************/
7647 #define RCC_CR2_HSI14ON_Pos                      (0U)                          
7648 #define RCC_CR2_HSI14ON_Msk                      (0x1U << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */
7649 #define RCC_CR2_HSI14ON                          RCC_CR2_HSI14ON_Msk           /*!< Internal High Speed 14MHz clock enable */
7650 #define RCC_CR2_HSI14RDY_Pos                     (1U)                          
7651 #define RCC_CR2_HSI14RDY_Msk                     (0x1U << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */
7652 #define RCC_CR2_HSI14RDY                         RCC_CR2_HSI14RDY_Msk          /*!< Internal High Speed 14MHz clock ready flag */
7653 #define RCC_CR2_HSI14DIS_Pos                     (2U)                          
7654 #define RCC_CR2_HSI14DIS_Msk                     (0x1U << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */
7655 #define RCC_CR2_HSI14DIS                         RCC_CR2_HSI14DIS_Msk          /*!< Internal High Speed 14MHz clock disable */
7656 #define RCC_CR2_HSI14TRIM_Pos                    (3U)                          
7657 #define RCC_CR2_HSI14TRIM_Msk                    (0x1FU << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */
7658 #define RCC_CR2_HSI14TRIM                        RCC_CR2_HSI14TRIM_Msk         /*!< Internal High Speed 14MHz clock trimming */
7659 #define RCC_CR2_HSI14CAL_Pos                     (8U)                          
7660 #define RCC_CR2_HSI14CAL_Msk                     (0xFFU << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */
7661 #define RCC_CR2_HSI14CAL                         RCC_CR2_HSI14CAL_Msk          /*!< Internal High Speed 14MHz clock Calibration */
7662 #define RCC_CR2_HSI48ON_Pos                      (16U)                         
7663 #define RCC_CR2_HSI48ON_Msk                      (0x1U << RCC_CR2_HSI48ON_Pos) /*!< 0x00010000 */
7664 #define RCC_CR2_HSI48ON                          RCC_CR2_HSI48ON_Msk           /*!< Internal High Speed 48MHz clock enable */
7665 #define RCC_CR2_HSI48RDY_Pos                     (17U)                         
7666 #define RCC_CR2_HSI48RDY_Msk                     (0x1U << RCC_CR2_HSI48RDY_Pos) /*!< 0x00020000 */
7667 #define RCC_CR2_HSI48RDY                         RCC_CR2_HSI48RDY_Msk          /*!< Internal High Speed 48MHz clock ready flag */
7668 #define RCC_CR2_HSI48CAL_Pos                     (24U)                         
7669 #define RCC_CR2_HSI48CAL_Msk                     (0xFFU << RCC_CR2_HSI48CAL_Pos) /*!< 0xFF000000 */
7670 #define RCC_CR2_HSI48CAL                         RCC_CR2_HSI48CAL_Msk          /*!< Internal High Speed 48MHz clock Calibration */
7671
7672 /*****************************************************************************/
7673 /*                                                                           */
7674 /*                           Real-Time Clock (RTC)                           */
7675 /*                                                                           */
7676 /*****************************************************************************/
7677 /*
7678 * @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
7679 */
7680 #define RTC_TAMPER1_SUPPORT  /*!< TAMPER 1 feature support */
7681 #define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
7682 #define RTC_BACKUP_SUPPORT   /*!< BACKUP register feature support */
7683
7684 /********************  Bits definition for RTC_TR register  ******************/
7685 #define RTC_TR_PM_Pos                (22U)                                     
7686 #define RTC_TR_PM_Msk                (0x1U << RTC_TR_PM_Pos)                   /*!< 0x00400000 */
7687 #define RTC_TR_PM                    RTC_TR_PM_Msk                             
7688 #define RTC_TR_HT_Pos                (20U)                                     
7689 #define RTC_TR_HT_Msk                (0x3U << RTC_TR_HT_Pos)                   /*!< 0x00300000 */
7690 #define RTC_TR_HT                    RTC_TR_HT_Msk                             
7691 #define RTC_TR_HT_0                  (0x1U << RTC_TR_HT_Pos)                   /*!< 0x00100000 */
7692 #define RTC_TR_HT_1                  (0x2U << RTC_TR_HT_Pos)                   /*!< 0x00200000 */
7693 #define RTC_TR_HU_Pos                (16U)                                     
7694 #define RTC_TR_HU_Msk                (0xFU << RTC_TR_HU_Pos)                   /*!< 0x000F0000 */
7695 #define RTC_TR_HU                    RTC_TR_HU_Msk                             
7696 #define RTC_TR_HU_0                  (0x1U << RTC_TR_HU_Pos)                   /*!< 0x00010000 */
7697 #define RTC_TR_HU_1                  (0x2U << RTC_TR_HU_Pos)                   /*!< 0x00020000 */
7698 #define RTC_TR_HU_2                  (0x4U << RTC_TR_HU_Pos)                   /*!< 0x00040000 */
7699 #define RTC_TR_HU_3                  (0x8U << RTC_TR_HU_Pos)                   /*!< 0x00080000 */
7700 #define RTC_TR_MNT_Pos               (12U)                                     
7701 #define RTC_TR_MNT_Msk               (0x7U << RTC_TR_MNT_Pos)                  /*!< 0x00007000 */
7702 #define RTC_TR_MNT                   RTC_TR_MNT_Msk                            
7703 #define RTC_TR_MNT_0                 (0x1U << RTC_TR_MNT_Pos)                  /*!< 0x00001000 */
7704 #define RTC_TR_MNT_1                 (0x2U << RTC_TR_MNT_Pos)                  /*!< 0x00002000 */
7705 #define RTC_TR_MNT_2                 (0x4U << RTC_TR_MNT_Pos)                  /*!< 0x00004000 */
7706 #define RTC_TR_MNU_Pos               (8U)                                      
7707 #define RTC_TR_MNU_Msk               (0xFU << RTC_TR_MNU_Pos)                  /*!< 0x00000F00 */
7708 #define RTC_TR_MNU                   RTC_TR_MNU_Msk                            
7709 #define RTC_TR_MNU_0                 (0x1U << RTC_TR_MNU_Pos)                  /*!< 0x00000100 */
7710 #define RTC_TR_MNU_1                 (0x2U << RTC_TR_MNU_Pos)                  /*!< 0x00000200 */
7711 #define RTC_TR_MNU_2                 (0x4U << RTC_TR_MNU_Pos)                  /*!< 0x00000400 */
7712 #define RTC_TR_MNU_3                 (0x8U << RTC_TR_MNU_Pos)                  /*!< 0x00000800 */
7713 #define RTC_TR_ST_Pos                (4U)                                      
7714 #define RTC_TR_ST_Msk                (0x7U << RTC_TR_ST_Pos)                   /*!< 0x00000070 */
7715 #define RTC_TR_ST                    RTC_TR_ST_Msk                             
7716 #define RTC_TR_ST_0                  (0x1U << RTC_TR_ST_Pos)                   /*!< 0x00000010 */
7717 #define RTC_TR_ST_1                  (0x2U << RTC_TR_ST_Pos)                   /*!< 0x00000020 */
7718 #define RTC_TR_ST_2                  (0x4U << RTC_TR_ST_Pos)                   /*!< 0x00000040 */
7719 #define RTC_TR_SU_Pos                (0U)                                      
7720 #define RTC_TR_SU_Msk                (0xFU << RTC_TR_SU_Pos)                   /*!< 0x0000000F */
7721 #define RTC_TR_SU                    RTC_TR_SU_Msk                             
7722 #define RTC_TR_SU_0                  (0x1U << RTC_TR_SU_Pos)                   /*!< 0x00000001 */
7723 #define RTC_TR_SU_1                  (0x2U << RTC_TR_SU_Pos)                   /*!< 0x00000002 */
7724 #define RTC_TR_SU_2                  (0x4U << RTC_TR_SU_Pos)                   /*!< 0x00000004 */
7725 #define RTC_TR_SU_3                  (0x8U << RTC_TR_SU_Pos)                   /*!< 0x00000008 */
7726
7727 /********************  Bits definition for RTC_DR register  ******************/
7728 #define RTC_DR_YT_Pos                (20U)                                     
7729 #define RTC_DR_YT_Msk                (0xFU << RTC_DR_YT_Pos)                   /*!< 0x00F00000 */
7730 #define RTC_DR_YT                    RTC_DR_YT_Msk                             
7731 #define RTC_DR_YT_0                  (0x1U << RTC_DR_YT_Pos)                   /*!< 0x00100000 */
7732 #define RTC_DR_YT_1                  (0x2U << RTC_DR_YT_Pos)                   /*!< 0x00200000 */
7733 #define RTC_DR_YT_2                  (0x4U << RTC_DR_YT_Pos)                   /*!< 0x00400000 */
7734 #define RTC_DR_YT_3                  (0x8U << RTC_DR_YT_Pos)                   /*!< 0x00800000 */
7735 #define RTC_DR_YU_Pos                (16U)                                     
7736 #define RTC_DR_YU_Msk                (0xFU << RTC_DR_YU_Pos)                   /*!< 0x000F0000 */
7737 #define RTC_DR_YU                    RTC_DR_YU_Msk                             
7738 #define RTC_DR_YU_0                  (0x1U << RTC_DR_YU_Pos)                   /*!< 0x00010000 */
7739 #define RTC_DR_YU_1                  (0x2U << RTC_DR_YU_Pos)                   /*!< 0x00020000 */
7740 #define RTC_DR_YU_2                  (0x4U << RTC_DR_YU_Pos)                   /*!< 0x00040000 */
7741 #define RTC_DR_YU_3                  (0x8U << RTC_DR_YU_Pos)                   /*!< 0x00080000 */
7742 #define RTC_DR_WDU_Pos               (13U)                                     
7743 #define RTC_DR_WDU_Msk               (0x7U << RTC_DR_WDU_Pos)                  /*!< 0x0000E000 */
7744 #define RTC_DR_WDU                   RTC_DR_WDU_Msk                            
7745 #define RTC_DR_WDU_0                 (0x1U << RTC_DR_WDU_Pos)                  /*!< 0x00002000 */
7746 #define RTC_DR_WDU_1                 (0x2U << RTC_DR_WDU_Pos)                  /*!< 0x00004000 */
7747 #define RTC_DR_WDU_2                 (0x4U << RTC_DR_WDU_Pos)                  /*!< 0x00008000 */
7748 #define RTC_DR_MT_Pos                (12U)                                     
7749 #define RTC_DR_MT_Msk                (0x1U << RTC_DR_MT_Pos)                   /*!< 0x00001000 */
7750 #define RTC_DR_MT                    RTC_DR_MT_Msk                             
7751 #define RTC_DR_MU_Pos                (8U)                                      
7752 #define RTC_DR_MU_Msk                (0xFU << RTC_DR_MU_Pos)                   /*!< 0x00000F00 */
7753 #define RTC_DR_MU                    RTC_DR_MU_Msk                             
7754 #define RTC_DR_MU_0                  (0x1U << RTC_DR_MU_Pos)                   /*!< 0x00000100 */
7755 #define RTC_DR_MU_1                  (0x2U << RTC_DR_MU_Pos)                   /*!< 0x00000200 */
7756 #define RTC_DR_MU_2                  (0x4U << RTC_DR_MU_Pos)                   /*!< 0x00000400 */
7757 #define RTC_DR_MU_3                  (0x8U << RTC_DR_MU_Pos)                   /*!< 0x00000800 */
7758 #define RTC_DR_DT_Pos                (4U)                                      
7759 #define RTC_DR_DT_Msk                (0x3U << RTC_DR_DT_Pos)                   /*!< 0x00000030 */
7760 #define RTC_DR_DT                    RTC_DR_DT_Msk                             
7761 #define RTC_DR_DT_0                  (0x1U << RTC_DR_DT_Pos)                   /*!< 0x00000010 */
7762 #define RTC_DR_DT_1                  (0x2U << RTC_DR_DT_Pos)                   /*!< 0x00000020 */
7763 #define RTC_DR_DU_Pos                (0U)                                      
7764 #define RTC_DR_DU_Msk                (0xFU << RTC_DR_DU_Pos)                   /*!< 0x0000000F */
7765 #define RTC_DR_DU                    RTC_DR_DU_Msk                             
7766 #define RTC_DR_DU_0                  (0x1U << RTC_DR_DU_Pos)                   /*!< 0x00000001 */
7767 #define RTC_DR_DU_1                  (0x2U << RTC_DR_DU_Pos)                   /*!< 0x00000002 */
7768 #define RTC_DR_DU_2                  (0x4U << RTC_DR_DU_Pos)                   /*!< 0x00000004 */
7769 #define RTC_DR_DU_3                  (0x8U << RTC_DR_DU_Pos)                   /*!< 0x00000008 */
7770
7771 /********************  Bits definition for RTC_CR register  ******************/
7772 #define RTC_CR_COE_Pos               (23U)                                     
7773 #define RTC_CR_COE_Msk               (0x1U << RTC_CR_COE_Pos)                  /*!< 0x00800000 */
7774 #define RTC_CR_COE                   RTC_CR_COE_Msk                            
7775 #define RTC_CR_OSEL_Pos              (21U)                                     
7776 #define RTC_CR_OSEL_Msk              (0x3U << RTC_CR_OSEL_Pos)                 /*!< 0x00600000 */
7777 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk                           
7778 #define RTC_CR_OSEL_0                (0x1U << RTC_CR_OSEL_Pos)                 /*!< 0x00200000 */
7779 #define RTC_CR_OSEL_1                (0x2U << RTC_CR_OSEL_Pos)                 /*!< 0x00400000 */
7780 #define RTC_CR_POL_Pos               (20U)                                     
7781 #define RTC_CR_POL_Msk               (0x1U << RTC_CR_POL_Pos)                  /*!< 0x00100000 */
7782 #define RTC_CR_POL                   RTC_CR_POL_Msk                            
7783 #define RTC_CR_COSEL_Pos             (19U)                                     
7784 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
7785 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
7786 #define RTC_CR_BKP_Pos               (18U)                                     
7787 #define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
7788 #define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
7789 #define RTC_CR_SUB1H_Pos             (17U)                                     
7790 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
7791 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
7792 #define RTC_CR_ADD1H_Pos             (16U)                                     
7793 #define RTC_CR_ADD1H_Msk             (0x1U << RTC_CR_ADD1H_Pos)                /*!< 0x00010000 */
7794 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk                          
7795 #define RTC_CR_TSIE_Pos              (15U)                                     
7796 #define RTC_CR_TSIE_Msk              (0x1U << RTC_CR_TSIE_Pos)                 /*!< 0x00008000 */
7797 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk                           
7798 #define RTC_CR_ALRAIE_Pos            (12U)                                     
7799 #define RTC_CR_ALRAIE_Msk            (0x1U << RTC_CR_ALRAIE_Pos)               /*!< 0x00001000 */
7800 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk                         
7801 #define RTC_CR_TSE_Pos               (11U)                                     
7802 #define RTC_CR_TSE_Msk               (0x1U << RTC_CR_TSE_Pos)                  /*!< 0x00000800 */
7803 #define RTC_CR_TSE                   RTC_CR_TSE_Msk                            
7804 #define RTC_CR_ALRAE_Pos             (8U)                                      
7805 #define RTC_CR_ALRAE_Msk             (0x1U << RTC_CR_ALRAE_Pos)                /*!< 0x00000100 */
7806 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk                          
7807 #define RTC_CR_FMT_Pos               (6U)                                      
7808 #define RTC_CR_FMT_Msk               (0x1U << RTC_CR_FMT_Pos)                  /*!< 0x00000040 */
7809 #define RTC_CR_FMT                   RTC_CR_FMT_Msk                            
7810 #define RTC_CR_BYPSHAD_Pos           (5U)                                      
7811 #define RTC_CR_BYPSHAD_Msk           (0x1U << RTC_CR_BYPSHAD_Pos)              /*!< 0x00000020 */
7812 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk                        
7813 #define RTC_CR_REFCKON_Pos           (4U)                                      
7814 #define RTC_CR_REFCKON_Msk           (0x1U << RTC_CR_REFCKON_Pos)              /*!< 0x00000010 */
7815 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk                        
7816 #define RTC_CR_TSEDGE_Pos            (3U)                                      
7817 #define RTC_CR_TSEDGE_Msk            (0x1U << RTC_CR_TSEDGE_Pos)               /*!< 0x00000008 */
7818 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk                         
7819
7820 /* Legacy defines */
7821 #define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
7822 #define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
7823 #define RTC_CR_BCK                   RTC_CR_BKP
7824
7825 /********************  Bits definition for RTC_ISR register  *****************/
7826 #define RTC_ISR_RECALPF_Pos          (16U)                                     
7827 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
7828 #define RTC_ISR_RECALPF              RTC_ISR_RECALPF_Msk                       
7829 #define RTC_ISR_TAMP2F_Pos           (14U)                                     
7830 #define RTC_ISR_TAMP2F_Msk           (0x1U << RTC_ISR_TAMP2F_Pos)              /*!< 0x00004000 */
7831 #define RTC_ISR_TAMP2F               RTC_ISR_TAMP2F_Msk                        
7832 #define RTC_ISR_TAMP1F_Pos           (13U)                                     
7833 #define RTC_ISR_TAMP1F_Msk           (0x1U << RTC_ISR_TAMP1F_Pos)              /*!< 0x00002000 */
7834 #define RTC_ISR_TAMP1F               RTC_ISR_TAMP1F_Msk                        
7835 #define RTC_ISR_TSOVF_Pos            (12U)                                     
7836 #define RTC_ISR_TSOVF_Msk            (0x1U << RTC_ISR_TSOVF_Pos)               /*!< 0x00001000 */
7837 #define RTC_ISR_TSOVF                RTC_ISR_TSOVF_Msk                         
7838 #define RTC_ISR_TSF_Pos              (11U)                                     
7839 #define RTC_ISR_TSF_Msk              (0x1U << RTC_ISR_TSF_Pos)                 /*!< 0x00000800 */
7840 #define RTC_ISR_TSF                  RTC_ISR_TSF_Msk                           
7841 #define RTC_ISR_ALRAF_Pos            (8U)                                      
7842 #define RTC_ISR_ALRAF_Msk            (0x1U << RTC_ISR_ALRAF_Pos)               /*!< 0x00000100 */
7843 #define RTC_ISR_ALRAF                RTC_ISR_ALRAF_Msk                         
7844 #define RTC_ISR_INIT_Pos             (7U)                                      
7845 #define RTC_ISR_INIT_Msk             (0x1U << RTC_ISR_INIT_Pos)                /*!< 0x00000080 */
7846 #define RTC_ISR_INIT                 RTC_ISR_INIT_Msk                          
7847 #define RTC_ISR_INITF_Pos            (6U)                                      
7848 #define RTC_ISR_INITF_Msk            (0x1U << RTC_ISR_INITF_Pos)               /*!< 0x00000040 */
7849 #define RTC_ISR_INITF                RTC_ISR_INITF_Msk                         
7850 #define RTC_ISR_RSF_Pos              (5U)                                      
7851 #define RTC_ISR_RSF_Msk              (0x1U << RTC_ISR_RSF_Pos)                 /*!< 0x00000020 */
7852 #define RTC_ISR_RSF                  RTC_ISR_RSF_Msk                           
7853 #define RTC_ISR_INITS_Pos            (4U)                                      
7854 #define RTC_ISR_INITS_Msk            (0x1U << RTC_ISR_INITS_Pos)               /*!< 0x00000010 */
7855 #define RTC_ISR_INITS                RTC_ISR_INITS_Msk                         
7856 #define RTC_ISR_SHPF_Pos             (3U)                                      
7857 #define RTC_ISR_SHPF_Msk             (0x1U << RTC_ISR_SHPF_Pos)                /*!< 0x00000008 */
7858 #define RTC_ISR_SHPF                 RTC_ISR_SHPF_Msk                          
7859 #define RTC_ISR_ALRAWF_Pos           (0U)                                      
7860 #define RTC_ISR_ALRAWF_Msk           (0x1U << RTC_ISR_ALRAWF_Pos)              /*!< 0x00000001 */
7861 #define RTC_ISR_ALRAWF               RTC_ISR_ALRAWF_Msk                        
7862
7863 /********************  Bits definition for RTC_PRER register  ****************/
7864 #define RTC_PRER_PREDIV_A_Pos        (16U)                                     
7865 #define RTC_PRER_PREDIV_A_Msk        (0x7FU << RTC_PRER_PREDIV_A_Pos)          /*!< 0x007F0000 */
7866 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk                     
7867 #define RTC_PRER_PREDIV_S_Pos        (0U)                                      
7868 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFU << RTC_PRER_PREDIV_S_Pos)        /*!< 0x00007FFF */
7869 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk                     
7870
7871 /********************  Bits definition for RTC_ALRMAR register  **************/
7872 #define RTC_ALRMAR_MSK4_Pos          (31U)                                     
7873 #define RTC_ALRMAR_MSK4_Msk          (0x1U << RTC_ALRMAR_MSK4_Pos)             /*!< 0x80000000 */
7874 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk                       
7875 #define RTC_ALRMAR_WDSEL_Pos         (30U)                                     
7876 #define RTC_ALRMAR_WDSEL_Msk         (0x1U << RTC_ALRMAR_WDSEL_Pos)            /*!< 0x40000000 */
7877 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk                      
7878 #define RTC_ALRMAR_DT_Pos            (28U)                                     
7879 #define RTC_ALRMAR_DT_Msk            (0x3U << RTC_ALRMAR_DT_Pos)               /*!< 0x30000000 */
7880 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk                         
7881 #define RTC_ALRMAR_DT_0              (0x1U << RTC_ALRMAR_DT_Pos)               /*!< 0x10000000 */
7882 #define RTC_ALRMAR_DT_1              (0x2U << RTC_ALRMAR_DT_Pos)               /*!< 0x20000000 */
7883 #define RTC_ALRMAR_DU_Pos            (24U)                                     
7884 #define RTC_ALRMAR_DU_Msk            (0xFU << RTC_ALRMAR_DU_Pos)               /*!< 0x0F000000 */
7885 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk                         
7886 #define RTC_ALRMAR_DU_0              (0x1U << RTC_ALRMAR_DU_Pos)               /*!< 0x01000000 */
7887 #define RTC_ALRMAR_DU_1              (0x2U << RTC_ALRMAR_DU_Pos)               /*!< 0x02000000 */
7888 #define RTC_ALRMAR_DU_2              (0x4U << RTC_ALRMAR_DU_Pos)               /*!< 0x04000000 */
7889 #define RTC_ALRMAR_DU_3              (0x8U << RTC_ALRMAR_DU_Pos)               /*!< 0x08000000 */
7890 #define RTC_ALRMAR_MSK3_Pos          (23U)                                     
7891 #define RTC_ALRMAR_MSK3_Msk          (0x1U << RTC_ALRMAR_MSK3_Pos)             /*!< 0x00800000 */
7892 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk                       
7893 #define RTC_ALRMAR_PM_Pos            (22U)                                     
7894 #define RTC_ALRMAR_PM_Msk            (0x1U << RTC_ALRMAR_PM_Pos)               /*!< 0x00400000 */
7895 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk                         
7896 #define RTC_ALRMAR_HT_Pos            (20U)                                     
7897 #define RTC_ALRMAR_HT_Msk            (0x3U << RTC_ALRMAR_HT_Pos)               /*!< 0x00300000 */
7898 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk                         
7899 #define RTC_ALRMAR_HT_0              (0x1U << RTC_ALRMAR_HT_Pos)               /*!< 0x00100000 */
7900 #define RTC_ALRMAR_HT_1              (0x2U << RTC_ALRMAR_HT_Pos)               /*!< 0x00200000 */
7901 #define RTC_ALRMAR_HU_Pos            (16U)                                     
7902 #define RTC_ALRMAR_HU_Msk            (0xFU << RTC_ALRMAR_HU_Pos)               /*!< 0x000F0000 */
7903 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk                         
7904 #define RTC_ALRMAR_HU_0              (0x1U << RTC_ALRMAR_HU_Pos)               /*!< 0x00010000 */
7905 #define RTC_ALRMAR_HU_1              (0x2U << RTC_ALRMAR_HU_Pos)               /*!< 0x00020000 */
7906 #define RTC_ALRMAR_HU_2              (0x4U << RTC_ALRMAR_HU_Pos)               /*!< 0x00040000 */
7907 #define RTC_ALRMAR_HU_3              (0x8U << RTC_ALRMAR_HU_Pos)               /*!< 0x00080000 */
7908 #define RTC_ALRMAR_MSK2_Pos          (15U)                                     
7909 #define RTC_ALRMAR_MSK2_Msk          (0x1U << RTC_ALRMAR_MSK2_Pos)             /*!< 0x00008000 */
7910 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk                       
7911 #define RTC_ALRMAR_MNT_Pos           (12U)                                     
7912 #define RTC_ALRMAR_MNT_Msk           (0x7U << RTC_ALRMAR_MNT_Pos)              /*!< 0x00007000 */
7913 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk                        
7914 #define RTC_ALRMAR_MNT_0             (0x1U << RTC_ALRMAR_MNT_Pos)              /*!< 0x00001000 */
7915 #define RTC_ALRMAR_MNT_1             (0x2U << RTC_ALRMAR_MNT_Pos)              /*!< 0x00002000 */
7916 #define RTC_ALRMAR_MNT_2             (0x4U << RTC_ALRMAR_MNT_Pos)              /*!< 0x00004000 */
7917 #define RTC_ALRMAR_MNU_Pos           (8U)                                      
7918 #define RTC_ALRMAR_MNU_Msk           (0xFU << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000F00 */
7919 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk                        
7920 #define RTC_ALRMAR_MNU_0             (0x1U << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000100 */
7921 #define RTC_ALRMAR_MNU_1             (0x2U << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000200 */
7922 #define RTC_ALRMAR_MNU_2             (0x4U << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000400 */
7923 #define RTC_ALRMAR_MNU_3             (0x8U << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000800 */
7924 #define RTC_ALRMAR_MSK1_Pos          (7U)                                      
7925 #define RTC_ALRMAR_MSK1_Msk          (0x1U << RTC_ALRMAR_MSK1_Pos)             /*!< 0x00000080 */
7926 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk                       
7927 #define RTC_ALRMAR_ST_Pos            (4U)                                      
7928 #define RTC_ALRMAR_ST_Msk            (0x7U << RTC_ALRMAR_ST_Pos)               /*!< 0x00000070 */
7929 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk                         
7930 #define RTC_ALRMAR_ST_0              (0x1U << RTC_ALRMAR_ST_Pos)               /*!< 0x00000010 */
7931 #define RTC_ALRMAR_ST_1              (0x2U << RTC_ALRMAR_ST_Pos)               /*!< 0x00000020 */
7932 #define RTC_ALRMAR_ST_2              (0x4U << RTC_ALRMAR_ST_Pos)               /*!< 0x00000040 */
7933 #define RTC_ALRMAR_SU_Pos            (0U)                                      
7934 #define RTC_ALRMAR_SU_Msk            (0xFU << RTC_ALRMAR_SU_Pos)               /*!< 0x0000000F */
7935 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk                         
7936 #define RTC_ALRMAR_SU_0              (0x1U << RTC_ALRMAR_SU_Pos)               /*!< 0x00000001 */
7937 #define RTC_ALRMAR_SU_1              (0x2U << RTC_ALRMAR_SU_Pos)               /*!< 0x00000002 */
7938 #define RTC_ALRMAR_SU_2              (0x4U << RTC_ALRMAR_SU_Pos)               /*!< 0x00000004 */
7939 #define RTC_ALRMAR_SU_3              (0x8U << RTC_ALRMAR_SU_Pos)               /*!< 0x00000008 */
7940
7941 /********************  Bits definition for RTC_WPR register  *****************/
7942 #define RTC_WPR_KEY_Pos              (0U)                                      
7943 #define RTC_WPR_KEY_Msk              (0xFFU << RTC_WPR_KEY_Pos)                /*!< 0x000000FF */
7944 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk                           
7945
7946 /********************  Bits definition for RTC_SSR register  *****************/
7947 #define RTC_SSR_SS_Pos               (0U)                                      
7948 #define RTC_SSR_SS_Msk               (0xFFFFU << RTC_SSR_SS_Pos)               /*!< 0x0000FFFF */
7949 #define RTC_SSR_SS                   RTC_SSR_SS_Msk                            
7950
7951 /********************  Bits definition for RTC_SHIFTR register  **************/
7952 #define RTC_SHIFTR_SUBFS_Pos         (0U)                                      
7953 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)         /*!< 0x00007FFF */
7954 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk                      
7955 #define RTC_SHIFTR_ADD1S_Pos         (31U)                                     
7956 #define RTC_SHIFTR_ADD1S_Msk         (0x1U << RTC_SHIFTR_ADD1S_Pos)            /*!< 0x80000000 */
7957 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk                      
7958
7959 /********************  Bits definition for RTC_TSTR register  ****************/
7960 #define RTC_TSTR_PM_Pos              (22U)                                     
7961 #define RTC_TSTR_PM_Msk              (0x1U << RTC_TSTR_PM_Pos)                 /*!< 0x00400000 */
7962 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk                           
7963 #define RTC_TSTR_HT_Pos              (20U)                                     
7964 #define RTC_TSTR_HT_Msk              (0x3U << RTC_TSTR_HT_Pos)                 /*!< 0x00300000 */
7965 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk                           
7966 #define RTC_TSTR_HT_0                (0x1U << RTC_TSTR_HT_Pos)                 /*!< 0x00100000 */
7967 #define RTC_TSTR_HT_1                (0x2U << RTC_TSTR_HT_Pos)                 /*!< 0x00200000 */
7968 #define RTC_TSTR_HU_Pos              (16U)                                     
7969 #define RTC_TSTR_HU_Msk              (0xFU << RTC_TSTR_HU_Pos)                 /*!< 0x000F0000 */
7970 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk                           
7971 #define RTC_TSTR_HU_0                (0x1U << RTC_TSTR_HU_Pos)                 /*!< 0x00010000 */
7972 #define RTC_TSTR_HU_1                (0x2U << RTC_TSTR_HU_Pos)                 /*!< 0x00020000 */
7973 #define RTC_TSTR_HU_2                (0x4U << RTC_TSTR_HU_Pos)                 /*!< 0x00040000 */
7974 #define RTC_TSTR_HU_3                (0x8U << RTC_TSTR_HU_Pos)                 /*!< 0x00080000 */
7975 #define RTC_TSTR_MNT_Pos             (12U)                                     
7976 #define RTC_TSTR_MNT_Msk             (0x7U << RTC_TSTR_MNT_Pos)                /*!< 0x00007000 */
7977 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk                          
7978 #define RTC_TSTR_MNT_0               (0x1U << RTC_TSTR_MNT_Pos)                /*!< 0x00001000 */
7979 #define RTC_TSTR_MNT_1               (0x2U << RTC_TSTR_MNT_Pos)                /*!< 0x00002000 */
7980 #define RTC_TSTR_MNT_2               (0x4U << RTC_TSTR_MNT_Pos)                /*!< 0x00004000 */
7981 #define RTC_TSTR_MNU_Pos             (8U)                                      
7982 #define RTC_TSTR_MNU_Msk             (0xFU << RTC_TSTR_MNU_Pos)                /*!< 0x00000F00 */
7983 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk                          
7984 #define RTC_TSTR_MNU_0               (0x1U << RTC_TSTR_MNU_Pos)                /*!< 0x00000100 */
7985 #define RTC_TSTR_MNU_1               (0x2U << RTC_TSTR_MNU_Pos)                /*!< 0x00000200 */
7986 #define RTC_TSTR_MNU_2               (0x4U << RTC_TSTR_MNU_Pos)                /*!< 0x00000400 */
7987 #define RTC_TSTR_MNU_3               (0x8U << RTC_TSTR_MNU_Pos)                /*!< 0x00000800 */
7988 #define RTC_TSTR_ST_Pos              (4U)                                      
7989 #define RTC_TSTR_ST_Msk              (0x7U << RTC_TSTR_ST_Pos)                 /*!< 0x00000070 */
7990 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk                           
7991 #define RTC_TSTR_ST_0                (0x1U << RTC_TSTR_ST_Pos)                 /*!< 0x00000010 */
7992 #define RTC_TSTR_ST_1                (0x2U << RTC_TSTR_ST_Pos)                 /*!< 0x00000020 */
7993 #define RTC_TSTR_ST_2                (0x4U << RTC_TSTR_ST_Pos)                 /*!< 0x00000040 */
7994 #define RTC_TSTR_SU_Pos              (0U)                                      
7995 #define RTC_TSTR_SU_Msk              (0xFU << RTC_TSTR_SU_Pos)                 /*!< 0x0000000F */
7996 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk                           
7997 #define RTC_TSTR_SU_0                (0x1U << RTC_TSTR_SU_Pos)                 /*!< 0x00000001 */
7998 #define RTC_TSTR_SU_1                (0x2U << RTC_TSTR_SU_Pos)                 /*!< 0x00000002 */
7999 #define RTC_TSTR_SU_2                (0x4U << RTC_TSTR_SU_Pos)                 /*!< 0x00000004 */
8000 #define RTC_TSTR_SU_3                (0x8U << RTC_TSTR_SU_Pos)                 /*!< 0x00000008 */
8001
8002 /********************  Bits definition for RTC_TSDR register  ****************/
8003 #define RTC_TSDR_WDU_Pos             (13U)                                     
8004 #define RTC_TSDR_WDU_Msk             (0x7U << RTC_TSDR_WDU_Pos)                /*!< 0x0000E000 */
8005 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk                          
8006 #define RTC_TSDR_WDU_0               (0x1U << RTC_TSDR_WDU_Pos)                /*!< 0x00002000 */
8007 #define RTC_TSDR_WDU_1               (0x2U << RTC_TSDR_WDU_Pos)                /*!< 0x00004000 */
8008 #define RTC_TSDR_WDU_2               (0x4U << RTC_TSDR_WDU_Pos)                /*!< 0x00008000 */
8009 #define RTC_TSDR_MT_Pos              (12U)                                     
8010 #define RTC_TSDR_MT_Msk              (0x1U << RTC_TSDR_MT_Pos)                 /*!< 0x00001000 */
8011 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk                           
8012 #define RTC_TSDR_MU_Pos              (8U)                                      
8013 #define RTC_TSDR_MU_Msk              (0xFU << RTC_TSDR_MU_Pos)                 /*!< 0x00000F00 */
8014 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk                           
8015 #define RTC_TSDR_MU_0                (0x1U << RTC_TSDR_MU_Pos)                 /*!< 0x00000100 */
8016 #define RTC_TSDR_MU_1                (0x2U << RTC_TSDR_MU_Pos)                 /*!< 0x00000200 */
8017 #define RTC_TSDR_MU_2                (0x4U << RTC_TSDR_MU_Pos)                 /*!< 0x00000400 */
8018 #define RTC_TSDR_MU_3                (0x8U << RTC_TSDR_MU_Pos)                 /*!< 0x00000800 */
8019 #define RTC_TSDR_DT_Pos              (4U)                                      
8020 #define RTC_TSDR_DT_Msk              (0x3U << RTC_TSDR_DT_Pos)                 /*!< 0x00000030 */
8021 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk                           
8022 #define RTC_TSDR_DT_0                (0x1U << RTC_TSDR_DT_Pos)                 /*!< 0x00000010 */
8023 #define RTC_TSDR_DT_1                (0x2U << RTC_TSDR_DT_Pos)                 /*!< 0x00000020 */
8024 #define RTC_TSDR_DU_Pos              (0U)                                      
8025 #define RTC_TSDR_DU_Msk              (0xFU << RTC_TSDR_DU_Pos)                 /*!< 0x0000000F */
8026 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk                           
8027 #define RTC_TSDR_DU_0                (0x1U << RTC_TSDR_DU_Pos)                 /*!< 0x00000001 */
8028 #define RTC_TSDR_DU_1                (0x2U << RTC_TSDR_DU_Pos)                 /*!< 0x00000002 */
8029 #define RTC_TSDR_DU_2                (0x4U << RTC_TSDR_DU_Pos)                 /*!< 0x00000004 */
8030 #define RTC_TSDR_DU_3                (0x8U << RTC_TSDR_DU_Pos)                 /*!< 0x00000008 */
8031
8032 /********************  Bits definition for RTC_TSSSR register  ***************/
8033 #define RTC_TSSSR_SS_Pos             (0U)                                      
8034 #define RTC_TSSSR_SS_Msk             (0xFFFFU << RTC_TSSSR_SS_Pos)             /*!< 0x0000FFFF */
8035 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk                          
8036
8037 /********************  Bits definition for RTC_CALR register  ****************/
8038 #define RTC_CALR_CALP_Pos            (15U)                                     
8039 #define RTC_CALR_CALP_Msk            (0x1U << RTC_CALR_CALP_Pos)               /*!< 0x00008000 */
8040 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk                         
8041 #define RTC_CALR_CALW8_Pos           (14U)                                     
8042 #define RTC_CALR_CALW8_Msk           (0x1U << RTC_CALR_CALW8_Pos)              /*!< 0x00004000 */
8043 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk                        
8044 #define RTC_CALR_CALW16_Pos          (13U)                                     
8045 #define RTC_CALR_CALW16_Msk          (0x1U << RTC_CALR_CALW16_Pos)             /*!< 0x00002000 */
8046 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk                       
8047 #define RTC_CALR_CALM_Pos            (0U)                                      
8048 #define RTC_CALR_CALM_Msk            (0x1FFU << RTC_CALR_CALM_Pos)             /*!< 0x000001FF */
8049 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk                         
8050 #define RTC_CALR_CALM_0              (0x001U << RTC_CALR_CALM_Pos)             /*!< 0x00000001 */
8051 #define RTC_CALR_CALM_1              (0x002U << RTC_CALR_CALM_Pos)             /*!< 0x00000002 */
8052 #define RTC_CALR_CALM_2              (0x004U << RTC_CALR_CALM_Pos)             /*!< 0x00000004 */
8053 #define RTC_CALR_CALM_3              (0x008U << RTC_CALR_CALM_Pos)             /*!< 0x00000008 */
8054 #define RTC_CALR_CALM_4              (0x010U << RTC_CALR_CALM_Pos)             /*!< 0x00000010 */
8055 #define RTC_CALR_CALM_5              (0x020U << RTC_CALR_CALM_Pos)             /*!< 0x00000020 */
8056 #define RTC_CALR_CALM_6              (0x040U << RTC_CALR_CALM_Pos)             /*!< 0x00000040 */
8057 #define RTC_CALR_CALM_7              (0x080U << RTC_CALR_CALM_Pos)             /*!< 0x00000080 */
8058 #define RTC_CALR_CALM_8              (0x100U << RTC_CALR_CALM_Pos)             /*!< 0x00000100 */
8059
8060 /********************  Bits definition for RTC_TAFCR register  ***************/
8061 #define RTC_TAFCR_PC15MODE_Pos       (23U)                                     
8062 #define RTC_TAFCR_PC15MODE_Msk       (0x1U << RTC_TAFCR_PC15MODE_Pos)          /*!< 0x00800000 */
8063 #define RTC_TAFCR_PC15MODE           RTC_TAFCR_PC15MODE_Msk                    
8064 #define RTC_TAFCR_PC15VALUE_Pos      (22U)                                     
8065 #define RTC_TAFCR_PC15VALUE_Msk      (0x1U << RTC_TAFCR_PC15VALUE_Pos)         /*!< 0x00400000 */
8066 #define RTC_TAFCR_PC15VALUE          RTC_TAFCR_PC15VALUE_Msk                   
8067 #define RTC_TAFCR_PC14MODE_Pos       (21U)                                     
8068 #define RTC_TAFCR_PC14MODE_Msk       (0x1U << RTC_TAFCR_PC14MODE_Pos)          /*!< 0x00200000 */
8069 #define RTC_TAFCR_PC14MODE           RTC_TAFCR_PC14MODE_Msk                    
8070 #define RTC_TAFCR_PC14VALUE_Pos      (20U)                                     
8071 #define RTC_TAFCR_PC14VALUE_Msk      (0x1U << RTC_TAFCR_PC14VALUE_Pos)         /*!< 0x00100000 */
8072 #define RTC_TAFCR_PC14VALUE          RTC_TAFCR_PC14VALUE_Msk                   
8073 #define RTC_TAFCR_PC13MODE_Pos       (19U)                                     
8074 #define RTC_TAFCR_PC13MODE_Msk       (0x1U << RTC_TAFCR_PC13MODE_Pos)          /*!< 0x00080000 */
8075 #define RTC_TAFCR_PC13MODE           RTC_TAFCR_PC13MODE_Msk                    
8076 #define RTC_TAFCR_PC13VALUE_Pos      (18U)                                     
8077 #define RTC_TAFCR_PC13VALUE_Msk      (0x1U << RTC_TAFCR_PC13VALUE_Pos)         /*!< 0x00040000 */
8078 #define RTC_TAFCR_PC13VALUE          RTC_TAFCR_PC13VALUE_Msk                   
8079 #define RTC_TAFCR_TAMPPUDIS_Pos      (15U)                                     
8080 #define RTC_TAFCR_TAMPPUDIS_Msk      (0x1U << RTC_TAFCR_TAMPPUDIS_Pos)         /*!< 0x00008000 */
8081 #define RTC_TAFCR_TAMPPUDIS          RTC_TAFCR_TAMPPUDIS_Msk                   
8082 #define RTC_TAFCR_TAMPPRCH_Pos       (13U)                                     
8083 #define RTC_TAFCR_TAMPPRCH_Msk       (0x3U << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00006000 */
8084 #define RTC_TAFCR_TAMPPRCH           RTC_TAFCR_TAMPPRCH_Msk                    
8085 #define RTC_TAFCR_TAMPPRCH_0         (0x1U << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00002000 */
8086 #define RTC_TAFCR_TAMPPRCH_1         (0x2U << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00004000 */
8087 #define RTC_TAFCR_TAMPFLT_Pos        (11U)                                     
8088 #define RTC_TAFCR_TAMPFLT_Msk        (0x3U << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001800 */
8089 #define RTC_TAFCR_TAMPFLT            RTC_TAFCR_TAMPFLT_Msk                     
8090 #define RTC_TAFCR_TAMPFLT_0          (0x1U << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00000800 */
8091 #define RTC_TAFCR_TAMPFLT_1          (0x2U << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001000 */
8092 #define RTC_TAFCR_TAMPFREQ_Pos       (8U)                                      
8093 #define RTC_TAFCR_TAMPFREQ_Msk       (0x7U << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000700 */
8094 #define RTC_TAFCR_TAMPFREQ           RTC_TAFCR_TAMPFREQ_Msk                    
8095 #define RTC_TAFCR_TAMPFREQ_0         (0x1U << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000100 */
8096 #define RTC_TAFCR_TAMPFREQ_1         (0x2U << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000200 */
8097 #define RTC_TAFCR_TAMPFREQ_2         (0x4U << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000400 */
8098 #define RTC_TAFCR_TAMPTS_Pos         (7U)                                      
8099 #define RTC_TAFCR_TAMPTS_Msk         (0x1U << RTC_TAFCR_TAMPTS_Pos)            /*!< 0x00000080 */
8100 #define RTC_TAFCR_TAMPTS             RTC_TAFCR_TAMPTS_Msk                      
8101 #define RTC_TAFCR_TAMP2TRG_Pos       (4U)                                      
8102 #define RTC_TAFCR_TAMP2TRG_Msk       (0x1U << RTC_TAFCR_TAMP2TRG_Pos)          /*!< 0x00000010 */
8103 #define RTC_TAFCR_TAMP2TRG           RTC_TAFCR_TAMP2TRG_Msk                    
8104 #define RTC_TAFCR_TAMP2E_Pos         (3U)                                      
8105 #define RTC_TAFCR_TAMP2E_Msk         (0x1U << RTC_TAFCR_TAMP2E_Pos)            /*!< 0x00000008 */
8106 #define RTC_TAFCR_TAMP2E             RTC_TAFCR_TAMP2E_Msk                      
8107 #define RTC_TAFCR_TAMPIE_Pos         (2U)                                      
8108 #define RTC_TAFCR_TAMPIE_Msk         (0x1U << RTC_TAFCR_TAMPIE_Pos)            /*!< 0x00000004 */
8109 #define RTC_TAFCR_TAMPIE             RTC_TAFCR_TAMPIE_Msk                      
8110 #define RTC_TAFCR_TAMP1TRG_Pos       (1U)                                      
8111 #define RTC_TAFCR_TAMP1TRG_Msk       (0x1U << RTC_TAFCR_TAMP1TRG_Pos)          /*!< 0x00000002 */
8112 #define RTC_TAFCR_TAMP1TRG           RTC_TAFCR_TAMP1TRG_Msk                    
8113 #define RTC_TAFCR_TAMP1E_Pos         (0U)                                      
8114 #define RTC_TAFCR_TAMP1E_Msk         (0x1U << RTC_TAFCR_TAMP1E_Pos)            /*!< 0x00000001 */
8115 #define RTC_TAFCR_TAMP1E             RTC_TAFCR_TAMP1E_Msk                      
8116
8117 /* Reference defines */
8118 #define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
8119
8120 /********************  Bits definition for RTC_ALRMASSR register  ************/
8121 #define RTC_ALRMASSR_MASKSS_Pos      (24U)                                     
8122 #define RTC_ALRMASSR_MASKSS_Msk      (0xFU << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x0F000000 */
8123 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk                   
8124 #define RTC_ALRMASSR_MASKSS_0        (0x1U << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x01000000 */
8125 #define RTC_ALRMASSR_MASKSS_1        (0x2U << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x02000000 */
8126 #define RTC_ALRMASSR_MASKSS_2        (0x4U << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x04000000 */
8127 #define RTC_ALRMASSR_MASKSS_3        (0x8U << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x08000000 */
8128 #define RTC_ALRMASSR_SS_Pos          (0U)                                      
8129 #define RTC_ALRMASSR_SS_Msk          (0x7FFFU << RTC_ALRMASSR_SS_Pos)          /*!< 0x00007FFF */
8130 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk                       
8131
8132 /********************  Bits definition for RTC_BKP0R register  ***************/
8133 #define RTC_BKP0R_Pos                (0U)                                      
8134 #define RTC_BKP0R_Msk                (0xFFFFFFFFU << RTC_BKP0R_Pos)            /*!< 0xFFFFFFFF */
8135 #define RTC_BKP0R                    RTC_BKP0R_Msk                             
8136
8137 /********************  Bits definition for RTC_BKP1R register  ***************/
8138 #define RTC_BKP1R_Pos                (0U)                                      
8139 #define RTC_BKP1R_Msk                (0xFFFFFFFFU << RTC_BKP1R_Pos)            /*!< 0xFFFFFFFF */
8140 #define RTC_BKP1R                    RTC_BKP1R_Msk                             
8141
8142 /********************  Bits definition for RTC_BKP2R register  ***************/
8143 #define RTC_BKP2R_Pos                (0U)                                      
8144 #define RTC_BKP2R_Msk                (0xFFFFFFFFU << RTC_BKP2R_Pos)            /*!< 0xFFFFFFFF */
8145 #define RTC_BKP2R                    RTC_BKP2R_Msk                             
8146
8147 /********************  Bits definition for RTC_BKP3R register  ***************/
8148 #define RTC_BKP3R_Pos                (0U)                                      
8149 #define RTC_BKP3R_Msk                (0xFFFFFFFFU << RTC_BKP3R_Pos)            /*!< 0xFFFFFFFF */
8150 #define RTC_BKP3R                    RTC_BKP3R_Msk                             
8151
8152 /********************  Bits definition for RTC_BKP4R register  ***************/
8153 #define RTC_BKP4R_Pos                (0U)                                      
8154 #define RTC_BKP4R_Msk                (0xFFFFFFFFU << RTC_BKP4R_Pos)            /*!< 0xFFFFFFFF */
8155 #define RTC_BKP4R                    RTC_BKP4R_Msk                             
8156
8157 /******************** Number of backup registers ******************************/
8158 #define RTC_BKP_NUMBER                       0x00000005U
8159
8160 /*****************************************************************************/
8161 /*                                                                           */
8162 /*                        Serial Peripheral Interface (SPI)                  */
8163 /*                                                                           */
8164 /*****************************************************************************/
8165
8166 /*
8167  * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
8168  */
8169 #define SPI_I2S_SUPPORT                       /*!< I2S support */
8170
8171 /*******************  Bit definition for SPI_CR1 register  *******************/
8172 #define SPI_CR1_CPHA_Pos            (0U)                                       
8173 #define SPI_CR1_CPHA_Msk            (0x1U << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
8174 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
8175 #define SPI_CR1_CPOL_Pos            (1U)                                       
8176 #define SPI_CR1_CPOL_Msk            (0x1U << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
8177 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
8178 #define SPI_CR1_MSTR_Pos            (2U)                                       
8179 #define SPI_CR1_MSTR_Msk            (0x1U << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
8180 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
8181 #define SPI_CR1_BR_Pos              (3U)                                       
8182 #define SPI_CR1_BR_Msk              (0x7U << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
8183 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
8184 #define SPI_CR1_BR_0                (0x1U << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
8185 #define SPI_CR1_BR_1                (0x2U << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
8186 #define SPI_CR1_BR_2                (0x4U << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
8187 #define SPI_CR1_SPE_Pos             (6U)                                       
8188 #define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
8189 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
8190 #define SPI_CR1_LSBFIRST_Pos        (7U)                                       
8191 #define SPI_CR1_LSBFIRST_Msk        (0x1U << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
8192 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
8193 #define SPI_CR1_SSI_Pos             (8U)                                       
8194 #define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
8195 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
8196 #define SPI_CR1_SSM_Pos             (9U)                                       
8197 #define SPI_CR1_SSM_Msk             (0x1U << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
8198 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
8199 #define SPI_CR1_RXONLY_Pos          (10U)                                      
8200 #define SPI_CR1_RXONLY_Msk          (0x1U << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
8201 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
8202 #define SPI_CR1_CRCL_Pos            (11U)                                      
8203 #define SPI_CR1_CRCL_Msk            (0x1U << SPI_CR1_CRCL_Pos)                 /*!< 0x00000800 */
8204 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
8205 #define SPI_CR1_CRCNEXT_Pos         (12U)                                      
8206 #define SPI_CR1_CRCNEXT_Msk         (0x1U << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
8207 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
8208 #define SPI_CR1_CRCEN_Pos           (13U)                                      
8209 #define SPI_CR1_CRCEN_Msk           (0x1U << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
8210 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
8211 #define SPI_CR1_BIDIOE_Pos          (14U)                                      
8212 #define SPI_CR1_BIDIOE_Msk          (0x1U << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
8213 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
8214 #define SPI_CR1_BIDIMODE_Pos        (15U)                                      
8215 #define SPI_CR1_BIDIMODE_Msk        (0x1U << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
8216 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
8217
8218 /*******************  Bit definition for SPI_CR2 register  *******************/
8219 #define SPI_CR2_RXDMAEN_Pos         (0U)                                       
8220 #define SPI_CR2_RXDMAEN_Msk         (0x1U << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
8221 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
8222 #define SPI_CR2_TXDMAEN_Pos         (1U)                                       
8223 #define SPI_CR2_TXDMAEN_Msk         (0x1U << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
8224 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
8225 #define SPI_CR2_SSOE_Pos            (2U)                                       
8226 #define SPI_CR2_SSOE_Msk            (0x1U << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
8227 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
8228 #define SPI_CR2_NSSP_Pos            (3U)                                       
8229 #define SPI_CR2_NSSP_Msk            (0x1U << SPI_CR2_NSSP_Pos)                 /*!< 0x00000008 */
8230 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
8231 #define SPI_CR2_FRF_Pos             (4U)                                       
8232 #define SPI_CR2_FRF_Msk             (0x1U << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
8233 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
8234 #define SPI_CR2_ERRIE_Pos           (5U)                                       
8235 #define SPI_CR2_ERRIE_Msk           (0x1U << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
8236 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
8237 #define SPI_CR2_RXNEIE_Pos          (6U)                                       
8238 #define SPI_CR2_RXNEIE_Msk          (0x1U << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
8239 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
8240 #define SPI_CR2_TXEIE_Pos           (7U)                                       
8241 #define SPI_CR2_TXEIE_Msk           (0x1U << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
8242 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
8243 #define SPI_CR2_DS_Pos              (8U)                                       
8244 #define SPI_CR2_DS_Msk              (0xFU << SPI_CR2_DS_Pos)                   /*!< 0x00000F00 */
8245 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
8246 #define SPI_CR2_DS_0                (0x1U << SPI_CR2_DS_Pos)                   /*!< 0x00000100 */
8247 #define SPI_CR2_DS_1                (0x2U << SPI_CR2_DS_Pos)                   /*!< 0x00000200 */
8248 #define SPI_CR2_DS_2                (0x4U << SPI_CR2_DS_Pos)                   /*!< 0x00000400 */
8249 #define SPI_CR2_DS_3                (0x8U << SPI_CR2_DS_Pos)                   /*!< 0x00000800 */
8250 #define SPI_CR2_FRXTH_Pos           (12U)                                      
8251 #define SPI_CR2_FRXTH_Msk           (0x1U << SPI_CR2_FRXTH_Pos)                /*!< 0x00001000 */
8252 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
8253 #define SPI_CR2_LDMARX_Pos          (13U)                                      
8254 #define SPI_CR2_LDMARX_Msk          (0x1U << SPI_CR2_LDMARX_Pos)               /*!< 0x00002000 */
8255 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
8256 #define SPI_CR2_LDMATX_Pos          (14U)                                      
8257 #define SPI_CR2_LDMATX_Msk          (0x1U << SPI_CR2_LDMATX_Pos)               /*!< 0x00004000 */
8258 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
8259
8260 /********************  Bit definition for SPI_SR register  *******************/
8261 #define SPI_SR_RXNE_Pos             (0U)                                       
8262 #define SPI_SR_RXNE_Msk             (0x1U << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
8263 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
8264 #define SPI_SR_TXE_Pos              (1U)                                       
8265 #define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
8266 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
8267 #define SPI_SR_CHSIDE_Pos           (2U)                                       
8268 #define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
8269 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
8270 #define SPI_SR_UDR_Pos              (3U)                                       
8271 #define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
8272 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
8273 #define SPI_SR_CRCERR_Pos           (4U)                                       
8274 #define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
8275 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
8276 #define SPI_SR_MODF_Pos             (5U)                                       
8277 #define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
8278 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
8279 #define SPI_SR_OVR_Pos              (6U)                                       
8280 #define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
8281 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
8282 #define SPI_SR_BSY_Pos              (7U)                                       
8283 #define SPI_SR_BSY_Msk              (0x1U << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
8284 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
8285 #define SPI_SR_FRE_Pos              (8U)                                       
8286 #define SPI_SR_FRE_Msk              (0x1U << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
8287 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
8288 #define SPI_SR_FRLVL_Pos            (9U)                                       
8289 #define SPI_SR_FRLVL_Msk            (0x3U << SPI_SR_FRLVL_Pos)                 /*!< 0x00000600 */
8290 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
8291 #define SPI_SR_FRLVL_0              (0x1U << SPI_SR_FRLVL_Pos)                 /*!< 0x00000200 */
8292 #define SPI_SR_FRLVL_1              (0x2U << SPI_SR_FRLVL_Pos)                 /*!< 0x00000400 */
8293 #define SPI_SR_FTLVL_Pos            (11U)                                      
8294 #define SPI_SR_FTLVL_Msk            (0x3U << SPI_SR_FTLVL_Pos)                 /*!< 0x00001800 */
8295 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
8296 #define SPI_SR_FTLVL_0              (0x1U << SPI_SR_FTLVL_Pos)                 /*!< 0x00000800 */
8297 #define SPI_SR_FTLVL_1              (0x2U << SPI_SR_FTLVL_Pos)                 /*!< 0x00001000 */
8298
8299 /********************  Bit definition for SPI_DR register  *******************/
8300 #define SPI_DR_DR_Pos               (0U)                                       
8301 #define SPI_DR_DR_Msk               (0xFFFFFFFFU << SPI_DR_DR_Pos)             /*!< 0xFFFFFFFF */
8302 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
8303
8304 /*******************  Bit definition for SPI_CRCPR register  *****************/
8305 #define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       
8306 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFFFFFU << SPI_CRCPR_CRCPOLY_Pos)     /*!< 0xFFFFFFFF */
8307 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
8308
8309 /******************  Bit definition for SPI_RXCRCR register  *****************/
8310 #define SPI_RXCRCR_RXCRC_Pos        (0U)                                       
8311 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFFFFFU << SPI_RXCRCR_RXCRC_Pos)      /*!< 0xFFFFFFFF */
8312 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
8313
8314 /******************  Bit definition for SPI_TXCRCR register  *****************/
8315 #define SPI_TXCRCR_TXCRC_Pos        (0U)                                       
8316 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFFFFFU << SPI_TXCRCR_TXCRC_Pos)      /*!< 0xFFFFFFFF */
8317 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
8318
8319 /******************  Bit definition for SPI_I2SCFGR register  ****************/
8320 #define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       
8321 #define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
8322 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
8323 #define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       
8324 #define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
8325 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
8326 #define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
8327 #define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
8328 #define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       
8329 #define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
8330 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
8331 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       
8332 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
8333 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
8334 #define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
8335 #define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
8336 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       
8337 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
8338 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
8339 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       
8340 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
8341 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
8342 #define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
8343 #define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
8344 #define SPI_I2SCFGR_I2SE_Pos        (10U)                                      
8345 #define SPI_I2SCFGR_I2SE_Msk        (0x1U << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
8346 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
8347 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      
8348 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
8349 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
8350
8351 /******************  Bit definition for SPI_I2SPR register  ******************/
8352 #define SPI_I2SPR_I2SDIV_Pos        (0U)                                       
8353 #define SPI_I2SPR_I2SDIV_Msk        (0xFFU << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
8354 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
8355 #define SPI_I2SPR_ODD_Pos           (8U)                                       
8356 #define SPI_I2SPR_ODD_Msk           (0x1U << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
8357 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
8358 #define SPI_I2SPR_MCKOE_Pos         (9U)                                       
8359 #define SPI_I2SPR_MCKOE_Msk         (0x1U << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
8360 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
8361
8362 /*****************************************************************************/
8363 /*                                                                           */
8364 /*                       System Configuration (SYSCFG)                       */
8365 /*                                                                           */
8366 /*****************************************************************************/
8367 /*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
8368 #define SYSCFG_CFGR1_MEM_MODE_Pos            (0U)                              
8369 #define SYSCFG_CFGR1_MEM_MODE_Msk            (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
8370 #define SYSCFG_CFGR1_MEM_MODE                SYSCFG_CFGR1_MEM_MODE_Msk           /*!< SYSCFG_Memory Remap Config */
8371 #define SYSCFG_CFGR1_MEM_MODE_0              (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
8372 #define SYSCFG_CFGR1_MEM_MODE_1              (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
8373 #define SYSCFG_CFGR1_PA11_PA12_RMP_Pos       (4U)                              
8374 #define SYSCFG_CFGR1_PA11_PA12_RMP_Msk       (0x1U << SYSCFG_CFGR1_PA11_PA12_RMP_Pos) /*!< 0x00000010 */
8375 #define SYSCFG_CFGR1_PA11_PA12_RMP           SYSCFG_CFGR1_PA11_PA12_RMP_Msk    /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages */
8376
8377 #define SYSCFG_CFGR1_DMA_RMP_Pos             (8U)                              
8378 #define SYSCFG_CFGR1_DMA_RMP_Msk             (0x1FU << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00001F00 */
8379 #define SYSCFG_CFGR1_DMA_RMP                 SYSCFG_CFGR1_DMA_RMP_Msk          /*!< DMA remap mask */
8380 #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos         (8U)                              
8381 #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk         (0x1U << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */
8382 #define SYSCFG_CFGR1_ADC_DMA_RMP             SYSCFG_CFGR1_ADC_DMA_RMP_Msk      /*!< ADC DMA remap */
8383 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos    (9U)                              
8384 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk    (0x1U << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */
8385 #define SYSCFG_CFGR1_USART1TX_DMA_RMP        SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */
8386 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos    (10U)                             
8387 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk    (0x1U << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */
8388 #define SYSCFG_CFGR1_USART1RX_DMA_RMP        SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */
8389 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos       (11U)                             
8390 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk       (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
8391 #define SYSCFG_CFGR1_TIM16_DMA_RMP           SYSCFG_CFGR1_TIM16_DMA_RMP_Msk    /*!< Timer 16 DMA remap */
8392 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos       (12U)                             
8393 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk       (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
8394 #define SYSCFG_CFGR1_TIM17_DMA_RMP           SYSCFG_CFGR1_TIM17_DMA_RMP_Msk    /*!< Timer 17 DMA remap */
8395
8396 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos         (16U)                             
8397 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk         (0x1U << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */
8398 #define SYSCFG_CFGR1_I2C_FMP_PB6             SYSCFG_CFGR1_I2C_FMP_PB6_Msk      /*!< I2C PB6 Fast mode plus */
8399 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos         (17U)                             
8400 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk         (0x1U << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */
8401 #define SYSCFG_CFGR1_I2C_FMP_PB7             SYSCFG_CFGR1_I2C_FMP_PB7_Msk      /*!< I2C PB7 Fast mode plus */
8402 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos         (18U)                             
8403 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk         (0x1U << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */
8404 #define SYSCFG_CFGR1_I2C_FMP_PB8             SYSCFG_CFGR1_I2C_FMP_PB8_Msk      /*!< I2C PB8 Fast mode plus */
8405 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos         (19U)                             
8406 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk         (0x1U << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */
8407 #define SYSCFG_CFGR1_I2C_FMP_PB9             SYSCFG_CFGR1_I2C_FMP_PB9_Msk      /*!< I2C PB9 Fast mode plus */
8408 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos        (20U)                             
8409 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Msk        (0x1U << SYSCFG_CFGR1_I2C_FMP_I2C1_Pos) /*!< 0x00100000 */
8410 #define SYSCFG_CFGR1_I2C_FMP_I2C1            SYSCFG_CFGR1_I2C_FMP_I2C1_Msk     /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7  */
8411 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Pos        (21U)                             
8412 #define SYSCFG_CFGR1_I2C_FMP_I2C2_Msk        (0x1U << SYSCFG_CFGR1_I2C_FMP_I2C2_Pos) /*!< 0x00200000 */
8413 #define SYSCFG_CFGR1_I2C_FMP_I2C2            SYSCFG_CFGR1_I2C_FMP_I2C2_Msk     /*!< Enable I2C2 Fast mode plus  */
8414 #define SYSCFG_CFGR1_I2C_FMP_PA9_Pos         (22U)                             
8415 #define SYSCFG_CFGR1_I2C_FMP_PA9_Msk         (0x1U << SYSCFG_CFGR1_I2C_FMP_PA9_Pos) /*!< 0x00400000 */
8416 #define SYSCFG_CFGR1_I2C_FMP_PA9             SYSCFG_CFGR1_I2C_FMP_PA9_Msk      /*!< Enable Fast Mode Plus on PA9  */
8417 #define SYSCFG_CFGR1_I2C_FMP_PA10_Pos        (23U)                             
8418 #define SYSCFG_CFGR1_I2C_FMP_PA10_Msk        (0x1U << SYSCFG_CFGR1_I2C_FMP_PA10_Pos) /*!< 0x00800000 */
8419 #define SYSCFG_CFGR1_I2C_FMP_PA10            SYSCFG_CFGR1_I2C_FMP_PA10_Msk     /*!< Enable Fast Mode Plus on PA10 */
8420
8421 /*****************  Bit definition for SYSCFG_EXTICR1 register  **************/
8422 #define SYSCFG_EXTICR1_EXTI0_Pos             (0U)                              
8423 #define SYSCFG_EXTICR1_EXTI0_Msk             (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
8424 #define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!< EXTI 0 configuration */
8425 #define SYSCFG_EXTICR1_EXTI1_Pos             (4U)                              
8426 #define SYSCFG_EXTICR1_EXTI1_Msk             (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
8427 #define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!< EXTI 1 configuration */
8428 #define SYSCFG_EXTICR1_EXTI2_Pos             (8U)                              
8429 #define SYSCFG_EXTICR1_EXTI2_Msk             (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
8430 #define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!< EXTI 2 configuration */
8431 #define SYSCFG_EXTICR1_EXTI3_Pos             (12U)                             
8432 #define SYSCFG_EXTICR1_EXTI3_Msk             (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
8433 #define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!< EXTI 3 configuration */
8434
8435 /** 
8436   * @brief  EXTI0 configuration
8437   */
8438 #define SYSCFG_EXTICR1_EXTI0_PA              (0x00000000U)                     /*!< PA[0] pin */
8439 #define SYSCFG_EXTICR1_EXTI0_PB              (0x00000001U)                     /*!< PB[0] pin */
8440 #define SYSCFG_EXTICR1_EXTI0_PC              (0x00000002U)                     /*!< PC[0] pin */
8441 #define SYSCFG_EXTICR1_EXTI0_PD              (0x00000003U)                     /*!< PD[0] pin */
8442 #define SYSCFG_EXTICR1_EXTI0_PF              (0x00000005U)                     /*!< PF[0] pin */
8443
8444 /** 
8445   * @brief  EXTI1 configuration  
8446   */ 
8447 #define SYSCFG_EXTICR1_EXTI1_PA              (0x00000000U)                     /*!< PA[1] pin */
8448 #define SYSCFG_EXTICR1_EXTI1_PB              (0x00000010U)                     /*!< PB[1] pin */
8449 #define SYSCFG_EXTICR1_EXTI1_PC              (0x00000020U)                     /*!< PC[1] pin */
8450 #define SYSCFG_EXTICR1_EXTI1_PD              (0x00000030U)                     /*!< PD[1] pin */
8451 #define SYSCFG_EXTICR1_EXTI1_PF              (0x00000050U)                     /*!< PF[1] pin */
8452
8453 /** 
8454   * @brief  EXTI2 configuration  
8455   */
8456 #define SYSCFG_EXTICR1_EXTI2_PA              (0x00000000U)                     /*!< PA[2] pin */
8457 #define SYSCFG_EXTICR1_EXTI2_PB              (0x00000100U)                     /*!< PB[2] pin */
8458 #define SYSCFG_EXTICR1_EXTI2_PC              (0x00000200U)                     /*!< PC[2] pin */
8459 #define SYSCFG_EXTICR1_EXTI2_PD              (0x00000300U)                     /*!< PD[2] pin */
8460 #define SYSCFG_EXTICR1_EXTI2_PF              (0x00000500U)                     /*!< PF[2] pin */
8461
8462 /** 
8463   * @brief  EXTI3 configuration  
8464   */
8465 #define SYSCFG_EXTICR1_EXTI3_PA              (0x00000000U)                     /*!< PA[3] pin */
8466 #define SYSCFG_EXTICR1_EXTI3_PB              (0x00001000U)                     /*!< PB[3] pin */
8467 #define SYSCFG_EXTICR1_EXTI3_PC              (0x00002000U)                     /*!< PC[3] pin */
8468 #define SYSCFG_EXTICR1_EXTI3_PD              (0x00003000U)                     /*!< PD[3] pin */
8469 #define SYSCFG_EXTICR1_EXTI3_PF              (0x00005000U)                     /*!< PF[3] pin */
8470
8471 /*****************  Bit definition for SYSCFG_EXTICR2 register  **************/
8472 #define SYSCFG_EXTICR2_EXTI4_Pos             (0U)                              
8473 #define SYSCFG_EXTICR2_EXTI4_Msk             (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
8474 #define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!< EXTI 4 configuration */
8475 #define SYSCFG_EXTICR2_EXTI5_Pos             (4U)                              
8476 #define SYSCFG_EXTICR2_EXTI5_Msk             (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
8477 #define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!< EXTI 5 configuration */
8478 #define SYSCFG_EXTICR2_EXTI6_Pos             (8U)                              
8479 #define SYSCFG_EXTICR2_EXTI6_Msk             (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
8480 #define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!< EXTI 6 configuration */
8481 #define SYSCFG_EXTICR2_EXTI7_Pos             (12U)                             
8482 #define SYSCFG_EXTICR2_EXTI7_Msk             (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
8483 #define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!< EXTI 7 configuration */
8484
8485 /** 
8486   * @brief  EXTI4 configuration  
8487   */
8488 #define SYSCFG_EXTICR2_EXTI4_PA              (0x00000000U)                     /*!< PA[4] pin */
8489 #define SYSCFG_EXTICR2_EXTI4_PB              (0x00000001U)                     /*!< PB[4] pin */
8490 #define SYSCFG_EXTICR2_EXTI4_PC              (0x00000002U)                     /*!< PC[4] pin */
8491 #define SYSCFG_EXTICR2_EXTI4_PD              (0x00000003U)                     /*!< PD[4] pin */
8492 #define SYSCFG_EXTICR2_EXTI4_PF              (0x00000005U)                     /*!< PF[4] pin */
8493
8494 /** 
8495   * @brief  EXTI5 configuration  
8496   */
8497 #define SYSCFG_EXTICR2_EXTI5_PA              (0x00000000U)                     /*!< PA[5] pin */
8498 #define SYSCFG_EXTICR2_EXTI5_PB              (0x00000010U)                     /*!< PB[5] pin */
8499 #define SYSCFG_EXTICR2_EXTI5_PC              (0x00000020U)                     /*!< PC[5] pin */
8500 #define SYSCFG_EXTICR2_EXTI5_PD              (0x00000030U)                     /*!< PD[5] pin */
8501 #define SYSCFG_EXTICR2_EXTI5_PF              (0x00000050U)                     /*!< PF[5] pin */
8502
8503 /** 
8504   * @brief  EXTI6 configuration  
8505   */
8506 #define SYSCFG_EXTICR2_EXTI6_PA              (0x00000000U)                     /*!< PA[6] pin */
8507 #define SYSCFG_EXTICR2_EXTI6_PB              (0x00000100U)                     /*!< PB[6] pin */
8508 #define SYSCFG_EXTICR2_EXTI6_PC              (0x00000200U)                     /*!< PC[6] pin */
8509 #define SYSCFG_EXTICR2_EXTI6_PD              (0x00000300U)                     /*!< PD[6] pin */
8510 #define SYSCFG_EXTICR2_EXTI6_PF              (0x00000500U)                     /*!< PF[6] pin */
8511
8512 /** 
8513   * @brief  EXTI7 configuration  
8514   */
8515 #define SYSCFG_EXTICR2_EXTI7_PA              (0x00000000U)                     /*!< PA[7] pin */
8516 #define SYSCFG_EXTICR2_EXTI7_PB              (0x00001000U)                     /*!< PB[7] pin */
8517 #define SYSCFG_EXTICR2_EXTI7_PC              (0x00002000U)                     /*!< PC[7] pin */
8518 #define SYSCFG_EXTICR2_EXTI7_PD              (0x00003000U)                     /*!< PD[7] pin */
8519 #define SYSCFG_EXTICR2_EXTI7_PF              (0x00005000U)                     /*!< PF[7] pin */
8520
8521 /*****************  Bit definition for SYSCFG_EXTICR3 register  **************/
8522 #define SYSCFG_EXTICR3_EXTI8_Pos             (0U)                              
8523 #define SYSCFG_EXTICR3_EXTI8_Msk             (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
8524 #define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!< EXTI 8 configuration */
8525 #define SYSCFG_EXTICR3_EXTI9_Pos             (4U)                              
8526 #define SYSCFG_EXTICR3_EXTI9_Msk             (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
8527 #define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!< EXTI 9 configuration */
8528 #define SYSCFG_EXTICR3_EXTI10_Pos            (8U)                              
8529 #define SYSCFG_EXTICR3_EXTI10_Msk            (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
8530 #define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!< EXTI 10 configuration */
8531 #define SYSCFG_EXTICR3_EXTI11_Pos            (12U)                             
8532 #define SYSCFG_EXTICR3_EXTI11_Msk            (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
8533 #define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!< EXTI 11 configuration */
8534
8535 /** 
8536   * @brief  EXTI8 configuration  
8537   */
8538 #define SYSCFG_EXTICR3_EXTI8_PA              (0x00000000U)                     /*!< PA[8] pin */
8539 #define SYSCFG_EXTICR3_EXTI8_PB              (0x00000001U)                     /*!< PB[8] pin */
8540 #define SYSCFG_EXTICR3_EXTI8_PC              (0x00000002U)                     /*!< PC[8] pin */
8541 #define SYSCFG_EXTICR3_EXTI8_PD              (0x00000003U)                     /*!< PD[8] pin */
8542 #define SYSCFG_EXTICR3_EXTI8_PE              (0x00000004U)                     /*!< PE[8] pin */
8543
8544
8545 /** 
8546   * @brief  EXTI9 configuration  
8547   */
8548 #define SYSCFG_EXTICR3_EXTI9_PA              (0x00000000U)                     /*!< PA[9] pin */
8549 #define SYSCFG_EXTICR3_EXTI9_PB              (0x00000010U)                     /*!< PB[9] pin */
8550 #define SYSCFG_EXTICR3_EXTI9_PC              (0x00000020U)                     /*!< PC[9] pin */
8551 #define SYSCFG_EXTICR3_EXTI9_PD              (0x00000030U)                     /*!< PD[9] pin */
8552 #define SYSCFG_EXTICR3_EXTI9_PF              (0x00000050U)                     /*!< PF[9] pin */
8553
8554 /** 
8555   * @brief  EXTI10 configuration  
8556   */
8557 #define SYSCFG_EXTICR3_EXTI10_PA             (0x00000000U)                     /*!< PA[10] pin */
8558 #define SYSCFG_EXTICR3_EXTI10_PB             (0x00000100U)                     /*!< PB[10] pin */
8559 #define SYSCFG_EXTICR3_EXTI10_PC             (0x00000200U)                     /*!< PC[10] pin */
8560 #define SYSCFG_EXTICR3_EXTI10_PD             (0x00000300U)                     /*!< PD[10] pin */
8561 #define SYSCFG_EXTICR3_EXTI10_PF             (0x00000500U)                     /*!< PF[10] pin */
8562
8563 /** 
8564   * @brief  EXTI11 configuration  
8565   */
8566 #define SYSCFG_EXTICR3_EXTI11_PA             (0x00000000U)                     /*!< PA[11] pin */
8567 #define SYSCFG_EXTICR3_EXTI11_PB             (0x00001000U)                     /*!< PB[11] pin */
8568 #define SYSCFG_EXTICR3_EXTI11_PC             (0x00002000U)                     /*!< PC[11] pin */
8569 #define SYSCFG_EXTICR3_EXTI11_PD             (0x00003000U)                     /*!< PD[11] pin */
8570 #define SYSCFG_EXTICR3_EXTI11_PE             (0x00004000U)                     /*!< PE[11] pin */
8571
8572 /*****************  Bit definition for SYSCFG_EXTICR4 register  **************/
8573 #define SYSCFG_EXTICR4_EXTI12_Pos            (0U)                              
8574 #define SYSCFG_EXTICR4_EXTI12_Msk            (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
8575 #define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!< EXTI 12 configuration */
8576 #define SYSCFG_EXTICR4_EXTI13_Pos            (4U)                              
8577 #define SYSCFG_EXTICR4_EXTI13_Msk            (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
8578 #define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!< EXTI 13 configuration */
8579 #define SYSCFG_EXTICR4_EXTI14_Pos            (8U)                              
8580 #define SYSCFG_EXTICR4_EXTI14_Msk            (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
8581 #define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!< EXTI 14 configuration */
8582 #define SYSCFG_EXTICR4_EXTI15_Pos            (12U)                             
8583 #define SYSCFG_EXTICR4_EXTI15_Msk            (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
8584 #define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!< EXTI 15 configuration */
8585
8586 /** 
8587   * @brief  EXTI12 configuration  
8588   */
8589 #define SYSCFG_EXTICR4_EXTI12_PA             (0x00000000U)                     /*!< PA[12] pin */
8590 #define SYSCFG_EXTICR4_EXTI12_PB             (0x00000001U)                     /*!< PB[12] pin */
8591 #define SYSCFG_EXTICR4_EXTI12_PC             (0x00000002U)                     /*!< PC[12] pin */
8592 #define SYSCFG_EXTICR4_EXTI12_PD             (0x00000003U)                     /*!< PD[12] pin */
8593 #define SYSCFG_EXTICR4_EXTI12_PE             (0x00000004U)                     /*!< PE[12] pin */
8594
8595 /** 
8596   * @brief  EXTI13 configuration  
8597   */
8598 #define SYSCFG_EXTICR4_EXTI13_PA             (0x00000000U)                     /*!< PA[13] pin */
8599 #define SYSCFG_EXTICR4_EXTI13_PB             (0x00000010U)                     /*!< PB[13] pin */
8600 #define SYSCFG_EXTICR4_EXTI13_PC             (0x00000020U)                     /*!< PC[13] pin */
8601 #define SYSCFG_EXTICR4_EXTI13_PD             (0x00000030U)                     /*!< PD[13] pin */
8602 #define SYSCFG_EXTICR4_EXTI13_PE             (0x00000040U)                     /*!< PE[13] pin */
8603
8604 /** 
8605   * @brief  EXTI14 configuration  
8606   */
8607 #define SYSCFG_EXTICR4_EXTI14_PA             (0x00000000U)                     /*!< PA[14] pin */
8608 #define SYSCFG_EXTICR4_EXTI14_PB             (0x00000100U)                     /*!< PB[14] pin */
8609 #define SYSCFG_EXTICR4_EXTI14_PC             (0x00000200U)                     /*!< PC[14] pin */
8610 #define SYSCFG_EXTICR4_EXTI14_PD             (0x00000300U)                     /*!< PD[14] pin */
8611 #define SYSCFG_EXTICR4_EXTI14_PE             (0x00000400U)                     /*!< PE[14] pin */
8612
8613 /** 
8614   * @brief  EXTI15 configuration  
8615   */
8616 #define SYSCFG_EXTICR4_EXTI15_PA             (0x00000000U)                     /*!< PA[15] pin */
8617 #define SYSCFG_EXTICR4_EXTI15_PB             (0x00001000U)                     /*!< PB[15] pin */
8618 #define SYSCFG_EXTICR4_EXTI15_PC             (0x00002000U)                     /*!< PC[15] pin */
8619 #define SYSCFG_EXTICR4_EXTI15_PD             (0x00003000U)                     /*!< PD[15] pin */
8620 #define SYSCFG_EXTICR4_EXTI15_PE             (0x00004000U)                     /*!< PE[15] pin */
8621
8622 /*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
8623 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos         (0U)                              
8624 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk         (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
8625 #define SYSCFG_CFGR2_LOCKUP_LOCK             SYSCFG_CFGR2_LOCKUP_LOCK_Msk      /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
8626 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos    (1U)                              
8627 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk    (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
8628 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK        SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
8629 #define SYSCFG_CFGR2_PVD_LOCK_Pos            (2U)                              
8630 #define SYSCFG_CFGR2_PVD_LOCK_Msk            (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
8631 #define SYSCFG_CFGR2_PVD_LOCK                SYSCFG_CFGR2_PVD_LOCK_Msk         /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
8632 #define SYSCFG_CFGR2_SRAM_PEF_Pos            (8U)                              
8633 #define SYSCFG_CFGR2_SRAM_PEF_Msk            (0x1U << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */
8634 #define SYSCFG_CFGR2_SRAM_PEF                SYSCFG_CFGR2_SRAM_PEF_Msk         /*!< SRAM Parity error flag */
8635 #define SYSCFG_CFGR2_SRAM_PE                 SYSCFG_CFGR2_SRAM_PEF  /*!< SRAM Parity error flag (define maintained for legacy purpose) */
8636
8637 /*****************************************************************************/
8638 /*                                                                           */
8639 /*                               Timers (TIM)                                */
8640 /*                                                                           */
8641 /*****************************************************************************/
8642 /*******************  Bit definition for TIM_CR1 register  *******************/
8643 #define TIM_CR1_CEN_Pos           (0U)                                         
8644 #define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
8645 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
8646 #define TIM_CR1_UDIS_Pos          (1U)                                         
8647 #define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
8648 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
8649 #define TIM_CR1_URS_Pos           (2U)                                         
8650 #define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
8651 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
8652 #define TIM_CR1_OPM_Pos           (3U)                                         
8653 #define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
8654 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
8655 #define TIM_CR1_DIR_Pos           (4U)                                         
8656 #define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
8657 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
8658
8659 #define TIM_CR1_CMS_Pos           (5U)                                         
8660 #define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
8661 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
8662 #define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
8663 #define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
8664
8665 #define TIM_CR1_ARPE_Pos          (7U)                                         
8666 #define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
8667 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
8668
8669 #define TIM_CR1_CKD_Pos           (8U)                                         
8670 #define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
8671 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
8672 #define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
8673 #define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
8674
8675 /*******************  Bit definition for TIM_CR2 register  *******************/
8676 #define TIM_CR2_CCPC_Pos          (0U)                                         
8677 #define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
8678 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
8679 #define TIM_CR2_CCUS_Pos          (2U)                                         
8680 #define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
8681 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
8682 #define TIM_CR2_CCDS_Pos          (3U)                                         
8683 #define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
8684 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
8685
8686 #define TIM_CR2_MMS_Pos           (4U)                                         
8687 #define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
8688 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
8689 #define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
8690 #define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
8691 #define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
8692
8693 #define TIM_CR2_TI1S_Pos          (7U)                                         
8694 #define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
8695 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
8696 #define TIM_CR2_OIS1_Pos          (8U)                                         
8697 #define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
8698 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
8699 #define TIM_CR2_OIS1N_Pos         (9U)                                         
8700 #define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
8701 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
8702 #define TIM_CR2_OIS2_Pos          (10U)                                        
8703 #define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
8704 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
8705 #define TIM_CR2_OIS2N_Pos         (11U)                                        
8706 #define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
8707 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
8708 #define TIM_CR2_OIS3_Pos          (12U)                                        
8709 #define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
8710 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
8711 #define TIM_CR2_OIS3N_Pos         (13U)                                        
8712 #define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
8713 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
8714 #define TIM_CR2_OIS4_Pos          (14U)                                        
8715 #define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
8716 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
8717
8718 /*******************  Bit definition for TIM_SMCR register  ******************/
8719 #define TIM_SMCR_SMS_Pos          (0U)                                         
8720 #define TIM_SMCR_SMS_Msk          (0x7U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
8721 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
8722 #define TIM_SMCR_SMS_0            (0x1U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
8723 #define TIM_SMCR_SMS_1            (0x2U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
8724 #define TIM_SMCR_SMS_2            (0x4U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
8725
8726 #define TIM_SMCR_OCCS_Pos         (3U)                                         
8727 #define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
8728 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
8729
8730 #define TIM_SMCR_TS_Pos           (4U)                                         
8731 #define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
8732 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
8733 #define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
8734 #define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
8735 #define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
8736
8737 #define TIM_SMCR_MSM_Pos          (7U)                                         
8738 #define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
8739 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
8740
8741 #define TIM_SMCR_ETF_Pos          (8U)                                         
8742 #define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
8743 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
8744 #define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
8745 #define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
8746 #define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
8747 #define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
8748
8749 #define TIM_SMCR_ETPS_Pos         (12U)                                        
8750 #define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
8751 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
8752 #define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
8753 #define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
8754
8755 #define TIM_SMCR_ECE_Pos          (14U)                                        
8756 #define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
8757 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
8758 #define TIM_SMCR_ETP_Pos          (15U)                                        
8759 #define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
8760 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
8761
8762 /*******************  Bit definition for TIM_DIER register  ******************/
8763 #define TIM_DIER_UIE_Pos          (0U)                                         
8764 #define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
8765 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
8766 #define TIM_DIER_CC1IE_Pos        (1U)                                         
8767 #define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
8768 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
8769 #define TIM_DIER_CC2IE_Pos        (2U)                                         
8770 #define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
8771 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
8772 #define TIM_DIER_CC3IE_Pos        (3U)                                         
8773 #define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
8774 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
8775 #define TIM_DIER_CC4IE_Pos        (4U)                                         
8776 #define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
8777 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
8778 #define TIM_DIER_COMIE_Pos        (5U)                                         
8779 #define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
8780 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
8781 #define TIM_DIER_TIE_Pos          (6U)                                         
8782 #define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
8783 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
8784 #define TIM_DIER_BIE_Pos          (7U)                                         
8785 #define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
8786 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
8787 #define TIM_DIER_UDE_Pos          (8U)                                         
8788 #define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
8789 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
8790 #define TIM_DIER_CC1DE_Pos        (9U)                                         
8791 #define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
8792 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
8793 #define TIM_DIER_CC2DE_Pos        (10U)                                        
8794 #define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
8795 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
8796 #define TIM_DIER_CC3DE_Pos        (11U)                                        
8797 #define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
8798 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
8799 #define TIM_DIER_CC4DE_Pos        (12U)                                        
8800 #define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
8801 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
8802 #define TIM_DIER_COMDE_Pos        (13U)                                        
8803 #define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
8804 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
8805 #define TIM_DIER_TDE_Pos          (14U)                                        
8806 #define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
8807 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
8808
8809 /********************  Bit definition for TIM_SR register  *******************/
8810 #define TIM_SR_UIF_Pos            (0U)                                         
8811 #define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
8812 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
8813 #define TIM_SR_CC1IF_Pos          (1U)                                         
8814 #define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
8815 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
8816 #define TIM_SR_CC2IF_Pos          (2U)                                         
8817 #define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
8818 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
8819 #define TIM_SR_CC3IF_Pos          (3U)                                         
8820 #define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
8821 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
8822 #define TIM_SR_CC4IF_Pos          (4U)                                         
8823 #define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
8824 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
8825 #define TIM_SR_COMIF_Pos          (5U)                                         
8826 #define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
8827 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
8828 #define TIM_SR_TIF_Pos            (6U)                                         
8829 #define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
8830 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
8831 #define TIM_SR_BIF_Pos            (7U)                                         
8832 #define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
8833 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
8834 #define TIM_SR_CC1OF_Pos          (9U)                                         
8835 #define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
8836 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
8837 #define TIM_SR_CC2OF_Pos          (10U)                                        
8838 #define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
8839 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
8840 #define TIM_SR_CC3OF_Pos          (11U)                                        
8841 #define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
8842 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
8843 #define TIM_SR_CC4OF_Pos          (12U)                                        
8844 #define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
8845 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
8846
8847 /*******************  Bit definition for TIM_EGR register  *******************/
8848 #define TIM_EGR_UG_Pos            (0U)                                         
8849 #define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
8850 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
8851 #define TIM_EGR_CC1G_Pos          (1U)                                         
8852 #define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
8853 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
8854 #define TIM_EGR_CC2G_Pos          (2U)                                         
8855 #define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
8856 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
8857 #define TIM_EGR_CC3G_Pos          (3U)                                         
8858 #define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
8859 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
8860 #define TIM_EGR_CC4G_Pos          (4U)                                         
8861 #define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
8862 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
8863 #define TIM_EGR_COMG_Pos          (5U)                                         
8864 #define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
8865 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
8866 #define TIM_EGR_TG_Pos            (6U)                                         
8867 #define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
8868 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
8869 #define TIM_EGR_BG_Pos            (7U)                                         
8870 #define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
8871 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
8872
8873 /******************  Bit definition for TIM_CCMR1 register  ******************/
8874 #define TIM_CCMR1_CC1S_Pos        (0U)                                         
8875 #define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
8876 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
8877 #define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
8878 #define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
8879
8880 #define TIM_CCMR1_OC1FE_Pos       (2U)                                         
8881 #define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
8882 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
8883 #define TIM_CCMR1_OC1PE_Pos       (3U)                                         
8884 #define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
8885 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
8886
8887 #define TIM_CCMR1_OC1M_Pos        (4U)                                         
8888 #define TIM_CCMR1_OC1M_Msk        (0x7U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
8889 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
8890 #define TIM_CCMR1_OC1M_0          (0x1U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
8891 #define TIM_CCMR1_OC1M_1          (0x2U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
8892 #define TIM_CCMR1_OC1M_2          (0x4U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
8893
8894 #define TIM_CCMR1_OC1CE_Pos       (7U)                                         
8895 #define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
8896 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
8897
8898 #define TIM_CCMR1_CC2S_Pos        (8U)                                         
8899 #define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
8900 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
8901 #define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
8902 #define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
8903
8904 #define TIM_CCMR1_OC2FE_Pos       (10U)                                        
8905 #define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
8906 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
8907 #define TIM_CCMR1_OC2PE_Pos       (11U)                                        
8908 #define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
8909 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
8910
8911 #define TIM_CCMR1_OC2M_Pos        (12U)                                        
8912 #define TIM_CCMR1_OC2M_Msk        (0x7U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
8913 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
8914 #define TIM_CCMR1_OC2M_0          (0x1U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
8915 #define TIM_CCMR1_OC2M_1          (0x2U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
8916 #define TIM_CCMR1_OC2M_2          (0x4U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
8917
8918 #define TIM_CCMR1_OC2CE_Pos       (15U)                                        
8919 #define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
8920 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
8921
8922 /*---------------------------------------------------------------------------*/
8923
8924 #define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
8925 #define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
8926 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
8927 #define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
8928 #define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
8929
8930 #define TIM_CCMR1_IC1F_Pos        (4U)                                         
8931 #define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
8932 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
8933 #define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
8934 #define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
8935 #define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
8936 #define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
8937
8938 #define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
8939 #define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
8940 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
8941 #define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
8942 #define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
8943
8944 #define TIM_CCMR1_IC2F_Pos        (12U)                                        
8945 #define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
8946 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
8947 #define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
8948 #define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
8949 #define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
8950 #define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
8951
8952 /******************  Bit definition for TIM_CCMR2 register  ******************/
8953 #define TIM_CCMR2_CC3S_Pos        (0U)                                         
8954 #define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
8955 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
8956 #define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
8957 #define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
8958
8959 #define TIM_CCMR2_OC3FE_Pos       (2U)                                         
8960 #define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
8961 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
8962 #define TIM_CCMR2_OC3PE_Pos       (3U)                                         
8963 #define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
8964 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
8965
8966 #define TIM_CCMR2_OC3M_Pos        (4U)                                         
8967 #define TIM_CCMR2_OC3M_Msk        (0x7U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
8968 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
8969 #define TIM_CCMR2_OC3M_0          (0x1U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
8970 #define TIM_CCMR2_OC3M_1          (0x2U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
8971 #define TIM_CCMR2_OC3M_2          (0x4U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
8972
8973 #define TIM_CCMR2_OC3CE_Pos       (7U)                                         
8974 #define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
8975 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
8976
8977 #define TIM_CCMR2_CC4S_Pos        (8U)                                         
8978 #define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
8979 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
8980 #define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
8981 #define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
8982
8983 #define TIM_CCMR2_OC4FE_Pos       (10U)                                        
8984 #define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
8985 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
8986 #define TIM_CCMR2_OC4PE_Pos       (11U)                                        
8987 #define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
8988 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
8989
8990 #define TIM_CCMR2_OC4M_Pos        (12U)                                        
8991 #define TIM_CCMR2_OC4M_Msk        (0x7U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
8992 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
8993 #define TIM_CCMR2_OC4M_0          (0x1U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
8994 #define TIM_CCMR2_OC4M_1          (0x2U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
8995 #define TIM_CCMR2_OC4M_2          (0x4U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
8996
8997 #define TIM_CCMR2_OC4CE_Pos       (15U)                                        
8998 #define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
8999 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
9000
9001 /*---------------------------------------------------------------------------*/
9002
9003 #define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
9004 #define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
9005 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
9006 #define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
9007 #define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
9008
9009 #define TIM_CCMR2_IC3F_Pos        (4U)                                         
9010 #define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
9011 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
9012 #define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
9013 #define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
9014 #define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
9015 #define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
9016
9017 #define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
9018 #define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
9019 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
9020 #define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
9021 #define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
9022
9023 #define TIM_CCMR2_IC4F_Pos        (12U)                                        
9024 #define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
9025 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
9026 #define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
9027 #define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
9028 #define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
9029 #define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
9030
9031 /*******************  Bit definition for TIM_CCER register  ******************/
9032 #define TIM_CCER_CC1E_Pos         (0U)                                         
9033 #define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
9034 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
9035 #define TIM_CCER_CC1P_Pos         (1U)                                         
9036 #define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
9037 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
9038 #define TIM_CCER_CC1NE_Pos        (2U)                                         
9039 #define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
9040 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
9041 #define TIM_CCER_CC1NP_Pos        (3U)                                         
9042 #define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
9043 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
9044 #define TIM_CCER_CC2E_Pos         (4U)                                         
9045 #define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
9046 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
9047 #define TIM_CCER_CC2P_Pos         (5U)                                         
9048 #define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
9049 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
9050 #define TIM_CCER_CC2NE_Pos        (6U)                                         
9051 #define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
9052 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
9053 #define TIM_CCER_CC2NP_Pos        (7U)                                         
9054 #define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
9055 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
9056 #define TIM_CCER_CC3E_Pos         (8U)                                         
9057 #define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
9058 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
9059 #define TIM_CCER_CC3P_Pos         (9U)                                         
9060 #define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
9061 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
9062 #define TIM_CCER_CC3NE_Pos        (10U)                                        
9063 #define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
9064 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
9065 #define TIM_CCER_CC3NP_Pos        (11U)                                        
9066 #define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
9067 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
9068 #define TIM_CCER_CC4E_Pos         (12U)                                        
9069 #define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
9070 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
9071 #define TIM_CCER_CC4P_Pos         (13U)                                        
9072 #define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
9073 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
9074 #define TIM_CCER_CC4NP_Pos        (15U)                                        
9075 #define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
9076 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
9077
9078 /*******************  Bit definition for TIM_CNT register  *******************/
9079 #define TIM_CNT_CNT_Pos           (0U)                                         
9080 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
9081 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
9082
9083 /*******************  Bit definition for TIM_PSC register  *******************/
9084 #define TIM_PSC_PSC_Pos           (0U)                                         
9085 #define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
9086 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
9087
9088 /*******************  Bit definition for TIM_ARR register  *******************/
9089 #define TIM_ARR_ARR_Pos           (0U)                                         
9090 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
9091 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
9092
9093 /*******************  Bit definition for TIM_RCR register  *******************/
9094 #define TIM_RCR_REP_Pos           (0U)                                         
9095 #define TIM_RCR_REP_Msk           (0xFFU << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
9096 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
9097
9098 /*******************  Bit definition for TIM_CCR1 register  ******************/
9099 #define TIM_CCR1_CCR1_Pos         (0U)                                         
9100 #define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
9101 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
9102
9103 /*******************  Bit definition for TIM_CCR2 register  ******************/
9104 #define TIM_CCR2_CCR2_Pos         (0U)                                         
9105 #define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
9106 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
9107
9108 /*******************  Bit definition for TIM_CCR3 register  ******************/
9109 #define TIM_CCR3_CCR3_Pos         (0U)                                         
9110 #define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
9111 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
9112
9113 /*******************  Bit definition for TIM_CCR4 register  ******************/
9114 #define TIM_CCR4_CCR4_Pos         (0U)                                         
9115 #define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
9116 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
9117
9118 /*******************  Bit definition for TIM_BDTR register  ******************/
9119 #define TIM_BDTR_DTG_Pos          (0U)                                         
9120 #define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
9121 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
9122 #define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
9123 #define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
9124 #define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
9125 #define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
9126 #define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
9127 #define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
9128 #define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
9129 #define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
9130
9131 #define TIM_BDTR_LOCK_Pos         (8U)                                         
9132 #define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
9133 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
9134 #define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
9135 #define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
9136
9137 #define TIM_BDTR_OSSI_Pos         (10U)                                        
9138 #define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
9139 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
9140 #define TIM_BDTR_OSSR_Pos         (11U)                                        
9141 #define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
9142 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
9143 #define TIM_BDTR_BKE_Pos          (12U)                                        
9144 #define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
9145 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable */
9146 #define TIM_BDTR_BKP_Pos          (13U)                                        
9147 #define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
9148 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity */
9149 #define TIM_BDTR_AOE_Pos          (14U)                                        
9150 #define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
9151 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
9152 #define TIM_BDTR_MOE_Pos          (15U)                                        
9153 #define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
9154 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
9155
9156 /*******************  Bit definition for TIM_DCR register  *******************/
9157 #define TIM_DCR_DBA_Pos           (0U)                                         
9158 #define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
9159 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
9160 #define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
9161 #define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
9162 #define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
9163 #define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
9164 #define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
9165
9166 #define TIM_DCR_DBL_Pos           (8U)                                         
9167 #define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
9168 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
9169 #define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
9170 #define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
9171 #define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
9172 #define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
9173 #define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
9174
9175 /*******************  Bit definition for TIM_DMAR register  ******************/
9176 #define TIM_DMAR_DMAB_Pos         (0U)                                         
9177 #define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
9178 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
9179
9180 /*******************  Bit definition for TIM14_OR register  ********************/
9181 #define TIM14_OR_TI1_RMP_Pos      (0U)                                         
9182 #define TIM14_OR_TI1_RMP_Msk      (0x3U << TIM14_OR_TI1_RMP_Pos)               /*!< 0x00000003 */
9183 #define TIM14_OR_TI1_RMP          TIM14_OR_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
9184 #define TIM14_OR_TI1_RMP_0        (0x1U << TIM14_OR_TI1_RMP_Pos)               /*!< 0x00000001 */
9185 #define TIM14_OR_TI1_RMP_1        (0x2U << TIM14_OR_TI1_RMP_Pos)               /*!< 0x00000002 */
9186
9187 /******************************************************************************/
9188 /*                                                                            */
9189 /*                          Touch Sensing Controller (TSC)                    */
9190 /*                                                                            */
9191 /******************************************************************************/
9192 /*******************  Bit definition for TSC_CR register  *********************/
9193 #define TSC_CR_TSCE_Pos          (0U)                                          
9194 #define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
9195 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
9196 #define TSC_CR_START_Pos         (1U)                                          
9197 #define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
9198 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
9199 #define TSC_CR_AM_Pos            (2U)                                          
9200 #define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
9201 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
9202 #define TSC_CR_SYNCPOL_Pos       (3U)                                          
9203 #define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
9204 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
9205 #define TSC_CR_IODEF_Pos         (4U)                                          
9206 #define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
9207 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
9208
9209 #define TSC_CR_MCV_Pos           (5U)                                          
9210 #define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
9211 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
9212 #define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
9213 #define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
9214 #define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
9215
9216 #define TSC_CR_PGPSC_Pos         (12U)                                         
9217 #define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
9218 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
9219 #define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
9220 #define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
9221 #define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
9222
9223 #define TSC_CR_SSPSC_Pos         (15U)                                         
9224 #define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
9225 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
9226 #define TSC_CR_SSE_Pos           (16U)                                         
9227 #define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
9228 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
9229
9230 #define TSC_CR_SSD_Pos           (17U)                                         
9231 #define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
9232 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
9233 #define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
9234 #define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
9235 #define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
9236 #define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
9237 #define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
9238 #define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
9239 #define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
9240
9241 #define TSC_CR_CTPL_Pos          (24U)                                         
9242 #define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
9243 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
9244 #define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
9245 #define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
9246 #define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
9247 #define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
9248
9249 #define TSC_CR_CTPH_Pos          (28U)                                         
9250 #define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
9251 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
9252 #define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
9253 #define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
9254 #define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
9255 #define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
9256
9257 /*******************  Bit definition for TSC_IER register  ********************/
9258 #define TSC_IER_EOAIE_Pos        (0U)                                          
9259 #define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
9260 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
9261 #define TSC_IER_MCEIE_Pos        (1U)                                          
9262 #define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
9263 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
9264
9265 /*******************  Bit definition for TSC_ICR register  ********************/
9266 #define TSC_ICR_EOAIC_Pos        (0U)                                          
9267 #define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
9268 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
9269 #define TSC_ICR_MCEIC_Pos        (1U)                                          
9270 #define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
9271 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
9272
9273 /*******************  Bit definition for TSC_ISR register  ********************/
9274 #define TSC_ISR_EOAF_Pos         (0U)                                          
9275 #define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
9276 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
9277 #define TSC_ISR_MCEF_Pos         (1U)                                          
9278 #define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
9279 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
9280
9281 /*******************  Bit definition for TSC_IOHCR register  ******************/
9282 #define TSC_IOHCR_G1_IO1_Pos     (0U)                                          
9283 #define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
9284 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
9285 #define TSC_IOHCR_G1_IO2_Pos     (1U)                                          
9286 #define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
9287 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
9288 #define TSC_IOHCR_G1_IO3_Pos     (2U)                                          
9289 #define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
9290 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
9291 #define TSC_IOHCR_G1_IO4_Pos     (3U)                                          
9292 #define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
9293 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
9294 #define TSC_IOHCR_G2_IO1_Pos     (4U)                                          
9295 #define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
9296 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
9297 #define TSC_IOHCR_G2_IO2_Pos     (5U)                                          
9298 #define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
9299 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
9300 #define TSC_IOHCR_G2_IO3_Pos     (6U)                                          
9301 #define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
9302 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
9303 #define TSC_IOHCR_G2_IO4_Pos     (7U)                                          
9304 #define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
9305 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
9306 #define TSC_IOHCR_G3_IO1_Pos     (8U)                                          
9307 #define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
9308 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
9309 #define TSC_IOHCR_G3_IO2_Pos     (9U)                                          
9310 #define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
9311 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
9312 #define TSC_IOHCR_G3_IO3_Pos     (10U)                                         
9313 #define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
9314 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
9315 #define TSC_IOHCR_G3_IO4_Pos     (11U)                                         
9316 #define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
9317 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
9318 #define TSC_IOHCR_G4_IO1_Pos     (12U)                                         
9319 #define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
9320 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
9321 #define TSC_IOHCR_G4_IO2_Pos     (13U)                                         
9322 #define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
9323 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
9324 #define TSC_IOHCR_G4_IO3_Pos     (14U)                                         
9325 #define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
9326 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
9327 #define TSC_IOHCR_G4_IO4_Pos     (15U)                                         
9328 #define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
9329 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
9330 #define TSC_IOHCR_G5_IO1_Pos     (16U)                                         
9331 #define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
9332 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
9333 #define TSC_IOHCR_G5_IO2_Pos     (17U)                                         
9334 #define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
9335 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
9336 #define TSC_IOHCR_G5_IO3_Pos     (18U)                                         
9337 #define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
9338 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
9339 #define TSC_IOHCR_G5_IO4_Pos     (19U)                                         
9340 #define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
9341 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
9342 #define TSC_IOHCR_G6_IO1_Pos     (20U)                                         
9343 #define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
9344 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
9345 #define TSC_IOHCR_G6_IO2_Pos     (21U)                                         
9346 #define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
9347 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
9348 #define TSC_IOHCR_G6_IO3_Pos     (22U)                                         
9349 #define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
9350 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
9351 #define TSC_IOHCR_G6_IO4_Pos     (23U)                                         
9352 #define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
9353 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
9354 #define TSC_IOHCR_G7_IO1_Pos     (24U)                                         
9355 #define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
9356 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
9357 #define TSC_IOHCR_G7_IO2_Pos     (25U)                                         
9358 #define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
9359 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
9360 #define TSC_IOHCR_G7_IO3_Pos     (26U)                                         
9361 #define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
9362 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
9363 #define TSC_IOHCR_G7_IO4_Pos     (27U)                                         
9364 #define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
9365 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
9366 #define TSC_IOHCR_G8_IO1_Pos     (28U)                                         
9367 #define TSC_IOHCR_G8_IO1_Msk     (0x1U << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
9368 #define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
9369 #define TSC_IOHCR_G8_IO2_Pos     (29U)                                         
9370 #define TSC_IOHCR_G8_IO2_Msk     (0x1U << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
9371 #define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
9372 #define TSC_IOHCR_G8_IO3_Pos     (30U)                                         
9373 #define TSC_IOHCR_G8_IO3_Msk     (0x1U << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
9374 #define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
9375 #define TSC_IOHCR_G8_IO4_Pos     (31U)                                         
9376 #define TSC_IOHCR_G8_IO4_Msk     (0x1U << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
9377 #define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
9378
9379 /*******************  Bit definition for TSC_IOASCR register  *****************/
9380 #define TSC_IOASCR_G1_IO1_Pos    (0U)                                          
9381 #define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
9382 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
9383 #define TSC_IOASCR_G1_IO2_Pos    (1U)                                          
9384 #define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
9385 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
9386 #define TSC_IOASCR_G1_IO3_Pos    (2U)                                          
9387 #define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
9388 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
9389 #define TSC_IOASCR_G1_IO4_Pos    (3U)                                          
9390 #define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
9391 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
9392 #define TSC_IOASCR_G2_IO1_Pos    (4U)                                          
9393 #define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
9394 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
9395 #define TSC_IOASCR_G2_IO2_Pos    (5U)                                          
9396 #define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
9397 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
9398 #define TSC_IOASCR_G2_IO3_Pos    (6U)                                          
9399 #define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
9400 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
9401 #define TSC_IOASCR_G2_IO4_Pos    (7U)                                          
9402 #define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
9403 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
9404 #define TSC_IOASCR_G3_IO1_Pos    (8U)                                          
9405 #define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
9406 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
9407 #define TSC_IOASCR_G3_IO2_Pos    (9U)                                          
9408 #define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
9409 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
9410 #define TSC_IOASCR_G3_IO3_Pos    (10U)                                         
9411 #define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
9412 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
9413 #define TSC_IOASCR_G3_IO4_Pos    (11U)                                         
9414 #define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
9415 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
9416 #define TSC_IOASCR_G4_IO1_Pos    (12U)                                         
9417 #define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
9418 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
9419 #define TSC_IOASCR_G4_IO2_Pos    (13U)                                         
9420 #define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
9421 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
9422 #define TSC_IOASCR_G4_IO3_Pos    (14U)                                         
9423 #define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
9424 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
9425 #define TSC_IOASCR_G4_IO4_Pos    (15U)                                         
9426 #define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
9427 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
9428 #define TSC_IOASCR_G5_IO1_Pos    (16U)                                         
9429 #define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
9430 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
9431 #define TSC_IOASCR_G5_IO2_Pos    (17U)                                         
9432 #define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
9433 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
9434 #define TSC_IOASCR_G5_IO3_Pos    (18U)                                         
9435 #define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
9436 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
9437 #define TSC_IOASCR_G5_IO4_Pos    (19U)                                         
9438 #define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
9439 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
9440 #define TSC_IOASCR_G6_IO1_Pos    (20U)                                         
9441 #define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
9442 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
9443 #define TSC_IOASCR_G6_IO2_Pos    (21U)                                         
9444 #define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
9445 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
9446 #define TSC_IOASCR_G6_IO3_Pos    (22U)                                         
9447 #define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
9448 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
9449 #define TSC_IOASCR_G6_IO4_Pos    (23U)                                         
9450 #define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
9451 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
9452 #define TSC_IOASCR_G7_IO1_Pos    (24U)                                         
9453 #define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
9454 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
9455 #define TSC_IOASCR_G7_IO2_Pos    (25U)                                         
9456 #define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
9457 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
9458 #define TSC_IOASCR_G7_IO3_Pos    (26U)                                         
9459 #define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
9460 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
9461 #define TSC_IOASCR_G7_IO4_Pos    (27U)                                         
9462 #define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
9463 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
9464 #define TSC_IOASCR_G8_IO1_Pos    (28U)                                         
9465 #define TSC_IOASCR_G8_IO1_Msk    (0x1U << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
9466 #define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
9467 #define TSC_IOASCR_G8_IO2_Pos    (29U)                                         
9468 #define TSC_IOASCR_G8_IO2_Msk    (0x1U << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
9469 #define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
9470 #define TSC_IOASCR_G8_IO3_Pos    (30U)                                         
9471 #define TSC_IOASCR_G8_IO3_Msk    (0x1U << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
9472 #define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
9473 #define TSC_IOASCR_G8_IO4_Pos    (31U)                                         
9474 #define TSC_IOASCR_G8_IO4_Msk    (0x1U << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
9475 #define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
9476
9477 /*******************  Bit definition for TSC_IOSCR register  ******************/
9478 #define TSC_IOSCR_G1_IO1_Pos     (0U)                                          
9479 #define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
9480 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
9481 #define TSC_IOSCR_G1_IO2_Pos     (1U)                                          
9482 #define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
9483 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
9484 #define TSC_IOSCR_G1_IO3_Pos     (2U)                                          
9485 #define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
9486 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
9487 #define TSC_IOSCR_G1_IO4_Pos     (3U)                                          
9488 #define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
9489 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
9490 #define TSC_IOSCR_G2_IO1_Pos     (4U)                                          
9491 #define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
9492 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
9493 #define TSC_IOSCR_G2_IO2_Pos     (5U)                                          
9494 #define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
9495 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
9496 #define TSC_IOSCR_G2_IO3_Pos     (6U)                                          
9497 #define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
9498 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
9499 #define TSC_IOSCR_G2_IO4_Pos     (7U)                                          
9500 #define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
9501 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
9502 #define TSC_IOSCR_G3_IO1_Pos     (8U)                                          
9503 #define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
9504 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
9505 #define TSC_IOSCR_G3_IO2_Pos     (9U)                                          
9506 #define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
9507 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
9508 #define TSC_IOSCR_G3_IO3_Pos     (10U)                                         
9509 #define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
9510 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
9511 #define TSC_IOSCR_G3_IO4_Pos     (11U)                                         
9512 #define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
9513 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
9514 #define TSC_IOSCR_G4_IO1_Pos     (12U)                                         
9515 #define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
9516 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
9517 #define TSC_IOSCR_G4_IO2_Pos     (13U)                                         
9518 #define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
9519 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
9520 #define TSC_IOSCR_G4_IO3_Pos     (14U)                                         
9521 #define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
9522 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
9523 #define TSC_IOSCR_G4_IO4_Pos     (15U)                                         
9524 #define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
9525 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
9526 #define TSC_IOSCR_G5_IO1_Pos     (16U)                                         
9527 #define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
9528 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
9529 #define TSC_IOSCR_G5_IO2_Pos     (17U)                                         
9530 #define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
9531 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
9532 #define TSC_IOSCR_G5_IO3_Pos     (18U)                                         
9533 #define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
9534 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
9535 #define TSC_IOSCR_G5_IO4_Pos     (19U)                                         
9536 #define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
9537 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
9538 #define TSC_IOSCR_G6_IO1_Pos     (20U)                                         
9539 #define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
9540 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
9541 #define TSC_IOSCR_G6_IO2_Pos     (21U)                                         
9542 #define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
9543 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
9544 #define TSC_IOSCR_G6_IO3_Pos     (22U)                                         
9545 #define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
9546 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
9547 #define TSC_IOSCR_G6_IO4_Pos     (23U)                                         
9548 #define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
9549 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
9550 #define TSC_IOSCR_G7_IO1_Pos     (24U)                                         
9551 #define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
9552 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
9553 #define TSC_IOSCR_G7_IO2_Pos     (25U)                                         
9554 #define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
9555 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
9556 #define TSC_IOSCR_G7_IO3_Pos     (26U)                                         
9557 #define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
9558 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
9559 #define TSC_IOSCR_G7_IO4_Pos     (27U)                                         
9560 #define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
9561 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
9562 #define TSC_IOSCR_G8_IO1_Pos     (28U)                                         
9563 #define TSC_IOSCR_G8_IO1_Msk     (0x1U << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
9564 #define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
9565 #define TSC_IOSCR_G8_IO2_Pos     (29U)                                         
9566 #define TSC_IOSCR_G8_IO2_Msk     (0x1U << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
9567 #define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
9568 #define TSC_IOSCR_G8_IO3_Pos     (30U)                                         
9569 #define TSC_IOSCR_G8_IO3_Msk     (0x1U << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
9570 #define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
9571 #define TSC_IOSCR_G8_IO4_Pos     (31U)                                         
9572 #define TSC_IOSCR_G8_IO4_Msk     (0x1U << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
9573 #define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
9574
9575 /*******************  Bit definition for TSC_IOCCR register  ******************/
9576 #define TSC_IOCCR_G1_IO1_Pos     (0U)                                          
9577 #define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
9578 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
9579 #define TSC_IOCCR_G1_IO2_Pos     (1U)                                          
9580 #define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
9581 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
9582 #define TSC_IOCCR_G1_IO3_Pos     (2U)                                          
9583 #define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
9584 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
9585 #define TSC_IOCCR_G1_IO4_Pos     (3U)                                          
9586 #define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
9587 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
9588 #define TSC_IOCCR_G2_IO1_Pos     (4U)                                          
9589 #define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
9590 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
9591 #define TSC_IOCCR_G2_IO2_Pos     (5U)                                          
9592 #define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
9593 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
9594 #define TSC_IOCCR_G2_IO3_Pos     (6U)                                          
9595 #define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
9596 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
9597 #define TSC_IOCCR_G2_IO4_Pos     (7U)                                          
9598 #define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
9599 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
9600 #define TSC_IOCCR_G3_IO1_Pos     (8U)                                          
9601 #define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
9602 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
9603 #define TSC_IOCCR_G3_IO2_Pos     (9U)                                          
9604 #define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
9605 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
9606 #define TSC_IOCCR_G3_IO3_Pos     (10U)                                         
9607 #define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
9608 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
9609 #define TSC_IOCCR_G3_IO4_Pos     (11U)                                         
9610 #define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
9611 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
9612 #define TSC_IOCCR_G4_IO1_Pos     (12U)                                         
9613 #define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
9614 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
9615 #define TSC_IOCCR_G4_IO2_Pos     (13U)                                         
9616 #define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
9617 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
9618 #define TSC_IOCCR_G4_IO3_Pos     (14U)                                         
9619 #define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
9620 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
9621 #define TSC_IOCCR_G4_IO4_Pos     (15U)                                         
9622 #define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
9623 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
9624 #define TSC_IOCCR_G5_IO1_Pos     (16U)                                         
9625 #define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
9626 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
9627 #define TSC_IOCCR_G5_IO2_Pos     (17U)                                         
9628 #define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
9629 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
9630 #define TSC_IOCCR_G5_IO3_Pos     (18U)                                         
9631 #define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
9632 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
9633 #define TSC_IOCCR_G5_IO4_Pos     (19U)                                         
9634 #define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
9635 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
9636 #define TSC_IOCCR_G6_IO1_Pos     (20U)                                         
9637 #define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
9638 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
9639 #define TSC_IOCCR_G6_IO2_Pos     (21U)                                         
9640 #define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
9641 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
9642 #define TSC_IOCCR_G6_IO3_Pos     (22U)                                         
9643 #define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
9644 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
9645 #define TSC_IOCCR_G6_IO4_Pos     (23U)                                         
9646 #define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
9647 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
9648 #define TSC_IOCCR_G7_IO1_Pos     (24U)                                         
9649 #define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
9650 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
9651 #define TSC_IOCCR_G7_IO2_Pos     (25U)                                         
9652 #define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
9653 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
9654 #define TSC_IOCCR_G7_IO3_Pos     (26U)                                         
9655 #define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
9656 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
9657 #define TSC_IOCCR_G7_IO4_Pos     (27U)                                         
9658 #define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
9659 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
9660 #define TSC_IOCCR_G8_IO1_Pos     (28U)                                         
9661 #define TSC_IOCCR_G8_IO1_Msk     (0x1U << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
9662 #define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
9663 #define TSC_IOCCR_G8_IO2_Pos     (29U)                                         
9664 #define TSC_IOCCR_G8_IO2_Msk     (0x1U << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
9665 #define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
9666 #define TSC_IOCCR_G8_IO3_Pos     (30U)                                         
9667 #define TSC_IOCCR_G8_IO3_Msk     (0x1U << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
9668 #define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
9669 #define TSC_IOCCR_G8_IO4_Pos     (31U)                                         
9670 #define TSC_IOCCR_G8_IO4_Msk     (0x1U << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
9671 #define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
9672
9673 /*******************  Bit definition for TSC_IOGCSR register  *****************/
9674 #define TSC_IOGCSR_G1E_Pos       (0U)                                          
9675 #define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
9676 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
9677 #define TSC_IOGCSR_G2E_Pos       (1U)                                          
9678 #define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
9679 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
9680 #define TSC_IOGCSR_G3E_Pos       (2U)                                          
9681 #define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
9682 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
9683 #define TSC_IOGCSR_G4E_Pos       (3U)                                          
9684 #define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
9685 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
9686 #define TSC_IOGCSR_G5E_Pos       (4U)                                          
9687 #define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
9688 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
9689 #define TSC_IOGCSR_G6E_Pos       (5U)                                          
9690 #define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
9691 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
9692 #define TSC_IOGCSR_G7E_Pos       (6U)                                          
9693 #define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
9694 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
9695 #define TSC_IOGCSR_G8E_Pos       (7U)                                          
9696 #define TSC_IOGCSR_G8E_Msk       (0x1U << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
9697 #define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
9698 #define TSC_IOGCSR_G1S_Pos       (16U)                                         
9699 #define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
9700 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
9701 #define TSC_IOGCSR_G2S_Pos       (17U)                                         
9702 #define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
9703 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
9704 #define TSC_IOGCSR_G3S_Pos       (18U)                                         
9705 #define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
9706 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
9707 #define TSC_IOGCSR_G4S_Pos       (19U)                                         
9708 #define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
9709 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
9710 #define TSC_IOGCSR_G5S_Pos       (20U)                                         
9711 #define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
9712 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
9713 #define TSC_IOGCSR_G6S_Pos       (21U)                                         
9714 #define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
9715 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
9716 #define TSC_IOGCSR_G7S_Pos       (22U)                                         
9717 #define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
9718 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
9719 #define TSC_IOGCSR_G8S_Pos       (23U)                                         
9720 #define TSC_IOGCSR_G8S_Msk       (0x1U << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
9721 #define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
9722
9723 /*******************  Bit definition for TSC_IOGXCR register  *****************/
9724 #define TSC_IOGXCR_CNT_Pos       (0U)                                          
9725 #define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
9726 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
9727
9728 /******************************************************************************/
9729 /*                                                                            */
9730 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
9731 /*                                                                            */
9732 /******************************************************************************/
9733
9734 /*
9735 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
9736 */
9737
9738 /* Support of 7 bits data length feature */
9739 #define USART_7BITS_SUPPORT
9740
9741 /* Support of LIN feature */
9742 #define USART_LIN_SUPPORT
9743
9744 /* Support of Smartcard feature */
9745 #define USART_SMARTCARD_SUPPORT
9746
9747 /* Support of Irda feature */
9748 #define USART_IRDA_SUPPORT
9749
9750 /* Support of Wake Up from Stop Mode feature */
9751 #define USART_WUSM_SUPPORT
9752
9753 /* Support of Full Auto Baud rate feature (4 modes) activation */
9754 #define USART_FABR_SUPPORT
9755
9756 /******************  Bit definition for USART_CR1 register  *******************/
9757 #define USART_CR1_UE_Pos              (0U)                                     
9758 #define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
9759 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
9760 #define USART_CR1_UESM_Pos            (1U)                                     
9761 #define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
9762 #define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
9763 #define USART_CR1_RE_Pos              (2U)                                     
9764 #define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
9765 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
9766 #define USART_CR1_TE_Pos              (3U)                                     
9767 #define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
9768 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
9769 #define USART_CR1_IDLEIE_Pos          (4U)                                     
9770 #define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
9771 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
9772 #define USART_CR1_RXNEIE_Pos          (5U)                                     
9773 #define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
9774 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
9775 #define USART_CR1_TCIE_Pos            (6U)                                     
9776 #define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
9777 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
9778 #define USART_CR1_TXEIE_Pos           (7U)                                     
9779 #define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
9780 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
9781 #define USART_CR1_PEIE_Pos            (8U)                                     
9782 #define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
9783 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
9784 #define USART_CR1_PS_Pos              (9U)                                     
9785 #define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
9786 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
9787 #define USART_CR1_PCE_Pos             (10U)                                    
9788 #define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
9789 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
9790 #define USART_CR1_WAKE_Pos            (11U)                                    
9791 #define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
9792 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
9793 #define USART_CR1_M0_Pos              (12U)                                    
9794 #define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
9795 #define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length bit 0 */
9796 #define USART_CR1_MME_Pos             (13U)                                    
9797 #define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
9798 #define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
9799 #define USART_CR1_CMIE_Pos            (14U)                                    
9800 #define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
9801 #define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
9802 #define USART_CR1_OVER8_Pos           (15U)                                    
9803 #define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
9804 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
9805 #define USART_CR1_DEDT_Pos            (16U)                                    
9806 #define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
9807 #define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
9808 #define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
9809 #define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
9810 #define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
9811 #define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
9812 #define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
9813 #define USART_CR1_DEAT_Pos            (21U)                                    
9814 #define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
9815 #define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
9816 #define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
9817 #define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
9818 #define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
9819 #define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
9820 #define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
9821 #define USART_CR1_RTOIE_Pos           (26U)                                    
9822 #define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
9823 #define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
9824 #define USART_CR1_EOBIE_Pos           (27U)                                    
9825 #define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
9826 #define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
9827 #define USART_CR1_M1_Pos              (28U)                                    
9828 #define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
9829 #define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length bit 1 */
9830 #define USART_CR1_M_Pos               (12U)                                    
9831 #define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
9832 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!< [M1:M0] Word length */
9833
9834 /******************  Bit definition for USART_CR2 register  *******************/
9835 #define USART_CR2_ADDM7_Pos           (4U)                                     
9836 #define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
9837 #define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
9838 #define USART_CR2_LBDL_Pos            (5U)                                     
9839 #define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
9840 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
9841 #define USART_CR2_LBDIE_Pos           (6U)                                     
9842 #define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
9843 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
9844 #define USART_CR2_LBCL_Pos            (8U)                                     
9845 #define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
9846 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
9847 #define USART_CR2_CPHA_Pos            (9U)                                     
9848 #define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
9849 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
9850 #define USART_CR2_CPOL_Pos            (10U)                                    
9851 #define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
9852 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
9853 #define USART_CR2_CLKEN_Pos           (11U)                                    
9854 #define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
9855 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
9856 #define USART_CR2_STOP_Pos            (12U)                                    
9857 #define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
9858 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
9859 #define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
9860 #define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
9861 #define USART_CR2_LINEN_Pos           (14U)                                    
9862 #define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
9863 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
9864 #define USART_CR2_SWAP_Pos            (15U)                                    
9865 #define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
9866 #define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
9867 #define USART_CR2_RXINV_Pos           (16U)                                    
9868 #define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
9869 #define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
9870 #define USART_CR2_TXINV_Pos           (17U)                                    
9871 #define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
9872 #define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
9873 #define USART_CR2_DATAINV_Pos         (18U)                                    
9874 #define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
9875 #define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
9876 #define USART_CR2_MSBFIRST_Pos        (19U)                                    
9877 #define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
9878 #define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
9879 #define USART_CR2_ABREN_Pos           (20U)                                    
9880 #define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
9881 #define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
9882 #define USART_CR2_ABRMODE_Pos         (21U)                                    
9883 #define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
9884 #define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
9885 #define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
9886 #define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
9887 #define USART_CR2_RTOEN_Pos           (23U)                                    
9888 #define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
9889 #define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
9890 #define USART_CR2_ADD_Pos             (24U)                                    
9891 #define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
9892 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
9893
9894 /******************  Bit definition for USART_CR3 register  *******************/
9895 #define USART_CR3_EIE_Pos             (0U)                                     
9896 #define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
9897 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
9898 #define USART_CR3_IREN_Pos            (1U)                                     
9899 #define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
9900 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
9901 #define USART_CR3_IRLP_Pos            (2U)                                     
9902 #define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
9903 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
9904 #define USART_CR3_HDSEL_Pos           (3U)                                     
9905 #define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
9906 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
9907 #define USART_CR3_NACK_Pos            (4U)                                     
9908 #define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
9909 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
9910 #define USART_CR3_SCEN_Pos            (5U)                                     
9911 #define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
9912 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
9913 #define USART_CR3_DMAR_Pos            (6U)                                     
9914 #define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
9915 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
9916 #define USART_CR3_DMAT_Pos            (7U)                                     
9917 #define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
9918 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
9919 #define USART_CR3_RTSE_Pos            (8U)                                     
9920 #define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
9921 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
9922 #define USART_CR3_CTSE_Pos            (9U)                                     
9923 #define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
9924 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
9925 #define USART_CR3_CTSIE_Pos           (10U)                                    
9926 #define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
9927 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
9928 #define USART_CR3_ONEBIT_Pos          (11U)                                    
9929 #define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
9930 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
9931 #define USART_CR3_OVRDIS_Pos          (12U)                                    
9932 #define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
9933 #define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
9934 #define USART_CR3_DDRE_Pos            (13U)                                    
9935 #define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
9936 #define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
9937 #define USART_CR3_DEM_Pos             (14U)                                    
9938 #define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
9939 #define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
9940 #define USART_CR3_DEP_Pos             (15U)                                    
9941 #define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
9942 #define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
9943 #define USART_CR3_SCARCNT_Pos         (17U)                                    
9944 #define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
9945 #define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
9946 #define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
9947 #define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
9948 #define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
9949 #define USART_CR3_WUS_Pos             (20U)                                    
9950 #define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
9951 #define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
9952 #define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
9953 #define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
9954 #define USART_CR3_WUFIE_Pos           (22U)                                    
9955 #define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
9956 #define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
9957
9958 /******************  Bit definition for USART_BRR register  *******************/
9959 #define USART_BRR_DIV_FRACTION_Pos    (0U)                                     
9960 #define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
9961 #define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
9962 #define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     
9963 #define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
9964 #define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
9965
9966 /******************  Bit definition for USART_GTPR register  ******************/
9967 #define USART_GTPR_PSC_Pos            (0U)                                     
9968 #define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
9969 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
9970 #define USART_GTPR_GT_Pos             (8U)                                     
9971 #define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
9972 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
9973
9974
9975 /*******************  Bit definition for USART_RTOR register  *****************/
9976 #define USART_RTOR_RTO_Pos            (0U)                                     
9977 #define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
9978 #define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
9979 #define USART_RTOR_BLEN_Pos           (24U)                                    
9980 #define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
9981 #define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
9982
9983 /*******************  Bit definition for USART_RQR register  ******************/
9984 #define USART_RQR_ABRRQ_Pos           (0U)                                     
9985 #define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
9986 #define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
9987 #define USART_RQR_SBKRQ_Pos           (1U)                                     
9988 #define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
9989 #define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
9990 #define USART_RQR_MMRQ_Pos            (2U)                                     
9991 #define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
9992 #define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
9993 #define USART_RQR_RXFRQ_Pos           (3U)                                     
9994 #define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
9995 #define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
9996 #define USART_RQR_TXFRQ_Pos           (4U)                                     
9997 #define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
9998 #define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
9999
10000 /*******************  Bit definition for USART_ISR register  ******************/
10001 #define USART_ISR_PE_Pos              (0U)                                     
10002 #define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
10003 #define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
10004 #define USART_ISR_FE_Pos              (1U)                                     
10005 #define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
10006 #define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
10007 #define USART_ISR_NE_Pos              (2U)                                     
10008 #define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
10009 #define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
10010 #define USART_ISR_ORE_Pos             (3U)                                     
10011 #define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
10012 #define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
10013 #define USART_ISR_IDLE_Pos            (4U)                                     
10014 #define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
10015 #define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
10016 #define USART_ISR_RXNE_Pos            (5U)                                     
10017 #define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
10018 #define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
10019 #define USART_ISR_TC_Pos              (6U)                                     
10020 #define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
10021 #define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
10022 #define USART_ISR_TXE_Pos             (7U)                                     
10023 #define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
10024 #define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
10025 #define USART_ISR_LBDF_Pos            (8U)                                     
10026 #define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
10027 #define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
10028 #define USART_ISR_CTSIF_Pos           (9U)                                     
10029 #define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
10030 #define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
10031 #define USART_ISR_CTS_Pos             (10U)                                    
10032 #define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
10033 #define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
10034 #define USART_ISR_RTOF_Pos            (11U)                                    
10035 #define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
10036 #define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
10037 #define USART_ISR_EOBF_Pos            (12U)                                    
10038 #define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
10039 #define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
10040 #define USART_ISR_ABRE_Pos            (14U)                                    
10041 #define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
10042 #define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
10043 #define USART_ISR_ABRF_Pos            (15U)                                    
10044 #define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
10045 #define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
10046 #define USART_ISR_BUSY_Pos            (16U)                                    
10047 #define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
10048 #define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
10049 #define USART_ISR_CMF_Pos             (17U)                                    
10050 #define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
10051 #define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
10052 #define USART_ISR_SBKF_Pos            (18U)                                    
10053 #define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
10054 #define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
10055 #define USART_ISR_RWU_Pos             (19U)                                    
10056 #define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
10057 #define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
10058 #define USART_ISR_WUF_Pos             (20U)                                    
10059 #define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
10060 #define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
10061 #define USART_ISR_TEACK_Pos           (21U)                                    
10062 #define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
10063 #define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
10064 #define USART_ISR_REACK_Pos           (22U)                                    
10065 #define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
10066 #define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
10067
10068 /*******************  Bit definition for USART_ICR register  ******************/
10069 #define USART_ICR_PECF_Pos            (0U)                                     
10070 #define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
10071 #define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
10072 #define USART_ICR_FECF_Pos            (1U)                                     
10073 #define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
10074 #define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
10075 #define USART_ICR_NCF_Pos             (2U)                                     
10076 #define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
10077 #define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
10078 #define USART_ICR_ORECF_Pos           (3U)                                     
10079 #define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
10080 #define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
10081 #define USART_ICR_IDLECF_Pos          (4U)                                     
10082 #define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
10083 #define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
10084 #define USART_ICR_TCCF_Pos            (6U)                                     
10085 #define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
10086 #define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
10087 #define USART_ICR_LBDCF_Pos           (8U)                                     
10088 #define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
10089 #define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
10090 #define USART_ICR_CTSCF_Pos           (9U)                                     
10091 #define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
10092 #define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
10093 #define USART_ICR_RTOCF_Pos           (11U)                                    
10094 #define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
10095 #define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
10096 #define USART_ICR_EOBCF_Pos           (12U)                                    
10097 #define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
10098 #define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
10099 #define USART_ICR_CMCF_Pos            (17U)                                    
10100 #define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
10101 #define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
10102 #define USART_ICR_WUCF_Pos            (20U)                                    
10103 #define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
10104 #define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
10105
10106 /*******************  Bit definition for USART_RDR register  ******************/
10107 #define USART_RDR_RDR                 ((uint16_t)0x01FFU)                      /*!< RDR[8:0] bits (Receive Data value) */
10108
10109 /*******************  Bit definition for USART_TDR register  ******************/
10110 #define USART_TDR_TDR                 ((uint16_t)0x01FFU)                      /*!< TDR[8:0] bits (Transmit Data value) */
10111
10112 /******************************************************************************/
10113 /*                                                                            */
10114 /*                         USB Device General registers                       */
10115 /*                                                                            */
10116 /******************************************************************************/
10117 #define USB_CNTR                             (USB_BASE + 0x40)             /*!< Control register */
10118 #define USB_ISTR                             (USB_BASE + 0x44)             /*!< Interrupt status register */
10119 #define USB_FNR                              (USB_BASE + 0x48)             /*!< Frame number register */
10120 #define USB_DADDR                            (USB_BASE + 0x4C)             /*!< Device address register */
10121 #define USB_BTABLE                           (USB_BASE + 0x50)             /*!< Buffer Table address register */
10122 #define USB_LPMCSR                           (USB_BASE + 0x54)             /*!< LPM Control and Status register */
10123 #define USB_BCDR                             (USB_BASE + 0x58)             /*!< Battery Charging detector register*/
10124
10125 /****************************  ISTR interrupt events  *************************/
10126 #define USB_ISTR_CTR                         ((uint16_t)0x8000U)               /*!< Correct TRansfer (clear-only bit) */
10127 #define USB_ISTR_PMAOVR                      ((uint16_t)0x4000U)               /*!< DMA OVeR/underrun (clear-only bit) */
10128 #define USB_ISTR_ERR                         ((uint16_t)0x2000U)               /*!< ERRor (clear-only bit) */
10129 #define USB_ISTR_WKUP                        ((uint16_t)0x1000U)               /*!< WaKe UP (clear-only bit) */
10130 #define USB_ISTR_SUSP                        ((uint16_t)0x0800U)               /*!< SUSPend (clear-only bit) */
10131 #define USB_ISTR_RESET                       ((uint16_t)0x0400U)               /*!< RESET (clear-only bit) */
10132 #define USB_ISTR_SOF                         ((uint16_t)0x0200U)               /*!< Start Of Frame (clear-only bit) */
10133 #define USB_ISTR_ESOF                        ((uint16_t)0x0100U)               /*!< Expected Start Of Frame (clear-only bit) */
10134 #define USB_ISTR_L1REQ                       ((uint16_t)0x0080U)               /*!< LPM L1 state request  */
10135 #define USB_ISTR_DIR                         ((uint16_t)0x0010U)               /*!< DIRection of transaction (read-only bit)  */
10136 #define USB_ISTR_EP_ID                       ((uint16_t)0x000FU)               /*!< EndPoint IDentifier (read-only bit)  */
10137
10138 #define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
10139 #define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
10140 #define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
10141 #define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
10142 #define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
10143 #define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
10144 #define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
10145 #define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
10146 #define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
10147
10148 /*************************  CNTR control register bits definitions  ***********/
10149 #define USB_CNTR_CTRM                        ((uint16_t)0x8000U)               /*!< Correct TRansfer Mask */
10150 #define USB_CNTR_PMAOVRM                     ((uint16_t)0x4000U)               /*!< DMA OVeR/underrun Mask */
10151 #define USB_CNTR_ERRM                        ((uint16_t)0x2000U)               /*!< ERRor Mask */
10152 #define USB_CNTR_WKUPM                       ((uint16_t)0x1000U)               /*!< WaKe UP Mask */
10153 #define USB_CNTR_SUSPM                       ((uint16_t)0x0800U)               /*!< SUSPend Mask */
10154 #define USB_CNTR_RESETM                      ((uint16_t)0x0400U)               /*!< RESET Mask   */
10155 #define USB_CNTR_SOFM                        ((uint16_t)0x0200U)               /*!< Start Of Frame Mask */
10156 #define USB_CNTR_ESOFM                       ((uint16_t)0x0100U)               /*!< Expected Start Of Frame Mask */
10157 #define USB_CNTR_L1REQM                      ((uint16_t)0x0080U)               /*!< LPM L1 state request interrupt mask */
10158 #define USB_CNTR_L1RESUME                    ((uint16_t)0x0020U)               /*!< LPM L1 Resume request */
10159 #define USB_CNTR_RESUME                      ((uint16_t)0x0010U)               /*!< RESUME request */
10160 #define USB_CNTR_FSUSP                       ((uint16_t)0x0008U)               /*!< Force SUSPend */
10161 #define USB_CNTR_LPMODE                      ((uint16_t)0x0004U)               /*!< Low-power MODE */
10162 #define USB_CNTR_PDWN                        ((uint16_t)0x0002U)               /*!< Power DoWN */
10163 #define USB_CNTR_FRES                        ((uint16_t)0x0001U)               /*!< Force USB RESet */
10164
10165 /*************************  BCDR control register bits definitions  ***********/
10166 #define USB_BCDR_DPPU                        ((uint16_t)0x8000U)               /*!< DP Pull-up Enable */  
10167 #define USB_BCDR_PS2DET                      ((uint16_t)0x0080U)               /*!< PS2 port or proprietary charger detected */  
10168 #define USB_BCDR_SDET                        ((uint16_t)0x0040U)               /*!< Secondary detection (SD) status */  
10169 #define USB_BCDR_PDET                        ((uint16_t)0x0020U)               /*!< Primary detection (PD) status */ 
10170 #define USB_BCDR_DCDET                       ((uint16_t)0x0010U)               /*!< Data contact detection (DCD) status */ 
10171 #define USB_BCDR_SDEN                        ((uint16_t)0x0008U)               /*!< Secondary detection (SD) mode enable */ 
10172 #define USB_BCDR_PDEN                        ((uint16_t)0x0004U)               /*!< Primary detection (PD) mode enable */  
10173 #define USB_BCDR_DCDEN                       ((uint16_t)0x0002U)               /*!< Data contact detection (DCD) mode enable */
10174 #define USB_BCDR_BCDEN                       ((uint16_t)0x0001U)               /*!< Battery charging detector (BCD) enable */
10175
10176 /***************************  LPM register bits definitions  ******************/
10177 #define USB_LPMCSR_BESL                      ((uint16_t)0x00F0U)               /*!< BESL value received with last ACKed LPM Token  */ 
10178 #define USB_LPMCSR_REMWAKE                   ((uint16_t)0x0008U)               /*!< bRemoteWake value received with last ACKed LPM Token */ 
10179 #define USB_LPMCSR_LPMACK                    ((uint16_t)0x0002U)               /*!< LPM Token acknowledge enable*/
10180 #define USB_LPMCSR_LMPEN                     ((uint16_t)0x0001U)               /*!< LPM support enable  */
10181
10182 /********************  FNR Frame Number Register bit definitions   ************/
10183 #define USB_FNR_RXDP                         ((uint16_t)0x8000U)               /*!< status of D+ data line */
10184 #define USB_FNR_RXDM                         ((uint16_t)0x4000U)               /*!< status of D- data line */
10185 #define USB_FNR_LCK                          ((uint16_t)0x2000U)               /*!< LoCKed */
10186 #define USB_FNR_LSOF                         ((uint16_t)0x1800U)               /*!< Lost SOF */
10187 #define USB_FNR_FN                           ((uint16_t)0x07FFU)               /*!< Frame Number */
10188
10189 /********************  DADDR Device ADDRess bit definitions    ****************/
10190 #define USB_DADDR_EF                         ((uint8_t)0x80U)                  /*!< USB device address Enable Function */
10191 #define USB_DADDR_ADD                        ((uint8_t)0x7FU)                  /*!< USB device address */
10192
10193 /******************************  Endpoint register    *************************/
10194 #define USB_EP0R                             USB_BASE                   /*!< endpoint 0 register address */
10195 #define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
10196 #define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
10197 #define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
10198 #define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
10199 #define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
10200 #define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
10201 #define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
10202 /* bit positions */ 
10203 #define USB_EP_CTR_RX                        ((uint16_t)0x8000U)               /*!<  EndPoint Correct TRansfer RX */
10204 #define USB_EP_DTOG_RX                       ((uint16_t)0x4000U)               /*!<  EndPoint Data TOGGLE RX */
10205 #define USB_EPRX_STAT                        ((uint16_t)0x3000U)               /*!<  EndPoint RX STATus bit field */
10206 #define USB_EP_SETUP                         ((uint16_t)0x0800U)               /*!<  EndPoint SETUP */
10207 #define USB_EP_T_FIELD                       ((uint16_t)0x0600U)               /*!<  EndPoint TYPE */
10208 #define USB_EP_KIND                          ((uint16_t)0x0100U)               /*!<  EndPoint KIND */
10209 #define USB_EP_CTR_TX                        ((uint16_t)0x0080U)               /*!<  EndPoint Correct TRansfer TX */
10210 #define USB_EP_DTOG_TX                       ((uint16_t)0x0040U)               /*!<  EndPoint Data TOGGLE TX */
10211 #define USB_EPTX_STAT                        ((uint16_t)0x0030U)               /*!<  EndPoint TX STATus bit field */
10212 #define USB_EPADDR_FIELD                     ((uint16_t)0x000FU)               /*!<  EndPoint ADDRess FIELD */
10213
10214 /* EndPoint REGister MASK (no toggle fields) */
10215 #define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
10216                                                                                /*!< EP_TYPE[1:0] EndPoint TYPE */
10217 #define USB_EP_TYPE_MASK                     ((uint16_t)0x0600U)               /*!< EndPoint TYPE Mask */
10218 #define USB_EP_BULK                          ((uint16_t)0x0000U)               /*!< EndPoint BULK */
10219 #define USB_EP_CONTROL                       ((uint16_t)0x0200U)               /*!< EndPoint CONTROL */
10220 #define USB_EP_ISOCHRONOUS                   ((uint16_t)0x0400U)               /*!< EndPoint ISOCHRONOUS */
10221 #define USB_EP_INTERRUPT                     ((uint16_t)0x0600U)               /*!< EndPoint INTERRUPT */
10222 #define USB_EP_T_MASK                        (((uint16_t)(~USB_EP_T_FIELD)) & USB_EPREG_MASK)
10223                                                                  
10224 #define USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
10225                                                                                /*!< STAT_TX[1:0] STATus for TX transfer */
10226 #define USB_EP_TX_DIS                        ((uint16_t)0x0000U)               /*!< EndPoint TX DISabled */
10227 #define USB_EP_TX_STALL                      ((uint16_t)0x0010U)               /*!< EndPoint TX STALLed */
10228 #define USB_EP_TX_NAK                        ((uint16_t)0x0020U)               /*!< EndPoint TX NAKed */
10229 #define USB_EP_TX_VALID                      ((uint16_t)0x0030U)               /*!< EndPoint TX VALID */
10230 #define USB_EPTX_DTOG1                       ((uint16_t)0x0010U)               /*!< EndPoint TX Data TOGgle bit1 */
10231 #define USB_EPTX_DTOG2                       ((uint16_t)0x0020U)               /*!< EndPoint TX Data TOGgle bit2 */
10232 #define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
10233                                                                                /*!< STAT_RX[1:0] STATus for RX transfer */
10234 #define USB_EP_RX_DIS                        ((uint16_t)0x0000U)               /*!< EndPoint RX DISabled */
10235 #define USB_EP_RX_STALL                      ((uint16_t)0x1000U)               /*!< EndPoint RX STALLed */
10236 #define USB_EP_RX_NAK                        ((uint16_t)0x2000U)               /*!< EndPoint RX NAKed */
10237 #define USB_EP_RX_VALID                      ((uint16_t)0x3000U)               /*!< EndPoint RX VALID */
10238 #define USB_EPRX_DTOG1                       ((uint16_t)0x1000U)               /*!< EndPoint RX Data TOGgle bit1 */
10239 #define USB_EPRX_DTOG2                       ((uint16_t)0x2000U)               /*!< EndPoint RX Data TOGgle bit1 */
10240 #define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
10241
10242 /******************************************************************************/
10243 /*                                                                            */
10244 /*                         Window WATCHDOG (WWDG)                             */
10245 /*                                                                            */
10246 /******************************************************************************/
10247
10248 /*******************  Bit definition for WWDG_CR register  ********************/
10249 #define WWDG_CR_T_Pos           (0U)                                           
10250 #define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
10251 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
10252 #define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
10253 #define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
10254 #define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
10255 #define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
10256 #define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
10257 #define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
10258 #define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
10259
10260 /* Legacy defines */
10261 #define  WWDG_CR_T0 WWDG_CR_T_0
10262 #define  WWDG_CR_T1 WWDG_CR_T_1
10263 #define  WWDG_CR_T2 WWDG_CR_T_2
10264 #define  WWDG_CR_T3 WWDG_CR_T_3
10265 #define  WWDG_CR_T4 WWDG_CR_T_4
10266 #define  WWDG_CR_T5 WWDG_CR_T_5
10267 #define  WWDG_CR_T6 WWDG_CR_T_6
10268
10269 #define WWDG_CR_WDGA_Pos        (7U)                                           
10270 #define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
10271 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
10272
10273 /*******************  Bit definition for WWDG_CFR register  *******************/
10274 #define WWDG_CFR_W_Pos          (0U)                                           
10275 #define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
10276 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
10277 #define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
10278 #define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
10279 #define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
10280 #define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
10281 #define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
10282 #define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
10283 #define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
10284
10285 /* Legacy defines */
10286 #define  WWDG_CFR_W0 WWDG_CFR_W_0
10287 #define  WWDG_CFR_W1 WWDG_CFR_W_1
10288 #define  WWDG_CFR_W2 WWDG_CFR_W_2
10289 #define  WWDG_CFR_W3 WWDG_CFR_W_3
10290 #define  WWDG_CFR_W4 WWDG_CFR_W_4
10291 #define  WWDG_CFR_W5 WWDG_CFR_W_5
10292 #define  WWDG_CFR_W6 WWDG_CFR_W_6
10293
10294 #define WWDG_CFR_WDGTB_Pos      (7U)                                           
10295 #define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
10296 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
10297 #define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
10298 #define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
10299
10300 /* Legacy defines */
10301 #define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
10302 #define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
10303
10304 #define WWDG_CFR_EWI_Pos        (9U)                                           
10305 #define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
10306 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
10307
10308 /*******************  Bit definition for WWDG_SR register  ********************/
10309 #define WWDG_SR_EWIF_Pos        (0U)                                           
10310 #define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
10311 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
10312
10313 /**
10314   * @}
10315   */
10316
10317  /**
10318   * @}
10319   */
10320
10321
10322 /** @addtogroup Exported_macro
10323   * @{
10324   */
10325
10326 /****************************** ADC Instances *********************************/
10327 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
10328
10329 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
10330
10331 /******************************* CAN Instances ********************************/
10332 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
10333
10334 /****************************** CEC Instances *********************************/
10335 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
10336
10337 /****************************** CRC Instances *********************************/
10338 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
10339                                       
10340 /******************************* DMA Instances ********************************/
10341 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
10342                                        ((INSTANCE) == DMA1_Channel2) || \
10343                                        ((INSTANCE) == DMA1_Channel3) || \
10344                                        ((INSTANCE) == DMA1_Channel4) || \
10345                                        ((INSTANCE) == DMA1_Channel5))
10346
10347 /****************************** GPIO Instances ********************************/
10348 #define IS_GPIO_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
10349                                          ((INSTANCE) == GPIOB) || \
10350                                          ((INSTANCE) == GPIOC) || \
10351                                          ((INSTANCE) == GPIOF))
10352                                          
10353 /**************************** GPIO Alternate Function Instances ***************/
10354 #define IS_GPIO_AF_INSTANCE(INSTANCE)   (((INSTANCE) == GPIOA) || \
10355                                          ((INSTANCE) == GPIOB) || \
10356                                          ((INSTANCE) == GPIOF))
10357
10358 /****************************** GPIO Lock Instances ***************************/
10359 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
10360                                          ((INSTANCE) == GPIOB))
10361
10362 /****************************** I2C Instances *********************************/
10363 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
10364
10365 /****************** I2C Instances : wakeup capability from stop modes *********/
10366 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
10367
10368 /****************************** I2S Instances *********************************/
10369 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
10370
10371 /****************************** IWDG Instances ********************************/
10372 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
10373
10374 /****************************** RTC Instances *********************************/
10375 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
10376
10377 /****************************** SMBUS Instances *********************************/
10378 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
10379
10380 /****************************** SPI Instances *********************************/
10381 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
10382                                        ((INSTANCE) == SPI2))
10383
10384 /****************************** TIM Instances *********************************/
10385 #define IS_TIM_INSTANCE(INSTANCE)\
10386   (((INSTANCE) == TIM1)    || \
10387    ((INSTANCE) == TIM2)    || \
10388    ((INSTANCE) == TIM3)    || \
10389    ((INSTANCE) == TIM14)   || \
10390    ((INSTANCE) == TIM16)   || \
10391    ((INSTANCE) == TIM17))
10392
10393 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
10394   (((INSTANCE) == TIM1)    || \
10395    ((INSTANCE) == TIM2)    || \
10396    ((INSTANCE) == TIM3)    || \
10397    ((INSTANCE) == TIM14)   || \
10398    ((INSTANCE) == TIM16)   || \
10399    ((INSTANCE) == TIM17))
10400
10401 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
10402   (((INSTANCE) == TIM1)    || \
10403    ((INSTANCE) == TIM2)    || \
10404    ((INSTANCE) == TIM3))
10405
10406 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
10407   (((INSTANCE) == TIM1)    || \
10408    ((INSTANCE) == TIM2)    || \
10409    ((INSTANCE) == TIM3))
10410
10411 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
10412   (((INSTANCE) == TIM1)    || \
10413    ((INSTANCE) == TIM2)    || \
10414    ((INSTANCE) == TIM3))
10415
10416 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
10417   (((INSTANCE) == TIM1))
10418
10419 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
10420   (((INSTANCE) == TIM1))
10421
10422 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
10423   (((INSTANCE) == TIM1)    || \
10424    ((INSTANCE) == TIM2)    || \
10425    ((INSTANCE) == TIM3))
10426    
10427
10428 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
10429   (((INSTANCE) == TIM1)    || \
10430    ((INSTANCE) == TIM2)    || \
10431    ((INSTANCE) == TIM3))
10432
10433 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
10434   (((INSTANCE) == TIM1)    || \
10435    ((INSTANCE) == TIM2)    || \
10436    ((INSTANCE) == TIM3))
10437
10438 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
10439   (((INSTANCE) == TIM1)    || \
10440    ((INSTANCE) == TIM2)    || \
10441    ((INSTANCE) == TIM3))
10442
10443 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
10444   (((INSTANCE) == TIM1)    || \
10445    ((INSTANCE) == TIM2)    || \
10446    ((INSTANCE) == TIM3))
10447
10448 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
10449   (((INSTANCE) == TIM1)    || \
10450    ((INSTANCE) == TIM2)    || \
10451    ((INSTANCE) == TIM3))
10452
10453 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
10454   (((INSTANCE) == TIM1)    || \
10455    ((INSTANCE) == TIM2)    || \
10456    ((INSTANCE) == TIM3))
10457
10458 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
10459   (((INSTANCE) == TIM1))
10460
10461 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
10462   (((INSTANCE) == TIM1))
10463
10464 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
10465   (((INSTANCE) == TIM1)    || \
10466    ((INSTANCE) == TIM2)    || \
10467    ((INSTANCE) == TIM3))
10468
10469 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
10470   (((INSTANCE) == TIM1)    || \
10471    ((INSTANCE) == TIM2)    || \
10472    ((INSTANCE) == TIM3))
10473
10474 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
10475   (((INSTANCE) == TIM1)    || \
10476    ((INSTANCE) == TIM2)    || \
10477    ((INSTANCE) == TIM3))
10478
10479 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
10480     (((INSTANCE) == TIM1)    || \
10481      ((INSTANCE) == TIM2)    || \
10482      ((INSTANCE) == TIM3))
10483
10484 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
10485     ((INSTANCE) == TIM2)
10486
10487 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
10488     (((INSTANCE) == TIM1)    || \
10489      ((INSTANCE) == TIM2)    || \
10490      ((INSTANCE) == TIM3)    || \
10491      ((INSTANCE) == TIM16)   || \
10492      ((INSTANCE) == TIM17))
10493
10494 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
10495       (((INSTANCE) == TIM1)    || \
10496        ((INSTANCE) == TIM16)   || \
10497        ((INSTANCE) == TIM17))
10498
10499 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
10500     ((((INSTANCE) == TIM1) &&                   \
10501      (((CHANNEL) == TIM_CHANNEL_1) ||          \
10502       ((CHANNEL) == TIM_CHANNEL_2) ||          \
10503       ((CHANNEL) == TIM_CHANNEL_3) ||          \
10504       ((CHANNEL) == TIM_CHANNEL_4)))           \
10505     ||                                         \
10506     (((INSTANCE) == TIM2) &&                   \
10507      (((CHANNEL) == TIM_CHANNEL_1) ||          \
10508       ((CHANNEL) == TIM_CHANNEL_2) ||          \
10509       ((CHANNEL) == TIM_CHANNEL_3) ||          \
10510       ((CHANNEL) == TIM_CHANNEL_4)))           \
10511     ||                                         \
10512     (((INSTANCE) == TIM3) &&                   \
10513      (((CHANNEL) == TIM_CHANNEL_1) ||          \
10514       ((CHANNEL) == TIM_CHANNEL_2) ||          \
10515       ((CHANNEL) == TIM_CHANNEL_3) ||          \
10516       ((CHANNEL) == TIM_CHANNEL_4)))           \
10517     ||                                         \
10518     (((INSTANCE) == TIM14) &&                  \
10519      (((CHANNEL) == TIM_CHANNEL_1)))           \
10520     ||                                         \
10521     (((INSTANCE) == TIM16) &&                  \
10522      (((CHANNEL) == TIM_CHANNEL_1)))           \
10523     ||                                         \
10524     (((INSTANCE) == TIM17) &&                  \
10525      (((CHANNEL) == TIM_CHANNEL_1))))
10526
10527 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
10528    ((((INSTANCE) == TIM1) &&                    \
10529      (((CHANNEL) == TIM_CHANNEL_1) ||           \
10530       ((CHANNEL) == TIM_CHANNEL_2) ||           \
10531       ((CHANNEL) == TIM_CHANNEL_3)))            \
10532     ||                                          \
10533     (((INSTANCE) == TIM16) &&                   \
10534      ((CHANNEL) == TIM_CHANNEL_1))              \
10535     ||                                          \
10536     (((INSTANCE) == TIM17) &&                   \
10537      ((CHANNEL) == TIM_CHANNEL_1)))
10538
10539 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
10540   (((INSTANCE) == TIM1)    || \
10541    ((INSTANCE) == TIM2)    || \
10542    ((INSTANCE) == TIM3))
10543
10544 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
10545   (((INSTANCE) == TIM1)    || \
10546    ((INSTANCE) == TIM16)   || \
10547    ((INSTANCE) == TIM17))
10548
10549 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
10550   (((INSTANCE) == TIM1)    || \
10551    ((INSTANCE) == TIM2)    || \
10552    ((INSTANCE) == TIM3)    || \
10553    ((INSTANCE) == TIM14)   || \
10554    ((INSTANCE) == TIM16)   || \
10555    ((INSTANCE) == TIM17))
10556
10557 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
10558   (((INSTANCE) == TIM1))
10559
10560 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
10561   (((INSTANCE) == TIM1))
10562
10563 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
10564   (((INSTANCE) == TIM1)    || \
10565    ((INSTANCE) == TIM2)    || \
10566    ((INSTANCE) == TIM3)    || \
10567    ((INSTANCE) == TIM16)   || \
10568    ((INSTANCE) == TIM17))
10569     
10570 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
10571   (((INSTANCE) == TIM1)    || \
10572    ((INSTANCE) == TIM2)    || \
10573    ((INSTANCE) == TIM3)    || \
10574    ((INSTANCE) == TIM16)   || \
10575    ((INSTANCE) == TIM17))
10576     
10577 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
10578   (((INSTANCE) == TIM1)    || \
10579    ((INSTANCE) == TIM16)   || \
10580    ((INSTANCE) == TIM17))
10581
10582 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
10583   (((INSTANCE) == TIM1)    || \
10584    ((INSTANCE) == TIM14))
10585
10586 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
10587   ((INSTANCE) == TIM1)
10588
10589 /****************************** TSC Instances *********************************/
10590 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
10591
10592 /*********************** UART Instances : IRDA mode ***************************/
10593 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10594
10595 /********************* UART Instances : Smard card mode ***********************/
10596 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10597
10598 /******************** USART Instances : Synchronous mode **********************/
10599 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10600                                      ((INSTANCE) == USART2))
10601                                      
10602 /******************** USART Instances : auto Baud rate detection **************/                                     
10603 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10604                                                                                               
10605 /******************** UART Instances : Asynchronous mode **********************/
10606 #define IS_UART_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
10607                                       ((INSTANCE) == USART2))
10608
10609 /******************** UART Instances : Half-Duplex mode **********************/
10610 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
10611                                                  ((INSTANCE) == USART2))
10612
10613 /****************** UART Instances : Hardware Flow control ********************/
10614 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10615                                            ((INSTANCE) == USART2))
10616
10617 /****************** UART Instances : LIN mode ********************/
10618 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10619
10620 /****************** UART Instances : wakeup from stop mode ********************/
10621 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10622 /* Old macro definition maintained for legacy purpose */
10623 #define IS_UART_WAKEUP_INSTANCE         IS_UART_WAKEUP_FROMSTOP_INSTANCE
10624
10625 /****************** UART Instances : Driver enable detection ********************/
10626 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10627                                                   ((INSTANCE) == USART2))
10628
10629 /****************************** USB Instances ********************************/
10630 #define IS_USB_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == USB)
10631
10632 /****************************** WWDG Instances ********************************/
10633 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
10634
10635 /**
10636   * @}
10637   */
10638
10639
10640 /******************************************************************************/
10641 /*  For a painless codes migration between the STM32F0xx device product       */
10642 /*  lines, the aliases defined below are put in place to overcome the         */
10643 /*  differences in the interrupt handlers and IRQn definitions.               */
10644 /*  No need to update developed interrupt code when moving across             */
10645 /*  product lines within the same STM32F0 Family                              */
10646 /******************************************************************************/
10647
10648 /* Aliases for __IRQn */
10649 #define ADC1_COMP_IRQn             ADC1_IRQn
10650 #define DMA1_Ch1_IRQn              DMA1_Channel1_IRQn
10651 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
10652 #define DMA1_Channel4_5_6_7_IRQn   DMA1_Channel4_5_IRQn
10653 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
10654 #define PVD_IRQn                   PVD_VDDIO2_IRQn
10655 #define VDDIO2_IRQn                PVD_VDDIO2_IRQn
10656 #define RCC_IRQn                   RCC_CRS_IRQn
10657
10658
10659 /* Aliases for __IRQHandler */
10660 #define ADC1_COMP_IRQHandler             ADC1_IRQHandler
10661 #define DMA1_Ch1_IRQHandler              DMA1_Channel1_IRQHandler
10662 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
10663 #define DMA1_Channel4_5_6_7_IRQHandler   DMA1_Channel4_5_IRQHandler
10664 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
10665 #define PVD_IRQHandler                   PVD_VDDIO2_IRQHandler
10666 #define VDDIO2_IRQHandler                PVD_VDDIO2_IRQHandler
10667 #define RCC_IRQHandler                   RCC_CRS_IRQHandler
10668
10669
10670 #ifdef __cplusplus
10671 }
10672 #endif /* __cplusplus */
10673
10674 #endif /* __STM32F042x6_H */
10675
10676 /**
10677   * @}
10678   */
10679
10680   /**
10681   * @}
10682   */
10683
10684 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/