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| 8b51c7 | 1 | /* ---------------------------------------------------------------------- |
| Q | 2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
| 3 | * | |
| 4 | * $Date: 19. March 2015 | |
| 5 | * $Revision: V.1.4.5 | |
| 6 | * | |
| 7 | * Project: CMSIS DSP Library | |
| 8 | * Title: arm_cmplx_dot_prod_f32.c | |
| 9 | * | |
| 10 | * Description: Floating-point complex dot product | |
| 11 | * | |
| 12 | * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 | |
| 13 | * | |
| 14 | * Redistribution and use in source and binary forms, with or without | |
| 15 | * modification, are permitted provided that the following conditions | |
| 16 | * are met: | |
| 17 | * - Redistributions of source code must retain the above copyright | |
| 18 | * notice, this list of conditions and the following disclaimer. | |
| 19 | * - Redistributions in binary form must reproduce the above copyright | |
| 20 | * notice, this list of conditions and the following disclaimer in | |
| 21 | * the documentation and/or other materials provided with the | |
| 22 | * distribution. | |
| 23 | * - Neither the name of ARM LIMITED nor the names of its contributors | |
| 24 | * may be used to endorse or promote products derived from this | |
| 25 | * software without specific prior written permission. | |
| 26 | * | |
| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | |
| 30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | |
| 31 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
| 32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, | |
| 33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
| 34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
| 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
| 36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN | |
| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
| 38 | * POSSIBILITY OF SUCH DAMAGE. | |
| 39 | * ---------------------------------------------------------------------------- */ | |
| 40 | ||
| 41 | #include "arm_math.h" | |
| 42 | ||
| 43 | /** | |
| 44 | * @ingroup groupCmplxMath | |
| 45 | */ | |
| 46 | ||
| 47 | /** | |
| 48 | * @defgroup cmplx_dot_prod Complex Dot Product | |
| 49 | * | |
| 50 | * Computes the dot product of two complex vectors. | |
| 51 | * The vectors are multiplied element-by-element and then summed. | |
| 52 | * | |
| 53 | * The <code>pSrcA</code> points to the first complex input vector and | |
| 54 | * <code>pSrcB</code> points to the second complex input vector. | |
| 55 | * <code>numSamples</code> specifies the number of complex samples | |
| 56 | * and the data in each array is stored in an interleaved fashion | |
| 57 | * (real, imag, real, imag, ...). | |
| 58 | * Each array has a total of <code>2*numSamples</code> values. | |
| 59 | * | |
| 60 | * The underlying algorithm is used: | |
| 61 | * <pre> | |
| 62 | * realResult=0; | |
| 63 | * imagResult=0; | |
| 64 | * for(n=0; n<numSamples; n++) { | |
| 65 | * realResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+0] - pSrcA[(2*n)+1]*pSrcB[(2*n)+1]; | |
| 66 | * imagResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+1] + pSrcA[(2*n)+1]*pSrcB[(2*n)+0]; | |
| 67 | * } | |
| 68 | * </pre> | |
| 69 | * | |
| 70 | * There are separate functions for floating-point, Q15, and Q31 data types. | |
| 71 | */ | |
| 72 | ||
| 73 | /** | |
| 74 | * @addtogroup cmplx_dot_prod | |
| 75 | * @{ | |
| 76 | */ | |
| 77 | ||
| 78 | /** | |
| 79 | * @brief Floating-point complex dot product | |
| 80 | * @param *pSrcA points to the first input vector | |
| 81 | * @param *pSrcB points to the second input vector | |
| 82 | * @param numSamples number of complex samples in each vector | |
| 83 | * @param *realResult real part of the result returned here | |
| 84 | * @param *imagResult imaginary part of the result returned here | |
| 85 | * @return none. | |
| 86 | */ | |
| 87 | ||
| 88 | void arm_cmplx_dot_prod_f32( | |
| 89 | float32_t * pSrcA, | |
| 90 | float32_t * pSrcB, | |
| 91 | uint32_t numSamples, | |
| 92 | float32_t * realResult, | |
| 93 | float32_t * imagResult) | |
| 94 | { | |
| 95 | float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result storage */ | |
| 96 | float32_t a0,b0,c0,d0; | |
| 97 | ||
| 98 | #ifndef ARM_MATH_CM0_FAMILY | |
| 99 | ||
| 100 | /* Run the below code for Cortex-M4 and Cortex-M3 */ | |
| 101 | uint32_t blkCnt; /* loop counter */ | |
| 102 | ||
| 103 | /*loop Unrolling */ | |
| 104 | blkCnt = numSamples >> 2u; | |
| 105 | ||
| 106 | /* First part of the processing with loop unrolling. Compute 4 outputs at a time. | |
| 107 | ** a second loop below computes the remaining 1 to 3 samples. */ | |
| 108 | while(blkCnt > 0u) | |
| 109 | { | |
| 110 | a0 = *pSrcA++; | |
| 111 | b0 = *pSrcA++; | |
| 112 | c0 = *pSrcB++; | |
| 113 | d0 = *pSrcB++; | |
| 114 | ||
| 115 | real_sum += a0 * c0; | |
| 116 | imag_sum += a0 * d0; | |
| 117 | real_sum -= b0 * d0; | |
| 118 | imag_sum += b0 * c0; | |
| 119 | ||
| 120 | a0 = *pSrcA++; | |
| 121 | b0 = *pSrcA++; | |
| 122 | c0 = *pSrcB++; | |
| 123 | d0 = *pSrcB++; | |
| 124 | ||
| 125 | real_sum += a0 * c0; | |
| 126 | imag_sum += a0 * d0; | |
| 127 | real_sum -= b0 * d0; | |
| 128 | imag_sum += b0 * c0; | |
| 129 | ||
| 130 | a0 = *pSrcA++; | |
| 131 | b0 = *pSrcA++; | |
| 132 | c0 = *pSrcB++; | |
| 133 | d0 = *pSrcB++; | |
| 134 | ||
| 135 | real_sum += a0 * c0; | |
| 136 | imag_sum += a0 * d0; | |
| 137 | real_sum -= b0 * d0; | |
| 138 | imag_sum += b0 * c0; | |
| 139 | ||
| 140 | a0 = *pSrcA++; | |
| 141 | b0 = *pSrcA++; | |
| 142 | c0 = *pSrcB++; | |
| 143 | d0 = *pSrcB++; | |
| 144 | ||
| 145 | real_sum += a0 * c0; | |
| 146 | imag_sum += a0 * d0; | |
| 147 | real_sum -= b0 * d0; | |
| 148 | imag_sum += b0 * c0; | |
| 149 | ||
| 150 | /* Decrement the loop counter */ | |
| 151 | blkCnt--; | |
| 152 | } | |
| 153 | ||
| 154 | /* If the numSamples is not a multiple of 4, compute any remaining output samples here. | |
| 155 | ** No loop unrolling is used. */ | |
| 156 | blkCnt = numSamples & 0x3u; | |
| 157 | ||
| 158 | while(blkCnt > 0u) | |
| 159 | { | |
| 160 | a0 = *pSrcA++; | |
| 161 | b0 = *pSrcA++; | |
| 162 | c0 = *pSrcB++; | |
| 163 | d0 = *pSrcB++; | |
| 164 | ||
| 165 | real_sum += a0 * c0; | |
| 166 | imag_sum += a0 * d0; | |
| 167 | real_sum -= b0 * d0; | |
| 168 | imag_sum += b0 * c0; | |
| 169 | ||
| 170 | /* Decrement the loop counter */ | |
| 171 | blkCnt--; | |
| 172 | } | |
| 173 | ||
| 174 | #else | |
| 175 | ||
| 176 | /* Run the below code for Cortex-M0 */ | |
| 177 | ||
| 178 | while(numSamples > 0u) | |
| 179 | { | |
| 180 | a0 = *pSrcA++; | |
| 181 | b0 = *pSrcA++; | |
| 182 | c0 = *pSrcB++; | |
| 183 | d0 = *pSrcB++; | |
| 184 | ||
| 185 | real_sum += a0 * c0; | |
| 186 | imag_sum += a0 * d0; | |
| 187 | real_sum -= b0 * d0; | |
| 188 | imag_sum += b0 * c0; | |
| 189 | ||
| 190 | /* Decrement the loop counter */ | |
| 191 | numSamples--; | |
| 192 | } | |
| 193 | ||
| 194 | #endif /* #ifndef ARM_MATH_CM0_FAMILY */ | |
| 195 | ||
| 196 | /* Store the real and imaginary results in the destination buffers */ | |
| 197 | *realResult = real_sum; | |
| 198 | *imagResult = imag_sum; | |
| 199 | } | |
| 200 | ||
| 201 | /** | |
| 202 | * @} end of cmplx_dot_prod group | |
| 203 | */ | |
