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8b51c7	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_ll_spi.h
	4	* @author MCD Application Team
	5	* @brief Header file of SPI LL module.
	6	******************************************************************************
	7	* @attention
	8	*
	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	10	*
	11	* Redistribution and use in source and binary forms, with or without modification,
	12	* are permitted provided that the following conditions are met:
	13	* 1. Redistributions of source code must retain the above copyright notice,
	14	* this list of conditions and the following disclaimer.
	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	19	* may be used to endorse or promote products derived from this software
	20	* without specific prior written permission.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	******************************************************************************
	34	*/
	35
	36	/* Define to prevent recursive inclusion -------------------------------------*/
	37	#ifndef __STM32F0xx_LL_SPI_H
	38	#define __STM32F0xx_LL_SPI_H
	39
	40	#ifdef __cplusplus
	41	extern "C" {
	42	#endif
	43
	44	/* Includes ------------------------------------------------------------------*/
	45	#include "stm32f0xx.h"
	46
	47	/** @addtogroup STM32F0xx_LL_Driver
	48	* @{
	49	*/
	50
	51	#if defined (SPI1) \|\| defined (SPI2)
	52
	53	/** @defgroup SPI_LL SPI
	54	* @{
	55	*/
	56
	57	/* Private types -------------------------------------------------------------*/
	58	/* Private variables ---------------------------------------------------------*/
	59	/* Private macros ------------------------------------------------------------*/
	60
	61	/* Exported types ------------------------------------------------------------*/
	62	#if defined(USE_FULL_LL_DRIVER)
	63	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
	64	* @{
	65	*/
	66
	67	/**
	68	* @brief SPI Init structures definition
	69	*/
	70	typedef struct
	71	{
	72	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
	73	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
	74
	75	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
	76
	77	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
	78	This parameter can be a value of @ref SPI_LL_EC_MODE.
	79
	80	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
	81
	82	uint32_t DataWidth; /*!< Specifies the SPI data width.
	83	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
	84
	85	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
	86
	87	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
	88	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
	89
	90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
	91
	92	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
	93	This parameter can be a value of @ref SPI_LL_EC_PHASE.
	94
	95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
	96
	97	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
	98	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
	99
	100	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
	101
	102	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
	103	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
	104	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
	105
	106	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
	107
	108	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
	109	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
	110
	111	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
	112
	113	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
	114	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
	115
	116	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
	117
	118	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
	120
	121	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
	122
	123	} LL_SPI_InitTypeDef;
	124
	125	/**
	126	* @}
	127	*/
	128	#endif /* USE_FULL_LL_DRIVER */
	129
	130	/* Exported constants --------------------------------------------------------*/
	131	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
	132	* @{
	133	*/
	134
	135	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
	136	* @brief Flags defines which can be used with LL_SPI_ReadReg function
	137	* @{
	138	*/
	139	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
	140	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
	141	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
	142	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
	143	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
	144	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
	145	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
	146	/**
	147	* @}
	148	*/
	149
	150	/** @defgroup SPI_LL_EC_IT IT Defines
	151	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
	152	* @{
	153	*/
	154	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
	155	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
	156	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
	157	/**
	158	* @}
	159	*/
	160
	161	/** @defgroup SPI_LL_EC_MODE Operation Mode
	162	* @{
	163	*/
	164	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
	165	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
	166	/**
	167	* @}
	168	*/
	169
	170	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
	171	* @{
	172	*/
	173	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
	174	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
	175	/**
	176	* @}
	177	*/
	178
	179	/** @defgroup SPI_LL_EC_PHASE Clock Phase
	180	* @{
	181	*/
	182	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
	183	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
	184	/**
	185	* @}
	186	*/
	187
	188	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
	189	* @{
	190	*/
	191	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
	192	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
	193	/**
	194	* @}
	195	*/
	196
	197	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
	198	* @{
	199	*/
	200	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
	201	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
	202	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
	203	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
	204	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
	205	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
	206	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
	207	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
	208	/**
	209	* @}
	210	*/
	211
	212	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
	213	* @{
	214	*/
	215	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
	216	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
	217	/**
	218	* @}
	219	*/
	220
	221	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
	222	* @{
	223	*/
	224	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
	225	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
	226	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
	227	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
	228	/**
	229	* @}
	230	*/
	231
	232	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
	233	* @{
	234	*/
	235	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
	236	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
	237	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
	238	/**
	239	* @}
	240	*/
	241
	242	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
	243	* @{
	244	*/
	245	#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 4 bits /
	246	#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /!< Data length for SPI transfer: 5 bits /
	247	#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 6 bits /
	248	#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 7 bits /
	249	#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 8 bits /
	250	#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /!< Data length for SPI transfer: 9 bits /
	251	#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 10 bits /
	252	#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 11 bits /
	253	#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 12 bits /
	254	#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2) /!< Data length for SPI transfer: 13 bits /
	255	#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 14 bits /
	256	#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 15 bits /
	257	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 16 bits /
	258	/**
	259	* @}
	260	*/
	261	#if defined(USE_FULL_LL_DRIVER)
	262
	263	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
	264	* @{
	265	*/
	266	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
	267	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
	268	/**
	269	* @}
	270	*/
	271	#endif /* USE_FULL_LL_DRIVER */
	272
	273	/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
	274	* @{
	275	*/
	276	#define LL_SPI_CRC_8BIT 0x00000000U /!< 8-bit CRC length /
	277	#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /!< 16-bit CRC length /
	278	/**
	279	* @}
	280	*/
	281
	282	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
	283	* @{
	284	*/
	285	#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) /
	286	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) /
	287	/**
	288	* @}
	289	*/
	290
	291	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
	292	* @{
	293	*/
	294	#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /!< FIFO reception empty /
	295	#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /!< FIFO reception 1/4 /
	296	#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /!< FIFO reception 1/2 /
	297	#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 \| SPI_SR_FRLVL_0) /!< FIFO reception full /
	298	/**
	299	* @}
	300	*/
	301
	302	/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
	303	* @{
	304	*/
	305	#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /!< FIFO transmission empty /
	306	#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /!< FIFO transmission 1/4 /
	307	#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /!< FIFO transmission 1/2 /
	308	#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 \| SPI_SR_FTLVL_0) /!< FIFO transmission full /
	309	/**
	310	* @}
	311	*/
	312
	313	/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
	314	* @{
	315	*/
	316	#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /!< Select DMA parity Even /
	317	#define LL_SPI_DMA_PARITY_ODD 0x00000001U /!< Select DMA parity Odd /
	318
	319	/**
	320	* @}
	321	*/
	322
	323	/**
	324	* @}
	325	*/
	326
	327	/* Exported macro ------------------------------------------------------------*/
	328	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
	329	* @{
	330	*/
	331
	332	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
	333	* @{
	334	*/
	335
	336	/**
	337	* @brief Write a value in SPI register
	338	* @param __INSTANCE__ SPI Instance
	339	* @param __REG__ Register to be written
	340	* @param __VALUE__ Value to be written in the register
	341	* @retval None
	342	*/
	343	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
	344
	345	/**
	346	* @brief Read a value in SPI register
	347	* @param __INSTANCE__ SPI Instance
	348	* @param __REG__ Register to be read
	349	* @retval Register value
	350	*/
	351	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
	352	/**
	353	* @}
	354	*/
	355
	356	/**
	357	* @}
	358	*/
	359
	360	/* Exported functions --------------------------------------------------------*/
	361	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
	362	* @{
	363	*/
	364
	365	/** @defgroup SPI_LL_EF_Configuration Configuration
	366	* @{
	367	*/
	368
	369	/**
	370	* @brief Enable SPI peripheral
	371	* @rmtoll CR1 SPE LL_SPI_Enable
	372	* @param SPIx SPI Instance
	373	* @retval None
	374	*/
	375	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
	376	{
	377	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
	378	}
	379
	380	/**
	381	* @brief Disable SPI peripheral
	382	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
	383	* @rmtoll CR1 SPE LL_SPI_Disable
	384	* @param SPIx SPI Instance
	385	* @retval None
	386	*/
	387	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
	388	{
	389	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
	390	}
	391
	392	/**
	393	* @brief Check if SPI peripheral is enabled
	394	* @rmtoll CR1 SPE LL_SPI_IsEnabled
	395	* @param SPIx SPI Instance
	396	* @retval State of bit (1 or 0).
	397	*/
	398	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
	399	{
	400	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
	401	}
	402
	403	/**
	404	* @brief Set SPI operation mode to Master or Slave
	405	* @note This bit should not be changed when communication is ongoing.
	406	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
	407	* CR1 SSI LL_SPI_SetMode
	408	* @param SPIx SPI Instance
	409	* @param Mode This parameter can be one of the following values:
	410	* @arg @ref LL_SPI_MODE_MASTER
	411	* @arg @ref LL_SPI_MODE_SLAVE
	412	* @retval None
	413	*/
	414	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
	415	{
	416	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
	417	}
	418
	419	/**
	420	* @brief Get SPI operation mode (Master or Slave)
	421	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
	422	* CR1 SSI LL_SPI_GetMode
	423	* @param SPIx SPI Instance
	424	* @retval Returned value can be one of the following values:
	425	* @arg @ref LL_SPI_MODE_MASTER
	426	* @arg @ref LL_SPI_MODE_SLAVE
	427	*/
	428	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
	429	{
	430	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
	431	}
	432
	433	/**
	434	* @brief Set serial protocol used
	435	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
	436	* @rmtoll CR2 FRF LL_SPI_SetStandard
	437	* @param SPIx SPI Instance
	438	* @param Standard This parameter can be one of the following values:
	439	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
	440	* @arg @ref LL_SPI_PROTOCOL_TI
	441	* @retval None
	442	*/
	443	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
	444	{
	445	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
	446	}
	447
	448	/**
	449	* @brief Get serial protocol used
	450	* @rmtoll CR2 FRF LL_SPI_GetStandard
	451	* @param SPIx SPI Instance
	452	* @retval Returned value can be one of the following values:
	453	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
	454	* @arg @ref LL_SPI_PROTOCOL_TI
	455	*/
	456	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
	457	{
	458	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
	459	}
	460
	461	/**
	462	* @brief Set clock phase
	463	* @note This bit should not be changed when communication is ongoing.
	464	* This bit is not used in SPI TI mode.
	465	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
	466	* @param SPIx SPI Instance
	467	* @param ClockPhase This parameter can be one of the following values:
	468	* @arg @ref LL_SPI_PHASE_1EDGE
	469	* @arg @ref LL_SPI_PHASE_2EDGE
	470	* @retval None
	471	*/
	472	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
	473	{
	474	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
	475	}
	476
	477	/**
	478	* @brief Get clock phase
	479	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
	480	* @param SPIx SPI Instance
	481	* @retval Returned value can be one of the following values:
	482	* @arg @ref LL_SPI_PHASE_1EDGE
	483	* @arg @ref LL_SPI_PHASE_2EDGE
	484	*/
	485	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
	486	{
	487	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
	488	}
	489
	490	/**
	491	* @brief Set clock polarity
	492	* @note This bit should not be changed when communication is ongoing.
	493	* This bit is not used in SPI TI mode.
	494	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
	495	* @param SPIx SPI Instance
	496	* @param ClockPolarity This parameter can be one of the following values:
	497	* @arg @ref LL_SPI_POLARITY_LOW
	498	* @arg @ref LL_SPI_POLARITY_HIGH
	499	* @retval None
	500	*/
	501	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
	502	{
	503	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
	504	}
	505
	506	/**
	507	* @brief Get clock polarity
	508	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
	509	* @param SPIx SPI Instance
	510	* @retval Returned value can be one of the following values:
	511	* @arg @ref LL_SPI_POLARITY_LOW
	512	* @arg @ref LL_SPI_POLARITY_HIGH
	513	*/
	514	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
	515	{
	516	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
	517	}
	518
	519	/**
	520	* @brief Set baud rate prescaler
	521	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
	522	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
	523	* @param SPIx SPI Instance
	524	* @param BaudRate This parameter can be one of the following values:
	525	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
	526	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
	527	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
	528	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
	529	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
	530	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
	531	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
	532	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
	533	* @retval None
	534	*/
	535	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
	536	{
	537	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
	538	}
	539
	540	/**
	541	* @brief Get baud rate prescaler
	542	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
	543	* @param SPIx SPI Instance
	544	* @retval Returned value can be one of the following values:
	545	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
	546	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
	547	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
	548	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
	549	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
	550	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
	551	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
	552	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
	553	*/
	554	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
	555	{
	556	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
	557	}
	558
	559	/**
	560	* @brief Set transfer bit order
	561	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
	562	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
	563	* @param SPIx SPI Instance
	564	* @param BitOrder This parameter can be one of the following values:
	565	* @arg @ref LL_SPI_LSB_FIRST
	566	* @arg @ref LL_SPI_MSB_FIRST
	567	* @retval None
	568	*/
	569	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
	570	{
	571	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
	572	}
	573
	574	/**
	575	* @brief Get transfer bit order
	576	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
	577	* @param SPIx SPI Instance
	578	* @retval Returned value can be one of the following values:
	579	* @arg @ref LL_SPI_LSB_FIRST
	580	* @arg @ref LL_SPI_MSB_FIRST
	581	*/
	582	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
	583	{
	584	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
	585	}
	586
	587	/**
	588	* @brief Set transfer direction mode
	589	* @note For Half-Duplex mode, Rx Direction is set by default.
	590	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
	591	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
	592	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
	593	* CR1 BIDIOE LL_SPI_SetTransferDirection
	594	* @param SPIx SPI Instance
	595	* @param TransferDirection This parameter can be one of the following values:
	596	* @arg @ref LL_SPI_FULL_DUPLEX
	597	* @arg @ref LL_SPI_SIMPLEX_RX
	598	* @arg @ref LL_SPI_HALF_DUPLEX_RX
	599	* @arg @ref LL_SPI_HALF_DUPLEX_TX
	600	* @retval None
	601	*/
	602	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
	603	{
	604	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
	605	}
	606
	607	/**
	608	* @brief Get transfer direction mode
	609	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
	610	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
	611	* CR1 BIDIOE LL_SPI_GetTransferDirection
	612	* @param SPIx SPI Instance
	613	* @retval Returned value can be one of the following values:
	614	* @arg @ref LL_SPI_FULL_DUPLEX
	615	* @arg @ref LL_SPI_SIMPLEX_RX
	616	* @arg @ref LL_SPI_HALF_DUPLEX_RX
	617	* @arg @ref LL_SPI_HALF_DUPLEX_TX
	618	*/
	619	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
	620	{
	621	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
	622	}
	623
	624	/**
	625	* @brief Set frame data width
	626	* @rmtoll CR2 DS LL_SPI_SetDataWidth
	627	* @param SPIx SPI Instance
	628	* @param DataWidth This parameter can be one of the following values:
	629	* @arg @ref LL_SPI_DATAWIDTH_4BIT
	630	* @arg @ref LL_SPI_DATAWIDTH_5BIT
	631	* @arg @ref LL_SPI_DATAWIDTH_6BIT
	632	* @arg @ref LL_SPI_DATAWIDTH_7BIT
	633	* @arg @ref LL_SPI_DATAWIDTH_8BIT
	634	* @arg @ref LL_SPI_DATAWIDTH_9BIT
	635	* @arg @ref LL_SPI_DATAWIDTH_10BIT
	636	* @arg @ref LL_SPI_DATAWIDTH_11BIT
	637	* @arg @ref LL_SPI_DATAWIDTH_12BIT
	638	* @arg @ref LL_SPI_DATAWIDTH_13BIT
	639	* @arg @ref LL_SPI_DATAWIDTH_14BIT
	640	* @arg @ref LL_SPI_DATAWIDTH_15BIT
	641	* @arg @ref LL_SPI_DATAWIDTH_16BIT
	642	* @retval None
	643	*/
	644	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
	645	{
	646	MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
	647	}
	648
	649	/**
	650	* @brief Get frame data width
	651	* @rmtoll CR2 DS LL_SPI_GetDataWidth
	652	* @param SPIx SPI Instance
	653	* @retval Returned value can be one of the following values:
	654	* @arg @ref LL_SPI_DATAWIDTH_4BIT
	655	* @arg @ref LL_SPI_DATAWIDTH_5BIT
	656	* @arg @ref LL_SPI_DATAWIDTH_6BIT
	657	* @arg @ref LL_SPI_DATAWIDTH_7BIT
	658	* @arg @ref LL_SPI_DATAWIDTH_8BIT
	659	* @arg @ref LL_SPI_DATAWIDTH_9BIT
	660	* @arg @ref LL_SPI_DATAWIDTH_10BIT
	661	* @arg @ref LL_SPI_DATAWIDTH_11BIT
	662	* @arg @ref LL_SPI_DATAWIDTH_12BIT
	663	* @arg @ref LL_SPI_DATAWIDTH_13BIT
	664	* @arg @ref LL_SPI_DATAWIDTH_14BIT
	665	* @arg @ref LL_SPI_DATAWIDTH_15BIT
	666	* @arg @ref LL_SPI_DATAWIDTH_16BIT
	667	*/
	668	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
	669	{
	670	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
	671	}
	672
	673	/**
	674	* @brief Set threshold of RXFIFO that triggers an RXNE event
	675	* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
	676	* @param SPIx SPI Instance
	677	* @param Threshold This parameter can be one of the following values:
	678	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
	679	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
	680	* @retval None
	681	*/
	682	__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
	683	{
	684	MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
	685	}
	686
	687	/**
	688	* @brief Get threshold of RXFIFO that triggers an RXNE event
	689	* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
	690	* @param SPIx SPI Instance
	691	* @retval Returned value can be one of the following values:
	692	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
	693	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
	694	*/
	695	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
	696	{
	697	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
	698	}
	699
	700	/**
	701	* @}
	702	*/
	703
	704	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
	705	* @{
	706	*/
	707
	708	/**
	709	* @brief Enable CRC
	710	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
	711	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
	712	* @param SPIx SPI Instance
	713	* @retval None
	714	*/
	715	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
	716	{
	717	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
	718	}
	719
	720	/**
	721	* @brief Disable CRC
	722	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
	723	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
	724	* @param SPIx SPI Instance
	725	* @retval None
	726	*/
	727	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
	728	{
	729	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
	730	}
	731
	732	/**
	733	* @brief Check if CRC is enabled
	734	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
	735	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
	736	* @param SPIx SPI Instance
	737	* @retval State of bit (1 or 0).
	738	*/
	739	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
	740	{
	741	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
	742	}
	743
	744	/**
	745	* @brief Set CRC Length
	746	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
	747	* @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
	748	* @param SPIx SPI Instance
	749	* @param CRCLength This parameter can be one of the following values:
	750	* @arg @ref LL_SPI_CRC_8BIT
	751	* @arg @ref LL_SPI_CRC_16BIT
	752	* @retval None
	753	*/
	754	__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
	755	{
	756	MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
	757	}
	758
	759	/**
	760	* @brief Get CRC Length
	761	* @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
	762	* @param SPIx SPI Instance
	763	* @retval Returned value can be one of the following values:
	764	* @arg @ref LL_SPI_CRC_8BIT
	765	* @arg @ref LL_SPI_CRC_16BIT
	766	*/
	767	__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
	768	{
	769	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
	770	}
	771
	772	/**
	773	* @brief Set CRCNext to transfer CRC on the line
	774	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
	775	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
	776	* @param SPIx SPI Instance
	777	* @retval None
	778	*/
	779	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
	780	{
	781	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
	782	}
	783
	784	/**
	785	* @brief Set polynomial for CRC calculation
	786	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
	787	* @param SPIx SPI Instance
	788	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
	789	* @retval None
	790	*/
	791	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
	792	{
	793	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
	794	}
	795
	796	/**
	797	* @brief Get polynomial for CRC calculation
	798	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
	799	* @param SPIx SPI Instance
	800	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
	801	*/
	802	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
	803	{
	804	return (uint32_t)(READ_REG(SPIx->CRCPR));
	805	}
	806
	807	/**
	808	* @brief Get Rx CRC
	809	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
	810	* @param SPIx SPI Instance
	811	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
	812	*/
	813	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
	814	{
	815	return (uint32_t)(READ_REG(SPIx->RXCRCR));
	816	}
	817
	818	/**
	819	* @brief Get Tx CRC
	820	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
	821	* @param SPIx SPI Instance
	822	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
	823	*/
	824	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
	825	{
	826	return (uint32_t)(READ_REG(SPIx->TXCRCR));
	827	}
	828
	829	/**
	830	* @}
	831	*/
	832
	833	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
	834	* @{
	835	*/
	836
	837	/**
	838	* @brief Set NSS mode
	839	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
	840	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
	841	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
	842	* @param SPIx SPI Instance
	843	* @param NSS This parameter can be one of the following values:
	844	* @arg @ref LL_SPI_NSS_SOFT
	845	* @arg @ref LL_SPI_NSS_HARD_INPUT
	846	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
	847	* @retval None
	848	*/
	849	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
	850	{
	851	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
	852	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
	853	}
	854
	855	/**
	856	* @brief Get NSS mode
	857	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
	858	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
	859	* @param SPIx SPI Instance
	860	* @retval Returned value can be one of the following values:
	861	* @arg @ref LL_SPI_NSS_SOFT
	862	* @arg @ref LL_SPI_NSS_HARD_INPUT
	863	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
	864	*/
	865	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
	866	{
	867	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
	868	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
	869	return (Ssm \| Ssoe);
	870	}
	871
	872	/**
	873	* @brief Enable NSS pulse management
	874	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
	875	* @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
	876	* @param SPIx SPI Instance
	877	* @retval None
	878	*/
	879	__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
	880	{
	881	SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
	882	}
	883
	884	/**
	885	* @brief Disable NSS pulse management
	886	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
	887	* @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
	888	* @param SPIx SPI Instance
	889	* @retval None
	890	*/
	891	__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
	892	{
	893	CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
	894	}
	895
	896	/**
	897	* @brief Check if NSS pulse is enabled
	898	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
	899	* @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
	900	* @param SPIx SPI Instance
	901	* @retval State of bit (1 or 0).
	902	*/
	903	__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
	904	{
	905	return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
	906	}
	907
	908	/**
	909	* @}
	910	*/
	911
	912	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
	913	* @{
	914	*/
	915
	916	/**
	917	* @brief Check if Rx buffer is not empty
	918	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
	919	* @param SPIx SPI Instance
	920	* @retval State of bit (1 or 0).
	921	*/
	922	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
	923	{
	924	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
	925	}
	926
	927	/**
	928	* @brief Check if Tx buffer is empty
	929	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
	930	* @param SPIx SPI Instance
	931	* @retval State of bit (1 or 0).
	932	*/
	933	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
	934	{
	935	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
	936	}
	937
	938	/**
	939	* @brief Get CRC error flag
	940	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
	941	* @param SPIx SPI Instance
	942	* @retval State of bit (1 or 0).
	943	*/
	944	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
	945	{
	946	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
	947	}
	948
	949	/**
	950	* @brief Get mode fault error flag
	951	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
	952	* @param SPIx SPI Instance
	953	* @retval State of bit (1 or 0).
	954	*/
	955	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
	956	{
	957	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
	958	}
	959
	960	/**
	961	* @brief Get overrun error flag
	962	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
	963	* @param SPIx SPI Instance
	964	* @retval State of bit (1 or 0).
	965	*/
	966	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
	967	{
	968	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
	969	}
	970
	971	/**
	972	* @brief Get busy flag
	973	* @note The BSY flag is cleared under any one of the following conditions:
	974	* -When the SPI is correctly disabled
	975	* -When a fault is detected in Master mode (MODF bit set to 1)
	976	* -In Master mode, when it finishes a data transmission and no new data is ready to be
	977	* sent
	978	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
	979	* each data transfer.
	980	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
	981	* @param SPIx SPI Instance
	982	* @retval State of bit (1 or 0).
	983	*/
	984	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
	985	{
	986	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
	987	}
	988
	989	/**
	990	* @brief Get frame format error flag
	991	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
	992	* @param SPIx SPI Instance
	993	* @retval State of bit (1 or 0).
	994	*/
	995	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
	996	{
	997	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
	998	}
	999
	1000	/**
	1001	* @brief Get FIFO reception Level
	1002	* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
	1003	* @param SPIx SPI Instance
	1004	* @retval Returned value can be one of the following values:
	1005	* @arg @ref LL_SPI_RX_FIFO_EMPTY
	1006	* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
	1007	* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
	1008	* @arg @ref LL_SPI_RX_FIFO_FULL
	1009	*/
	1010	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
	1011	{
	1012	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
	1013	}
	1014
	1015	/**
	1016	* @brief Get FIFO Transmission Level
	1017	* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
	1018	* @param SPIx SPI Instance
	1019	* @retval Returned value can be one of the following values:
	1020	* @arg @ref LL_SPI_TX_FIFO_EMPTY
	1021	* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
	1022	* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
	1023	* @arg @ref LL_SPI_TX_FIFO_FULL
	1024	*/
	1025	__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
	1026	{
	1027	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
	1028	}
	1029
	1030	/**
	1031	* @brief Clear CRC error flag
	1032	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
	1033	* @param SPIx SPI Instance
	1034	* @retval None
	1035	*/
	1036	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
	1037	{
	1038	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
	1039	}
	1040
	1041	/**
	1042	* @brief Clear mode fault error flag
	1043	* @note Clearing this flag is done by a read access to the SPIx_SR
	1044	* register followed by a write access to the SPIx_CR1 register
	1045	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
	1046	* @param SPIx SPI Instance
	1047	* @retval None
	1048	*/
	1049	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
	1050	{
	1051	__IO uint32_t tmpreg;
	1052	tmpreg = SPIx->SR;
	1053	(void) tmpreg;
	1054	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
	1055	(void) tmpreg;
	1056	}
	1057
	1058	/**
	1059	* @brief Clear overrun error flag
	1060	* @note Clearing this flag is done by a read access to the SPIx_DR
	1061	* register followed by a read access to the SPIx_SR register
	1062	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
	1063	* @param SPIx SPI Instance
	1064	* @retval None
	1065	*/
	1066	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
	1067	{
	1068	__IO uint32_t tmpreg;
	1069	tmpreg = SPIx->DR;
	1070	(void) tmpreg;
	1071	tmpreg = SPIx->SR;
	1072	(void) tmpreg;
	1073	}
	1074
	1075	/**
	1076	* @brief Clear frame format error flag
	1077	* @note Clearing this flag is done by reading SPIx_SR register
	1078	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
	1079	* @param SPIx SPI Instance
	1080	* @retval None
	1081	*/
	1082	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
	1083	{
	1084	__IO uint32_t tmpreg;
	1085	tmpreg = SPIx->SR;
	1086	(void) tmpreg;
	1087	}
	1088
	1089	/**
	1090	* @}
	1091	*/
	1092
	1093	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
	1094	* @{
	1095	*/
	1096
	1097	/**
	1098	* @brief Enable error interrupt
	1099	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
	1100	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
	1101	* @param SPIx SPI Instance
	1102	* @retval None
	1103	*/
	1104	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
	1105	{
	1106	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
	1107	}
	1108
	1109	/**
	1110	* @brief Enable Rx buffer not empty interrupt
	1111	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
	1112	* @param SPIx SPI Instance
	1113	* @retval None
	1114	*/
	1115	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
	1116	{
	1117	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
	1118	}
	1119
	1120	/**
	1121	* @brief Enable Tx buffer empty interrupt
	1122	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
	1123	* @param SPIx SPI Instance
	1124	* @retval None
	1125	*/
	1126	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
	1127	{
	1128	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
	1129	}
	1130
	1131	/**
	1132	* @brief Disable error interrupt
	1133	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
	1134	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
	1135	* @param SPIx SPI Instance
	1136	* @retval None
	1137	*/
	1138	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
	1139	{
	1140	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
	1141	}
	1142
	1143	/**
	1144	* @brief Disable Rx buffer not empty interrupt
	1145	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
	1146	* @param SPIx SPI Instance
	1147	* @retval None
	1148	*/
	1149	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
	1150	{
	1151	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
	1152	}
	1153
	1154	/**
	1155	* @brief Disable Tx buffer empty interrupt
	1156	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
	1157	* @param SPIx SPI Instance
	1158	* @retval None
	1159	*/
	1160	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
	1161	{
	1162	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
	1163	}
	1164
	1165	/**
	1166	* @brief Check if error interrupt is enabled
	1167	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
	1168	* @param SPIx SPI Instance
	1169	* @retval State of bit (1 or 0).
	1170	*/
	1171	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
	1172	{
	1173	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
	1174	}
	1175
	1176	/**
	1177	* @brief Check if Rx buffer not empty interrupt is enabled
	1178	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
	1179	* @param SPIx SPI Instance
	1180	* @retval State of bit (1 or 0).
	1181	*/
	1182	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
	1183	{
	1184	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
	1185	}
	1186
	1187	/**
	1188	* @brief Check if Tx buffer empty interrupt
	1189	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
	1190	* @param SPIx SPI Instance
	1191	* @retval State of bit (1 or 0).
	1192	*/
	1193	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
	1194	{
	1195	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
	1196	}
	1197
	1198	/**
	1199	* @}
	1200	*/
	1201
	1202	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
	1203	* @{
	1204	*/
	1205
	1206	/**
	1207	* @brief Enable DMA Rx
	1208	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
	1209	* @param SPIx SPI Instance
	1210	* @retval None
	1211	*/
	1212	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
	1213	{
	1214	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
	1215	}
	1216
	1217	/**
	1218	* @brief Disable DMA Rx
	1219	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
	1220	* @param SPIx SPI Instance
	1221	* @retval None
	1222	*/
	1223	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
	1224	{
	1225	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
	1226	}
	1227
	1228	/**
	1229	* @brief Check if DMA Rx is enabled
	1230	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
	1231	* @param SPIx SPI Instance
	1232	* @retval State of bit (1 or 0).
	1233	*/
	1234	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
	1235	{
	1236	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
	1237	}
	1238
	1239	/**
	1240	* @brief Enable DMA Tx
	1241	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
	1242	* @param SPIx SPI Instance
	1243	* @retval None
	1244	*/
	1245	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
	1246	{
	1247	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
	1248	}
	1249
	1250	/**
	1251	* @brief Disable DMA Tx
	1252	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
	1253	* @param SPIx SPI Instance
	1254	* @retval None
	1255	*/
	1256	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
	1257	{
	1258	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
	1259	}
	1260
	1261	/**
	1262	* @brief Check if DMA Tx is enabled
	1263	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
	1264	* @param SPIx SPI Instance
	1265	* @retval State of bit (1 or 0).
	1266	*/
	1267	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
	1268	{
	1269	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
	1270	}
	1271
	1272	/**
	1273	* @brief Set parity of Last DMA reception
	1274	* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
	1275	* @param SPIx SPI Instance
	1276	* @param Parity This parameter can be one of the following values:
	1277	* @arg @ref LL_SPI_DMA_PARITY_ODD
	1278	* @arg @ref LL_SPI_DMA_PARITY_EVEN
	1279	* @retval None
	1280	*/
	1281	__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
	1282	{
	1283	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
	1284	}
	1285
	1286	/**
	1287	* @brief Get parity configuration for Last DMA reception
	1288	* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
	1289	* @param SPIx SPI Instance
	1290	* @retval Returned value can be one of the following values:
	1291	* @arg @ref LL_SPI_DMA_PARITY_ODD
	1292	* @arg @ref LL_SPI_DMA_PARITY_EVEN
	1293	*/
	1294	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
	1295	{
	1296	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
	1297	}
	1298
	1299	/**
	1300	* @brief Set parity of Last DMA transmission
	1301	* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
	1302	* @param SPIx SPI Instance
	1303	* @param Parity This parameter can be one of the following values:
	1304	* @arg @ref LL_SPI_DMA_PARITY_ODD
	1305	* @arg @ref LL_SPI_DMA_PARITY_EVEN
	1306	* @retval None
	1307	*/
	1308	__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
	1309	{
	1310	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
	1311	}
	1312
	1313	/**
	1314	* @brief Get parity configuration for Last DMA transmission
	1315	* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
	1316	* @param SPIx SPI Instance
	1317	* @retval Returned value can be one of the following values:
	1318	* @arg @ref LL_SPI_DMA_PARITY_ODD
	1319	* @arg @ref LL_SPI_DMA_PARITY_EVEN
	1320	*/
	1321	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
	1322	{
	1323	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
	1324	}
	1325
	1326	/**
	1327	* @brief Get the data register address used for DMA transfer
	1328	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
	1329	* @param SPIx SPI Instance
	1330	* @retval Address of data register
	1331	*/
	1332	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
	1333	{
	1334	return (uint32_t) & (SPIx->DR);
	1335	}
	1336
	1337	/**
	1338	* @}
	1339	*/
	1340
	1341	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
	1342	* @{
	1343	*/
	1344
	1345	/**
	1346	* @brief Read 8-Bits in the data register
	1347	* @rmtoll DR DR LL_SPI_ReceiveData8
	1348	* @param SPIx SPI Instance
	1349	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
	1350	*/
	1351	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
	1352	{
	1353	return (uint8_t)(READ_REG(SPIx->DR));
	1354	}
	1355
	1356	/**
	1357	* @brief Read 16-Bits in the data register
	1358	* @rmtoll DR DR LL_SPI_ReceiveData16
	1359	* @param SPIx SPI Instance
	1360	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
	1361	*/
	1362	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
	1363	{
	1364	return (uint16_t)(READ_REG(SPIx->DR));
	1365	}
	1366
	1367	/**
	1368	* @brief Write 8-Bits in the data register
	1369	* @rmtoll DR DR LL_SPI_TransmitData8
	1370	* @param SPIx SPI Instance
	1371	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
	1372	* @retval None
	1373	*/
	1374	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
	1375	{
	1376	((__IO uint8_t )&SPIx->DR) = TxData;
	1377	}
	1378
	1379	/**
	1380	* @brief Write 16-Bits in the data register
	1381	* @rmtoll DR DR LL_SPI_TransmitData16
	1382	* @param SPIx SPI Instance
	1383	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
	1384	* @retval None
	1385	*/
	1386	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
	1387	{
	1388	((__IO uint16_t )&SPIx->DR) = TxData;
	1389	}
	1390
	1391	/**
	1392	* @}
	1393	*/
	1394	#if defined(USE_FULL_LL_DRIVER)
	1395	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
	1396	* @{
	1397	*/
	1398
	1399	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
	1400	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
	1401	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
	1402
	1403	/**
	1404	* @}
	1405	*/
	1406	#endif /* USE_FULL_LL_DRIVER */
	1407	/**
	1408	* @}
	1409	*/
	1410
	1411	/**
	1412	* @}
	1413	*/
	1414
	1415	#if defined(SPI_I2S_SUPPORT)
	1416	/** @defgroup I2S_LL I2S
	1417	* @{
	1418	*/
	1419
	1420	/* Private variables ---------------------------------------------------------*/
	1421	/* Private constants ---------------------------------------------------------*/
	1422	/* Private macros ------------------------------------------------------------*/
	1423
	1424	/* Exported types ------------------------------------------------------------*/
	1425	#if defined(USE_FULL_LL_DRIVER)
	1426	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
	1427	* @{
	1428	*/
	1429
	1430	/**
	1431	* @brief I2S Init structure definition
	1432	*/
	1433
	1434	typedef struct
	1435	{
	1436	uint32_t Mode; /*!< Specifies the I2S operating mode.
	1437	This parameter can be a value of @ref I2S_LL_EC_MODE
	1438
	1439	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
	1440
	1441	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
	1442	This parameter can be a value of @ref I2S_LL_EC_STANDARD
	1443
	1444	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
	1445
	1446
	1447	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
	1448	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
	1449
	1450	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
	1451
	1452
	1453	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
	1454	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
	1455
	1456	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
	1457
	1458
	1459	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
	1460	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
	1461
	1462	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
	1463	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
	1464
	1465
	1466	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
	1467	This parameter can be a value of @ref I2S_LL_EC_POLARITY
	1468
	1469	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
	1470
	1471	} LL_I2S_InitTypeDef;
	1472
	1473	/**
	1474	* @}
	1475	*/
	1476	#endif /USE_FULL_LL_DRIVER/
	1477
	1478	/* Exported constants --------------------------------------------------------*/
	1479	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
	1480	* @{
	1481	*/
	1482
	1483	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
	1484	* @brief Flags defines which can be used with LL_I2S_ReadReg function
	1485	* @{
	1486	*/
	1487	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
	1488	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
	1489	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
	1490	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
	1491	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
	1492	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
	1493	/**
	1494	* @}
	1495	*/
	1496
	1497	/** @defgroup SPI_LL_EC_IT IT Defines
	1498	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
	1499	* @{
	1500	*/
	1501	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
	1502	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
	1503	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
	1504	/**
	1505	* @}
	1506	*/
	1507
	1508	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
	1509	* @{
	1510	*/
	1511	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
	1512	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
	1513	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
	1514	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
	1515	/**
	1516	* @}
	1517	*/
	1518
	1519	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
	1520	* @{
	1521	*/
	1522	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
	1523	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
	1524	/**
	1525	* @}
	1526	*/
	1527
	1528	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
	1529	* @{
	1530	*/
	1531	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
	1532	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
	1533	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
	1534	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
	1535	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
	1536	/**
	1537	* @}
	1538	*/
	1539
	1540	/** @defgroup I2S_LL_EC_MODE Operation Mode
	1541	* @{
	1542	*/
	1543	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
	1544	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
	1545	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
	1546	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
	1547	/**
	1548	* @}
	1549	*/
	1550
	1551	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
	1552	* @{
	1553	*/
	1554	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
	1555	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
	1556	/**
	1557	* @}
	1558	*/
	1559
	1560	#if defined(USE_FULL_LL_DRIVER)
	1561
	1562	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
	1563	* @{
	1564	*/
	1565	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
	1566	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
	1567	/**
	1568	* @}
	1569	*/
	1570
	1571	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
	1572	* @{
	1573	*/
	1574
	1575	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
	1576	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
	1577	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
	1578	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
	1579	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
	1580	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
	1581	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
	1582	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
	1583	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
	1584	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
	1585	/**
	1586	* @}
	1587	*/
	1588	#endif /* USE_FULL_LL_DRIVER */
	1589
	1590	/**
	1591	* @}
	1592	*/
	1593
	1594	/* Exported macro ------------------------------------------------------------*/
	1595	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
	1596	* @{
	1597	*/
	1598
	1599	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
	1600	* @{
	1601	*/
	1602
	1603	/**
	1604	* @brief Write a value in I2S register
	1605	* @param __INSTANCE__ I2S Instance
	1606	* @param __REG__ Register to be written
	1607	* @param __VALUE__ Value to be written in the register
	1608	* @retval None
	1609	*/
	1610	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
	1611
	1612	/**
	1613	* @brief Read a value in I2S register
	1614	* @param __INSTANCE__ I2S Instance
	1615	* @param __REG__ Register to be read
	1616	* @retval Register value
	1617	*/
	1618	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
	1619	/**
	1620	* @}
	1621	*/
	1622
	1623	/**
	1624	* @}
	1625	*/
	1626
	1627
	1628	/* Exported functions --------------------------------------------------------*/
	1629
	1630	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
	1631	* @{
	1632	*/
	1633
	1634	/** @defgroup I2S_LL_EF_Configuration Configuration
	1635	* @{
	1636	*/
	1637
	1638	/**
	1639	* @brief Select I2S mode and Enable I2S peripheral
	1640	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
	1641	* I2SCFGR I2SE LL_I2S_Enable
	1642	* @param SPIx SPI Instance
	1643	* @retval None
	1644	*/
	1645	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
	1646	{
	1647	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
	1648	}
	1649
	1650	/**
	1651	* @brief Disable I2S peripheral
	1652	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
	1653	* @param SPIx SPI Instance
	1654	* @retval None
	1655	*/
	1656	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
	1657	{
	1658	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
	1659	}
	1660
	1661	/**
	1662	* @brief Check if I2S peripheral is enabled
	1663	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
	1664	* @param SPIx SPI Instance
	1665	* @retval State of bit (1 or 0).
	1666	*/
	1667	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
	1668	{
	1669	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
	1670	}
	1671
	1672	/**
	1673	* @brief Set I2S data frame length
	1674	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
	1675	* I2SCFGR CHLEN LL_I2S_SetDataFormat
	1676	* @param SPIx SPI Instance
	1677	* @param DataFormat This parameter can be one of the following values:
	1678	* @arg @ref LL_I2S_DATAFORMAT_16B
	1679	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
	1680	* @arg @ref LL_I2S_DATAFORMAT_24B
	1681	* @arg @ref LL_I2S_DATAFORMAT_32B
	1682	* @retval None
	1683	*/
	1684	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
	1685	{
	1686	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
	1687	}
	1688
	1689	/**
	1690	* @brief Get I2S data frame length
	1691	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
	1692	* I2SCFGR CHLEN LL_I2S_GetDataFormat
	1693	* @param SPIx SPI Instance
	1694	* @retval Returned value can be one of the following values:
	1695	* @arg @ref LL_I2S_DATAFORMAT_16B
	1696	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
	1697	* @arg @ref LL_I2S_DATAFORMAT_24B
	1698	* @arg @ref LL_I2S_DATAFORMAT_32B
	1699	*/
	1700	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
	1701	{
	1702	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
	1703	}
	1704
	1705	/**
	1706	* @brief Set I2S clock polarity
	1707	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
	1708	* @param SPIx SPI Instance
	1709	* @param ClockPolarity This parameter can be one of the following values:
	1710	* @arg @ref LL_I2S_POLARITY_LOW
	1711	* @arg @ref LL_I2S_POLARITY_HIGH
	1712	* @retval None
	1713	*/
	1714	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
	1715	{
	1716	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
	1717	}
	1718
	1719	/**
	1720	* @brief Get I2S clock polarity
	1721	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
	1722	* @param SPIx SPI Instance
	1723	* @retval Returned value can be one of the following values:
	1724	* @arg @ref LL_I2S_POLARITY_LOW
	1725	* @arg @ref LL_I2S_POLARITY_HIGH
	1726	*/
	1727	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
	1728	{
	1729	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
	1730	}
	1731
	1732	/**
	1733	* @brief Set I2S standard protocol
	1734	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
	1735	* I2SCFGR PCMSYNC LL_I2S_SetStandard
	1736	* @param SPIx SPI Instance
	1737	* @param Standard This parameter can be one of the following values:
	1738	* @arg @ref LL_I2S_STANDARD_PHILIPS
	1739	* @arg @ref LL_I2S_STANDARD_MSB
	1740	* @arg @ref LL_I2S_STANDARD_LSB
	1741	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
	1742	* @arg @ref LL_I2S_STANDARD_PCM_LONG
	1743	* @retval None
	1744	*/
	1745	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
	1746	{
	1747	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
	1748	}
	1749
	1750	/**
	1751	* @brief Get I2S standard protocol
	1752	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
	1753	* I2SCFGR PCMSYNC LL_I2S_GetStandard
	1754	* @param SPIx SPI Instance
	1755	* @retval Returned value can be one of the following values:
	1756	* @arg @ref LL_I2S_STANDARD_PHILIPS
	1757	* @arg @ref LL_I2S_STANDARD_MSB
	1758	* @arg @ref LL_I2S_STANDARD_LSB
	1759	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
	1760	* @arg @ref LL_I2S_STANDARD_PCM_LONG
	1761	*/
	1762	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
	1763	{
	1764	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
	1765	}
	1766
	1767	/**
	1768	* @brief Set I2S transfer mode
	1769	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
	1770	* @param SPIx SPI Instance
	1771	* @param Mode This parameter can be one of the following values:
	1772	* @arg @ref LL_I2S_MODE_SLAVE_TX
	1773	* @arg @ref LL_I2S_MODE_SLAVE_RX
	1774	* @arg @ref LL_I2S_MODE_MASTER_TX
	1775	* @arg @ref LL_I2S_MODE_MASTER_RX
	1776	* @retval None
	1777	*/
	1778	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
	1779	{
	1780	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
	1781	}
	1782
	1783	/**
	1784	* @brief Get I2S transfer mode
	1785	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
	1786	* @param SPIx SPI Instance
	1787	* @retval Returned value can be one of the following values:
	1788	* @arg @ref LL_I2S_MODE_SLAVE_TX
	1789	* @arg @ref LL_I2S_MODE_SLAVE_RX
	1790	* @arg @ref LL_I2S_MODE_MASTER_TX
	1791	* @arg @ref LL_I2S_MODE_MASTER_RX
	1792	*/
	1793	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
	1794	{
	1795	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
	1796	}
	1797
	1798	/**
	1799	* @brief Set I2S linear prescaler
	1800	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
	1801	* @param SPIx SPI Instance
	1802	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
	1803	* @retval None
	1804	*/
	1805	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
	1806	{
	1807	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
	1808	}
	1809
	1810	/**
	1811	* @brief Get I2S linear prescaler
	1812	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
	1813	* @param SPIx SPI Instance
	1814	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
	1815	*/
	1816	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
	1817	{
	1818	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
	1819	}
	1820
	1821	/**
	1822	* @brief Set I2S parity prescaler
	1823	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
	1824	* @param SPIx SPI Instance
	1825	* @param PrescalerParity This parameter can be one of the following values:
	1826	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
	1827	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
	1828	* @retval None
	1829	*/
	1830	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
	1831	{
	1832	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
	1833	}
	1834
	1835	/**
	1836	* @brief Get I2S parity prescaler
	1837	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
	1838	* @param SPIx SPI Instance
	1839	* @retval Returned value can be one of the following values:
	1840	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
	1841	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
	1842	*/
	1843	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
	1844	{
	1845	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
	1846	}
	1847
	1848	/**
	1849	* @brief Enable the master clock ouput (Pin MCK)
	1850	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
	1851	* @param SPIx SPI Instance
	1852	* @retval None
	1853	*/
	1854	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
	1855	{
	1856	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
	1857	}
	1858
	1859	/**
	1860	* @brief Disable the master clock ouput (Pin MCK)
	1861	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
	1862	* @param SPIx SPI Instance
	1863	* @retval None
	1864	*/
	1865	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
	1866	{
	1867	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
	1868	}
	1869
	1870	/**
	1871	* @brief Check if the master clock ouput (Pin MCK) is enabled
	1872	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
	1873	* @param SPIx SPI Instance
	1874	* @retval State of bit (1 or 0).
	1875	*/
	1876	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
	1877	{
	1878	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
	1879	}
	1880
	1881	#if defined(SPI_I2SCFGR_ASTRTEN)
	1882	/**
	1883	* @brief Enable asynchronous start
	1884	* @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
	1885	* @param SPIx SPI Instance
	1886	* @retval None
	1887	*/
	1888	__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
	1889	{
	1890	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
	1891	}
	1892
	1893	/**
	1894	* @brief Disable asynchronous start
	1895	* @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
	1896	* @param SPIx SPI Instance
	1897	* @retval None
	1898	*/
	1899	__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
	1900	{
	1901	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
	1902	}
	1903
	1904	/**
	1905	* @brief Check if asynchronous start is enabled
	1906	* @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
	1907	* @param SPIx SPI Instance
	1908	* @retval State of bit (1 or 0).
	1909	*/
	1910	__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
	1911	{
	1912	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
	1913	}
	1914	#endif /* SPI_I2SCFGR_ASTRTEN */
	1915
	1916	/**
	1917	* @}
	1918	*/
	1919
	1920	/** @defgroup I2S_LL_EF_FLAG FLAG Management
	1921	* @{
	1922	*/
	1923
	1924	/**
	1925	* @brief Check if Rx buffer is not empty
	1926	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
	1927	* @param SPIx SPI Instance
	1928	* @retval State of bit (1 or 0).
	1929	*/
	1930	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
	1931	{
	1932	return LL_SPI_IsActiveFlag_RXNE(SPIx);
	1933	}
	1934
	1935	/**
	1936	* @brief Check if Tx buffer is empty
	1937	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
	1938	* @param SPIx SPI Instance
	1939	* @retval State of bit (1 or 0).
	1940	*/
	1941	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
	1942	{
	1943	return LL_SPI_IsActiveFlag_TXE(SPIx);
	1944	}
	1945
	1946	/**
	1947	* @brief Get busy flag
	1948	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
	1949	* @param SPIx SPI Instance
	1950	* @retval State of bit (1 or 0).
	1951	*/
	1952	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
	1953	{
	1954	return LL_SPI_IsActiveFlag_BSY(SPIx);
	1955	}
	1956
	1957	/**
	1958	* @brief Get overrun error flag
	1959	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
	1960	* @param SPIx SPI Instance
	1961	* @retval State of bit (1 or 0).
	1962	*/
	1963	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
	1964	{
	1965	return LL_SPI_IsActiveFlag_OVR(SPIx);
	1966	}
	1967
	1968	/**
	1969	* @brief Get underrun error flag
	1970	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
	1971	* @param SPIx SPI Instance
	1972	* @retval State of bit (1 or 0).
	1973	*/
	1974	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
	1975	{
	1976	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
	1977	}
	1978
	1979	/**
	1980	* @brief Get frame format error flag
	1981	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
	1982	* @param SPIx SPI Instance
	1983	* @retval State of bit (1 or 0).
	1984	*/
	1985	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
	1986	{
	1987	return LL_SPI_IsActiveFlag_FRE(SPIx);
	1988	}
	1989
	1990	/**
	1991	* @brief Get channel side flag.
	1992	* @note 0: Channel Left has to be transmitted or has been received\n
	1993	* 1: Channel Right has to be transmitted or has been received\n
	1994	* It has no significance in PCM mode.
	1995	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
	1996	* @param SPIx SPI Instance
	1997	* @retval State of bit (1 or 0).
	1998	*/
	1999	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
	2000	{
	2001	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
	2002	}
	2003
	2004	/**
	2005	* @brief Clear overrun error flag
	2006	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
	2007	* @param SPIx SPI Instance
	2008	* @retval None
	2009	*/
	2010	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
	2011	{
	2012	LL_SPI_ClearFlag_OVR(SPIx);
	2013	}
	2014
	2015	/**
	2016	* @brief Clear underrun error flag
	2017	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
	2018	* @param SPIx SPI Instance
	2019	* @retval None
	2020	*/
	2021	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
	2022	{
	2023	__IO uint32_t tmpreg;
	2024	tmpreg = SPIx->SR;
	2025	(void)tmpreg;
	2026	}
	2027
	2028	/**
	2029	* @brief Clear frame format error flag
	2030	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
	2031	* @param SPIx SPI Instance
	2032	* @retval None
	2033	*/
	2034	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
	2035	{
	2036	LL_SPI_ClearFlag_FRE(SPIx);
	2037	}
	2038
	2039	/**
	2040	* @}
	2041	*/
	2042
	2043	/** @defgroup I2S_LL_EF_IT Interrupt Management
	2044	* @{
	2045	*/
	2046
	2047	/**
	2048	* @brief Enable error IT
	2049	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
	2050	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
	2051	* @param SPIx SPI Instance
	2052	* @retval None
	2053	*/
	2054	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
	2055	{
	2056	LL_SPI_EnableIT_ERR(SPIx);
	2057	}
	2058
	2059	/**
	2060	* @brief Enable Rx buffer not empty IT
	2061	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
	2062	* @param SPIx SPI Instance
	2063	* @retval None
	2064	*/
	2065	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
	2066	{
	2067	LL_SPI_EnableIT_RXNE(SPIx);
	2068	}
	2069
	2070	/**
	2071	* @brief Enable Tx buffer empty IT
	2072	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
	2073	* @param SPIx SPI Instance
	2074	* @retval None
	2075	*/
	2076	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
	2077	{
	2078	LL_SPI_EnableIT_TXE(SPIx);
	2079	}
	2080
	2081	/**
	2082	* @brief Disable error IT
	2083	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
	2084	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
	2085	* @param SPIx SPI Instance
	2086	* @retval None
	2087	*/
	2088	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
	2089	{
	2090	LL_SPI_DisableIT_ERR(SPIx);
	2091	}
	2092
	2093	/**
	2094	* @brief Disable Rx buffer not empty IT
	2095	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
	2096	* @param SPIx SPI Instance
	2097	* @retval None
	2098	*/
	2099	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
	2100	{
	2101	LL_SPI_DisableIT_RXNE(SPIx);
	2102	}
	2103
	2104	/**
	2105	* @brief Disable Tx buffer empty IT
	2106	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
	2107	* @param SPIx SPI Instance
	2108	* @retval None
	2109	*/
	2110	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
	2111	{
	2112	LL_SPI_DisableIT_TXE(SPIx);
	2113	}
	2114
	2115	/**
	2116	* @brief Check if ERR IT is enabled
	2117	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
	2118	* @param SPIx SPI Instance
	2119	* @retval State of bit (1 or 0).
	2120	*/
	2121	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
	2122	{
	2123	return LL_SPI_IsEnabledIT_ERR(SPIx);
	2124	}
	2125
	2126	/**
	2127	* @brief Check if RXNE IT is enabled
	2128	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
	2129	* @param SPIx SPI Instance
	2130	* @retval State of bit (1 or 0).
	2131	*/
	2132	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
	2133	{
	2134	return LL_SPI_IsEnabledIT_RXNE(SPIx);
	2135	}
	2136
	2137	/**
	2138	* @brief Check if TXE IT is enabled
	2139	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
	2140	* @param SPIx SPI Instance
	2141	* @retval State of bit (1 or 0).
	2142	*/
	2143	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
	2144	{
	2145	return LL_SPI_IsEnabledIT_TXE(SPIx);
	2146	}
	2147
	2148	/**
	2149	* @}
	2150	*/
	2151
	2152	/** @defgroup I2S_LL_EF_DMA DMA Management
	2153	* @{
	2154	*/
	2155
	2156	/**
	2157	* @brief Enable DMA Rx
	2158	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
	2159	* @param SPIx SPI Instance
	2160	* @retval None
	2161	*/
	2162	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
	2163	{
	2164	LL_SPI_EnableDMAReq_RX(SPIx);
	2165	}
	2166
	2167	/**
	2168	* @brief Disable DMA Rx
	2169	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
	2170	* @param SPIx SPI Instance
	2171	* @retval None
	2172	*/
	2173	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
	2174	{
	2175	LL_SPI_DisableDMAReq_RX(SPIx);
	2176	}
	2177
	2178	/**
	2179	* @brief Check if DMA Rx is enabled
	2180	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
	2181	* @param SPIx SPI Instance
	2182	* @retval State of bit (1 or 0).
	2183	*/
	2184	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
	2185	{
	2186	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
	2187	}
	2188
	2189	/**
	2190	* @brief Enable DMA Tx
	2191	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
	2192	* @param SPIx SPI Instance
	2193	* @retval None
	2194	*/
	2195	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
	2196	{
	2197	LL_SPI_EnableDMAReq_TX(SPIx);
	2198	}
	2199
	2200	/**
	2201	* @brief Disable DMA Tx
	2202	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
	2203	* @param SPIx SPI Instance
	2204	* @retval None
	2205	*/
	2206	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
	2207	{
	2208	LL_SPI_DisableDMAReq_TX(SPIx);
	2209	}
	2210
	2211	/**
	2212	* @brief Check if DMA Tx is enabled
	2213	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
	2214	* @param SPIx SPI Instance
	2215	* @retval State of bit (1 or 0).
	2216	*/
	2217	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
	2218	{
	2219	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
	2220	}
	2221
	2222	/**
	2223	* @}
	2224	*/
	2225
	2226	/** @defgroup I2S_LL_EF_DATA DATA Management
	2227	* @{
	2228	*/
	2229
	2230	/**
	2231	* @brief Read 16-Bits in data register
	2232	* @rmtoll DR DR LL_I2S_ReceiveData16
	2233	* @param SPIx SPI Instance
	2234	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
	2235	*/
	2236	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
	2237	{
	2238	return LL_SPI_ReceiveData16(SPIx);
	2239	}
	2240
	2241	/**
	2242	* @brief Write 16-Bits in data register
	2243	* @rmtoll DR DR LL_I2S_TransmitData16
	2244	* @param SPIx SPI Instance
	2245	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
	2246	* @retval None
	2247	*/
	2248	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
	2249	{
	2250	LL_SPI_TransmitData16(SPIx, TxData);
	2251	}
	2252
	2253	/**
	2254	* @}
	2255	*/
	2256
	2257	#if defined(USE_FULL_LL_DRIVER)
	2258	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
	2259	* @{
	2260	*/
	2261
	2262	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
	2263	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
	2264	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
	2265	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
	2266
	2267	/**
	2268	* @}
	2269	*/
	2270	#endif /* USE_FULL_LL_DRIVER */
	2271
	2272	/**
	2273	* @}
	2274	*/
	2275
	2276	/**
	2277	* @}
	2278	*/
	2279	#endif /* SPI_I2S_SUPPORT */
	2280
	2281	#endif /* defined (SPI1) \|\| defined (SPI2) */
	2282
	2283	/**
	2284	* @}
	2285	*/
	2286
	2287	#ifdef __cplusplus
	2288	}
	2289	#endif
	2290
	2291	#endif /* __STM32F0xx_LL_SPI_H */
	2292
	2293	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/