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8b51c7	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_hal_tim.h
	4	* @author MCD Application Team
	5	* @brief Header file of TIM HAL module.
	6	******************************************************************************
	7	* @attention
	8	*
	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	10	*
	11	* Redistribution and use in source and binary forms, with or without modification,
	12	* are permitted provided that the following conditions are met:
	13	* 1. Redistributions of source code must retain the above copyright notice,
	14	* this list of conditions and the following disclaimer.
	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	19	* may be used to endorse or promote products derived from this software
	20	* without specific prior written permission.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	******************************************************************************
	34	*/
	35
	36	/* Define to prevent recursive inclusion -------------------------------------*/
	37	#ifndef __STM32F0xx_HAL_TIM_H
	38	#define __STM32F0xx_HAL_TIM_H
	39
	40	#ifdef __cplusplus
	41	extern "C" {
	42	#endif
	43
	44	/* Includes ------------------------------------------------------------------*/
	45	#include "stm32f0xx_hal_def.h"
	46
	47	/** @addtogroup STM32F0xx_HAL_Driver
	48	* @{
	49	*/
	50
	51	/** @addtogroup TIM
	52	* @{
	53	*/
	54
	55	/* Exported types ------------------------------------------------------------*/
	56	/** @defgroup TIM_Exported_Types TIM Exported Types
	57	* @{
	58	*/
	59	/**
	60	* @brief TIM Time base Configuration Structure definition
	61	*/
	62	typedef struct
	63	{
	64	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
	65	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
	66
	67	uint32_t CounterMode; /*!< Specifies the counter mode.
	68	This parameter can be a value of @ref TIM_Counter_Mode */
	69
	70	uint32_t Period; /*!< Specifies the period value to be loaded into the active
	71	Auto-Reload Register at the next update event.
	72	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
	73
	74	uint32_t ClockDivision; /*!< Specifies the clock division.
	75	This parameter can be a value of @ref TIM_ClockDivision */
	76
	77	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
	78	reaches zero, an update event is generated and counting restarts
	79	from the RCR value (N).
	80	This means in PWM mode that (N+1) corresponds to:
	81	- the number of PWM periods in edge-aligned mode
	82	- the number of half PWM period in center-aligned mode
	83	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
	84	@note This parameter is valid only for TIM1 and TIM8. */
	85
	86	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
	87	This parameter can be a value of @ref TIM_AutoReloadPreload */
	88	} TIM_Base_InitTypeDef;
	89
	90	/**
	91	* @brief TIM Output Compare Configuration Structure definition
	92	*/
	93	typedef struct
	94	{
	95	uint32_t OCMode; /*!< Specifies the TIM mode.
	96	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
	97
	98	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
	99	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
	100
	101	uint32_t OCPolarity; /*!< Specifies the output polarity.
	102	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
	103
	104	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
	105	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
	106	@note This parameter is valid only for TIM1 and TIM8. */
	107
	108	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
	109	This parameter can be a value of @ref TIM_Output_Fast_State
	110	@note This parameter is valid only in PWM1 and PWM2 mode. */
	111
	112
	113	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
	114	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
	115	@note This parameter is valid only for TIM1 and TIM8. */
	116
	117	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
	118	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
	119	@note This parameter is valid only for TIM1 and TIM8. */
	120	} TIM_OC_InitTypeDef;
	121
	122	/**
	123	* @brief TIM One Pulse Mode Configuration Structure definition
	124	*/
	125	typedef struct
	126	{
	127	uint32_t OCMode; /*!< Specifies the TIM mode.
	128	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
	129
	130	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
	131	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
	132
	133	uint32_t OCPolarity; /*!< Specifies the output polarity.
	134	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
	135
	136	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
	137	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
	138	@note This parameter is valid only for TIM1 and TIM8. */
	139
	140	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
	141	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
	142	@note This parameter is valid only for TIM1 and TIM8. */
	143
	144	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
	145	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
	146	@note This parameter is valid only for TIM1 and TIM8. */
	147
	148	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
	149	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
	150
	151	uint32_t ICSelection; /*!< Specifies the input.
	152	This parameter can be a value of @ref TIM_Input_Capture_Selection */
	153
	154	uint32_t ICFilter; /*!< Specifies the input capture filter.
	155	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
	156	} TIM_OnePulse_InitTypeDef;
	157
	158
	159	/**
	160	* @brief TIM Input Capture Configuration Structure definition
	161	*/
	162	typedef struct
	163	{
	164	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
	165	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
	166
	167	uint32_t ICSelection; /*!< Specifies the input.
	168	This parameter can be a value of @ref TIM_Input_Capture_Selection */
	169
	170	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
	171	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
	172
	173	uint32_t ICFilter; /*!< Specifies the input capture filter.
	174	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
	175	} TIM_IC_InitTypeDef;
	176
	177	/**
	178	* @brief TIM Encoder Configuration Structure definition
	179	*/
	180	typedef struct
	181	{
	182	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
	183	This parameter can be a value of @ref TIM_Encoder_Mode */
	184
	185	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
	186	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
	187
	188	uint32_t IC1Selection; /*!< Specifies the input.
	189	This parameter can be a value of @ref TIM_Input_Capture_Selection */
	190
	191	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
	192	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
	193
	194	uint32_t IC1Filter; /*!< Specifies the input capture filter.
	195	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
	196
	197	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
	198	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
	199
	200	uint32_t IC2Selection; /*!< Specifies the input.
	201	This parameter can be a value of @ref TIM_Input_Capture_Selection */
	202
	203	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
	204	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
	205
	206	uint32_t IC2Filter; /*!< Specifies the input capture filter.
	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
	208	} TIM_Encoder_InitTypeDef;
	209
	210
	211	/**
	212	* @brief TIM Clock Configuration Handle Structure definition
	213	*/
	214	typedef struct
	215	{
	216	uint32_t ClockSource; /*!< TIM clock sources
	217	This parameter can be a value of @ref TIM_Clock_Source */
	218	uint32_t ClockPolarity; /*!< TIM clock polarity
	219	This parameter can be a value of @ref TIM_Clock_Polarity */
	220	uint32_t ClockPrescaler; /*!< TIM clock prescaler
	221	This parameter can be a value of @ref TIM_Clock_Prescaler */
	222	uint32_t ClockFilter; /*!< TIM clock filter
	223	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
	224	}TIM_ClockConfigTypeDef;
	225
	226	/**
	227	* @brief TIM Clear Input Configuration Handle Structure definition
	228	*/
	229	typedef struct
	230	{
	231	uint32_t ClearInputState; /*!< TIM clear Input state
	232	This parameter can be ENABLE or DISABLE */
	233	uint32_t ClearInputSource; /*!< TIM clear Input sources
	234	This parameter can be a value of @ref TIMEx_Clock_Clear_Input_Source */
	235	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
	236	This parameter can be a value of @ref TIM_ClearInput_Polarity */
	237	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
	238	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
	239	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
	240	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
	241	}TIM_ClearInputConfigTypeDef;
	242
	243	/**
	244	* @brief TIM Slave configuration Structure definition
	245	*/
	246	typedef struct {
	247	uint32_t SlaveMode; /*!< Slave mode selection
	248	This parameter can be a value of @ref TIM_Slave_Mode */
	249	uint32_t InputTrigger; /*!< Input Trigger source
	250	This parameter can be a value of @ref TIM_Trigger_Selection */
	251	uint32_t TriggerPolarity; /*!< Input Trigger polarity
	252	This parameter can be a value of @ref TIM_Trigger_Polarity */
	253	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
	254	This parameter can be a value of @ref TIM_Trigger_Prescaler */
	255	uint32_t TriggerFilter; /*!< Input trigger filter
	256	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
	257
	258	}TIM_SlaveConfigTypeDef;
	259
	260	/**
	261	* @brief HAL State structures definition
	262	*/
	263	typedef enum
	264	{
	265	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
	266	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
	267	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
	268	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
	269	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
	270	}HAL_TIM_StateTypeDef;
	271
	272	/**
	273	* @brief HAL Active channel structures definition
	274	*/
	275	typedef enum
	276	{
	277	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
	278	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
	279	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
	280	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
	281	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
	282	}HAL_TIM_ActiveChannel;
	283
	284	/**
	285	* @brief TIM Time Base Handle Structure definition
	286	*/
	287	typedef struct
	288	{
	289	TIM_TypeDef Instance; /!< Register base address */
	290	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
	291	HAL_TIM_ActiveChannel Channel; /!< Active channel /
	292	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
	293	This array is accessed by a @ref TIM_DMA_Handle_index */
	294	HAL_LockTypeDef Lock; /!< Locking object /
	295	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
	296	}TIM_HandleTypeDef;
	297
	298	/**
	299	* @}
	300	*/
	301
	302	/* Exported constants --------------------------------------------------------*/
	303	/** @defgroup TIM_Exported_Constants TIM Exported Constants
	304	* @{
	305	*/
	306
	307	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
	308	* @{
	309	*/
	310	#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /!< Polarity for TIx source /
	311	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
	312	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
	313	/**
	314	* @}
	315	*/
	316
	317	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
	318	* @{
	319	*/
	320	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
	321	#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /!< Polarity for ETR source /
	322	/**
	323	* @}
	324	*/
	325
	326	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
	327	* @{
	328	*/
	329	#define TIM_ETRPRESCALER_DIV1 (0x0000U) /!< No prescaler is used /
	330	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
	331	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
	332	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
	333	/**
	334	* @}
	335	*/
	336
	337	/** @defgroup TIM_Counter_Mode TIM Counter Mode
	338	* @{
	339	*/
	340	#define TIM_COUNTERMODE_UP (0x0000U)
	341	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
	342	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
	343	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
	344	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
	345	/**
	346	* @}
	347	*/
	348
	349	/** @defgroup TIM_ClockDivision TIM Clock Division
	350	* @{
	351	*/
	352	#define TIM_CLOCKDIVISION_DIV1 (0x0000U)
	353	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
	354	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
	355	/**
	356	* @}
	357	*/
	358
	359	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
	360	* @{
	361	*/
	362	#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /!< TIMx_ARR register is not buffered /
	363	#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /!< TIMx_ARR register is buffered /
	364	/**
	365	* @}
	366	*/
	367
	368	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
	369	* @{
	370	*/
	371	#define TIM_OCMODE_TIMING (0x0000U)
	372	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
	373	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
	374	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
	375	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
	376	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
	377	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
	378	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
	379	/**
	380	* @}
	381	*/
	382
	383	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
	384	* @{
	385	*/
	386	#define TIM_OCFAST_DISABLE (0x0000U)
	387	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
	388	/**
	389	* @}
	390	*/
	391
	392	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
	393	* @{
	394	*/
	395	#define TIM_OCPOLARITY_HIGH (0x0000U)
	396	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
	397	/**
	398	* @}
	399	*/
	400
	401	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
	402	* @{
	403	*/
	404	#define TIM_OCNPOLARITY_HIGH (0x0000U)
	405	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
	406	/**
	407	* @}
	408	*/
	409
	410	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
	411	* @{
	412	*/
	413	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
	414	#define TIM_OCIDLESTATE_RESET (0x0000U)
	415	/**
	416	* @}
	417	*/
	418
	419	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
	420	* @{
	421	*/
	422	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
	423	#define TIM_OCNIDLESTATE_RESET (0x0000U)
	424	/**
	425	* @}
	426	*/
	427
	428	/** @defgroup TIM_Channel TIM Channel
	429	* @{
	430	*/
	431	#define TIM_CHANNEL_1 (0x0000U)
	432	#define TIM_CHANNEL_2 (0x0004U)
	433	#define TIM_CHANNEL_3 (0x0008U)
	434	#define TIM_CHANNEL_4 (0x000CU)
	435	#define TIM_CHANNEL_ALL (0x0018U)
	436	/**
	437	* @}
	438	*/
	439
	440	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
	441	* @{
	442	*/
	443	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
	444	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
	445	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
	446	/**
	447	* @}
	448	*/
	449
	450	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
	451	* @{
	452	*/
	453	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
	454	connected to IC1, IC2, IC3 or IC4, respectively */
	455	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
	456	connected to IC2, IC1, IC4 or IC3, respectively */
	457	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
	458	/**
	459	* @}
	460	*/
	461
	462	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
	463	* @{
	464	*/
	465	#define TIM_ICPSC_DIV1 (0x0000U) /!< Capture performed each time an edge is detected on the capture input /
	466	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
	467	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
	468	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
	469	/**
	470	* @}
	471	*/
	472
	473	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
	474	* @{
	475	*/
	476	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
	477	#define TIM_OPMODE_REPETITIVE (0x0000U)
	478	/**
	479	* @}
	480	*/
	481
	482	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
	483	* @{
	484	*/
	485	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
	486	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
	487	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
	488	/**
	489	* @}
	490	*/
	491
	492	/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
	493	* @{
	494	*/
	495	#define TIM_IT_UPDATE (TIM_DIER_UIE)
	496	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
	497	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
	498	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
	499	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
	500	#define TIM_IT_COM (TIM_DIER_COMIE)
	501	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
	502	#define TIM_IT_BREAK (TIM_DIER_BIE)
	503	/**
	504	* @}
	505	*/
	506
	507	/** @defgroup TIM_Commutation_Source TIM Commutation Source
	508	* @{
	509	*/
	510	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
	511	#define TIM_COMMUTATION_SOFTWARE (0x0000U)
	512
	513	/**
	514	* @}
	515	*/
	516
	517	/** @defgroup TIM_DMA_sources TIM DMA Sources
	518	* @{
	519	*/
	520	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
	521	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
	522	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
	523	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
	524	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
	525	#define TIM_DMA_COM (TIM_DIER_COMDE)
	526	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
	527	/**
	528	* @}
	529	*/
	530
	531	/** @defgroup TIM_Event_Source TIM Event Source
	532	* @{
	533	*/
	534	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
	535	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
	536	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
	537	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
	538	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
	539	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
	540	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
	541	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
	542	/**
	543	* @}
	544	*/
	545
	546	/** @defgroup TIM_Flag_definition TIM Flag Definition
	547	* @{
	548	*/
	549	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
	550	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
	551	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
	552	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
	553	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
	554	#define TIM_FLAG_COM (TIM_SR_COMIF)
	555	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
	556	#define TIM_FLAG_BREAK (TIM_SR_BIF)
	557	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
	558	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
	559	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
	560	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
	561	/**
	562	* @}
	563	*/
	564
	565	/** @defgroup TIM_Clock_Source TIM Clock Source
	566	* @{
	567	*/
	568	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
	569	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
	570	#define TIM_CLOCKSOURCE_ITR0 (0x0000U)
	571	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
	572	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
	573	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
	574	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
	575	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
	576	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
	577	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
	578	/**
	579	* @}
	580	*/
	581
	582	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
	583	* @{
	584	*/
	585	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
	586	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
	587	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
	588	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
	589	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
	590	/**
	591	* @}
	592	*/
	593
	594	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
	595	* @{
	596	*/
	597	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
	598	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
	599	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
	600	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
	601	/**
	602	* @}
	603	*/
	604
	605	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
	606	* @{
	607	*/
	608	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
	609	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
	610	/**
	611	* @}
	612	*/
	613
	614	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
	615	* @{
	616	*/
	617	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
	618	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
	619	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
	620	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
	621	/**
	622	* @}
	623	*/
	624
	625	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
	626	* @{
	627	*/
	628	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
	629	#define TIM_OSSR_DISABLE (0x0000U)
	630	/**
	631	* @}
	632	*/
	633
	634	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
	635	* @{
	636	*/
	637	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
	638	#define TIM_OSSI_DISABLE (0x0000U)
	639	/**
	640	* @}
	641	*/
	642
	643	/** @defgroup TIM_Lock_level TIM Lock level
	644	* @{
	645	*/
	646	#define TIM_LOCKLEVEL_OFF (0x0000U)
	647	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
	648	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
	649	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
	650	/**
	651	* @}
	652	*/
	653
	654	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
	655	* @{
	656	*/
	657	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
	658	#define TIM_BREAK_DISABLE (0x0000U)
	659	/**
	660	* @}
	661	*/
	662
	663	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
	664	* @{
	665	*/
	666	#define TIM_BREAKPOLARITY_LOW (0x0000U)
	667	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
	668	/**
	669	* @}
	670	*/
	671	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
	672	* @{
	673	*/
	674	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
	675	#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
	676	/**
	677	* @}
	678	*/
	679
	680	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
	681	* @{
	682	*/
	683	#define TIM_TRGO_RESET (0x0000U)
	684	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
	685	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
	686	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
	687	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
	688	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
	689	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
	690	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
	691	/**
	692	* @}
	693	*/
	694
	695	/** @defgroup TIM_Slave_Mode TIM Slave Mode
	696	* @{
	697	*/
	698	#define TIM_SLAVEMODE_DISABLE (0x0000U)
	699	#define TIM_SLAVEMODE_RESET (0x0004U)
	700	#define TIM_SLAVEMODE_GATED (0x0005U)
	701	#define TIM_SLAVEMODE_TRIGGER (0x0006U)
	702	#define TIM_SLAVEMODE_EXTERNAL1 (0x0007U)
	703	/**
	704	* @}
	705	*/
	706
	707	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
	708	* @{
	709	*/
	710	#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
	711	#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
	712	/**
	713	* @}
	714	*/
	715
	716	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
	717	* @{
	718	*/
	719	#define TIM_TS_ITR0 (0x0000U)
	720	#define TIM_TS_ITR1 (0x0010U)
	721	#define TIM_TS_ITR2 (0x0020U)
	722	#define TIM_TS_ITR3 (0x0030U)
	723	#define TIM_TS_TI1F_ED (0x0040U)
	724	#define TIM_TS_TI1FP1 (0x0050U)
	725	#define TIM_TS_TI2FP2 (0x0060U)
	726	#define TIM_TS_ETRF (0x0070U)
	727	#define TIM_TS_NONE (0xFFFFU)
	728	/**
	729	* @}
	730	*/
	731
	732	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
	733	* @{
	734	*/
	735	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
	736	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
	737	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
	738	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
	739	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
	740	/**
	741	* @}
	742	*/
	743
	744	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
	745	* @{
	746	*/
	747	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
	748	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
	749	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
	750	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
	751	/**
	752	* @}
	753	*/
	754
	755	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
	756	* @{
	757	*/
	758	#define TIM_TI1SELECTION_CH1 (0x0000U)
	759	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
	760	/**
	761	* @}
	762	*/
	763
	764	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
	765	* @{
	766	*/
	767	#define TIM_DMABASE_CR1 (0x00000000)
	768	#define TIM_DMABASE_CR2 (0x00000001)
	769	#define TIM_DMABASE_SMCR (0x00000002)
	770	#define TIM_DMABASE_DIER (0x00000003)
	771	#define TIM_DMABASE_SR (0x00000004)
	772	#define TIM_DMABASE_EGR (0x00000005)
	773	#define TIM_DMABASE_CCMR1 (0x00000006)
	774	#define TIM_DMABASE_CCMR2 (0x00000007)
	775	#define TIM_DMABASE_CCER (0x00000008)
	776	#define TIM_DMABASE_CNT (0x00000009)
	777	#define TIM_DMABASE_PSC (0x0000000A)
	778	#define TIM_DMABASE_ARR (0x0000000B)
	779	#define TIM_DMABASE_RCR (0x0000000C)
	780	#define TIM_DMABASE_CCR1 (0x0000000D)
	781	#define TIM_DMABASE_CCR2 (0x0000000E)
	782	#define TIM_DMABASE_CCR3 (0x0000000F)
	783	#define TIM_DMABASE_CCR4 (0x00000010)
	784	#define TIM_DMABASE_BDTR (0x00000011)
	785	#define TIM_DMABASE_DCR (0x00000012)
	786	#define TIM_DMABASE_OR (0x00000013)
	787	/**
	788	* @}
	789	*/
	790
	791	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
	792	* @{
	793	*/
	794	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
	795	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
	796	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
	797	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
	798	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
	799	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
	800	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
	801	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
	802	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
	803	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
	804	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
	805	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
	806	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
	807	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
	808	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
	809	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
	810	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
	811	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
	812	/**
	813	* @}
	814	*/
	815
	816	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
	817	* @{
	818	*/
	819	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /!< Index of the DMA handle used for Update DMA requests /
	820	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
	821	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
	822	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
	823	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
	824	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /!< Index of the DMA handle used for Commutation DMA requests /
	825	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /!< Index of the DMA handle used for Trigger DMA requests /
	826	/**
	827	* @}
	828	*/
	829
	830	/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
	831	* @{
	832	*/
	833	#define TIM_CCx_ENABLE (0x0001U)
	834	#define TIM_CCx_DISABLE (0x0000U)
	835	#define TIM_CCxN_ENABLE (0x0004U)
	836	#define TIM_CCxN_DISABLE (0x0000U)
	837	/**
	838	* @}
	839	*/
	840
	841	/**
	842	* @}
	843	*/
	844
	845	/* Private Constants -----------------------------------------------------------*/
	846	/** @defgroup TIM_Private_Constants TIM Private Constants
	847	* @{
	848	*/
	849
	850	/* The counter of a timer instance is disabled only if all the CCx and CCxN
	851	channels have been disabled */
	852	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
	853	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
	854
	855	/**
	856	* @}
	857	*/
	858
	859	/* Private Macros -----------------------------------------------------------*/
	860	/** @defgroup TIM_Private_Macros TIM Private Macros
	861	* @{
	862	*/
	863
	864	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
	865	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
	866	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
	867	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
	868	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
	869
	870	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
	871	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
	872	((DIV) == TIM_CLOCKDIVISION_DIV4))
	873
	874	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
	875	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
	876
	877	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
	878	((MODE) == TIM_OCMODE_PWM2))
	879
	880	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
	881	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
	882	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
	883	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
	884	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
	885	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
	886
	887	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
	888	((STATE) == TIM_OCFAST_ENABLE))
	889
	890	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
	891	((POLARITY) == TIM_OCPOLARITY_LOW))
	892
	893	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
	894	((POLARITY) == TIM_OCNPOLARITY_LOW))
	895
	896	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
	897	((STATE) == TIM_OCIDLESTATE_RESET))
	898
	899	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
	900	((STATE) == TIM_OCNIDLESTATE_RESET))
	901
	902	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
	903	((CHANNEL) == TIM_CHANNEL_2) \|\| \
	904	((CHANNEL) == TIM_CHANNEL_3) \|\| \
	905	((CHANNEL) == TIM_CHANNEL_4) \|\| \
	906	((CHANNEL) == TIM_CHANNEL_ALL))
	907
	908	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
	909	((CHANNEL) == TIM_CHANNEL_2))
	910
	911	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
	912	((CHANNEL) == TIM_CHANNEL_2) \|\| \
	913	((CHANNEL) == TIM_CHANNEL_3))
	914
	915	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
	916	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
	917	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
	918
	919	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
	920	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
	921	((SELECTION) == TIM_ICSELECTION_TRC))
	922
	923	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
	924	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
	925	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
	926	((PRESCALER) == TIM_ICPSC_DIV8))
	927
	928	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
	929	((MODE) == TIM_OPMODE_REPETITIVE))
	930
	931	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
	932	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
	933	((MODE) == TIM_ENCODERMODE_TI12))
	934
	935	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
	936
	937	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
	938
	939	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
	940	((FLAG) == TIM_FLAG_CC1) \|\| \
	941	((FLAG) == TIM_FLAG_CC2) \|\| \
	942	((FLAG) == TIM_FLAG_CC3) \|\| \
	943	((FLAG) == TIM_FLAG_CC4) \|\| \
	944	((FLAG) == TIM_FLAG_COM) \|\| \
	945	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
	946	((FLAG) == TIM_FLAG_BREAK) \|\| \
	947	((FLAG) == TIM_FLAG_CC1OF) \|\| \
	948	((FLAG) == TIM_FLAG_CC2OF) \|\| \
	949	((FLAG) == TIM_FLAG_CC3OF) \|\| \
	950	((FLAG) == TIM_FLAG_CC4OF))
	951
	952	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
	953	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
	954	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
	955	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
	956	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
	957	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
	958	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
	959	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
	960	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
	961	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
	962
	963	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
	964	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
	965	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
	966	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
	967	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
	968
	969	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
	970	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
	971	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
	972	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
	973
	974	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
	975
	976	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
	977	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
	978
	979	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
	980	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
	981	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
	982	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
	983
	984	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
	985
	986	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
	987	((STATE) == TIM_OSSR_DISABLE))
	988
	989	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
	990	((STATE) == TIM_OSSI_DISABLE))
	991
	992	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
	993	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
	994	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
	995	((LEVEL) == TIM_LOCKLEVEL_3))
	996
	997	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
	998	((STATE) == TIM_BREAK_DISABLE))
	999
	1000	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
	1001	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
	1002
	1003	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
	1004	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
	1005
	1006	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
	1007	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
	1008	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
	1009	((SOURCE) == TIM_TRGO_OC1) \|\| \
	1010	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
	1011	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
	1012	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
	1013	((SOURCE) == TIM_TRGO_OC4REF))
	1014
	1015	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
	1016	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
	1017	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
	1018	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
	1019	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
	1020
	1021	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
	1022	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
	1023
	1024	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
	1025	((SELECTION) == TIM_TS_ITR1) \|\| \
	1026	((SELECTION) == TIM_TS_ITR2) \|\| \
	1027	((SELECTION) == TIM_TS_ITR3) \|\| \
	1028	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
	1029	((SELECTION) == TIM_TS_TI1FP1) \|\| \
	1030	((SELECTION) == TIM_TS_TI2FP2) \|\| \
	1031	((SELECTION) == TIM_TS_ETRF))
	1032
	1033	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
	1034	((SELECTION) == TIM_TS_ITR1) \|\| \
	1035	((SELECTION) == TIM_TS_ITR2) \|\| \
	1036	((SELECTION) == TIM_TS_ITR3) \|\| \
	1037	((SELECTION) == TIM_TS_NONE))
	1038
	1039	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
	1040	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
	1041	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
	1042	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
	1043	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
	1044
	1045	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
	1046	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
	1047	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
	1048	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
	1049
	1050	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
	1051
	1052	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
	1053	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
	1054
	1055	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
	1056	((BASE) == TIM_DMABASE_CR2) \|\| \
	1057	((BASE) == TIM_DMABASE_SMCR) \|\| \
	1058	((BASE) == TIM_DMABASE_DIER) \|\| \
	1059	((BASE) == TIM_DMABASE_SR) \|\| \
	1060	((BASE) == TIM_DMABASE_EGR) \|\| \
	1061	((BASE) == TIM_DMABASE_CCMR1) \|\| \
	1062	((BASE) == TIM_DMABASE_CCMR2) \|\| \
	1063	((BASE) == TIM_DMABASE_CCER) \|\| \
	1064	((BASE) == TIM_DMABASE_CNT) \|\| \
	1065	((BASE) == TIM_DMABASE_PSC) \|\| \
	1066	((BASE) == TIM_DMABASE_ARR) \|\| \
	1067	((BASE) == TIM_DMABASE_RCR) \|\| \
	1068	((BASE) == TIM_DMABASE_CCR1) \|\| \
	1069	((BASE) == TIM_DMABASE_CCR2) \|\| \
	1070	((BASE) == TIM_DMABASE_CCR3) \|\| \
	1071	((BASE) == TIM_DMABASE_CCR4) \|\| \
	1072	((BASE) == TIM_DMABASE_BDTR) \|\| \
	1073	((BASE) == TIM_DMABASE_DCR) \|\| \
	1074	((BASE) == TIM_DMABASE_OR))
	1075
	1076	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
	1077	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
	1078	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
	1079	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
	1080	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
	1081	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
	1082	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
	1083	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
	1084	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
	1085	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
	1086	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
	1087	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
	1088	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
	1089	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
	1090	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
	1091	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
	1092	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
	1093	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
	1094
	1095	#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
	1096
	1097	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
	1098
	1099	/** @brief Set TIM IC prescaler
	1100	* @param __HANDLE__ TIM handle
	1101	* @param __CHANNEL__ specifies TIM Channel
	1102	* @param __ICPSC__ specifies the prescaler value.
	1103	* @retval None
	1104	*/
	1105	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
	1106	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
	1107	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
	1108	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
	1109	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
	1110
	1111	/** @brief Reset TIM IC prescaler
	1112	* @param __HANDLE__ TIM handle
	1113	* @param __CHANNEL__ specifies TIM Channel
	1114	* @retval None
	1115	*/
	1116	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
	1117	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
	1118	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
	1119	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
	1120	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
	1121
	1122
	1123	/** @brief Set TIM IC polarity
	1124	* @param __HANDLE__ TIM handle
	1125	* @param __CHANNEL__ specifies TIM Channel
	1126	* @param __POLARITY__ specifies TIM Channel Polarity
	1127	* @retval None
	1128	*/
	1129	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
	1130	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
	1131	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
	1132	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
	1133	((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 12U)))
	1134
	1135	/** @brief Reset TIM IC polarity
	1136	* @param __HANDLE__ TIM handle
	1137	* @param __CHANNEL__ specifies TIM Channel
	1138	* @retval None
	1139	*/
	1140	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
	1141	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
	1142	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
	1143	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
	1144	((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P \| TIM_CCER_CC4NP)))
	1145
	1146	/**
	1147	* @}
	1148	*/
	1149
	1150	/* Private Functions --------------------------------------------------------*/
	1151	/** @addtogroup TIM_Private_Functions
	1152	* @{
	1153	*/
	1154	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
	1155	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
	1156	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
	1157	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
	1158	void TIM_DMAError(DMA_HandleTypeDef *hdma);
	1159	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
	1160	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
	1161	/**
	1162	* @}
	1163	*/
	1164
	1165	/* Exported macros -----------------------------------------------------------*/
	1166	/** @defgroup TIM_Exported_Macros TIM Exported Macros
	1167	* @{
	1168	*/
	1169
	1170	/** @brief Reset TIM handle state
	1171	* @param __HANDLE__ TIM handle.
	1172	* @retval None
	1173	*/
	1174	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
	1175
	1176	/**
	1177	* @brief Enable the TIM peripheral.
	1178	* @param __HANDLE__ TIM handle
	1179	* @retval None
	1180	*/
	1181	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
	1182
	1183	/**
	1184	* @brief Enable the TIM main Output.
	1185	* @param __HANDLE__ TIM handle
	1186	* @retval None
	1187	*/
	1188	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
	1189
	1190	/**
	1191	* @brief Disable the TIM peripheral.
	1192	* @param __HANDLE__ TIM handle
	1193	* @retval None
	1194	*/
	1195	#define __HAL_TIM_DISABLE(__HANDLE__) \
	1196	do { \
	1197	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
	1198	{ \
	1199	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
	1200	{ \
	1201	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
	1202	} \
	1203	} \
	1204	} while(0)
	1205	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
	1206	channels have been disabled */
	1207	/**
	1208	* @brief Disable the TIM main Output.
	1209	* @param __HANDLE__ TIM handle
	1210	* @retval None
	1211	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
	1212	*/
	1213	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
	1214	do { \
	1215	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
	1216	{ \
	1217	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
	1218	{ \
	1219	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
	1220	} \
	1221	} \
	1222	} while(0)
	1223
	1224	/* The Main Output Enable of a timer instance is disabled unconditionally */
	1225	/**
	1226	* @brief Disable the TIM main Output.
	1227	* @param __HANDLE__ TIM handle
	1228	* @retval None
	1229	* @note The Main Output Enable of a timer instance is disabled uncondiotionally
	1230	*/
	1231	#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
	1232
	1233	/**
	1234	* @brief Enables the specified TIM interrupt.
	1235	* @param __HANDLE__ specifies the TIM Handle.
	1236	* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
	1237	* This parameter can be one of the following values:
	1238	* @arg TIM_IT_UPDATE: Update interrupt
	1239	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
	1240	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
	1241	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
	1242	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
	1243	* @arg TIM_IT_COM: Commutation interrupt
	1244	* @arg TIM_IT_TRIGGER: Trigger interrupt
	1245	* @arg TIM_IT_BREAK: Break interrupt
	1246	* @retval None
	1247	*/
	1248	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
	1249
	1250	/**
	1251	* @brief Disables the specified TIM interrupt.
	1252	* @param __HANDLE__ specifies the TIM Handle.
	1253	* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
	1254	* This parameter can be one of the following values:
	1255	* @arg TIM_IT_UPDATE: Update interrupt
	1256	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
	1257	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
	1258	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
	1259	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
	1260	* @arg TIM_IT_COM: Commutation interrupt
	1261	* @arg TIM_IT_TRIGGER: Trigger interrupt
	1262	* @arg TIM_IT_BREAK: Break interrupt
	1263	* @retval None
	1264	*/
	1265	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
	1266
	1267	/**
	1268	* @brief Enables the specified DMA request.
	1269	* @param __HANDLE__ specifies the TIM Handle.
	1270	* @param __DMA__ specifies the TIM DMA request to enable.
	1271	* This parameter can be one of the following values:
	1272	* @arg TIM_DMA_UPDATE: Update DMA request
	1273	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
	1274	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
	1275	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
	1276	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
	1277	* @arg TIM_DMA_COM: Commutation DMA request
	1278	* @arg TIM_DMA_TRIGGER: Trigger DMA request
	1279	* @retval None
	1280	*/
	1281	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
	1282
	1283	/**
	1284	* @brief Disables the specified DMA request.
	1285	* @param __HANDLE__ specifies the TIM Handle.
	1286	* @param __DMA__ specifies the TIM DMA request to disable.
	1287	* This parameter can be one of the following values:
	1288	* @arg TIM_DMA_UPDATE: Update DMA request
	1289	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
	1290	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
	1291	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
	1292	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
	1293	* @arg TIM_DMA_COM: Commutation DMA request
	1294	* @arg TIM_DMA_TRIGGER: Trigger DMA request
	1295	* @retval None
	1296	*/
	1297	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
	1298
	1299	/**
	1300	* @brief Checks whether the specified TIM interrupt flag is set or not.
	1301	* @param __HANDLE__ specifies the TIM Handle.
	1302	* @param __FLAG__ specifies the TIM interrupt flag to check.
	1303	* This parameter can be one of the following values:
	1304	* @arg TIM_FLAG_UPDATE: Update interrupt flag
	1305	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
	1306	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
	1307	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
	1308	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
	1309	* @arg TIM_FLAG_COM: Commutation interrupt flag
	1310	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
	1311	* @arg TIM_FLAG_BREAK: Break interrupt flag
	1312	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
	1313	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
	1314	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
	1315	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
	1316	* @retval The new state of __FLAG__ (TRUE or FALSE).
	1317	*/
	1318	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
	1319
	1320	/**
	1321	* @brief Clears the specified TIM interrupt flag.
	1322	* @param __HANDLE__ specifies the TIM Handle.
	1323	* @param __FLAG__ specifies the TIM interrupt flag to clear.
	1324	* This parameter can be one of the following values:
	1325	* @arg TIM_FLAG_UPDATE: Update interrupt flag
	1326	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
	1327	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
	1328	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
	1329	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
	1330	* @arg TIM_FLAG_COM: Commutation interrupt flag
	1331	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
	1332	* @arg TIM_FLAG_BREAK: Break interrupt flag
	1333	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
	1334	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
	1335	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
	1336	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
	1337	* @retval The new state of __FLAG__ (TRUE or FALSE).
	1338	*/
	1339	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
	1340
	1341	/**
	1342	* @brief Checks whether the specified TIM interrupt has occurred or not.
	1343	* @param __HANDLE__ TIM handle
	1344	* @param __INTERRUPT__ specifies the TIM interrupt source to check.
	1345	* @retval The state of TIM_IT (SET or RESET).
	1346	*/
	1347	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
	1348
	1349	/**
	1350	* @brief Clear the TIM interrupt pending bits
	1351	* @param __HANDLE__ TIM handle
	1352	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
	1353	* @retval None
	1354	*/
	1355	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
	1356
	1357	/**
	1358	* @brief Indicates whether or not the TIM Counter is used as downcounter
	1359	* @param __HANDLE__ TIM handle.
	1360	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
	1361	* @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
	1362	mode.
	1363	*/
	1364	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
	1365
	1366	/**
	1367	* @brief Sets the TIM active prescaler register value on update event.
	1368	* @param __HANDLE__ TIM handle.
	1369	* @param __PRESC__ specifies the active prescaler register new value.
	1370	* @retval None
	1371	*/
	1372	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
	1373
	1374	/**
	1375	* @brief Sets the TIM Capture Compare Register value on runtime without
	1376	* calling another time ConfigChannel function.
	1377	* @param __HANDLE__ TIM handle.
	1378	* @param __CHANNEL__ TIM Channels to be configured.
	1379	* This parameter can be one of the following values:
	1380	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1381	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1382	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1383	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1384	* @param __COMPARE__ specifies the Capture Compare register new value.
	1385	* @retval None
	1386	*/
	1387	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
	1388	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
	1389
	1390	/**
	1391	* @brief Gets the TIM Capture Compare Register value on runtime
	1392	* @param __HANDLE__ TIM handle.
	1393	* @param __CHANNEL__ TIM Channel associated with the capture compare register
	1394	* This parameter can be one of the following values:
	1395	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
	1396	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
	1397	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
	1398	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
	1399	* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
	1400	*/
	1401	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
	1402	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
	1403
	1404	/**
	1405	* @brief Sets the TIM Counter Register value on runtime.
	1406	* @param __HANDLE__ TIM handle.
	1407	* @param __COUNTER__ specifies the Counter register new value.
	1408	* @retval None
	1409	*/
	1410	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
	1411
	1412	/**
	1413	* @brief Gets the TIM Counter Register value on runtime.
	1414	* @param __HANDLE__ TIM handle.
	1415	* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
	1416	*/
	1417	#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
	1418	((__HANDLE__)->Instance->CNT)
	1419
	1420	/**
	1421	* @brief Sets the TIM Autoreload Register value on runtime without calling
	1422	* another time any Init function.
	1423	* @param __HANDLE__ TIM handle.
	1424	* @param __AUTORELOAD__ specifies the Counter register new value.
	1425	* @retval None
	1426	*/
	1427	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
	1428	do{ \
	1429	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
	1430	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
	1431	} while(0)
	1432
	1433	/**
	1434	* @brief Gets the TIM Autoreload Register value on runtime
	1435	* @param __HANDLE__ TIM handle.
	1436	* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
	1437	*/
	1438	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
	1439	((__HANDLE__)->Instance->ARR)
	1440
	1441	/**
	1442	* @brief Sets the TIM Clock Division value on runtime without calling
	1443	* another time any Init function.
	1444	* @param __HANDLE__ TIM handle.
	1445	* @param __CKD__ specifies the clock division value.
	1446	* This parameter can be one of the following value:
	1447	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
	1448	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
	1449	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
	1450	* @retval None
	1451	*/
	1452	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
	1453	do{ \
	1454	(__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
	1455	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
	1456	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
	1457	} while(0)
	1458
	1459	/**
	1460	* @brief Gets the TIM Clock Division value on runtime
	1461	* @param __HANDLE__ TIM handle.
	1462	* @retval The clock division can be one of the following values:
	1463	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
	1464	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
	1465	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
	1466	*/
	1467	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
	1468	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
	1469
	1470	/**
	1471	* @brief Sets the TIM Output compare preload.
	1472	* @param __HANDLE__ TIM handle.
	1473	* @param __CHANNEL__ TIM Channels to be configured.
	1474	* This parameter can be one of the following values:
	1475	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1476	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1477	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1478	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1479	* @retval None
	1480	*/
	1481	#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
	1482	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1PE) :\
	1483	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2PE) :\
	1484	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3PE) :\
	1485	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4PE))
	1486
	1487	/**
	1488	* @brief Resets the TIM Output compare preload.
	1489	* @param __HANDLE__ TIM handle.
	1490	* @param __CHANNEL__ TIM Channels to be configured.
	1491	* This parameter can be one of the following values:
	1492	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1493	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1494	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1495	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1496	* @retval None
	1497	*/
	1498	#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
	1499	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
	1500	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
	1501	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
	1502	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
	1503
	1504
	1505	/**
	1506	* @brief Sets the TIM Input Capture prescaler on runtime without calling
	1507	* another time HAL_TIM_IC_ConfigChannel() function.
	1508	* @param __HANDLE__ TIM handle.
	1509	* @param __CHANNEL__ TIM Channels to be configured.
	1510	* This parameter can be one of the following values:
	1511	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1512	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1513	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1514	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1515	* @param __ICPSC__ specifies the Input Capture4 prescaler new value.
	1516	* This parameter can be one of the following values:
	1517	* @arg TIM_ICPSC_DIV1: no prescaler
	1518	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
	1519	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
	1520	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
	1521	* @retval None
	1522	*/
	1523	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
	1524	do{ \
	1525	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
	1526	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
	1527	} while(0)
	1528
	1529	/**
	1530	* @brief Gets the TIM Input Capture prescaler on runtime
	1531	* @param __HANDLE__ TIM handle.
	1532	* @param __CHANNEL__ TIM Channels to be configured.
	1533	* This parameter can be one of the following values:
	1534	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
	1535	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
	1536	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
	1537	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
	1538	* @retval The input capture prescaler can be one of the following values:
	1539	* @arg TIM_ICPSC_DIV1: no prescaler
	1540	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
	1541	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
	1542	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
	1543	*/
	1544	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
	1545	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
	1546	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
	1547	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
	1548	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
	1549
	1550	/**
	1551	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
	1552	* @param __HANDLE__ TIM handle.
	1553	* @note When the USR bit of the TIMx_CR1 register is set, only counter
	1554	* overflow/underflow generates an update interrupt or DMA request (if
	1555	* enabled)
	1556	* @retval None
	1557	*/
	1558	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
	1559	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
	1560
	1561	/**
	1562	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
	1563	* @param __HANDLE__ TIM handle.
	1564	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
	1565	* following events generate an update interrupt or DMA request (if
	1566	* enabled):
	1567	* (+) Counter overflow/underflow
	1568	* (+) Setting the UG bit
	1569	* (+) Update generation through the slave mode controller
	1570	* @retval None
	1571	*/
	1572	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
	1573	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
	1574
	1575	/**
	1576	* @brief Sets the TIM Capture x input polarity on runtime.
	1577	* @param __HANDLE__ TIM handle.
	1578	* @param __CHANNEL__ TIM Channels to be configured.
	1579	* This parameter can be one of the following values:
	1580	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
	1581	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
	1582	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
	1583	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
	1584	* @param __POLARITY__ Polarity for TIx source
	1585	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
	1586	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
	1587	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
	1588	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
	1589	* @retval None
	1590	*/
	1591	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
	1592	do{ \
	1593	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
	1594	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
	1595	}while(0)
	1596
	1597	/**
	1598	* @}
	1599	*/
	1600
	1601	/* Include TIM HAL Extension module */
	1602	#include "stm32f0xx_hal_tim_ex.h"
	1603
	1604	/* Exported functions --------------------------------------------------------*/
	1605	/** @addtogroup TIM_Exported_Functions
	1606	* @{
	1607	*/
	1608
	1609	/** @addtogroup TIM_Exported_Functions_Group1
	1610	* @{
	1611	*/
	1612	/* Time Base functions ********************************************************/
	1613	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
	1614	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
	1615	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
	1616	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
	1617	/* Blocking mode: Polling */
	1618	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
	1619	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
	1620	/* Non-Blocking mode: Interrupt */
	1621	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
	1622	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
	1623	/* Non-Blocking mode: DMA */
	1624	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
	1625	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
	1626	/**
	1627	* @}
	1628	*/
	1629
	1630	/** @addtogroup TIM_Exported_Functions_Group2
	1631	* @{
	1632	*/
	1633	/* Timer Output Compare functions **********************************************/
	1634	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
	1635	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
	1636	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
	1637	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
	1638	/* Blocking mode: Polling */
	1639	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
	1640	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
	1641	/* Non-Blocking mode: Interrupt */
	1642	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
	1643	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
	1644	/* Non-Blocking mode: DMA */
	1645	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
	1646	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
	1647
	1648	/**
	1649	* @}
	1650	*/
	1651
	1652	/** @addtogroup TIM_Exported_Functions_Group3
	1653	* @{
	1654	*/
	1655	/* Timer PWM functions *********************************************************/
	1656	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
	1657	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
	1658	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
	1659	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
	1660	/* Blocking mode: Polling */
	1661	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
	1662	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
	1663	/* Non-Blocking mode: Interrupt */
	1664	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
	1665	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
	1666	/* Non-Blocking mode: DMA */
	1667	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
	1668	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
	1669	/**
	1670	* @}
	1671	*/
	1672
	1673	/** @addtogroup TIM_Exported_Functions_Group4
	1674	* @{
	1675	*/
	1676	/* Timer Input Capture functions ***********************************************/
	1677	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
	1678	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
	1679	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
	1680	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
	1681	/* Blocking mode: Polling */
	1682	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
	1683	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
	1684	/* Non-Blocking mode: Interrupt */
	1685	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
	1686	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
	1687	/* Non-Blocking mode: DMA */
	1688	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
	1689	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
	1690	/**
	1691	* @}
	1692	*/
	1693
	1694	/** @addtogroup TIM_Exported_Functions_Group5
	1695	* @{
	1696	*/
	1697	/* Timer One Pulse functions ***************************************************/
	1698	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
	1699	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
	1700	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
	1701	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
	1702	/* Blocking mode: Polling */
	1703	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
	1704	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
	1705	/* Non-Blocking mode: Interrupt */
	1706	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
	1707	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
	1708	/**
	1709	* @}
	1710	*/
	1711
	1712	/** @addtogroup TIM_Exported_Functions_Group6
	1713	* @{
	1714	*/
	1715	/* Timer Encoder functions *****************************************************/
	1716	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
	1717	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
	1718	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
	1719	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
	1720	/* Blocking mode: Polling */
	1721	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
	1722	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
	1723	/* Non-Blocking mode: Interrupt */
	1724	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
	1725	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
	1726	/* Non-Blocking mode: DMA */
	1727	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
	1728	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
	1729
	1730	/**
	1731	* @}
	1732	*/
	1733
	1734	/** @addtogroup TIM_Exported_Functions_Group7
	1735	* @{
	1736	*/
	1737	/* Interrupt Handler functions **********************************************/
	1738	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
	1739	/**
	1740	* @}
	1741	*/
	1742
	1743	/** @addtogroup TIM_Exported_Functions_Group8
	1744	* @{
	1745	*/
	1746	/* Control functions *********************************************************/
	1747	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
	1748	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
	1749	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
	1750	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
	1751	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
	1752	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
	1753	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
	1754	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
	1755	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
	1756	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
	1757	uint32_t *BurstBuffer, uint32_t BurstLength);
	1758	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
	1759	uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
	1760	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
	1761	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
	1762	uint32_t *BurstBuffer, uint32_t BurstLength);
	1763	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
	1764	uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
	1765	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
	1766	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
	1767	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
	1768
	1769	/**
	1770	* @}
	1771	*/
	1772
	1773	/** @addtogroup TIM_Exported_Functions_Group9
	1774	* @{
	1775	*/
	1776	/* Callback in non blocking modes (Interrupt and DMA) *************************/
	1777	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
	1778	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
	1779	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
	1780	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
	1781	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
	1782	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
	1783	/**
	1784	* @}
	1785	*/
	1786
	1787	/** @addtogroup TIM_Exported_Functions_Group10
	1788	* @{
	1789	*/
	1790	/* Peripheral State functions **************************************************/
	1791	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
	1792	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
	1793	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
	1794	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
	1795	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
	1796	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
	1797
	1798	/**
	1799	* @}
	1800	*/
	1801
	1802	/**
	1803	* @}
	1804	*/
	1805
	1806	/* Private Functions --------------------------------------------------------*/
	1807	/** @addtogroup TIM_Private_Functions
	1808	* @{
	1809	*/
	1810	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
	1811	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
	1812	/**
	1813	* @}
	1814	*/
	1815
	1816	/**
	1817	* @}
	1818	*/
	1819
	1820	/**
	1821	* @}
	1822	*/
	1823
	1824	#ifdef __cplusplus
	1825	}
	1826	#endif
	1827
	1828	#endif /* __STM32F0xx_HAL_TIM_H */
	1829
	1830	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/