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| 8b51c7 | 1 | /** |
| Q | 2 | ****************************************************************************** |
| 3 | * @file stm32f0xx_hal_dma.h | |
| 4 | * @author MCD Application Team | |
| 5 | * @brief Header file of DMA HAL module. | |
| 6 | ****************************************************************************** | |
| 7 | * @attention | |
| 8 | * | |
| 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> | |
| 10 | * | |
| 11 | * Redistribution and use in source and binary forms, with or without modification, | |
| 12 | * are permitted provided that the following conditions are met: | |
| 13 | * 1. Redistributions of source code must retain the above copyright notice, | |
| 14 | * this list of conditions and the following disclaimer. | |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, | |
| 16 | * this list of conditions and the following disclaimer in the documentation | |
| 17 | * and/or other materials provided with the distribution. | |
| 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
| 19 | * may be used to endorse or promote products derived from this software | |
| 20 | * without specific prior written permission. | |
| 21 | * | |
| 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
| 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
| 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
| 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
| 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
| 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 32 | * | |
| 33 | ****************************************************************************** | |
| 34 | */ | |
| 35 | ||
| 36 | /* Define to prevent recursive inclusion -------------------------------------*/ | |
| 37 | #ifndef __STM32F0xx_HAL_DMA_H | |
| 38 | #define __STM32F0xx_HAL_DMA_H | |
| 39 | ||
| 40 | #ifdef __cplusplus | |
| 41 | extern "C" { | |
| 42 | #endif | |
| 43 | ||
| 44 | /* Includes ------------------------------------------------------------------*/ | |
| 45 | #include "stm32f0xx_hal_def.h" | |
| 46 | ||
| 47 | /** @addtogroup STM32F0xx_HAL_Driver | |
| 48 | * @{ | |
| 49 | */ | |
| 50 | ||
| 51 | /** @addtogroup DMA | |
| 52 | * @{ | |
| 53 | */ | |
| 54 | ||
| 55 | /* Exported types ------------------------------------------------------------*/ | |
| 56 | ||
| 57 | /** @defgroup DMA_Exported_Types DMA Exported Types | |
| 58 | * @{ | |
| 59 | */ | |
| 60 | ||
| 61 | /** | |
| 62 | * @brief DMA Configuration Structure definition | |
| 63 | */ | |
| 64 | typedef struct | |
| 65 | { | |
| 66 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, | |
| 67 | from memory to memory or from peripheral to memory. | |
| 68 | This parameter can be a value of @ref DMA_Data_transfer_direction */ | |
| 69 | ||
| 70 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. | |
| 71 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ | |
| 72 | ||
| 73 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. | |
| 74 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ | |
| 75 | ||
| 76 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. | |
| 77 | This parameter can be a value of @ref DMA_Peripheral_data_size */ | |
| 78 | ||
| 79 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. | |
| 80 | This parameter can be a value of @ref DMA_Memory_data_size */ | |
| 81 | ||
| 82 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. | |
| 83 | This parameter can be a value of @ref DMA_mode | |
| 84 | @note The circular buffer mode cannot be used if the memory-to-memory | |
| 85 | data transfer is configured on the selected Channel */ | |
| 86 | ||
| 87 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. | |
| 88 | This parameter can be a value of @ref DMA_Priority_level */ | |
| 89 | } DMA_InitTypeDef; | |
| 90 | ||
| 91 | /** | |
| 92 | * @brief HAL DMA State structures definition | |
| 93 | */ | |
| 94 | typedef enum | |
| 95 | { | |
| 96 | HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ | |
| 97 | HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ | |
| 98 | HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ | |
| 99 | HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ | |
| 100 | }HAL_DMA_StateTypeDef; | |
| 101 | ||
| 102 | /** | |
| 103 | * @brief HAL DMA Error Code structure definition | |
| 104 | */ | |
| 105 | typedef enum | |
| 106 | { | |
| 107 | HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ | |
| 108 | HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ | |
| 109 | }HAL_DMA_LevelCompleteTypeDef; | |
| 110 | ||
| 111 | /** | |
| 112 | * @brief HAL DMA Callback ID structure definition | |
| 113 | */ | |
| 114 | typedef enum | |
| 115 | { | |
| 116 | HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ | |
| 117 | HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ | |
| 118 | HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ | |
| 119 | HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ | |
| 120 | HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ | |
| 121 | ||
| 122 | }HAL_DMA_CallbackIDTypeDef; | |
| 123 | ||
| 124 | /** | |
| 125 | * @brief DMA handle Structure definition | |
| 126 | */ | |
| 127 | typedef struct __DMA_HandleTypeDef | |
| 128 | { | |
| 129 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ | |
| 130 | ||
| 131 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ | |
| 132 | ||
| 133 | HAL_LockTypeDef Lock; /*!< DMA locking object */ | |
| 134 | ||
| 135 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ | |
| 136 | ||
| 137 | void *Parent; /*!< Parent object state */ | |
| 138 | ||
| 139 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ | |
| 140 | ||
| 141 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ | |
| 142 | ||
| 143 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ | |
| 144 | ||
| 145 | void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ | |
| 146 | ||
| 147 | __IO uint32_t ErrorCode; /*!< DMA Error code */ | |
| 148 | ||
| 149 | DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ | |
| 150 | ||
| 151 | uint32_t ChannelIndex; /*!< DMA Channel Index */ | |
| 152 | } DMA_HandleTypeDef; | |
| 153 | ||
| 154 | /** | |
| 155 | * @} | |
| 156 | */ | |
| 157 | ||
| 158 | /* Exported constants --------------------------------------------------------*/ | |
| 159 | ||
| 160 | /** @defgroup DMA_Exported_Constants DMA Exported Constants | |
| 161 | * @{ | |
| 162 | */ | |
| 163 | ||
| 164 | /** @defgroup DMA_Error_Code DMA Error Code | |
| 165 | * @{ | |
| 166 | */ | |
| 167 | #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ | |
| 168 | #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ | |
| 169 | #define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ | |
| 170 | #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ | |
| 171 | #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ | |
| 172 | /** | |
| 173 | * @} | |
| 174 | */ | |
| 175 | ||
| 176 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction | |
| 177 | * @{ | |
| 178 | */ | |
| 179 | #define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ | |
| 180 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ | |
| 181 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ | |
| 182 | ||
| 183 | /** | |
| 184 | * @} | |
| 185 | */ | |
| 186 | ||
| 187 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode | |
| 188 | * @{ | |
| 189 | */ | |
| 190 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ | |
| 191 | #define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ | |
| 192 | /** | |
| 193 | * @} | |
| 194 | */ | |
| 195 | ||
| 196 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode | |
| 197 | * @{ | |
| 198 | */ | |
| 199 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ | |
| 200 | #define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ | |
| 201 | /** | |
| 202 | * @} | |
| 203 | */ | |
| 204 | ||
| 205 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size | |
| 206 | * @{ | |
| 207 | */ | |
| 208 | #define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ | |
| 209 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ | |
| 210 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ | |
| 211 | /** | |
| 212 | * @} | |
| 213 | */ | |
| 214 | ||
| 215 | /** @defgroup DMA_Memory_data_size DMA Memory data size | |
| 216 | * @{ | |
| 217 | */ | |
| 218 | #define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ | |
| 219 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ | |
| 220 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ | |
| 221 | /** | |
| 222 | * @} | |
| 223 | */ | |
| 224 | ||
| 225 | /** @defgroup DMA_mode DMA mode | |
| 226 | * @{ | |
| 227 | */ | |
| 228 | #define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ | |
| 229 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ | |
| 230 | /** | |
| 231 | * @} | |
| 232 | */ | |
| 233 | ||
| 234 | /** @defgroup DMA_Priority_level DMA Priority level | |
| 235 | * @{ | |
| 236 | */ | |
| 237 | #define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ | |
| 238 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ | |
| 239 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ | |
| 240 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ | |
| 241 | /** | |
| 242 | * @} | |
| 243 | */ | |
| 244 | ||
| 245 | ||
| 246 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions | |
| 247 | * @{ | |
| 248 | */ | |
| 249 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) | |
| 250 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) | |
| 251 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) | |
| 252 | /** | |
| 253 | * @} | |
| 254 | */ | |
| 255 | ||
| 256 | /** @defgroup DMA_flag_definitions DMA flag definitions | |
| 257 | * @{ | |
| 258 | */ | |
| 259 | ||
| 260 | #define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */ | |
| 261 | #define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */ | |
| 262 | #define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */ | |
| 263 | #define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */ | |
| 264 | #define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */ | |
| 265 | #define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */ | |
| 266 | #define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */ | |
| 267 | #define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */ | |
| 268 | #define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */ | |
| 269 | #define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */ | |
| 270 | #define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */ | |
| 271 | #define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */ | |
| 272 | #define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */ | |
| 273 | #define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */ | |
| 274 | #define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */ | |
| 275 | #define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */ | |
| 276 | #define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */ | |
| 277 | #define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */ | |
| 278 | #define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */ | |
| 279 | #define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */ | |
| 280 | #define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */ | |
| 281 | #define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */ | |
| 282 | #define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */ | |
| 283 | #define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */ | |
| 284 | #define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */ | |
| 285 | #define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */ | |
| 286 | #define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */ | |
| 287 | #define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */ | |
| 288 | ||
| 289 | /** | |
| 290 | * @} | |
| 291 | */ | |
| 292 | ||
| 293 | #if defined(SYSCFG_CFGR1_DMA_RMP) | |
| 294 | /** @defgroup HAL_DMA_remapping HAL DMA remapping | |
| 295 | * Elements values convention: 0xYYYYYYYY | |
| 296 | * - YYYYYYYY : Position in the SYSCFG register CFGR1 | |
| 297 | * @{ | |
| 298 | */ | |
| 299 | #define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap | |
| 300 | 0: No remap (ADC DMA requests mapped on DMA channel 1 | |
| 301 | 1: Remap (ADC DMA requests mapped on DMA channel 2 */ | |
| 302 | #define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap | |
| 303 | 0: No remap (USART1_TX DMA request mapped on DMA channel 2 | |
| 304 | 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ | |
| 305 | #define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap | |
| 306 | 0: No remap (USART1_RX DMA request mapped on DMA channel 3 | |
| 307 | 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ | |
| 308 | #define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap | |
| 309 | 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) | |
| 310 | 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ | |
| 311 | #define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap | |
| 312 | 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 | |
| 313 | 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ | |
| 314 | #if defined (STM32F070xB) | |
| 315 | #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only. | |
| 316 | 0: Disabled, need to remap before use | |
| 317 | 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ | |
| 318 | ||
| 319 | #endif | |
| 320 | ||
| 321 | #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) | |
| 322 | #define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only | |
| 323 | 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) | |
| 324 | 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ | |
| 325 | #define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only | |
| 326 | 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) | |
| 327 | 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ | |
| 328 | #define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. | |
| 329 | 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) | |
| 330 | 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ | |
| 331 | #define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. | |
| 332 | 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) | |
| 333 | 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ | |
| 334 | #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. | |
| 335 | 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) | |
| 336 | 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ | |
| 337 | #define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. | |
| 338 | 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) | |
| 339 | 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ | |
| 340 | #define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. | |
| 341 | 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) | |
| 342 | 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ | |
| 343 | #define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. | |
| 344 | 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) | |
| 345 | 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ | |
| 346 | #define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. | |
| 347 | 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) | |
| 348 | 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ | |
| 349 | #endif | |
| 350 | ||
| 351 | /** | |
| 352 | * @} | |
| 353 | */ | |
| 354 | ||
| 355 | #endif /* SYSCFG_CFGR1_DMA_RMP */ | |
| 356 | /** | |
| 357 | * @} | |
| 358 | */ | |
| 359 | ||
| 360 | /* Exported macro ------------------------------------------------------------*/ | |
| 361 | /** @defgroup DMA_Exported_Macros DMA Exported Macros | |
| 362 | * @{ | |
| 363 | */ | |
| 364 | ||
| 365 | /** @brief Reset DMA handle state | |
| 366 | * @param __HANDLE__ DMA handle. | |
| 367 | * @retval None | |
| 368 | */ | |
| 369 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) | |
| 370 | ||
| 371 | /** | |
| 372 | * @brief Enable the specified DMA Channel. | |
| 373 | * @param __HANDLE__ DMA handle | |
| 374 | * @retval None | |
| 375 | */ | |
| 376 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) | |
| 377 | ||
| 378 | /** | |
| 379 | * @brief Disable the specified DMA Channel. | |
| 380 | * @param __HANDLE__ DMA handle | |
| 381 | * @retval None | |
| 382 | */ | |
| 383 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) | |
| 384 | ||
| 385 | ||
| 386 | /* Interrupt & Flag management */ | |
| 387 | ||
| 388 | /** | |
| 389 | * @brief Enables the specified DMA Channel interrupts. | |
| 390 | * @param __HANDLE__ DMA handle | |
| 391 | * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. | |
| 392 | * This parameter can be any combination of the following values: | |
| 393 | * @arg DMA_IT_TC: Transfer complete interrupt mask | |
| 394 | * @arg DMA_IT_HT: Half transfer complete interrupt mask | |
| 395 | * @arg DMA_IT_TE: Transfer error interrupt mask | |
| 396 | * @retval None | |
| 397 | */ | |
| 398 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) | |
| 399 | ||
| 400 | /** | |
| 401 | * @brief Disables the specified DMA Channel interrupts. | |
| 402 | * @param __HANDLE__ DMA handle | |
| 403 | * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. | |
| 404 | * This parameter can be any combination of the following values: | |
| 405 | * @arg DMA_IT_TC: Transfer complete interrupt mask | |
| 406 | * @arg DMA_IT_HT: Half transfer complete interrupt mask | |
| 407 | * @arg DMA_IT_TE: Transfer error interrupt mask | |
| 408 | * @retval None | |
| 409 | */ | |
| 410 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) | |
| 411 | ||
| 412 | /** | |
| 413 | * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. | |
| 414 | * @param __HANDLE__ DMA handle | |
| 415 | * @param __INTERRUPT__ specifies the DMA interrupt source to check. | |
| 416 | * This parameter can be one of the following values: | |
| 417 | * @arg DMA_IT_TC: Transfer complete interrupt mask | |
| 418 | * @arg DMA_IT_HT: Half transfer complete interrupt mask | |
| 419 | * @arg DMA_IT_TE: Transfer error interrupt mask | |
| 420 | * @retval The state of DMA_IT (SET or RESET). | |
| 421 | */ | |
| 422 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) | |
| 423 | ||
| 424 | /** | |
| 425 | * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. | |
| 426 | * @param __HANDLE__ DMA handle | |
| 427 | * | |
| 428 | * @retval The number of remaining data units in the current DMA Channel transfer. | |
| 429 | */ | |
| 430 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) | |
| 431 | ||
| 432 | #if defined(SYSCFG_CFGR1_DMA_RMP) | |
| 433 | /** @brief DMA remapping enable/disable macros | |
| 434 | * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping | |
| 435 | */ | |
| 436 | #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ | |
| 437 | SYSCFG->CFGR1 |= (__DMA_REMAP__); \ | |
| 438 | }while(0) | |
| 439 | #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ | |
| 440 | SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ | |
| 441 | }while(0) | |
| 442 | #endif /* SYSCFG_CFGR1_DMA_RMP */ | |
| 443 | ||
| 444 | /** | |
| 445 | * @} | |
| 446 | */ | |
| 447 | ||
| 448 | /* Include DMA HAL Extension module */ | |
| 449 | #include "stm32f0xx_hal_dma_ex.h" | |
| 450 | ||
| 451 | /* Exported functions --------------------------------------------------------*/ | |
| 452 | /** @addtogroup DMA_Exported_Functions | |
| 453 | * @{ | |
| 454 | */ | |
| 455 | ||
| 456 | /** @addtogroup DMA_Exported_Functions_Group1 | |
| 457 | * @{ | |
| 458 | */ | |
| 459 | /* Initialization and de-initialization functions *****************************/ | |
| 460 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); | |
| 461 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); | |
| 462 | /** | |
| 463 | * @} | |
| 464 | */ | |
| 465 | ||
| 466 | /** @addtogroup DMA_Exported_Functions_Group2 | |
| 467 | * @{ | |
| 468 | */ | |
| 469 | /* Input and Output operation functions *****************************************************/ | |
| 470 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); | |
| 471 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); | |
| 472 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); | |
| 473 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); | |
| 474 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); | |
| 475 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); | |
| 476 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); | |
| 477 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); | |
| 478 | ||
| 479 | /** | |
| 480 | * @} | |
| 481 | */ | |
| 482 | ||
| 483 | /** @addtogroup DMA_Exported_Functions_Group3 | |
| 484 | * @{ | |
| 485 | */ | |
| 486 | /* Peripheral State and Error functions ***************************************/ | |
| 487 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); | |
| 488 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); | |
| 489 | /** | |
| 490 | * @} | |
| 491 | */ | |
| 492 | ||
| 493 | /** | |
| 494 | * @} | |
| 495 | */ | |
| 496 | ||
| 497 | /** @addtogroup DMA_Private_Macros | |
| 498 | * @{ | |
| 499 | */ | |
| 500 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ | |
| 501 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ | |
| 502 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) | |
| 503 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ | |
| 504 | ((STATE) == DMA_PINC_DISABLE)) | |
| 505 | ||
| 506 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ | |
| 507 | ((STATE) == DMA_MINC_DISABLE)) | |
| 508 | ||
| 509 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ | |
| 510 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ | |
| 511 | ((SIZE) == DMA_PDATAALIGN_WORD)) | |
| 512 | ||
| 513 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ | |
| 514 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ | |
| 515 | ((SIZE) == DMA_MDATAALIGN_WORD )) | |
| 516 | ||
| 517 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ | |
| 518 | ((MODE) == DMA_CIRCULAR)) | |
| 519 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ | |
| 520 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ | |
| 521 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ | |
| 522 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) | |
| 523 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) | |
| 524 | ||
| 525 | #if defined(SYSCFG_CFGR1_DMA_RMP) | |
| 526 | ||
| 527 | #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) | |
| 528 | #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ | |
| 529 | ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ | |
| 530 | ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ | |
| 531 | ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ | |
| 532 | ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \ | |
| 533 | ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \ | |
| 534 | ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \ | |
| 535 | ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \ | |
| 536 | ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \ | |
| 537 | ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ | |
| 538 | ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \ | |
| 539 | ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \ | |
| 540 | ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \ | |
| 541 | ((RMP) == DMA_REMAP_TIM3_DMA_CH6)) | |
| 542 | #elif defined (STM32F070xB) | |
| 543 | #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ | |
| 544 | ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ | |
| 545 | ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ | |
| 546 | ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ | |
| 547 | ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ | |
| 548 | ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) | |
| 549 | #else | |
| 550 | #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ | |
| 551 | ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ | |
| 552 | ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ | |
| 553 | ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ | |
| 554 | ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) | |
| 555 | #endif | |
| 556 | ||
| 557 | #endif /* SYSCFG_CFGR1_DMA_RMP */ | |
| 558 | ||
| 559 | ||
| 560 | /** | |
| 561 | * @} | |
| 562 | */ | |
| 563 | ||
| 564 | /** | |
| 565 | * @} | |
| 566 | */ | |
| 567 | ||
| 568 | /** | |
| 569 | * @} | |
| 570 | */ | |
| 571 | ||
| 572 | #ifdef __cplusplus | |
| 573 | } | |
| 574 | #endif | |
| 575 | ||
| 576 | #endif /* __STM32F0xx_HAL_DMA_H */ | |
| 577 | ||
| 578 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ | |
| 579 | ||
