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2023-10-08 483170e190a0dd4666b2a63e5d31466052ba0c6a

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483170	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_ll_spi.c
	4	* @author MCD Application Team
	5	* @brief SPI LL module driver.
	6	******************************************************************************
	7	* @attention
	8	*
	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	10	*
	11	* Redistribution and use in source and binary forms, with or without modification,
	12	* are permitted provided that the following conditions are met:
	13	* 1. Redistributions of source code must retain the above copyright notice,
	14	* this list of conditions and the following disclaimer.
	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
	16	* this list of conditions and the following disclaimer in the documentation
	17	* and/or other materials provided with the distribution.
	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	19	* may be used to endorse or promote products derived from this software
	20	* without specific prior written permission.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	******************************************************************************
	34	*/
	35	#if defined(USE_FULL_LL_DRIVER)
	36
	37	/* Includes ------------------------------------------------------------------*/
	38	#include "stm32f0xx_ll_spi.h"
	39	#include "stm32f0xx_ll_bus.h"
	40	#include "stm32f0xx_ll_rcc.h"
	41
	42	#ifdef USE_FULL_ASSERT
	43	#include "stm32_assert.h"
	44	#else
	45	#define assert_param(expr) ((void)0U)
	46	#endif
	47
	48	/** @addtogroup STM32F0xx_LL_Driver
	49	* @{
	50	*/
	51
	52	#if defined (SPI1) \|\| defined (SPI2)
	53
	54	/** @addtogroup SPI_LL
	55	* @{
	56	*/
	57
	58	/* Private types -------------------------------------------------------------*/
	59	/* Private variables ---------------------------------------------------------*/
	60
	61	/* Private constants ---------------------------------------------------------*/
	62	/** @defgroup SPI_LL_Private_Constants SPI Private Constants
	63	* @{
	64	*/
	65	/* SPI registers Masks */
	66	#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA \| SPI_CR1_CPOL \| SPI_CR1_MSTR \| \
	67	SPI_CR1_BR \| SPI_CR1_LSBFIRST \| SPI_CR1_SSI \| \
	68	SPI_CR1_SSM \| SPI_CR1_RXONLY \| SPI_CR1_CRCL \| \
	69	SPI_CR1_CRCNEXT \| SPI_CR1_CRCEN \| SPI_CR1_BIDIOE \| \
	70	SPI_CR1_BIDIMODE)
	71	/**
	72	* @}
	73	*/
	74
	75	/* Private macros ------------------------------------------------------------*/
	76	/** @defgroup SPI_LL_Private_Macros SPI Private Macros
	77	* @{
	78	*/
	79	#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
	80	\|\| ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
	81	\|\| ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
	82	\|\| ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
	83
	84	#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
	85	\|\| ((__VALUE__) == LL_SPI_MODE_SLAVE))
	86
	87	#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
	88	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
	89	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
	90	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
	91	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
	92	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
	93	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
	94	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
	95	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
	96	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
	97	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
	98	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
	99	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
	100
	101	#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
	102	\|\| ((__VALUE__) == LL_SPI_POLARITY_HIGH))
	103
	104	#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
	105	\|\| ((__VALUE__) == LL_SPI_PHASE_2EDGE))
	106
	107	#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
	108	\|\| ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
	109	\|\| ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
	110
	111	#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
	112	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
	113	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
	114	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
	115	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
	116	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
	117	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
	118	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
	119
	120	#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
	121	\|\| ((__VALUE__) == LL_SPI_MSB_FIRST))
	122
	123	#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
	124	\|\| ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
	125
	126	#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
	127
	128	/**
	129	* @}
	130	*/
	131
	132	/* Private function prototypes -----------------------------------------------*/
	133
	134	/* Exported functions --------------------------------------------------------*/
	135	/** @addtogroup SPI_LL_Exported_Functions
	136	* @{
	137	*/
	138
	139	/** @addtogroup SPI_LL_EF_Init
	140	* @{
	141	*/
	142
	143	/**
	144	* @brief De-initialize the SPI registers to their default reset values.
	145	* @param SPIx SPI Instance
	146	* @retval An ErrorStatus enumeration value:
	147	* - SUCCESS: SPI registers are de-initialized
	148	* - ERROR: SPI registers are not de-initialized
	149	*/
	150	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
	151	{
	152	ErrorStatus status = ERROR;
	153
	154	/* Check the parameters */
	155	assert_param(IS_SPI_ALL_INSTANCE(SPIx));
	156
	157	#if defined(SPI1)
	158	if (SPIx == SPI1)
	159	{
	160	/* Force reset of SPI clock */
	161	LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SPI1);
	162
	163	/* Release reset of SPI clock */
	164	LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SPI1);
	165
	166	status = SUCCESS;
	167	}
	168	#endif /* SPI1 */
	169	#if defined(SPI2)
	170	if (SPIx == SPI2)
	171	{
	172	/* Force reset of SPI clock */
	173	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
	174
	175	/* Release reset of SPI clock */
	176	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
	177
	178	status = SUCCESS;
	179	}
	180	#endif /* SPI2 */
	181
	182	return status;
	183	}
	184
	185	/**
	186	* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
	187	* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
	188	* SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
	189	* @param SPIx SPI Instance
	190	* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
	191	* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
	192	*/
	193	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct)
	194	{
	195	ErrorStatus status = ERROR;
	196
	197	/* Check the SPI Instance SPIx*/
	198	assert_param(IS_SPI_ALL_INSTANCE(SPIx));
	199
	200	/* Check the SPI parameters from SPI_InitStruct*/
	201	assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
	202	assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
	203	assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
	204	assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
	205	assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
	206	assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
	207	assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
	208	assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
	209	assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
	210
	211	if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
	212	{
	213	/*---------------------------- SPIx CR1 Configuration ------------------------
	214	* Configure SPIx CR1 with parameters:
	215	* - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
	216	* - Master/Slave Mode: SPI_CR1_MSTR bit
	217	* - ClockPolarity: SPI_CR1_CPOL bit
	218	* - ClockPhase: SPI_CR1_CPHA bit
	219	* - NSS management: SPI_CR1_SSM bit
	220	* - BaudRate prescaler: SPI_CR1_BR[2:0] bits
	221	* - BitOrder: SPI_CR1_LSBFIRST bit
	222	* - CRCCalculation: SPI_CR1_CRCEN bit
	223	*/
	224	MODIFY_REG(SPIx->CR1,
	225	SPI_CR1_CLEAR_MASK,
	226	SPI_InitStruct->TransferDirection \| SPI_InitStruct->Mode \|
	227	SPI_InitStruct->ClockPolarity \| SPI_InitStruct->ClockPhase \|
	228	SPI_InitStruct->NSS \| SPI_InitStruct->BaudRate \|
	229	SPI_InitStruct->BitOrder \| SPI_InitStruct->CRCCalculation);
	230
	231	/*---------------------------- SPIx CR2 Configuration ------------------------
	232	* Configure SPIx CR2 with parameters:
	233	* - DataWidth: DS[3:0] bits
	234	* - NSS management: SSOE bit
	235	*/
	236	MODIFY_REG(SPIx->CR2,
	237	SPI_CR2_DS \| SPI_CR2_SSOE,
	238	SPI_InitStruct->DataWidth \| (SPI_InitStruct->NSS >> 16U));
	239
	240	/*---------------------------- SPIx CRCPR Configuration ----------------------
	241	* Configure SPIx CRCPR with parameters:
	242	* - CRCPoly: CRCPOLY[15:0] bits
	243	*/
	244	if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
	245	{
	246	assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
	247	LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
	248	}
	249	status = SUCCESS;
	250	}
	251
	252	#if defined (SPI_I2S_SUPPORT)
	253	/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
	254	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
	255	#endif /* SPI_I2S_SUPPORT */
	256	return status;
	257	}
	258
	259	/**
	260	* @brief Set each @ref LL_SPI_InitTypeDef field to default value.
	261	* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
	262	* whose fields will be set to default values.
	263	* @retval None
	264	*/
	265	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
	266	{
	267	/* Set SPI_InitStruct fields to default values */
	268	SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
	269	SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
	270	SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
	271	SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
	272	SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
	273	SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
	274	SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
	275	SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
	276	SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
	277	SPI_InitStruct->CRCPoly = 7U;
	278	}
	279
	280	/**
	281	* @}
	282	*/
	283
	284	/**
	285	* @}
	286	*/
	287
	288	/**
	289	* @}
	290	*/
	291
	292	#if defined(SPI_I2S_SUPPORT)
	293	/** @addtogroup I2S_LL
	294	* @{
	295	*/
	296
	297	/* Private types -------------------------------------------------------------*/
	298	/* Private variables ---------------------------------------------------------*/
	299	/* Private constants ---------------------------------------------------------*/
	300	/** @defgroup I2S_LL_Private_Constants I2S Private Constants
	301	* @{
	302	*/
	303	/* I2S registers Masks */
	304	#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN \| \
	305	SPI_I2SCFGR_CKPOL \| SPI_I2SCFGR_I2SSTD \| \
	306	SPI_I2SCFGR_I2SCFG \| SPI_I2SCFGR_I2SMOD )
	307
	308	#define I2S_I2SPR_CLEAR_MASK 0x0002U
	309	/**
	310	* @}
	311	*/
	312	/* Private macros ------------------------------------------------------------*/
	313	/** @defgroup I2S_LL_Private_Macros I2S Private Macros
	314	* @{
	315	*/
	316
	317	#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
	318	\|\| ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
	319	\|\| ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
	320	\|\| ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
	321
	322	#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
	323	\|\| ((__VALUE__) == LL_I2S_POLARITY_HIGH))
	324
	325	#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
	326	\|\| ((__VALUE__) == LL_I2S_STANDARD_MSB) \
	327	\|\| ((__VALUE__) == LL_I2S_STANDARD_LSB) \
	328	\|\| ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
	329	\|\| ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
	330
	331	#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
	332	\|\| ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
	333	\|\| ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
	334	\|\| ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
	335
	336	#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
	337	\|\| ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
	338
	339	#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
	340	&& ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
	341	\|\| ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
	342
	343	#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
	344
	345	#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
	346	\|\| ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
	347	/**
	348	* @}
	349	*/
	350
	351	/* Private function prototypes -----------------------------------------------*/
	352
	353	/* Exported functions --------------------------------------------------------*/
	354	/** @addtogroup I2S_LL_Exported_Functions
	355	* @{
	356	*/
	357
	358	/** @addtogroup I2S_LL_EF_Init
	359	* @{
	360	*/
	361
	362	/**
	363	* @brief De-initialize the SPI/I2S registers to their default reset values.
	364	* @param SPIx SPI Instance
	365	* @retval An ErrorStatus enumeration value:
	366	* - SUCCESS: SPI registers are de-initialized
	367	* - ERROR: SPI registers are not de-initialized
	368	*/
	369	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
	370	{
	371	return LL_SPI_DeInit(SPIx);
	372	}
	373
	374	/**
	375	* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
	376	* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
	377	* SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
	378	* @param SPIx SPI Instance
	379	* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
	380	* @retval An ErrorStatus enumeration value:
	381	* - SUCCESS: SPI registers are Initialized
	382	* - ERROR: SPI registers are not Initialized
	383	*/
	384	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct)
	385	{
	386	uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
	387	uint32_t tmp = 0U;
	388	LL_RCC_ClocksTypeDef rcc_clocks;
	389	uint32_t sourceclock = 0U;
	390	ErrorStatus status = ERROR;
	391
	392	/* Check the I2S parameters */
	393	assert_param(IS_I2S_ALL_INSTANCE(SPIx));
	394	assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
	395	assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
	396	assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
	397	assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
	398	assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
	399	assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
	400
	401	if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
	402	{
	403	/*---------------------------- SPIx I2SCFGR Configuration --------------------
	404	* Configure SPIx I2SCFGR with parameters:
	405	* - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
	406	* - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
	407	* - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
	408	* - ClockPolarity: SPI_I2SCFGR_CKPOL bit
	409	*/
	410
	411	/* Write to SPIx I2SCFGR */
	412	MODIFY_REG(SPIx->I2SCFGR,
	413	I2S_I2SCFGR_CLEAR_MASK,
	414	I2S_InitStruct->Mode \| I2S_InitStruct->Standard \|
	415	I2S_InitStruct->DataFormat \| I2S_InitStruct->ClockPolarity \|
	416	SPI_I2SCFGR_I2SMOD);
	417
	418	/*---------------------------- SPIx I2SPR Configuration ----------------------
	419	* Configure SPIx I2SPR with parameters:
	420	* - MCLKOutput: SPI_I2SPR_MCKOE bit
	421	* - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
	422	*/
	423
	424	/* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
	425	* else, default values are used: i2sodd = 0U, i2sdiv = 2U.
	426	*/
	427	if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
	428	{
	429	/* Check the frame length (For the Prescaler computing)
	430	* Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
	431	*/
	432	if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
	433	{
	434	/* Packet length is 32 bits */
	435	packetlength = 2U;
	436	}
	437
	438	/* I2S Clock source is System clock: Get System Clock frequency */
	439	LL_RCC_GetSystemClocksFreq(&rcc_clocks);
	440
	441	/* Get the source clock value: based on System Clock value */
	442	sourceclock = rcc_clocks.SYSCLK_Frequency;
	443
	444	/* Compute the Real divider depending on the MCLK output state with a floating point */
	445	if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
	446	{
	447	/* MCLK output is enabled */
	448	tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
	449	}
	450	else
	451	{
	452	/* MCLK output is disabled */
	453	tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
	454	}
	455
	456	/* Remove the floating point */
	457	tmp = tmp / 10U;
	458
	459	/* Check the parity of the divider */
	460	i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
	461
	462	/* Compute the i2sdiv prescaler */
	463	i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
	464
	465	/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
	466	i2sodd = (uint16_t)(i2sodd << 8U);
	467	}
	468
	469	/* Test if the divider is 1 or 0 or greater than 0xFF */
	470	if ((i2sdiv < 2U) \|\| (i2sdiv > 0xFFU))
	471	{
	472	/* Set the default values */
	473	i2sdiv = 2U;
	474	i2sodd = 0U;
	475	}
	476
	477	/* Write to SPIx I2SPR register the computed value */
	478	WRITE_REG(SPIx->I2SPR, i2sdiv \| i2sodd \| I2S_InitStruct->MCLKOutput);
	479
	480	status = SUCCESS;
	481	}
	482	return status;
	483	}
	484
	485	/**
	486	* @brief Set each @ref LL_I2S_InitTypeDef field to default value.
	487	* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
	488	* whose fields will be set to default values.
	489	* @retval None
	490	*/
	491	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
	492	{
	493	/--------------- Reset I2S init structure parameters values -----------------/
	494	I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
	495	I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
	496	I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
	497	I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
	498	I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
	499	I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
	500	}
	501
	502	/**
	503	* @brief Set linear and parity prescaler.
	504	* @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
	505	* Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
	506	* @param SPIx SPI Instance
	507	* @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
	508	* @param PrescalerParity This parameter can be one of the following values:
	509	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
	510	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
	511	* @retval None
	512	*/
	513	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
	514	{
	515	/* Check the I2S parameters */
	516	assert_param(IS_I2S_ALL_INSTANCE(SPIx));
	517	assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
	518	assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
	519
	520	/* Write to SPIx I2SPR */
	521	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV \| SPI_I2SPR_ODD, PrescalerLinear \| (PrescalerParity << 8U));
	522	}
	523
	524	/**
	525	* @}
	526	*/
	527
	528	/**
	529	* @}
	530	*/
	531
	532	/**
	533	* @}
	534	*/
	535	#endif /* SPI_I2S_SUPPORT */
	536
	537	#endif /* defined (SPI1) \|\| defined (SPI2) */
	538
	539	/**
	540	* @}
	541	*/
	542
	543	#endif /* USE_FULL_LL_DRIVER */
	544
	545	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/