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483170	1	/**
Q	2	******************************************************************************
	3	* @file stm32f0xx_hal_adc.c
	4	* @author MCD Application Team
	5	* @brief This file provides firmware functions to manage the following
	6	* functionalities of the Analog to Digital Convertor (ADC)
	7	* peripheral:
	8	* + Initialization and de-initialization functions
	9	* ++ Initialization and Configuration of ADC
	10	* + Operation functions
	11	* ++ Start, stop, get result of conversions of regular
	12	* group, using 3 possible modes: polling, interruption or DMA.
	13	* + Control functions
	14	* ++ Channels configuration on regular group
	15	* ++ Analog Watchdog configuration
	16	* + State functions
	17	* ++ ADC state machine management
	18	* ++ Interrupts and flags management
	19	* Other functions (extended functions) are available in file
	20	* "stm32f0xx_hal_adc_ex.c".
	21	*
	22	@verbatim
	23	==============================================================================
	24	##### ADC peripheral features #####
	25	==============================================================================
	26	[..]
	27	(+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
	28
	29	(+) Interrupt generation at the end of regular conversion and in case of
	30	analog watchdog or overrun events.
	31
	32	(+) Single and continuous conversion modes.
	33
	34	(+) Scan mode for conversion of several channels sequentially.
	35
	36	(+) Data alignment with in-built data coherency.
	37
	38	(+) Programmable sampling time (common for all channels)
	39
	40	(+) ADC conversion of regular group.
	41
	42	(+) External trigger (timer or EXTI) with configurable polarity
	43
	44	(+) DMA request generation for transfer of conversions data of regular group.
	45
	46	(+) ADC calibration
	47
	48	(+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
	49	slower speed.
	50
	51	(+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
	52	Vdda or to an external voltage reference).
	53
	54
	55	##### How to use this driver #####
	56	==============================================================================
	57	[..]
	58
	59	* Configuration of top level parameters related to ADC *
	60	============================================================
	61	[..]
	62
	63	(#) Enable the ADC interface
	64	(++) As prerequisite, ADC clock must be configured at RCC top level.
	65	Caution: On STM32F0, ADC clock frequency max is 14MHz (refer
	66	to device datasheet).
	67	Therefore, ADC clock prescaler must be configured in
	68	function of ADC clock source frequency to remain below
	69	this maximum frequency.
	70
	71	(++) Two clock settings are mandatory:
	72	(+++) ADC clock (core clock, also possibly conversion clock).
	73
	74	(+++) ADC clock (conversions clock).
	75	Two possible clock sources: synchronous clock derived from APB clock
	76	or asynchronous clock derived from ADC dedicated HSI RC oscillator
	77	14MHz.
	78	If asynchronous clock is selected, parameter "HSI14State" must be set either:
	79	- to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control
	80	the HSI14 oscillator enable/disable (if not used to supply the main
	81	system clock): feature used if ADC mode LowPowerAutoPowerOff is
	82	enabled.
	83	- to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator
	84	always enabled: can be used to supply the main system clock.
	85
	86	(+++) Example:
	87	Into HAL_ADC_MspInit() (recommended code location) or with
	88	other device clock parameters configuration:
	89	(+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory)
	90
	91	HI14 enable or let under control of ADC: (optional: if asynchronous clock selected)
	92	(+++) RCC_OscInitTypeDef RCC_OscInitStructure;
	93	(+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
	94	(+++) RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
	95	(+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL;
	96	(+++) RCC_OscInitStructure.PLL... (optional if used for system clock)
	97	(+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
	98
	99	(++) ADC clock source and clock prescaler are configured at ADC level with
	100	parameter "ClockPrescaler" using function HAL_ADC_Init().
	101
	102	(#) ADC pins configuration
	103	(++) Enable the clock for the ADC GPIOs
	104	using macro __HAL_RCC_GPIOx_CLK_ENABLE()
	105	(++) Configure these ADC pins in analog mode
	106	using function HAL_GPIO_Init()
	107
	108	(#) Optionally, in case of usage of ADC with interruptions:
	109	(++) Configure the NVIC for ADC
	110	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
	111	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
	112	into the function of corresponding ADC interruption vector
	113	ADCx_IRQHandler().
	114
	115	(#) Optionally, in case of usage of DMA:
	116	(++) Configure the DMA (DMA channel, mode normal or circular, ...)
	117	using function HAL_DMA_Init().
	118	(++) Configure the NVIC for DMA
	119	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
	120	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
	121	into the function of corresponding DMA interruption vector
	122	DMAx_Channelx_IRQHandler().
	123
	124	* Configuration of ADC, group regular, channels parameters *
	125	================================================================
	126	[..]
	127
	128	(#) Configure the ADC parameters (resolution, data alignment, ...)
	129	and regular group parameters (conversion trigger, sequencer, ...)
	130	using function HAL_ADC_Init().
	131
	132	(#) Configure the channels for regular group parameters (channel number,
	133	channel rank into sequencer, ..., into regular group)
	134	using function HAL_ADC_ConfigChannel().
	135
	136	(#) Optionally, configure the analog watchdog parameters (channels
	137	monitored, thresholds, ...)
	138	using function HAL_ADC_AnalogWDGConfig().
	139
	140	* Execution of ADC conversions *
	141	====================================
	142	[..]
	143
	144	(#) Optionally, perform an automatic ADC calibration to improve the
	145	conversion accuracy
	146	using function HAL_ADCEx_Calibration_Start().
	147
	148	(#) ADC driver can be used among three modes: polling, interruption,
	149	transfer by DMA.
	150
	151	(++) ADC conversion by polling:
	152	(+++) Activate the ADC peripheral and start conversions
	153	using function HAL_ADC_Start()
	154	(+++) Wait for ADC conversion completion
	155	using function HAL_ADC_PollForConversion()
	156	(+++) Retrieve conversion results
	157	using function HAL_ADC_GetValue()
	158	(+++) Stop conversion and disable the ADC peripheral
	159	using function HAL_ADC_Stop()
	160
	161	(++) ADC conversion by interruption:
	162	(+++) Activate the ADC peripheral and start conversions
	163	using function HAL_ADC_Start_IT()
	164	(+++) Wait for ADC conversion completion by call of function
	165	HAL_ADC_ConvCpltCallback()
	166	(this function must be implemented in user program)
	167	(+++) Retrieve conversion results
	168	using function HAL_ADC_GetValue()
	169	(+++) Stop conversion and disable the ADC peripheral
	170	using function HAL_ADC_Stop_IT()
	171
	172	(++) ADC conversion with transfer by DMA:
	173	(+++) Activate the ADC peripheral and start conversions
	174	using function HAL_ADC_Start_DMA()
	175	(+++) Wait for ADC conversion completion by call of function
	176	HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
	177	(these functions must be implemented in user program)
	178	(+++) Conversion results are automatically transferred by DMA into
	179	destination variable address.
	180	(+++) Stop conversion and disable the ADC peripheral
	181	using function HAL_ADC_Stop_DMA()
	182
	183	[..]
	184
	185	(@) Callback functions must be implemented in user program:
	186	(+@) HAL_ADC_ErrorCallback()
	187	(+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
	188	(+@) HAL_ADC_ConvCpltCallback()
	189	(+@) HAL_ADC_ConvHalfCpltCallback
	190
	191	* Deinitialization of ADC *
	192	============================================================
	193	[..]
	194
	195	(#) Disable the ADC interface
	196	(++) ADC clock can be hard reset and disabled at RCC top level.
	197	(++) Hard reset of ADC peripherals
	198	using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
	199	(++) ADC clock disable
	200	using the equivalent macro/functions as configuration step.
	201	(+++) Example:
	202	Into HAL_ADC_MspDeInit() (recommended code location) or with
	203	other device clock parameters configuration:
	204	(+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
	205	(+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
	206	(+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
	207
	208	(#) ADC pins configuration
	209	(++) Disable the clock for the ADC GPIOs
	210	using macro __HAL_RCC_GPIOx_CLK_DISABLE()
	211
	212	(#) Optionally, in case of usage of ADC with interruptions:
	213	(++) Disable the NVIC for ADC
	214	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
	215
	216	(#) Optionally, in case of usage of DMA:
	217	(++) Deinitialize the DMA
	218	using function HAL_DMA_Init().
	219	(++) Disable the NVIC for DMA
	220	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
	221
	222	[..]
	223
	224	@endverbatim
	225	******************************************************************************
	226	* @attention
	227	*
	228	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
	229	*
	230	* Redistribution and use in source and binary forms, with or without modification,
	231	* are permitted provided that the following conditions are met:
	232	* 1. Redistributions of source code must retain the above copyright notice,
	233	* this list of conditions and the following disclaimer.
	234	* 2. Redistributions in binary form must reproduce the above copyright notice,
	235	* this list of conditions and the following disclaimer in the documentation
	236	* and/or other materials provided with the distribution.
	237	* 3. Neither the name of STMicroelectronics nor the names of its contributors
	238	* may be used to endorse or promote products derived from this software
	239	* without specific prior written permission.
	240	*
	241	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	242	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	243	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	244	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
	245	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	246	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	247	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	248	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	249	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	250	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	251	*
	252	******************************************************************************
	253	*/
	254
	255	/* Includes ------------------------------------------------------------------*/
	256	#include "stm32f0xx_hal.h"
	257
	258	/** @addtogroup STM32F0xx_HAL_Driver
	259	* @{
	260	*/
	261
	262	/** @defgroup ADC ADC
	263	* @brief ADC HAL module driver
	264	* @{
	265	*/
	266
	267	#ifdef HAL_ADC_MODULE_ENABLED
	268
	269	/* Private typedef -----------------------------------------------------------*/
	270	/* Private define ------------------------------------------------------------*/
	271	/** @defgroup ADC_Private_Constants ADC Private Constants
	272	* @{
	273	*/
	274
	275	/* Fixed timeout values for ADC calibration, enable settling time, disable */
	276	/* settling time. */
	277	/* Values defined to be higher than worst cases: low clock frequency, */
	278	/* maximum prescaler. */
	279	/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
	280	/* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */
	281	/* Unit: ms */
	282	#define ADC_ENABLE_TIMEOUT ( 2U)
	283	#define ADC_DISABLE_TIMEOUT ( 2U)
	284	#define ADC_STOP_CONVERSION_TIMEOUT ( 2U)
	285
	286	/* Delay for ADC stabilization time. */
	287	/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
	288	/* Unit: us */
	289	#define ADC_STAB_DELAY_US ( 1U)
	290
	291	/* Delay for temperature sensor stabilization time. */
	292	/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
	293	/* Unit: us */
	294	#define ADC_TEMPSENSOR_DELAY_US ( 10U)
	295
	296	/**
	297	* @}
	298	*/
	299
	300	/* Private macro -------------------------------------------------------------*/
	301	/* Private variables ---------------------------------------------------------*/
	302	/* Private function prototypes -----------------------------------------------*/
	303	/** @defgroup ADC_Private_Functions ADC Private Functions
	304	* @{
	305	*/
	306	static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
	307	static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
	308	static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc);
	309	static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
	310	static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
	311	static void ADC_DMAError(DMA_HandleTypeDef *hdma);
	312	/**
	313	* @}
	314	*/
	315
	316	/* Exported functions ---------------------------------------------------------*/
	317
	318	/** @defgroup ADC_Exported_Functions ADC Exported Functions
	319	* @{
	320	*/
	321
	322	/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
	323	* @brief Initialization and Configuration functions
	324	*
	325	@verbatim
	326	===============================================================================
	327	##### Initialization and de-initialization functions #####
	328	===============================================================================
	329	[..] This section provides functions allowing to:
	330	(+) Initialize and configure the ADC.
	331	(+) De-initialize the ADC
	332	@endverbatim
	333	* @{
	334	*/
	335
	336	/**
	337	* @brief Initializes the ADC peripheral and regular group according to
	338	* parameters specified in structure "ADC_InitTypeDef".
	339	* @note As prerequisite, ADC clock must be configured at RCC top level
	340	* depending on both possible clock sources: APB clock of HSI clock.
	341	* See commented example code below that can be copied and uncommented
	342	* into HAL_ADC_MspInit().
	343	* @note Possibility to update parameters on the fly:
	344	* This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
	345	* coming from ADC state reset. Following calls to this function can
	346	* be used to reconfigure some parameters of ADC_InitTypeDef
	347	* structure on the fly, without modifying MSP configuration. If ADC
	348	* MSP has to be modified again, HAL_ADC_DeInit() must be called
	349	* before HAL_ADC_Init().
	350	* The setting of these parameters is conditioned to ADC state.
	351	* For parameters constraints, see comments of structure
	352	* "ADC_InitTypeDef".
	353	* @note This function configures the ADC within 2 scopes: scope of entire
	354	* ADC and scope of regular group. For parameters details, see comments
	355	* of structure "ADC_InitTypeDef".
	356	* @param hadc ADC handle
	357	* @retval HAL status
	358	*/
	359	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
	360	{
	361	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
	362	uint32_t tmpCFGR1 = 0U;
	363
	364	/* Check ADC handle */
	365	if(hadc == NULL)
	366	{
	367	return HAL_ERROR;
	368	}
	369
	370	/* Check the parameters */
	371	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	372	assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
	373	assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
	374	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
	375	assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
	376	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
	377	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
	378	assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
	379	assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
	380	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
	381	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
	382	assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
	383	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
	384	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
	385
	386	/* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
	387	/* at RCC top level depending on both possible clock sources: */
	388	/* APB clock or HSI clock. */
	389	/* Refer to header of this file for more details on clock enabling procedure*/
	390
	391	/* Actions performed only if ADC is coming from state reset: */
	392	/* - Initialization of ADC MSP */
	393	/* - ADC voltage regulator enable */
	394	if (hadc->State == HAL_ADC_STATE_RESET)
	395	{
	396	/* Initialize ADC error code */
	397	ADC_CLEAR_ERRORCODE(hadc);
	398
	399	/* Allocate lock resource and initialize it */
	400	hadc->Lock = HAL_UNLOCKED;
	401
	402	/* Init the low level hardware */
	403	HAL_ADC_MspInit(hadc);
	404	}
	405
	406	/* Configuration of ADC parameters if previous preliminary actions are */
	407	/* correctly completed. */
	408	/* and if there is no conversion on going on regular group (ADC can be */
	409	/* enabled anyway, in case of call of this function to update a parameter */
	410	/* on the fly). */
	411	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
	412	(tmp_hal_status == HAL_OK) &&
	413	(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
	414	{
	415	/* Set ADC state */
	416	ADC_STATE_CLR_SET(hadc->State,
	417	HAL_ADC_STATE_REG_BUSY,
	418	HAL_ADC_STATE_BUSY_INTERNAL);
	419
	420	/* Parameters update conditioned to ADC state: */
	421	/* Parameters that can be updated only when ADC is disabled: */
	422	/* - ADC clock mode */
	423	/* - ADC clock prescaler */
	424	/* - ADC resolution */
	425	if (ADC_IS_ENABLE(hadc) == RESET)
	426	{
	427	/* Some parameters of this register are not reset, since they are set */
	428	/* by other functions and must be kept in case of usage of this */
	429	/* function on the fly (update of a parameter of ADC_InitTypeDef */
	430	/* without needing to reconfigure all other ADC groups/channels */
	431	/* parameters): */
	432	/* - internal measurement paths: Vbat, temperature sensor, Vref */
	433	/* (set into HAL_ADC_ConfigChannel() ) */
	434
	435	/* Configuration of ADC resolution */
	436	MODIFY_REG(hadc->Instance->CFGR1,
	437	ADC_CFGR1_RES ,
	438	hadc->Init.Resolution );
	439
	440	/* Configuration of ADC clock mode: clock source AHB or HSI with */
	441	/* selectable prescaler */
	442	MODIFY_REG(hadc->Instance->CFGR2 ,
	443	ADC_CFGR2_CKMODE ,
	444	hadc->Init.ClockPrescaler );
	445	}
	446
	447	/* Configuration of ADC: */
	448	/* - discontinuous mode */
	449	/* - LowPowerAutoWait mode */
	450	/* - LowPowerAutoPowerOff mode */
	451	/* - continuous conversion mode */
	452	/* - overrun */
	453	/* - external trigger to start conversion */
	454	/* - external trigger polarity */
	455	/* - data alignment */
	456	/* - resolution */
	457	/* - scan direction */
	458	/* - DMA continuous request */
	459	hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN \|
	460	ADC_CFGR1_AUTOFF \|
	461	ADC_CFGR1_AUTDLY \|
	462	ADC_CFGR1_CONT \|
	463	ADC_CFGR1_OVRMOD \|
	464	ADC_CFGR1_EXTSEL \|
	465	ADC_CFGR1_EXTEN \|
	466	ADC_CFGR1_ALIGN \|
	467	ADC_CFGR1_SCANDIR \|
	468	ADC_CFGR1_DMACFG );
	469
	470	tmpCFGR1 \|= (ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) \|
	471	ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) \|
	472	ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) \|
	473	ADC_CFGR1_OVERRUN(hadc->Init.Overrun) \|
	474	hadc->Init.DataAlign \|
	475	ADC_SCANDIR(hadc->Init.ScanConvMode) \|
	476	ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
	477
	478	/* Enable discontinuous mode only if continuous mode is disabled */
	479	if (hadc->Init.DiscontinuousConvMode == ENABLE)
	480	{
	481	if (hadc->Init.ContinuousConvMode == DISABLE)
	482	{
	483	/* Enable the selected ADC group regular discontinuous mode */
	484	tmpCFGR1 \|= ADC_CFGR1_DISCEN;
	485	}
	486	else
	487	{
	488	/* ADC regular group discontinuous was intended to be enabled, */
	489	/* but ADC regular group modes continuous and sequencer discontinuous */
	490	/* cannot be enabled simultaneously. */
	491
	492	/* Update ADC state machine to error */
	493	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
	494
	495	/* Set ADC error code to ADC IP internal error */
	496	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
	497	}
	498	}
	499
	500	/* Enable external trigger if trigger selection is different of software */
	501	/* start. */
	502	/* Note: This configuration keeps the hardware feature of parameter */
	503	/* ExternalTrigConvEdge "trigger edge none" equivalent to */
	504	/* software start. */
	505	if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
	506	{
	507	tmpCFGR1 \|= ( hadc->Init.ExternalTrigConv \|
	508	hadc->Init.ExternalTrigConvEdge );
	509	}
	510
	511	/* Update ADC configuration register with previous settings */
	512	hadc->Instance->CFGR1 \|= tmpCFGR1;
	513
	514	/* Channel sampling time configuration */
	515	/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
	516	/* (obsolete): sampling time set in this function if parameter */
	517	/* "SamplingTimeCommon" has been set to a valid sampling time. */
	518	/* Otherwise, sampling time is set into ADC channel initialization */
	519	/* structure with parameter "SamplingTime" (obsolete). */
	520	if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
	521	{
	522	/* Channel sampling time configuration */
	523	/* Clear the old sample time */
	524	hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
	525
	526	/* Set the new sample time */
	527	hadc->Instance->SMPR \|= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon);
	528	}
	529
	530	/* Check back that ADC registers have effectively been configured to */
	531	/* ensure of no potential problem of ADC core IP clocking. */
	532	/* Check through register CFGR1 (excluding analog watchdog configuration: */
	533	/* set into separate dedicated function, and bits of ADC resolution set */
	534	/* out of temporary variable 'tmpCFGR1'). */
	535	if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_RES))
	536	== tmpCFGR1)
	537	{
	538	/* Set ADC error code to none */
	539	ADC_CLEAR_ERRORCODE(hadc);
	540
	541	/* Set the ADC state */
	542	ADC_STATE_CLR_SET(hadc->State,
	543	HAL_ADC_STATE_BUSY_INTERNAL,
	544	HAL_ADC_STATE_READY);
	545	}
	546	else
	547	{
	548	/* Update ADC state machine to error */
	549	ADC_STATE_CLR_SET(hadc->State,
	550	HAL_ADC_STATE_BUSY_INTERNAL,
	551	HAL_ADC_STATE_ERROR_INTERNAL);
	552
	553	/* Set ADC error code to ADC IP internal error */
	554	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
	555
	556	tmp_hal_status = HAL_ERROR;
	557	}
	558
	559	}
	560	else
	561	{
	562	/* Update ADC state machine to error */
	563	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
	564
	565	tmp_hal_status = HAL_ERROR;
	566	}
	567
	568	/* Return function status */
	569	return tmp_hal_status;
	570	}
	571
	572
	573	/**
	574	* @brief Deinitialize the ADC peripheral registers to their default reset
	575	* values, with deinitialization of the ADC MSP.
	576	* @note For devices with several ADCs: reset of ADC common registers is done
	577	* only if all ADCs sharing the same common group are disabled.
	578	* If this is not the case, reset of these common parameters reset is
	579	* bypassed without error reporting: it can be the intended behaviour in
	580	* case of reset of a single ADC while the other ADCs sharing the same
	581	* common group is still running.
	582	* @param hadc ADC handle
	583	* @retval HAL status
	584	*/
	585	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
	586	{
	587	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
	588
	589	/* Check ADC handle */
	590	if(hadc == NULL)
	591	{
	592	return HAL_ERROR;
	593	}
	594
	595	/* Check the parameters */
	596	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	597
	598	/* Set ADC state */
	599	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
	600
	601	/* Stop potential conversion on going, on regular group */
	602	tmp_hal_status = ADC_ConversionStop(hadc);
	603
	604	/* Disable ADC peripheral if conversions are effectively stopped */
	605	if (tmp_hal_status == HAL_OK)
	606	{
	607	/* Disable the ADC peripheral */
	608	tmp_hal_status = ADC_Disable(hadc);
	609
	610	/* Check if ADC is effectively disabled */
	611	if (tmp_hal_status != HAL_ERROR)
	612	{
	613	/* Change ADC state */
	614	hadc->State = HAL_ADC_STATE_READY;
	615	}
	616	}
	617
	618
	619	/* Configuration of ADC parameters if previous preliminary actions are */
	620	/* correctly completed. */
	621	if (tmp_hal_status != HAL_ERROR)
	622	{
	623
	624	/* ========== Reset ADC registers ========== */
	625	/* Reset register IER */
	626	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD \| ADC_IT_OVR \|
	627	ADC_IT_EOS \| ADC_IT_EOC \|
	628	ADC_IT_EOSMP \| ADC_IT_RDY ) );
	629
	630	/* Reset register ISR */
	631	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD \| ADC_FLAG_OVR \|
	632	ADC_FLAG_EOS \| ADC_FLAG_EOC \|
	633	ADC_FLAG_EOSMP \| ADC_FLAG_RDY ) );
	634
	635	/* Reset register CR */
	636	/* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
	637	/* "read-set": no direct reset applicable. */
	638
	639	/* Reset register CFGR1 */
	640	hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_DISCEN \|
	641	ADC_CFGR1_AUTOFF \| ADC_CFGR1_WAIT \| ADC_CFGR1_CONT \| ADC_CFGR1_OVRMOD \|
	642	ADC_CFGR1_EXTEN \| ADC_CFGR1_EXTSEL \| ADC_CFGR1_ALIGN \| ADC_CFGR1_RES \|
	643	ADC_CFGR1_SCANDIR \| ADC_CFGR1_DMACFG \| ADC_CFGR1_DMAEN );
	644
	645	/* Reset register CFGR2 */
	646	/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
	647	/* already done above. */
	648	hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
	649
	650	/* Reset register SMPR */
	651	hadc->Instance->SMPR &= ~ADC_SMPR_SMP;
	652
	653	/* Reset register TR1 */
	654	hadc->Instance->TR &= ~(ADC_TR_HT \| ADC_TR_LT);
	655
	656	/* Reset register CHSELR */
	657	hadc->Instance->CHSELR &= ~(ADC_CHSELR_CHSEL18 \| ADC_CHSELR_CHSEL17 \| ADC_CHSELR_CHSEL16 \|
	658	ADC_CHSELR_CHSEL15 \| ADC_CHSELR_CHSEL14 \| ADC_CHSELR_CHSEL13 \| ADC_CHSELR_CHSEL12 \|
	659	ADC_CHSELR_CHSEL11 \| ADC_CHSELR_CHSEL10 \| ADC_CHSELR_CHSEL9 \| ADC_CHSELR_CHSEL8 \|
	660	ADC_CHSELR_CHSEL7 \| ADC_CHSELR_CHSEL6 \| ADC_CHSELR_CHSEL5 \| ADC_CHSELR_CHSEL4 \|
	661	ADC_CHSELR_CHSEL3 \| ADC_CHSELR_CHSEL2 \| ADC_CHSELR_CHSEL1 \| ADC_CHSELR_CHSEL0 );
	662
	663	/* Reset register DR */
	664	/* bits in access mode read only, no direct reset applicable*/
	665
	666	/* Reset register CCR */
	667	ADC->CCR &= ~(ADC_CCR_ALL);
	668
	669	/* ========== Hard reset ADC peripheral ========== */
	670	/* Performs a global reset of the entire ADC peripheral: ADC state is */
	671	/* forced to a similar state after device power-on. */
	672	/* If needed, copy-paste and uncomment the following reset code into */
	673	/* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
	674	/* */
	675	/* __HAL_RCC_ADC1_FORCE_RESET() */
	676	/* __HAL_RCC_ADC1_RELEASE_RESET() */
	677
	678	/* DeInit the low level hardware */
	679	HAL_ADC_MspDeInit(hadc);
	680
	681	/* Set ADC error code to none */
	682	ADC_CLEAR_ERRORCODE(hadc);
	683
	684	/* Set ADC state */
	685	hadc->State = HAL_ADC_STATE_RESET;
	686	}
	687
	688	/* Process unlocked */
	689	__HAL_UNLOCK(hadc);
	690
	691	/* Return function status */
	692	return tmp_hal_status;
	693	}
	694
	695
	696	/**
	697	* @brief Initializes the ADC MSP.
	698	* @param hadc ADC handle
	699	* @retval None
	700	*/
	701	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
	702	{
	703	/* Prevent unused argument(s) compilation warning */
	704	UNUSED(hadc);
	705
	706	/* NOTE : This function should not be modified. When the callback is needed,
	707	function HAL_ADC_MspInit must be implemented in the user file.
	708	*/
	709	}
	710
	711	/**
	712	* @brief DeInitializes the ADC MSP.
	713	* @param hadc ADC handle
	714	* @retval None
	715	*/
	716	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
	717	{
	718	/* Prevent unused argument(s) compilation warning */
	719	UNUSED(hadc);
	720
	721	/* NOTE : This function should not be modified. When the callback is needed,
	722	function HAL_ADC_MspDeInit must be implemented in the user file.
	723	*/
	724	}
	725
	726	/**
	727	* @}
	728	*/
	729
	730	/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
	731	* @brief IO operation functions
	732	*
	733	@verbatim
	734	===============================================================================
	735	##### IO operation functions #####
	736	===============================================================================
	737	[..] This section provides functions allowing to:
	738	(+) Start conversion of regular group.
	739	(+) Stop conversion of regular group.
	740	(+) Poll for conversion complete on regular group.
	741	(+) Poll for conversion event.
	742	(+) Get result of regular channel conversion.
	743	(+) Start conversion of regular group and enable interruptions.
	744	(+) Stop conversion of regular group and disable interruptions.
	745	(+) Handle ADC interrupt request
	746	(+) Start conversion of regular group and enable DMA transfer.
	747	(+) Stop conversion of regular group and disable ADC DMA transfer.
	748	@endverbatim
	749	* @{
	750	*/
	751
	752	/**
	753	* @brief Enables ADC, starts conversion of regular group.
	754	* Interruptions enabled in this function: None.
	755	* @param hadc ADC handle
	756	* @retval HAL status
	757	*/
	758	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
	759	{
	760	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
	761
	762	/* Check the parameters */
	763	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	764
	765	/* Perform ADC enable and conversion start if no conversion is on going */
	766	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
	767	{
	768	/* Process locked */
	769	__HAL_LOCK(hadc);
	770
	771	/* Enable the ADC peripheral */
	772	/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
	773	/* performed automatically by hardware. */
	774	if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
	775	{
	776	tmp_hal_status = ADC_Enable(hadc);
	777	}
	778
	779	/* Start conversion if ADC is effectively enabled */
	780	if (tmp_hal_status == HAL_OK)
	781	{
	782	/* Set ADC state */
	783	/* - Clear state bitfield related to regular group conversion results */
	784	/* - Set state bitfield related to regular operation */
	785	ADC_STATE_CLR_SET(hadc->State,
	786	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR \| HAL_ADC_STATE_REG_EOSMP,
	787	HAL_ADC_STATE_REG_BUSY);
	788
	789	/* Reset ADC all error code fields */
	790	ADC_CLEAR_ERRORCODE(hadc);
	791
	792	/* Process unlocked */
	793	/* Unlock before starting ADC conversions: in case of potential */
	794	/* interruption, to let the process to ADC IRQ Handler. */
	795	__HAL_UNLOCK(hadc);
	796
	797	/* Clear regular group conversion flag and overrun flag */
	798	/* (To ensure of no unknown state from potential previous ADC */
	799	/* operations) */
	800	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
	801
	802	/* Enable conversion of regular group. */
	803	/* If software start has been selected, conversion starts immediately. */
	804	/* If external trigger has been selected, conversion will start at next */
	805	/* trigger event. */
	806	hadc->Instance->CR \|= ADC_CR_ADSTART;
	807	}
	808	}
	809	else
	810	{
	811	tmp_hal_status = HAL_BUSY;
	812	}
	813
	814	/* Return function status */
	815	return tmp_hal_status;
	816	}
	817
	818	/**
	819	* @brief Stop ADC conversion of regular group, disable ADC peripheral.
	820	* @param hadc ADC handle
	821	* @retval HAL status.
	822	*/
	823	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
	824	{
	825	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
	826
	827	/* Check the parameters */
	828	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	829
	830	/* Process locked */
	831	__HAL_LOCK(hadc);
	832
	833	/* 1. Stop potential conversion on going, on regular group */
	834	tmp_hal_status = ADC_ConversionStop(hadc);
	835
	836	/* Disable ADC peripheral if conversions are effectively stopped */
	837	if (tmp_hal_status == HAL_OK)
	838	{
	839	/* 2. Disable the ADC peripheral */
	840	tmp_hal_status = ADC_Disable(hadc);
	841
	842	/* Check if ADC is effectively disabled */
	843	if (tmp_hal_status == HAL_OK)
	844	{
	845	/* Set ADC state */
	846	ADC_STATE_CLR_SET(hadc->State,
	847	HAL_ADC_STATE_REG_BUSY,
	848	HAL_ADC_STATE_READY);
	849	}
	850	}
	851
	852	/* Process unlocked */
	853	__HAL_UNLOCK(hadc);
	854
	855	/* Return function status */
	856	return tmp_hal_status;
	857	}
	858
	859	/**
	860	* @brief Wait for regular group conversion to be completed.
	861	* @note ADC conversion flags EOS (end of sequence) and EOC (end of
	862	* conversion) are cleared by this function, with an exception:
	863	* if low power feature "LowPowerAutoWait" is enabled, flags are
	864	* not cleared to not interfere with this feature until data register
	865	* is read using function HAL_ADC_GetValue().
	866	* @note This function cannot be used in a particular setup: ADC configured
	867	* in DMA mode and polling for end of each conversion (ADC init
	868	* parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
	869	* In this case, DMA resets the flag EOC and polling cannot be
	870	* performed on each conversion. Nevertheless, polling can still
	871	* be performed on the complete sequence (ADC init
	872	* parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
	873	* @param hadc ADC handle
	874	* @param Timeout Timeout value in millisecond.
	875	* @retval HAL status
	876	*/
	877	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
	878	{
	879	uint32_t tickstart;
	880	uint32_t tmp_Flag_EOC;
	881
	882	/* Check the parameters */
	883	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	884
	885	/* If end of conversion selected to end of sequence */
	886	if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
	887	{
	888	tmp_Flag_EOC = ADC_FLAG_EOS;
	889	}
	890	/* If end of conversion selected to end of each conversion */
	891	else /* ADC_EOC_SINGLE_CONV */
	892	{
	893	/* Verification that ADC configuration is compliant with polling for */
	894	/* each conversion: */
	895	/* Particular case is ADC configured in DMA mode and ADC sequencer with */
	896	/* several ranks and polling for end of each conversion. */
	897	/* For code simplicity sake, this particular case is generalized to */
	898	/* ADC configured in DMA mode and and polling for end of each conversion. */
	899	if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN))
	900	{
	901	/* Update ADC state machine to error */
	902	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
	903
	904	/* Process unlocked */
	905	__HAL_UNLOCK(hadc);
	906
	907	return HAL_ERROR;
	908	}
	909	else
	910	{
	911	tmp_Flag_EOC = (ADC_FLAG_EOC \| ADC_FLAG_EOS);
	912	}
	913	}
	914
	915	/* Get tick count */
	916	tickstart = HAL_GetTick();
	917
	918	/* Wait until End of Conversion flag is raised */
	919	while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
	920	{
	921	/* Check if timeout is disabled (set to infinite wait) */
	922	if(Timeout != HAL_MAX_DELAY)
	923	{
	924	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
	925	{
	926	/* Update ADC state machine to timeout */
	927	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
	928
	929	/* Process unlocked */
	930	__HAL_UNLOCK(hadc);
	931
	932	return HAL_TIMEOUT;
	933	}
	934	}
	935	}
	936
	937	/* Update ADC state machine */
	938	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
	939
	940	/* Determine whether any further conversion upcoming on group regular */
	941	/* by external trigger, continuous mode or scan sequence on going. */
	942	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
	943	(hadc->Init.ContinuousConvMode == DISABLE) )
	944	{
	945	/* If End of Sequence is reached, disable interrupts */
	946	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
	947	{
	948	/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
	949	/* ADSTART==0 (no conversion on going) */
	950	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
	951	{
	952	/* Disable ADC end of single conversion interrupt on group regular */
	953	/* Note: Overrun interrupt was enabled with EOC interrupt in */
	954	/* HAL_Start_IT(), but is not disabled here because can be used */
	955	/* by overrun IRQ process below. */
	956	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC \| ADC_IT_EOS);
	957
	958	/* Set ADC state */
	959	ADC_STATE_CLR_SET(hadc->State,
	960	HAL_ADC_STATE_REG_BUSY,
	961	HAL_ADC_STATE_READY);
	962	}
	963	else
	964	{
	965	/* Change ADC state to error state */
	966	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
	967
	968	/* Set ADC error code to ADC IP internal error */
	969	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
	970	}
	971	}
	972	}
	973
	974	/* Clear end of conversion flag of regular group if low power feature */
	975	/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
	976	/* until data register is read using function HAL_ADC_GetValue(). */
	977	if (hadc->Init.LowPowerAutoWait == DISABLE)
	978	{
	979	/* Clear regular group conversion flag */
	980	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS));
	981	}
	982
	983	/* Return ADC state */
	984	return HAL_OK;
	985	}
	986
	987	/**
	988	* @brief Poll for conversion event.
	989	* @param hadc ADC handle
	990	* @param EventType the ADC event type.
	991	* This parameter can be one of the following values:
	992	* @arg ADC_AWD_EVENT: ADC Analog watchdog event
	993	* @arg ADC_OVR_EVENT: ADC Overrun event
	994	* @param Timeout Timeout value in millisecond.
	995	* @retval HAL status
	996	*/
	997	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
	998	{
	999	uint32_t tickstart=0;
	1000
	1001	/* Check the parameters */
	1002	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	1003	assert_param(IS_ADC_EVENT_TYPE(EventType));
	1004
	1005	/* Get tick count */
	1006	tickstart = HAL_GetTick();
	1007
	1008	/* Check selected event flag */
	1009	while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
	1010	{
	1011	/* Check if timeout is disabled (set to infinite wait) */
	1012	if(Timeout != HAL_MAX_DELAY)
	1013	{
	1014	if((Timeout == 0U) \|\| ((HAL_GetTick()-tickstart) > Timeout))
	1015	{
	1016	/* Update ADC state machine to timeout */
	1017	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
	1018
	1019	/* Process unlocked */
	1020	__HAL_UNLOCK(hadc);
	1021
	1022	return HAL_TIMEOUT;
	1023	}
	1024	}
	1025	}
	1026
	1027	switch(EventType)
	1028	{
	1029	/* Analog watchdog (level out of window) event */
	1030	case ADC_AWD_EVENT:
	1031	/* Set ADC state */
	1032	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
	1033
	1034	/* Clear ADC analog watchdog flag */
	1035	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
	1036	break;
	1037
	1038	/* Overrun event */
	1039	default: /* Case ADC_OVR_EVENT */
	1040	/* If overrun is set to overwrite previous data, overrun event is not */
	1041	/* considered as an error. */
	1042	/* (cf ref manual "Managing conversions without using the DMA and without */
	1043	/* overrun ") */
	1044	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
	1045	{
	1046	/* Set ADC state */
	1047	SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
	1048
	1049	/* Set ADC error code to overrun */
	1050	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
	1051	}
	1052
	1053	/* Clear ADC Overrun flag */
	1054	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
	1055	break;
	1056	}
	1057
	1058	/* Return ADC state */
	1059	return HAL_OK;
	1060	}
	1061
	1062	/**
	1063	* @brief Enables ADC, starts conversion of regular group with interruption.
	1064	* Interruptions enabled in this function:
	1065	* - EOC (end of conversion of regular group) or EOS (end of
	1066	* sequence of regular group) depending on ADC initialization
	1067	* parameter "EOCSelection"
	1068	* - overrun (if available)
	1069	* Each of these interruptions has its dedicated callback function.
	1070	* @param hadc ADC handle
	1071	* @retval HAL status
	1072	*/
	1073	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
	1074	{
	1075	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
	1076
	1077	/* Check the parameters */
	1078	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	1079
	1080	/* Perform ADC enable and conversion start if no conversion is on going */
	1081	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
	1082	{
	1083	/* Process locked */
	1084	__HAL_LOCK(hadc);
	1085
	1086	/* Enable the ADC peripheral */
	1087	/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
	1088	/* performed automatically by hardware. */
	1089	if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
	1090	{
	1091	tmp_hal_status = ADC_Enable(hadc);
	1092	}
	1093
	1094	/* Start conversion if ADC is effectively enabled */
	1095	if (tmp_hal_status == HAL_OK)
	1096	{
	1097	/* Set ADC state */
	1098	/* - Clear state bitfield related to regular group conversion results */
	1099	/* - Set state bitfield related to regular operation */
	1100	ADC_STATE_CLR_SET(hadc->State,
	1101	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR \| HAL_ADC_STATE_REG_EOSMP,
	1102	HAL_ADC_STATE_REG_BUSY);
	1103
	1104	/* Reset ADC all error code fields */
	1105	ADC_CLEAR_ERRORCODE(hadc);
	1106
	1107	/* Process unlocked */
	1108	/* Unlock before starting ADC conversions: in case of potential */
	1109	/* interruption, to let the process to ADC IRQ Handler. */
	1110	__HAL_UNLOCK(hadc);
	1111
	1112	/* Clear regular group conversion flag and overrun flag */
	1113	/* (To ensure of no unknown state from potential previous ADC */
	1114	/* operations) */
	1115	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
	1116
	1117	/* Enable ADC end of conversion interrupt */
	1118	/* Enable ADC overrun interrupt */
	1119	switch(hadc->Init.EOCSelection)
	1120	{
	1121	case ADC_EOC_SEQ_CONV:
	1122	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
	1123	__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS \| ADC_IT_OVR));
	1124	break;
	1125	/* case ADC_EOC_SINGLE_CONV */
	1126	default:
	1127	__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
	1128	break;
	1129	}
	1130
	1131	/* Enable conversion of regular group. */
	1132	/* If software start has been selected, conversion starts immediately. */
	1133	/* If external trigger has been selected, conversion will start at next */
	1134	/* trigger event. */
	1135	hadc->Instance->CR \|= ADC_CR_ADSTART;
	1136	}
	1137	}
	1138	else
	1139	{
	1140	tmp_hal_status = HAL_BUSY;
	1141	}
	1142
	1143	/* Return function status */
	1144	return tmp_hal_status;
	1145	}
	1146
	1147
	1148	/**
	1149	* @brief Stop ADC conversion of regular group, disable interruption of
	1150	* end-of-conversion, disable ADC peripheral.
	1151	* @param hadc ADC handle
	1152	* @retval HAL status.
	1153	*/
	1154	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
	1155	{
	1156	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
	1157
	1158	/* Check the parameters */
	1159	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	1160
	1161	/* Process locked */
	1162	__HAL_LOCK(hadc);
	1163
	1164	/* 1. Stop potential conversion on going, on regular group */
	1165	tmp_hal_status = ADC_ConversionStop(hadc);
	1166
	1167	/* Disable ADC peripheral if conversions are effectively stopped */
	1168	if (tmp_hal_status == HAL_OK)
	1169	{
	1170	/* Disable ADC end of conversion interrupt for regular group */
	1171	/* Disable ADC overrun interrupt */
	1172	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
	1173
	1174	/* 2. Disable the ADC peripheral */
	1175	tmp_hal_status = ADC_Disable(hadc);
	1176
	1177	/* Check if ADC is effectively disabled */
	1178	if (tmp_hal_status == HAL_OK)
	1179	{
	1180	/* Set ADC state */
	1181	ADC_STATE_CLR_SET(hadc->State,
	1182	HAL_ADC_STATE_REG_BUSY,
	1183	HAL_ADC_STATE_READY);
	1184	}
	1185	}
	1186
	1187	/* Process unlocked */
	1188	__HAL_UNLOCK(hadc);
	1189
	1190	/* Return function status */
	1191	return tmp_hal_status;
	1192	}
	1193
	1194	/**
	1195	* @brief Enables ADC, starts conversion of regular group and transfers result
	1196	* through DMA.
	1197	* Interruptions enabled in this function:
	1198	* - DMA transfer complete
	1199	* - DMA half transfer
	1200	* - overrun
	1201	* Each of these interruptions has its dedicated callback function.
	1202	* @param hadc ADC handle
	1203	* @param pData The destination Buffer address.
	1204	* @param Length The length of data to be transferred from ADC peripheral to memory.
	1205	* @retval None
	1206	*/
	1207	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
	1208	{
	1209	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
	1210
	1211	/* Check the parameters */
	1212	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	1213
	1214	/* Perform ADC enable and conversion start if no conversion is on going */
	1215	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
	1216	{
	1217	/* Process locked */
	1218	__HAL_LOCK(hadc);
	1219
	1220	/* Enable the ADC peripheral */
	1221	/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
	1222	/* performed automatically by hardware. */
	1223	if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
	1224	{
	1225	tmp_hal_status = ADC_Enable(hadc);
	1226	}
	1227
	1228	/* Start conversion if ADC is effectively enabled */
	1229	if (tmp_hal_status == HAL_OK)
	1230	{
	1231	/* Set ADC state */
	1232	/* - Clear state bitfield related to regular group conversion results */
	1233	/* - Set state bitfield related to regular operation */
	1234	ADC_STATE_CLR_SET(hadc->State,
	1235	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR \| HAL_ADC_STATE_REG_EOSMP,
	1236	HAL_ADC_STATE_REG_BUSY);
	1237
	1238	/* Reset ADC all error code fields */
	1239	ADC_CLEAR_ERRORCODE(hadc);
	1240
	1241	/* Process unlocked */
	1242	/* Unlock before starting ADC conversions: in case of potential */
	1243	/* interruption, to let the process to ADC IRQ Handler. */
	1244	__HAL_UNLOCK(hadc);
	1245
	1246	/* Set the DMA transfer complete callback */
	1247	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
	1248
	1249	/* Set the DMA half transfer complete callback */
	1250	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
	1251
	1252	/* Set the DMA error callback */
	1253	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
	1254
	1255
	1256	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
	1257	/* start (in case of SW start): */
	1258
	1259	/* Clear regular group conversion flag and overrun flag */
	1260	/* (To ensure of no unknown state from potential previous ADC */
	1261	/* operations) */
	1262	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
	1263
	1264	/* Enable ADC overrun interrupt */
	1265	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
	1266
	1267	/* Enable ADC DMA mode */
	1268	hadc->Instance->CFGR1 \|= ADC_CFGR1_DMAEN;
	1269
	1270	/* Start the DMA channel */
	1271	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
	1272
	1273	/* Enable conversion of regular group. */
	1274	/* If software start has been selected, conversion starts immediately. */
	1275	/* If external trigger has been selected, conversion will start at next */
	1276	/* trigger event. */
	1277	hadc->Instance->CR \|= ADC_CR_ADSTART;
	1278	}
	1279	}
	1280	else
	1281	{
	1282	tmp_hal_status = HAL_BUSY;
	1283	}
	1284
	1285	/* Return function status */
	1286	return tmp_hal_status;
	1287	}
	1288
	1289	/**
	1290	* @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable
	1291	* ADC peripheral.
	1292	* Each of these interruptions has its dedicated callback function.
	1293	* @param hadc ADC handle
	1294	* @retval HAL status.
	1295	*/
	1296	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
	1297	{
	1298	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
	1299
	1300	/* Check the parameters */
	1301	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	1302
	1303	/* Process locked */
	1304	__HAL_LOCK(hadc);
	1305
	1306	/* 1. Stop potential conversion on going, on regular group */
	1307	tmp_hal_status = ADC_ConversionStop(hadc);
	1308
	1309	/* Disable ADC peripheral if conversions are effectively stopped */
	1310	if (tmp_hal_status == HAL_OK)
	1311	{
	1312	/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
	1313	hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN;
	1314
	1315	/* Disable the DMA channel (in case of DMA in circular mode or stop while */
	1316	/* while DMA transfer is on going) */
	1317	tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
	1318
	1319	/* Check if DMA channel effectively disabled */
	1320	if (tmp_hal_status != HAL_OK)
	1321	{
	1322	/* Update ADC state machine to error */
	1323	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
	1324	}
	1325
	1326	/* Disable ADC overrun interrupt */
	1327	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
	1328
	1329	/* 2. Disable the ADC peripheral */
	1330	/* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */
	1331	/* in memory a potential failing status. */
	1332	if (tmp_hal_status == HAL_OK)
	1333	{
	1334	tmp_hal_status = ADC_Disable(hadc);
	1335	}
	1336	else
	1337	{
	1338	ADC_Disable(hadc);
	1339	}
	1340
	1341	/* Check if ADC is effectively disabled */
	1342	if (tmp_hal_status == HAL_OK)
	1343	{
	1344	/* Set ADC state */
	1345	ADC_STATE_CLR_SET(hadc->State,
	1346	HAL_ADC_STATE_REG_BUSY,
	1347	HAL_ADC_STATE_READY);
	1348	}
	1349
	1350	}
	1351
	1352	/* Process unlocked */
	1353	__HAL_UNLOCK(hadc);
	1354
	1355	/* Return function status */
	1356	return tmp_hal_status;
	1357	}
	1358
	1359	/**
	1360	* @brief Get ADC regular group conversion result.
	1361	* @note Reading register DR automatically clears ADC flag EOC
	1362	* (ADC group regular end of unitary conversion).
	1363	* @note This function does not clear ADC flag EOS
	1364	* (ADC group regular end of sequence conversion).
	1365	* Occurrence of flag EOS rising:
	1366	* - If sequencer is composed of 1 rank, flag EOS is equivalent
	1367	* to flag EOC.
	1368	* - If sequencer is composed of several ranks, during the scan
	1369	* sequence flag EOC only is raised, at the end of the scan sequence
	1370	* both flags EOC and EOS are raised.
	1371	* To clear this flag, either use function:
	1372	* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
	1373	* model polling: @ref HAL_ADC_PollForConversion()
	1374	* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
	1375	* @param hadc ADC handle
	1376	* @retval ADC group regular conversion data
	1377	*/
	1378	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
	1379	{
	1380	/* Check the parameters */
	1381	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	1382
	1383	/* Note: EOC flag is not cleared here by software because automatically */
	1384	/* cleared by hardware when reading register DR. */
	1385
	1386	/* Return ADC converted value */
	1387	return hadc->Instance->DR;
	1388	}
	1389
	1390	/**
	1391	* @brief Handles ADC interrupt request.
	1392	* @param hadc ADC handle
	1393	* @retval None
	1394	*/
	1395	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
	1396	{
	1397	/* Check the parameters */
	1398	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	1399	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
	1400	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
	1401
	1402	/* ========== Check End of Conversion flag for regular group ========== */
	1403	if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) \|\|
	1404	(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
	1405	{
	1406	/* Update state machine on conversion status if not in error state */
	1407	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
	1408	{
	1409	/* Set ADC state */
	1410	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
	1411	}
	1412
	1413	/* Determine whether any further conversion upcoming on group regular */
	1414	/* by external trigger, continuous mode or scan sequence on going. */
	1415	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
	1416	(hadc->Init.ContinuousConvMode == DISABLE) )
	1417	{
	1418	/* If End of Sequence is reached, disable interrupts */
	1419	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
	1420	{
	1421	/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
	1422	/* ADSTART==0 (no conversion on going) */
	1423	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
	1424	{
	1425	/* Disable ADC end of single conversion interrupt on group regular */
	1426	/* Note: Overrun interrupt was enabled with EOC interrupt in */
	1427	/* HAL_Start_IT(), but is not disabled here because can be used */
	1428	/* by overrun IRQ process below. */
	1429	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC \| ADC_IT_EOS);
	1430
	1431	/* Set ADC state */
	1432	ADC_STATE_CLR_SET(hadc->State,
	1433	HAL_ADC_STATE_REG_BUSY,
	1434	HAL_ADC_STATE_READY);
	1435	}
	1436	else
	1437	{
	1438	/* Change ADC state to error state */
	1439	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
	1440
	1441	/* Set ADC error code to ADC IP internal error */
	1442	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
	1443	}
	1444	}
	1445	}
	1446
	1447	/* Conversion complete callback */
	1448	/* Note: into callback, to determine if conversion has been triggered */
	1449	/* from EOC or EOS, possibility to use: */
	1450	/* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
	1451	HAL_ADC_ConvCpltCallback(hadc);
	1452
	1453
	1454	/* Clear regular group conversion flag */
	1455	/* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
	1456	/* conversion flags clear induces the release of the preserved data.*/
	1457	/* Therefore, if the preserved data value is needed, it must be */
	1458	/* read preliminarily into HAL_ADC_ConvCpltCallback(). */
	1459	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS) );
	1460	}
	1461
	1462	/* ========== Check Analog watchdog flags ========== */
	1463	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
	1464	{
	1465	/* Set ADC state */
	1466	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
	1467
	1468	/* Level out of window callback */
	1469	HAL_ADC_LevelOutOfWindowCallback(hadc);
	1470
	1471	/* Clear ADC Analog watchdog flag */
	1472	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
	1473
	1474	}
	1475
	1476
	1477	/* ========== Check Overrun flag ========== */
	1478	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
	1479	{
	1480	/* If overrun is set to overwrite previous data (default setting), */
	1481	/* overrun event is not considered as an error. */
	1482	/* (cf ref manual "Managing conversions without using the DMA and without */
	1483	/* overrun ") */
	1484	/* Exception for usage with DMA overrun event always considered as an */
	1485	/* error. */
	1486	if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) \|\|
	1487	HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) )
	1488	{
	1489	/* Set ADC error code to overrun */
	1490	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
	1491
	1492	/* Clear ADC overrun flag */
	1493	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
	1494
	1495	/* Error callback */
	1496	HAL_ADC_ErrorCallback(hadc);
	1497	}
	1498
	1499	/* Clear the Overrun flag */
	1500	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
	1501	}
	1502
	1503	}
	1504
	1505
	1506	/**
	1507	* @brief Conversion complete callback in non blocking mode
	1508	* @param hadc ADC handle
	1509	* @retval None
	1510	*/
	1511	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
	1512	{
	1513	/* Prevent unused argument(s) compilation warning */
	1514	UNUSED(hadc);
	1515
	1516	/* NOTE : This function should not be modified. When the callback is needed,
	1517	function HAL_ADC_ConvCpltCallback must be implemented in the user file.
	1518	*/
	1519	}
	1520
	1521	/**
	1522	* @brief Conversion DMA half-transfer callback in non blocking mode
	1523	* @param hadc ADC handle
	1524	* @retval None
	1525	*/
	1526	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
	1527	{
	1528	/* Prevent unused argument(s) compilation warning */
	1529	UNUSED(hadc);
	1530
	1531	/* NOTE : This function should not be modified. When the callback is needed,
	1532	function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
	1533	*/
	1534	}
	1535
	1536	/**
	1537	* @brief Analog watchdog callback in non blocking mode.
	1538	* @param hadc ADC handle
	1539	* @retval None
	1540	*/
	1541	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
	1542	{
	1543	/* Prevent unused argument(s) compilation warning */
	1544	UNUSED(hadc);
	1545
	1546	/* NOTE : This function should not be modified. When the callback is needed,
	1547	function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
	1548	*/
	1549	}
	1550
	1551	/**
	1552	* @brief ADC error callback in non blocking mode
	1553	* (ADC conversion with interruption or transfer by DMA)
	1554	* @param hadc ADC handle
	1555	* @retval None
	1556	*/
	1557	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
	1558	{
	1559	/* Prevent unused argument(s) compilation warning */
	1560	UNUSED(hadc);
	1561
	1562	/* NOTE : This function should not be modified. When the callback is needed,
	1563	function HAL_ADC_ErrorCallback must be implemented in the user file.
	1564	*/
	1565	}
	1566
	1567
	1568	/**
	1569	* @}
	1570	*/
	1571
	1572	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
	1573	* @brief Peripheral Control functions
	1574	*
	1575	@verbatim
	1576	===============================================================================
	1577	##### Peripheral Control functions #####
	1578	===============================================================================
	1579	[..] This section provides functions allowing to:
	1580	(+) Configure channels on regular group
	1581	(+) Configure the analog watchdog
	1582
	1583	@endverbatim
	1584	* @{
	1585	*/
	1586
	1587	/**
	1588	* @brief Configures the the selected channel to be linked to the regular
	1589	* group.
	1590	* @note In case of usage of internal measurement channels:
	1591	* VrefInt/Vbat/TempSensor.
	1592	* Sampling time constraints must be respected (sampling time can be
	1593	* adjusted in function of ADC clock frequency and sampling time
	1594	* setting).
	1595	* Refer to device datasheet for timings values, parameters TS_vrefint,
	1596	* TS_vbat, TS_temp (values rough order: 5us to 17us).
	1597	* These internal paths can be be disabled using function
	1598	* HAL_ADC_DeInit().
	1599	* @note Possibility to update parameters on the fly:
	1600	* This function initializes channel into regular group, following
	1601	* calls to this function can be used to reconfigure some parameters
	1602	* of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
	1603	* the ADC.
	1604	* The setting of these parameters is conditioned to ADC state.
	1605	* For parameters constraints, see comments of structure
	1606	* "ADC_ChannelConfTypeDef".
	1607	* @param hadc ADC handle
	1608	* @param sConfig Structure of ADC channel for regular group.
	1609	* @retval HAL status
	1610	*/
	1611	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
	1612	{
	1613	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
	1614	__IO uint32_t wait_loop_index = 0U;
	1615
	1616	/* Check the parameters */
	1617	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	1618	assert_param(IS_ADC_CHANNEL(sConfig->Channel));
	1619	assert_param(IS_ADC_RANK(sConfig->Rank));
	1620
	1621	if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
	1622	{
	1623	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
	1624	}
	1625
	1626	/* Process locked */
	1627	__HAL_LOCK(hadc);
	1628
	1629	/* Parameters update conditioned to ADC state: */
	1630	/* Parameters that can be updated when ADC is disabled or enabled without */
	1631	/* conversion on going on regular group: */
	1632	/* - Channel number */
	1633	/* - Channel sampling time */
	1634	/* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
	1635	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
	1636	{
	1637	/* Configure channel: depending on rank setting, add it or remove it from */
	1638	/* ADC conversion sequencer. */
	1639	if (sConfig->Rank != ADC_RANK_NONE)
	1640	{
	1641	/* Regular sequence configuration */
	1642	/* Set the channel selection register from the selected channel */
	1643	hadc->Instance->CHSELR \|= ADC_CHSELR_CHANNEL(sConfig->Channel);
	1644
	1645	/* Channel sampling time configuration */
	1646	/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
	1647	/* (obsolete): sampling time set in this function with */
	1648	/* parameter "SamplingTime" (obsolete) only if not already set into */
	1649	/* ADC initialization structure with parameter "SamplingTimeCommon". */
	1650	if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
	1651	{
	1652	/* Modify sampling time if needed (not needed in case of reoccurrence */
	1653	/* for several channels programmed consecutively into the sequencer) */
	1654	if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc))
	1655	{
	1656	/* Channel sampling time configuration */
	1657	/* Clear the old sample time */
	1658	hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
	1659
	1660	/* Set the new sample time */
	1661	hadc->Instance->SMPR \|= ADC_SMPR_SET(sConfig->SamplingTime);
	1662	}
	1663	}
	1664
	1665	/* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
	1666	/* internal measurement paths enable: If internal channel selected, */
	1667	/* enable dedicated internal buffers and path. */
	1668	/* Note: these internal measurement paths can be disabled using */
	1669	/* HAL_ADC_DeInit() or removing the channel from sequencer with */
	1670	/* channel configuration parameter "Rank". */
	1671	if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
	1672	{
	1673	/* If Channel_16 is selected, enable Temp. sensor measurement path. */
	1674	/* If Channel_17 is selected, enable VREFINT measurement path. */
	1675	/* If Channel_18 is selected, enable VBAT measurement path. */
	1676	ADC->CCR \|= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
	1677
	1678	/* If Temp. sensor is selected, wait for stabilization delay */
	1679	if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
	1680	{
	1681	/* Delay for temperature sensor stabilization time */
	1682	/* Compute number of CPU cycles to wait for */
	1683	wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
	1684	while(wait_loop_index != 0U)
	1685	{
	1686	wait_loop_index--;
	1687	}
	1688	}
	1689	}
	1690	}
	1691	else
	1692	{
	1693	/* Regular sequence configuration */
	1694	/* Reset the channel selection register from the selected channel */
	1695	hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel);
	1696
	1697	/* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
	1698	/* internal measurement paths disable: If internal channel selected, */
	1699	/* disable dedicated internal buffers and path. */
	1700	if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
	1701	{
	1702	/* If Channel_16 is selected, disable Temp. sensor measurement path. */
	1703	/* If Channel_17 is selected, disable VREFINT measurement path. */
	1704	/* If Channel_18 is selected, disable VBAT measurement path. */
	1705	ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
	1706	}
	1707	}
	1708
	1709	}
	1710
	1711	/* If a conversion is on going on regular group, no update on regular */
	1712	/* channel could be done on neither of the channel configuration structure */
	1713	/* parameters. */
	1714	else
	1715	{
	1716	/* Update ADC state machine to error */
	1717	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
	1718
	1719	tmp_hal_status = HAL_ERROR;
	1720	}
	1721
	1722	/* Process unlocked */
	1723	__HAL_UNLOCK(hadc);
	1724
	1725	/* Return function status */
	1726	return tmp_hal_status;
	1727	}
	1728
	1729
	1730	/**
	1731	* @brief Configures the analog watchdog.
	1732	* @note Possibility to update parameters on the fly:
	1733	* This function initializes the selected analog watchdog, following
	1734	* calls to this function can be used to reconfigure some parameters
	1735	* of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
	1736	* the ADC.
	1737	* The setting of these parameters is conditioned to ADC state.
	1738	* For parameters constraints, see comments of structure
	1739	* "ADC_AnalogWDGConfTypeDef".
	1740	* @param hadc ADC handle
	1741	* @param AnalogWDGConfig Structure of ADC analog watchdog configuration
	1742	* @retval HAL status
	1743	*/
	1744	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
	1745	{
	1746	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
	1747
	1748	uint32_t tmpAWDHighThresholdShifted;
	1749	uint32_t tmpAWDLowThresholdShifted;
	1750
	1751	/* Check the parameters */
	1752	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	1753	assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
	1754	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
	1755
	1756	/* Verify if threshold is within the selected ADC resolution */
	1757	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
	1758	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
	1759
	1760	if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
	1761	{
	1762	assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
	1763	}
	1764
	1765	/* Process locked */
	1766	__HAL_LOCK(hadc);
	1767
	1768	/* Parameters update conditioned to ADC state: */
	1769	/* Parameters that can be updated when ADC is disabled or enabled without */
	1770	/* conversion on going on regular group: */
	1771	/* - Analog watchdog channels */
	1772	/* - Analog watchdog thresholds */
	1773	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
	1774	{
	1775	/* Configuration of analog watchdog: */
	1776	/* - Set the analog watchdog enable mode: one or overall group of */
	1777	/* channels. */
	1778	/* - Set the Analog watchdog channel (is not used if watchdog */
	1779	/* mode "all channels": ADC_CFGR_AWD1SGL=0). */
	1780	hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL \|
	1781	ADC_CFGR1_AWDEN \|
	1782	ADC_CFGR1_AWDCH );
	1783
	1784	hadc->Instance->CFGR1 \|= ( AnalogWDGConfig->WatchdogMode \|
	1785	ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) );
	1786
	1787	/* Shift the offset in function of the selected ADC resolution: Thresholds*/
	1788	/* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
	1789	tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
	1790	tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
	1791
	1792	/* Set the high and low thresholds */
	1793	hadc->Instance->TR &= ~(ADC_TR_HT \| ADC_TR_LT);
	1794	hadc->Instance->TR \|= ( ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \|
	1795	tmpAWDLowThresholdShifted );
	1796
	1797	/* Clear the ADC Analog watchdog flag (in case of left enabled by */
	1798	/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
	1799	/* or HAL_ADC_PollForEvent(). */
	1800	__HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD);
	1801
	1802	/* Configure ADC Analog watchdog interrupt */
	1803	if(AnalogWDGConfig->ITMode == ENABLE)
	1804	{
	1805	/* Enable the ADC Analog watchdog interrupt */
	1806	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
	1807	}
	1808	else
	1809	{
	1810	/* Disable the ADC Analog watchdog interrupt */
	1811	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
	1812	}
	1813
	1814	}
	1815	/* If a conversion is on going on regular group, no update could be done */
	1816	/* on neither of the AWD configuration structure parameters. */
	1817	else
	1818	{
	1819	/* Update ADC state machine to error */
	1820	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
	1821
	1822	tmp_hal_status = HAL_ERROR;
	1823	}
	1824
	1825
	1826	/* Process unlocked */
	1827	__HAL_UNLOCK(hadc);
	1828
	1829	/* Return function status */
	1830	return tmp_hal_status;
	1831	}
	1832
	1833
	1834	/**
	1835	* @}
	1836	*/
	1837
	1838
	1839	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
	1840	* @brief Peripheral State functions
	1841	*
	1842	@verbatim
	1843	===============================================================================
	1844	##### Peripheral State and Errors functions #####
	1845	===============================================================================
	1846	[..]
	1847	This subsection provides functions to get in run-time the status of the
	1848	peripheral.
	1849	(+) Check the ADC state
	1850	(+) Check the ADC error code
	1851
	1852	@endverbatim
	1853	* @{
	1854	*/
	1855
	1856	/**
	1857	* @brief Return the ADC state
	1858	* @note ADC state machine is managed by bitfields, ADC status must be
	1859	* compared with states bits.
	1860	* For example:
	1861	* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
	1862	* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
	1863	* @param hadc ADC handle
	1864	* @retval HAL state
	1865	*/
	1866	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
	1867	{
	1868	/* Check the parameters */
	1869	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	1870
	1871	/* Return ADC state */
	1872	return hadc->State;
	1873	}
	1874
	1875	/**
	1876	* @brief Return the ADC error code
	1877	* @param hadc ADC handle
	1878	* @retval ADC Error Code
	1879	*/
	1880	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
	1881	{
	1882	return hadc->ErrorCode;
	1883	}
	1884
	1885	/**
	1886	* @}
	1887	*/
	1888
	1889	/**
	1890	* @}
	1891	*/
	1892
	1893	/** @defgroup ADC_Private_Functions ADC Private Functions
	1894	* @{
	1895	*/
	1896
	1897	/**
	1898	* @brief Enable the selected ADC.
	1899	* @note Prerequisite condition to use this function: ADC must be disabled
	1900	* and voltage regulator must be enabled (done into HAL_ADC_Init()).
	1901	* @note If low power mode AutoPowerOff is enabled, power-on/off phases are
	1902	* performed automatically by hardware.
	1903	* In this mode, this function is useless and must not be called because
	1904	* flag ADC_FLAG_RDY is not usable.
	1905	* Therefore, this function must be called under condition of
	1906	* "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
	1907	* @param hadc ADC handle
	1908	* @retval HAL status.
	1909	*/
	1910	static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
	1911	{
	1912	uint32_t tickstart = 0U;
	1913	__IO uint32_t wait_loop_index = 0U;
	1914
	1915	/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
	1916	/* enabling phase not yet completed: flag ADC ready not yet set). */
	1917	/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
	1918	/* causes: ADC clock not running, ...). */
	1919	if (ADC_IS_ENABLE(hadc) == RESET)
	1920	{
	1921	/* Check if conditions to enable the ADC are fulfilled */
	1922	if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
	1923	{
	1924	/* Update ADC state machine to error */
	1925	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
	1926
	1927	/* Set ADC error code to ADC IP internal error */
	1928	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
	1929
	1930	return HAL_ERROR;
	1931	}
	1932
	1933	/* Enable the ADC peripheral */
	1934	__HAL_ADC_ENABLE(hadc);
	1935
	1936	/* Delay for ADC stabilization time */
	1937	/* Compute number of CPU cycles to wait for */
	1938	wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
	1939	while(wait_loop_index != 0U)
	1940	{
	1941	wait_loop_index--;
	1942	}
	1943
	1944	/* Get tick count */
	1945	tickstart = HAL_GetTick();
	1946
	1947	/* Wait for ADC effectively enabled */
	1948	while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
	1949	{
	1950	if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
	1951	{
	1952	/* Update ADC state machine to error */
	1953	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
	1954
	1955	/* Set ADC error code to ADC IP internal error */
	1956	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
	1957
	1958	return HAL_ERROR;
	1959	}
	1960	}
	1961
	1962	}
	1963
	1964	/* Return HAL status */
	1965	return HAL_OK;
	1966	}
	1967
	1968	/**
	1969	* @brief Disable the selected ADC.
	1970	* @note Prerequisite condition to use this function: ADC conversions must be
	1971	* stopped.
	1972	* @param hadc ADC handle
	1973	* @retval HAL status.
	1974	*/
	1975	static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
	1976	{
	1977	uint32_t tickstart = 0U;
	1978
	1979	/* Verification if ADC is not already disabled: */
	1980	/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
	1981	/* disabled. */
	1982	if (ADC_IS_ENABLE(hadc) != RESET)
	1983	{
	1984	/* Check if conditions to disable the ADC are fulfilled */
	1985	if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
	1986	{
	1987	/* Disable the ADC peripheral */
	1988	__HAL_ADC_DISABLE(hadc);
	1989	}
	1990	else
	1991	{
	1992	/* Update ADC state machine to error */
	1993	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
	1994
	1995	/* Set ADC error code to ADC IP internal error */
	1996	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
	1997
	1998	return HAL_ERROR;
	1999	}
	2000
	2001	/* Wait for ADC effectively disabled */
	2002	/* Get tick count */
	2003	tickstart = HAL_GetTick();
	2004
	2005	while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
	2006	{
	2007	if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
	2008	{
	2009	/* Update ADC state machine to error */
	2010	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
	2011
	2012	/* Set ADC error code to ADC IP internal error */
	2013	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
	2014
	2015	return HAL_ERROR;
	2016	}
	2017	}
	2018	}
	2019
	2020	/* Return HAL status */
	2021	return HAL_OK;
	2022	}
	2023
	2024
	2025	/**
	2026	* @brief Stop ADC conversion.
	2027	* @note Prerequisite condition to use this function: ADC conversions must be
	2028	* stopped to disable the ADC.
	2029	* @param hadc ADC handle
	2030	* @retval HAL status.
	2031	*/
	2032	static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
	2033	{
	2034	uint32_t tickstart = 0U;
	2035
	2036	/* Check the parameters */
	2037	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
	2038
	2039	/* Verification if ADC is not already stopped on regular group to bypass */
	2040	/* this function if not needed. */
	2041	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
	2042	{
	2043
	2044	/* Stop potential conversion on going on regular group */
	2045	/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
	2046	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
	2047	HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
	2048	{
	2049	/* Stop conversions on regular group */
	2050	hadc->Instance->CR \|= ADC_CR_ADSTP;
	2051	}
	2052
	2053	/* Wait for conversion effectively stopped */
	2054	/* Get tick count */
	2055	tickstart = HAL_GetTick();
	2056
	2057	while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
	2058	{
	2059	if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
	2060	{
	2061	/* Update ADC state machine to error */
	2062	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
	2063
	2064	/* Set ADC error code to ADC IP internal error */
	2065	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
	2066
	2067	return HAL_ERROR;
	2068	}
	2069	}
	2070
	2071	}
	2072
	2073	/* Return HAL status */
	2074	return HAL_OK;
	2075	}
	2076
	2077
	2078	/**
	2079	* @brief DMA transfer complete callback.
	2080	* @param hdma pointer to DMA handle.
	2081	* @retval None
	2082	*/
	2083	static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
	2084	{
	2085	/* Retrieve ADC handle corresponding to current DMA handle */
	2086	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
	2087
	2088	/* Update state machine on conversion status if not in error state */
	2089	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL \| HAL_ADC_STATE_ERROR_DMA))
	2090	{
	2091	/* Set ADC state */
	2092	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
	2093
	2094	/* Determine whether any further conversion upcoming on group regular */
	2095	/* by external trigger, continuous mode or scan sequence on going. */
	2096	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
	2097	(hadc->Init.ContinuousConvMode == DISABLE) )
	2098	{
	2099	/* If End of Sequence is reached, disable interrupts */
	2100	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
	2101	{
	2102	/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
	2103	/* ADSTART==0 (no conversion on going) */
	2104	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
	2105	{
	2106	/* Disable ADC end of single conversion interrupt on group regular */
	2107	/* Note: Overrun interrupt was enabled with EOC interrupt in */
	2108	/* HAL_Start_IT(), but is not disabled here because can be used */
	2109	/* by overrun IRQ process below. */
	2110	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC \| ADC_IT_EOS);
	2111
	2112	/* Set ADC state */
	2113	ADC_STATE_CLR_SET(hadc->State,
	2114	HAL_ADC_STATE_REG_BUSY,
	2115	HAL_ADC_STATE_READY);
	2116	}
	2117	else
	2118	{
	2119	/* Change ADC state to error state */
	2120	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
	2121
	2122	/* Set ADC error code to ADC IP internal error */
	2123	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
	2124	}
	2125	}
	2126	}
	2127
	2128	/* Conversion complete callback */
	2129	HAL_ADC_ConvCpltCallback(hadc);
	2130	}
	2131	else
	2132	{
	2133	/* Call DMA error callback */
	2134	hadc->DMA_Handle->XferErrorCallback(hdma);
	2135	}
	2136
	2137	}
	2138
	2139	/**
	2140	* @brief DMA half transfer complete callback.
	2141	* @param hdma pointer to DMA handle.
	2142	* @retval None
	2143	*/
	2144	static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
	2145	{
	2146	/* Retrieve ADC handle corresponding to current DMA handle */
	2147	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
	2148
	2149	/* Half conversion callback */
	2150	HAL_ADC_ConvHalfCpltCallback(hadc);
	2151	}
	2152
	2153	/**
	2154	* @brief DMA error callback
	2155	* @param hdma pointer to DMA handle.
	2156	* @retval None
	2157	*/
	2158	static void ADC_DMAError(DMA_HandleTypeDef *hdma)
	2159	{
	2160	/* Retrieve ADC handle corresponding to current DMA handle */
	2161	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
	2162
	2163	/* Set ADC state */
	2164	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
	2165
	2166	/* Set ADC error code to DMA error */
	2167	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
	2168
	2169	/* Error callback */
	2170	HAL_ADC_ErrorCallback(hadc);
	2171	}
	2172
	2173	/**
	2174	* @}
	2175	*/
	2176
	2177	#endif /* HAL_ADC_MODULE_ENABLED */
	2178	/**
	2179	* @}
	2180	*/
	2181
	2182	/**
	2183	* @}
	2184	*/
	2185
	2186	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/